Radar signal processing system and method

Abstract

The embodiment of the invention provides a radar signal processing system and method, and relates to the field of radar signal processing, the system comprises an ARM processor and a field programmable gate array, the ARM processor comprises a first processor and a second processor, the field programmable gate array is used for carrying out AD sampling, data preprocessing, pulse compression, fast Fourier transform and CFAR detection on received radar echo signals to obtain target radar echo signals, and the first processor is used for dividing the target radar echo signals into first target radar echo signals and second target radar echo signals; the first processor is used for carrying out target identification based on the first target radar echo signal to obtain a first identification result, the second processor is used for carrying out target identification based on the second target radar echo signal to obtain a second identification result, the first identification result and the second identification result are fused to obtain a final detection result, and the radar signal processing efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the field of radar signal processing, and in particular to a radar signal processing system and method. Background Art

[0002] Radar signal processing has a vital impact on the performance of radar systems. Radar signal processing is the core link in radar systems. It extracts useful information through a series of complex processing and analysis of received radar signals, thereby completing tasks such as target detection, tracking and identification.

[0003] However, the signal processing efficiency of existing radar signal processing systems is low. Summary of the invention

[0004] The object of the present invention is to provide a radar signal processing system and method, which can improve the efficiency of signal processing.

[0005] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows:

[0006] In a first aspect, an embodiment of the present invention provides a radar signal processing system, the radar signal processing system comprising: an ARM processor and a field programmable gate array, the ARM processor comprising a first processor and a second processor;

[0007] The field programmable gate array is used to perform AD sampling, data preprocessing, pulse compression, fast Fourier transform and CFAR detection on the received radar echo signal to obtain the target radar echo signal;

[0008] The first processor is used to divide the target radar echo signal into a first target radar echo signal and a second target radar echo signal, send the second target radar echo signal to the second processor, perform target recognition based on the first target radar echo signal, and obtain a first recognition result;

[0009] The second processor is used to receive the first recognition result, perform target recognition based on the second target radar echo signal to obtain a second recognition result, and fuse the first recognition result and the second recognition result to obtain a final detection result.

[0010] In an optional embodiment, the radar signal processing system further includes a non-volatile memory;

[0011] The non-volatile memory stores a first mirror program and a second mirror program, wherein the first mirror program is stored in a first data block, and the second mirror program is stored in a second data block, the first data block is a data block with a front storage address, and the second data block is a data block with a back storage address, the first mirror program is a program to be upgraded, and the second mirror program is an upgrade program of the first mirror program.

[0012] In an optional implementation, the first mirror program includes a first file, a second file, a third file, and a fourth file, the first file is a startup program of the radar signal processing system, the second file is a startup program of a field programmable gate array, the third file is a startup program of the first processor, and the fourth file is a startup program of the second processor;

[0013] The radar signal processing system is used to load the first file and the second file in sequence;

[0014] When it is detected that the serial port of the field programmable gate array receives an update signal, the second mirror program is loaded to update the first mirror program.

[0015] In an optional implementation, the radar signal processing system is further configured to: load the third file and the fourth file in sequence when it is not detected that the serial port of the field programmable gate array has received an update signal.

[0016] In an optional embodiment, the radar signal processing system is also used to: load the second mirror program when it is detected that the serial port of the field programmable gate array receives an update signal, receive update information sent by the computer, and update the first mirror program based on the second mirror program and the update information.

[0017] In an optional implementation, the non-volatile memory also stores operating parameter information of the radar signal processing system.

[0018] In an optional implementation, the ARM processor and the field programmable gate array are further used for:

[0019] Loading the operating parameter information from the non-volatile memory;

[0020] The field programmable gate array is further used to configure the working state based on the first parameter information in the working parameter information;

[0021] The ARM processor is also used to perform working state configuration based on the second parameter information in the working parameter information.

[0022] In an optional implementation, when the radar signal processing system receives a first instruction to modify a parameter in operation, the radar signal processing system obtains the operating parameter information loaded in the non-volatile memory based on the first instruction, and modifies the operating parameter information loaded in the non-volatile memory to obtain a first parameter;

[0023] determining a target data segment in a working procedure based on the first parameter;

[0024] The target data segment is modified based on the first parameter.

[0025] In an optional embodiment, when the radar signal processing system receives a modification instruction to load the operating parameter information into the non-volatile memory, the radar signal processing system modifies the operating parameter information based on the modification instruction and rewrites the modified operating parameter information into the non-volatile memory.

[0026] In a second aspect, an embodiment of the present invention provides a radar signal processing method, which detects radar signals through a radar signal processing system.

[0027] The present invention has the following beneficial effects:

[0028] The radar signal processing system provided by the present invention comprises: an ARM processor and a field programmable gate array, the ARM processor comprises a first processor and a second processor, the field programmable gate array is used for performing AD sampling, data preprocessing, pulse compression, fast Fourier transform and CFAR detection on a received radar echo signal to obtain a target radar echo signal, the first processor is used for dividing the target radar echo signal into a first target radar echo signal and a second target radar echo signal, sending the second target radar echo signal to the second processor, performing target recognition based on the first target radar echo signal to obtain a first recognition result, the second processor is used for receiving the first recognition result, performing target recognition based on the second target radar echo signal to obtain a second recognition result, fusing the first recognition result and the second recognition result to obtain a final detection result, thereby improving the efficiency of radar signal processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 A diagram of the ZYNQ system architecture in the prior art provided for an embodiment of the present invention;

[0031] Figure 2 A structural block diagram of a radar signal processing system provided by an embodiment of the present invention;

[0032] Figure 3 One of the schematic diagrams of the non-volatile memory provided by the embodiment of the present invention;

[0033] Figure 4 One of the flowcharts of the radar signal processing method provided by an embodiment of the present invention;

[0034] Figure 5 A second schematic diagram of a non-volatile memory provided by an embodiment of the present invention;

[0035] Figure 6 A second flowchart of a radar signal processing method provided by an embodiment of the present invention;

[0036] Figure 7 The third flowchart of the radar signal processing method provided by the embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0038] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0040] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0041] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0042] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0043] After extensive research, the inventors found that the current radar signal processing system usually uses the ZYNQ platform, such as Figure 1 As shown in the figure, it is the ZYNQ system architecture diagram. The Zynq series chips integrate 2 ARM processors (commonly known as PS) and 1 FPGA (commonly known as PL) on one chip, providing powerful processing capabilities and real-time performance, which is very suitable for complex tasks such as radar signal processing, target detection and tracking.

[0044] In radar applications, the advantages of the Zynq platform include:

[0045] 1. Hardware acceleration: The FPGA part can accelerate signal processing algorithms, such as FFT, filtering, CFAR, etc., to improve the real-time performance of the system.

[0046] 2. Flexibility: The hardware circuit can be customized according to needs to adapt to different radar application scenarios, such as ground target detection, ocean monitoring, air early warning, etc.

[0047] 3. Compact integration: The processor and programmable logic are integrated on a single chip, which greatly reduces the size and power consumption of the system, making it particularly suitable for radar systems on portable or unmanned platforms.

[0048] 4. Real-time performance: With the help of the ARM processor of the ZYNQ system, the real-time responsiveness of the software architecture can be guaranteed when processing system-level tasks (such as target tracking and recognition).

[0049] As the complexity of modern radar systems increases, the need for efficient and real-time processing has made ZYNQ systems a common choice. More and more radar systems, especially embedded radars, use ZYNQ systems to implement high-performance signal processing and control functions.

[0050] Application of ZYNQ system in radar system: PS function: Control and management: configure FPGA, initialize radar system, manage task scheduling. Advanced algorithm processing: execute target detection, tracking and recognition algorithms. User interface: display radar data, user interaction interface. Data storage and management: store radar data, record operation log. PL function: Real-time signal processing: realize high-performance processing tasks such as FFT and pulse compression. Parallel data processing: process data of multiple radar channels and perform parallel computing tasks. Hardware acceleration: accelerate specific algorithms, such as CFAR detection. Data flow management: manage and optimize radar data flow to ensure efficient data transmission.

[0051] The PS part is mainly responsible for system control, configuration, application layer logic, high-level data processing, user interaction and external communication. The PL part is mainly responsible for hardware acceleration, real-time signal processing, custom hardware functions and data flow management. Through this division of labor, the ZYNQ system can fully utilize the computing and management capabilities of the PS and the hardware acceleration capabilities of the PL to achieve efficient and flexible system design.

[0052] However, in the prior art, the method of radar signal processing based on the ZYNQ system is usually as follows: the analog echo signal is converted into a digital echo signal and then sent to the PL end of the ZYNQ system; the PL end preprocesses the received digital echo signal; the PL end completes the distance dimension Fourier transform, the velocity dimension Fourier transform and the receiving digital beam DBF formation, and generates velocity dimension FFT data; the PS end of the ZYNQ system reads the velocity dimension FFT data, performs CFAR detection and angle detection; the PS end performs point track condensation to generate a radar track, and sends the radar track to the host computer.

[0053] In the existing ZYNQ system, CFAR processing is completed in the PS during radar signal processing. The CFAR algorithm is implemented in the processing system (PS) of the ZYNQ system. Although the CPU resources in the PS can be used for flexible algorithm implementation, there are also some obvious disadvantages. The following is an analysis of the main disadvantages: Large computational load: The CFAR algorithm has a very large amount of computation in radar signal processing. Especially when processing a large number of data points, the CPU in the PS may not be able to complete the CFAR processing in real time, resulting in processing delays or failure to meet real-time requirements. This may cause missed detection of targets or increase false alarm rates in target detection systems. Limited data throughput: The data transmission rate in the PS is lower than that in the PL part. When processing high-throughput data, the PS may become a bottleneck of the system. High latency: CFAR requires sliding window operations, sorting, and comparison of a large amount of input data, which requires a large number of CPU cycles in the PS. If the amount of data is very large or the window is wide, the PS may not be able to complete all calculations under strict real-time requirements, thereby affecting the real-time performance of the overall system. Interrupt processing interference: Multiple tasks may run simultaneously in the PS, resulting in frequent interrupt processing. Since CFAR processing is time-sensitive, frequent interrupts will interfere with the continuity of CFAR processing and increase latency. Resource conflict: CFAR processing in PS consumes a lot of CPU resources and may affect the execution of other tasks, especially in a multi-tasking environment. This resource competition may cause other critical tasks to fail to complete in time, affecting the stability and reliability of the system. Scheduling complexity: Implementing complex algorithms such as CFAR in PS usually requires careful scheduling of other tasks to ensure that the overall performance of the system is not affected. This increases the complexity of software design and may cause difficulties in system debugging and maintenance. Difficulty in algorithm optimization: Although the implementation of CFAR in PS can flexibly adjust parameters and algorithms through software, this flexibility may not be enough to make up for the performance deficiencies in scenarios that pursue extreme performance and real-time performance. At the same time, software optimization is difficult to achieve hardware-level efficiency. Unable to fully utilize the parallel computing capabilities of PL: The CFAR implementation in PS cannot fully utilize the parallel computing capabilities of the PL part of the ZYNQ system, which means that the advantages of the ZYNQ system architecture are not fully utilized. PL has a high degree of parallel processing capabilities and is particularly suitable for implementing large-scale data processing and algorithms with high real-time requirements, such as CFAR.

[0054] Therefore, although the CFAR algorithm implemented in the PS of the ZYNQ system can provide certain flexibility and software programmability, its main disadvantages include performance bottlenecks, lack of real-time performance, high power consumption, resource competition, and lack of flexibility. These disadvantages are particularly prominent in radar systems that have strict requirements on real-time performance and high data throughput.

[0055] Secondly, when a traditional radar system is started, the operating parameters are fixed in the code. In the initialization state, the operating parameters are set by the program in the initialization state. Once the system is started, the functions are fixed and cannot be dynamically updated during operation. This architecture has certain advantages in scenarios with simple and fixed requirements, but when the requirements change or new threats emerge, it is difficult for the system to respond quickly and adjust the functions.

[0056] Although embedding working parameters into embedded programs, that is, writing parameters directly into the code or fixing them in the firmware, can bring convenience in development and deployment in some simple systems, it also has many disadvantages. The following is an analysis of the main disadvantages of embedding working parameters into embedded programs: Unable to adjust dynamically: Once the working parameters in the embedded program are fixed in the code or firmware, any adjustment requires recompiling and burning the firmware. This means that each parameter modification requires updating the entire program, and it is impossible to dynamically adjust according to the actual situation at runtime. Poor environmental adaptability: In actual applications, the system may need to adjust parameters according to changes in test conditions. If the parameters are fixed in the program, the system cannot automatically optimize the operation in different environments, resulting in performance degradation or instability. Extended development cycle: Each parameter adjustment requires rewriting the code, compiling and testing. This not only increases development time, but may also introduce new errors. In addition, frequent firmware updates during multiple debugging processes will increase the burden on developers. High maintenance cost: During the product life cycle, if parameters need to be adjusted or system performance needs to be optimized, the firmware must be recompiled and updated. This may require recall or field upgrades for deployed devices, increasing the complexity and cost of maintenance. Parameter leakage risk: Embedding sensitive working parameters directly into the code may lead to leakage during reverse engineering or memory extraction. If these parameters involve security or critical operations, it may pose a serious security risk. Tampering risk: Embedded parameters may be easily tampered in the firmware, especially when the firmware is cracked or accessed without authorization. Malicious users can modify the parameters, which may affect the normal operation of the system or trigger unexpected behavior. Frequent firmware updates: Every parameter change requires a firmware update, resulting in an increased frequency of system updates. This not only imposes a burden on development and deployment, but may also increase the risk of failure during the firmware update process (such as an update interruption causing the system to fail to start). Complex version management: Frequent firmware updates may complicate version management, especially when the system is deployed in multiple devices or different batches. Different versions of firmware may contain different parameters, which increases the difficulty of management and tracking.

[0057] Although embedding working parameters into embedded programs can provide some convenience in the early stages of development, it brings many problems in terms of flexibility, security, maintainability and system scalability.

[0058] Furthermore, the existing ZYNQ system upgrades commonly use two solutions: fsbl upgrade and uboot upgrade. UBOOT is usually used for RTOS (real-time operating system) and Linux system upgrade program solutions. FSBL is used for bare metal program upgrade solutions. The upgrade file can be stored on an external storage device, such as an SD card, USB storage device, or obtained through a network (such as TFTP).

[0059] FSBL usually includes the following parts: Hardware initialization: After execution, FSBL will first initialize basic hardware resources, such as DDR memory, clock, PLL, serial port, etc. Boot process: After completing hardware initialization, FSBL will load the second-stage boot program (such as U-Boot) from a predetermined storage device (such as SD card, eMMC, QSPI Flash, etc.) or directly load the operating system kernel. Upgrade logic: Firmware upgrade logic can be embedded in FSBL to trigger firmware update operations under specific conditions.

[0060] In the existing upgrade method, after the ZYNQ system is powered on, the boot rom will be run first, and the fsbl part will be loaded and run. Fsbl will load the bitsteam configuration from the flash to the PL. After completion, it will detect whether there is an upgrade mark. Whether the upgrade mark is valid is the condition for triggering the upgrade. The existing solutions generally have the following methods: External trigger: The upgrade mode can be triggered by setting a specific hardware signal (such as GPIO) or pressing a certain button at startup. Software trigger: Write logic in FSBL to detect a flag bit (such as a flag stored in EEPROM or Flash). If the flag bit indicates that an upgrade is required, the upgrade process will be entered. Automatic detection: FSBL can automatically detect whether there is a new upgrade file in the storage device at each startup, and if so, it will automatically enter the upgrade process.

[0061] The existing FSBL upgrade program can only be triggered and upgraded through the PS-side peripherals, and its disadvantages are as follows: Dependence on the PS-side peripheral storage device. On the PS side, the upgrade trigger of FSBL usually depends on external storage devices (such as EEPROM, Flash) or GPIO pins. In some systems that lack PS peripherals, the upgrade process will not be triggered correctly, so the existing solution has certain limitations. If the PS peripheral (such as Flash memory) fails during the upgrade process, it may cause the upgrade to fail or the system to crash. This situation is especially dangerous when FSBL needs to write to the peripherals through the PS side, because once the PS peripheral fails to respond correctly, the entire system may not be able to recover. When upgrading the image at the FSBL stage, if an abnormality occurs (such as power failure or write error), the current firmware image may be destroyed, causing the system to fail to start. This is a particularly important risk in the single-image upgrade solution, because there is usually no backup image to roll back. The entire product will become a "brick", and the risk factor is extremely high. In the single-image upgrade solution, FSBL usually does not support complex multi-image management functions (such as automatic rollback, image version control). This means that after an upgrade failure, the system has limited ability to recover and requires manual intervention or redeployment of the image.

[0062] In view of the discovery of the above problems, the present embodiment provides a radar signal processing system and method, which can be used to perform AD sampling, data preprocessing, pulse compression, fast Fourier transform and CFAR detection on the received radar echo signal through a field programmable gate array to obtain a target radar echo signal. The first processor is used to divide the target radar echo signal into a first target radar echo signal and a second target radar echo signal, and send the second target radar echo signal to the second processor. The target is identified based on the first target radar echo signal to obtain a first identification result. The second processor is used to receive the first identification result, and the target is identified based on the second target radar echo signal to obtain a second identification result. The first identification result and the second identification result are merged to obtain a final detection result, which can improve the efficiency of radar signal processing. The scheme provided in the present embodiment is elaborated in detail below.

[0063] Please refer to Figure 2 , Figure 2 For application Figure 1 A structural diagram of a radar signal processing system of an electronic device 100 is shown, and the method including various steps is described in detail below.

[0064] The radar signal processing system includes: an ARM processor 1 and a field programmable gate array 2, the ARM processor includes a first processor 11 and a second processor 12; the field programmable gate array 2 is used to perform AD sampling, data preprocessing, pulse compression, fast Fourier transform and CFAR detection on the received radar echo signal to obtain a target radar echo signal; the first processor 11 is used to divide the target radar echo signal into a first target radar echo signal and a second target radar echo signal, send the second target radar echo signal to the second processor, perform target identification based on the first target radar echo signal, and obtain a first identification result; the second processor 12 is used to receive the first identification result, perform target identification based on the second target radar echo signal, and obtain a second identification result, and fuse the first identification result and the second identification result to obtain a final detection result.

[0065] The present invention concentrates data preprocessing, pulse compression, FFT and CFAR functions on the field programmable gate array. These functions are implemented by hardware acceleration in the field programmable gate array part of the processor of the ZYNQ system, thereby significantly improving the computing efficiency. The field programmable gate array can efficiently perform computationally intensive tasks such as pulse compression, FFT (Fast Fourier Transform), CFAR operations, etc., reducing the burden on the ARM processor while improving real-time processing capabilities.

[0066] The CFAR result of the field programmable gate array is divided into half and input into the first processor, and the other half is input into the second processor. The first processor and the second processor simultaneously perform target detection and target recognition according to the CFAR result and output the result.

[0067] The dual-core processing power can be used to the maximum extent, ensuring the stability of the system in high target density scenarios.

[0068] The radar signal processing system provided by the present invention fully utilizes the dual-core processing capability of the ZYNQ system and the hardware acceleration characteristics of the programmable logic part to achieve efficient and flexible radar signal processing and target recognition.

[0069] The first processor, the second processor and the field programmable gate array can achieve efficient data transmission and sharing by utilizing the high-bandwidth on-chip interconnect and fast memory access technology of the ZYNQ system, thereby further improving the overall performance of the system.

[0070] Placing the CFAR algorithm in the field-programmable gate array part for processing can bring many system optimization advantages, especially in terms of real-time performance, resource management, and flexibility. The following are the main advantages: Low latency: The field-programmable gate array implements the CFAR algorithm based on hardware, which can achieve extremely low processing latency. This is crucial for real-time radar signal processing, because in radar systems, real-time directly affects the accuracy of target detection and tracking. High parallel processing capability: PL is able to process large amounts of data in parallel, which means that the CFAR algorithm can run simultaneously on multiple data channels, thereby improving overall processing efficiency and response speed.

[0071] Resource allocation optimization: Moving the CFAR algorithm to the FPGA can significantly reduce the computational burden on the ARM processor. This allows the ARM processor to focus on other critical tasks, such as high-level data analysis, system control, and user interface, thereby improving the overall performance of the system. Improve system stability: By moving computationally intensive tasks such as CFAR to the FPGA, the ARM processor can run stably without being affected by high loads, which helps improve system stability and reliability.

[0072] Dedicated hardware acceleration: FPGAs can accelerate the CFAR algorithm through hardware, thereby improving processing efficiency and throughput. Hardware-implemented algorithms can usually process data faster and handle more data streams than software-implemented algorithms. Optimized resource usage: FPGAs can be optimized for the specific needs of the CFAR algorithm, using the optimal configuration of hardware resources to reduce computing time and resource consumption.

[0073] Algorithm customization: FPGA allows hardware-level customization and optimization of the CFAR algorithm according to specific needs. This customization capability can make the CFAR algorithm better suited to specific application scenarios and performance requirements. Fast iteration: Modification and optimization of the CFAR algorithm in the FPGA can be achieved by reprogramming the hardware, which allows fast iteration and testing of different algorithm versions without changing the PS code or recompiling the entire system.

[0074] Large bandwidth data processing: The hardware architecture of the FPGA can handle high-bandwidth data streams, which is especially important for CFAR algorithms that need to process large amounts of radar data. The parallel processing capabilities of the FPGA can effectively handle high data rate signal streams.

[0075] Reduce the impact of software failures: Moving key algorithms to hardware can reduce system stability issues caused by software failures. Field programmable gate array hardware implementations can provide higher reliability because hardware implementations are generally less prone to errors than software implementations.

[0076] Placing the CFAR algorithm on a field programmable gate array can significantly improve the system's real-time performance, processing efficiency and stability, while reducing the computational burden of the ARM processor and providing greater flexibility and optimization space. This hardware acceleration solution is particularly valuable for radar systems that require high performance, low latency and high reliability.

[0077] like Figure 3 As shown, it is a schematic diagram of a non-volatile memory, wherein the non-volatile memory stores a first mirror program and a second mirror program, wherein the first mirror program is stored in a first data block, and the second mirror program is stored in a second data block, the first data block is a data block with a front storage address, and the second data block is a data block with a back storage address, the first mirror program is a program to be upgraded, and the second mirror program is an upgrade program of the first mirror program.

[0078] Exemplarily, the first image program consists of Fsbl.elf, USER.bit, PS0.elf, and PS1.elf. Fsbl.elf is the first file, USER.bit is the second file, PS0.elf is the third file, and PS1.elf is the fourth file. The second image program consists of Fsbl2.elf, USER2.bit, and PS0_2.elf. The first image program is the program to be upgraded. The second image program is a program that will not be modified, receives serial port instructions and data, and writes them into the non-volatile memory to complete the upgrade.

[0079] Fsbl.elf is an important executable file on the ZYNQ system, and its full name is the first-stage boot loader. It is responsible for initializing the hardware, loading and running the second-stage boot loader (such as U-Boot) or directly loading the operating system kernel. USER.bit is a bitstream file in the FPGA project, which contains all the information required to configure the FPGA. This file is generated by Vivado Design Suite or other Xilinx tools and is used to load the design logic into the FPGA. The USER.bit file contains all the necessary configuration information for initializing the logic units, routing resources, etc. of the FPGA. The PS0.elf file is usually an executable file for the ZYNQ system. It represents a part of the ARM processor. Specifically, PS0.elf usually refers to an application running on one core of a dual-core ARM processor. The PS1.elf file is usually an executable file for the ZYNQ system, similar to PS0.elf, but it is generated by another core in the ARM processor. Specifically, in a dual-core ARM processor, PS0.elf and PS1.elf correspond to different cores, namely the first processor and the second processor.

[0080] When upgrading, Figure 4 As shown, the following steps are included:

[0081] S101: The radar signal processing system is used to load the first file and the second file in sequence.

[0082] S102: When it is detected that the serial port of the field programmable gate array receives an update signal, a second image program is loaded to update the first image program.

[0083] During the startup of the first image program, when it is detected that the serial port of the field programmable gate array receives an update signal sent by the host computer or the computer, the second image program is loaded. After the second image program is loaded, the update information sent by the computer is received, and the update information indicates an update program package of the first image program. The first processor updates the first image program based on the update program package, and overwrites the first image program stored in the non-volatile memory with the updated first image program.

[0084] The present invention sets a first mirror program and a second mirror program. When the first mirror program needs to be upgraded, the first mirror program is not directly upgraded and covered, but the second mirror program is loaded, and the first mirror program is upgraded and covered based on the second mirror program, thereby avoiding that when there is only the first mirror program, when the first mirror program is written incorrectly or is not completed, the first mirror program is damaged, resulting in the inability to load the first mirror program when the radar signal processing system is powered on again, resulting in the radar signal processing system being unable to be used normally.

[0085] S103: When it is not detected that the serial port of the field programmable gate array receives an update signal, load the third file and the fourth file in sequence.

[0086] Combining the multi-image upgrade solution with field programmable gate array as a trigger condition can bring several significant advantages, especially in terms of system flexibility, real-time and reliability. The following are the main advantages:

[0087] Low-latency triggering: The hardware triggering mechanism of the FPGA can achieve extremely low triggering latency. This is especially important for upgrade operations that require fast response, ensuring that the system can quickly start the upgrade process after receiving the trigger signal. High parallel processing capability: The FPGA can process multiple trigger signals in parallel, which enables the system to handle multiple upgrade tasks or conditions at the same time, improving overall processing efficiency.

[0088] Reduced processing burden: By transferring the trigger condition processing from the ARM processor to the FPGA, the computing resources of the ARM processor part can be focused on other key tasks, such as system control, data processing, and user interface. This resource allocation optimization can improve the overall performance of the system. Improved system stability: The independence of the FPGA can reduce the burden on the ARM processor in processing the upgrade trigger process, reducing system stability issues caused by ARM processor overload or failure.

[0089] Custom trigger conditions: The FPGA part allows the design and implementation of various custom trigger conditions, which can be optimized and adjusted according to specific needs. Compared with the fixed ARM processor peripheral trigger, the FPGA provides greater flexibility to meet the needs of specific applications. Support multiple communication protocols: The FPGA can implement multiple communication protocols and support complex trigger logic, which makes the upgrade trigger mechanism adaptable to different application scenarios and needs.

[0090] Hardware-level isolation: The FPGA and ARM processor parts are physically and logically independent, and the trigger conditions processed by the FPGA can isolate potential security risks. This hardware isolation helps prevent unauthorized triggers or malicious attacks from affecting the core parts of the system. Enhanced security measures: The FPGA part can implement hardware-based security measures such as signal encryption and authentication to ensure the authenticity and integrity of the trigger signal and improve the overall security of the system.

[0091] Separation of trigger and upgrade logic: Separating the trigger condition processing and upgrade logic can make the system design more modular and efficient. The FPGA is responsible for the trigger part, and the FSBL is responsible for the upgrade logic, which simplifies the system design and optimizes resource management. Reduce storage pressure: Since the FPGA handles the trigger mechanism, the FSBL can focus on handling the upgrade task, thereby reducing the demand for storage space and avoiding the pressure of complex trigger logic on storage.

[0092] Fast iteration: The hardware design of the FPGA part can be quickly iterated and updated, allowing the system to adapt to changing needs and environments. By quickly adjusting the FPGA trigger logic, flexible configuration and maintenance can be performed during system operation. Simplified maintenance: The FPGA handles the trigger conditions, which can simplify the maintenance of the ARM processor part, making system maintenance more efficient and convenient.

[0093] Combining the FSBL multi-image upgrade solution with the field programmable gate array as a trigger condition can significantly improve the system's real-time performance, flexibility, security, and resource management efficiency. This solution can effectively improve the overall performance and stability of the system by reducing the burden on the ARM processor, supporting custom trigger logic, and optimizing storage and resource management.

[0094] Compared with the existing static fixed architecture, the present invention provides stronger system expansion capability and adaptability, can respond quickly to new threats or mission changes, and has higher system stability.

[0095] like Figure 5 As shown, the non-volatile memory also stores operating parameter information. The operating parameter information includes operating parameter information of each component in the radar signal processing system and operating parameter information of each operating program.

[0096] When calling the working parameter information, such as Figure 6 As shown, the following steps are included:

[0097] S201: Loading operating parameter information from a non-volatile memory.

[0098] S202: The field programmable gate array is further used to configure the working state based on the first parameter information in the working parameter information.

[0099] S203: The ARM processor is further configured to perform working state configuration based on the second parameter information in the working parameter information.

[0100] Load the operating parameter information from the non-volatile memory, and configure the field programmable gate array and the ARM processor based on the operating parameter information, that is, initialize the field programmable gate array and the ARM processor based on the operating parameter information, such as Figure 5 The parameter area in the non-volatile memory will store waveform parameters, radar parameters, detection and recognition model parameters, etc. When used in the working state, it needs to be configured to each module.

[0101] When modifying the working parameters in the program, such as Figure 7 As shown, the following steps are included:

[0102] S301: When a first instruction for modifying a working parameter is received, loading working parameter information in a non-volatile memory is acquired based on the first instruction, and the loading working parameter information in the non-volatile memory is modified to obtain a first parameter.

[0103] S302: Determine a target data segment in the working program based on the first parameter.

[0104] S303: Modify the target data segment based on the first parameter.

[0105] When receiving a first instruction from a host computer or computer to modify the working parameters in a program, the working parameter information is loaded from a non-volatile memory, and the working parameter information loaded in the non-volatile memory is modified based on the first instruction to obtain a first parameter. The program corresponding to the first parameter is modified accordingly, that is, the target data segment is modified.

[0106] When the operating parameter information stored in the non-volatile memory is modified, the operating parameter information may be modified based on the modification instruction, and the modified operating parameter information may be rewritten into the non-volatile memory.

[0107] The working parameter information and working code of the present invention, namely the mirror program, the working parameters and the code are respectively stored in different data blocks of the non-volatile memory. After the device is powered on, the program is loaded and then the working parameter information is loaded. The working parameter information can be modified through the external serial port.

[0108] The present invention separates the working parameter information from the program and stores it in a non-volatile memory, and quickly modifies and updates it through a serial port. This approach brings several significant advantages:

[0109] Dynamic adjustment: Operating parameters are stored in non-volatile memory and modified through the serial port, allowing the system to dynamically adjust parameters while running. This flexibility enables the system to quickly adjust parameters to optimize performance in different operating environments or application scenarios. Simplified testing and verification: During the testing and verification phase, updating parameters in non-volatile memory through the serial port can quickly implement new settings and configurations, thereby speeding up the test cycle and verification process without recompiling and burning programs.

[0110] Reduce the number of reprogramming times: After separating the parameters from the program, when updating the firmware, you only need to focus on the program itself, rather than frequently updating and adjusting the parameters. This reduces the impact on system stability and performance during each firmware update, and reduces potential problems caused by parameter adjustments. Reduce the number of flash writes: Because the parameters are separated from the program, the firmware update of the program does not need to be frequently written to the non-volatile memory, which can reduce the number of erase and write times of the non-volatile memory, thereby extending the service life of the non-volatile memory.

[0111] Easy maintenance and upgrade: Storing operating parameter information in non-volatile memory and supporting updates via the serial port makes system maintenance more efficient. Maintenance personnel can quickly adjust parameters without complex firmware modifications or reprogramming.

[0112] Separation of code and data: By stripping parameters from the program, the management of code and data is optimized, so that the program code remains concise and parameter management is more centralized. This separation can simplify the process of program development and debugging. Reduce program complexity: By moving adjustable parameters to non-volatile memory, the program itself can remain concise and stable. This can reduce the complexity of the program code, reduce the possibility of bugs, and improve the reliability of the system.

[0113] Avoid accidental modification: Storing working parameter information in non-volatile memory and updating it through the serial port can set appropriate permissions and verification mechanisms to avoid unauthorized modifications, thereby improving the security of the system. Rollback and recovery: In some cases, if the new parameter configuration causes system instability, the system can be restored to normal operation by reloading the previous parameter configuration. This capability is very important for system stability.

[0114] Accelerate the development cycle: During the prototype development phase, dynamically modifying the operating parameter information in the non-volatile memory through the serial port can quickly test different configurations and settings. This ability to quickly iterate helps accelerate the development process and optimize the design.

[0115] The present invention also provides a radar signal processing method, and the radar echo signal is detected through the radar signal processing system.

[0116] In the embodiments provided by the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0117] In addition, each functional module in each embodiment of the present invention can be integrated together to form an independent part, or each module can exist separately, or two or more modules can be integrated to form an independent part. If the function is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program code.

[0118] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0119] The above are only various embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A radar signal processing system, characterized in that: The radar signal processing system comprises: an ARM processor and a field programmable gate array, wherein the ARM processor comprises a first processor and a second processor; The field programmable gate array is used to perform AD sampling, data preprocessing, pulse compression, fast Fourier transform and CFAR detection on the received radar echo signal to obtain the target radar echo signal; The first processor is used to divide the target radar echo signal into a first target radar echo signal and a second target radar echo signal, send the second target radar echo signal to the second processor, perform target recognition based on the first target radar echo signal, and obtain a first recognition result; The second processor is used to receive the first recognition result, perform target recognition based on the second target radar echo signal to obtain a second recognition result, and fuse the first recognition result and the second recognition result to obtain a final detection result.

2. The system according to claim 1, characterized in that The radar signal processing system also includes a non-volatile memory; The non-volatile memory stores a first mirror program and a second mirror program, wherein the first mirror program is stored in a first data block, and the second mirror program is stored in a second data block, the first data block is a data block with a front storage address, and the second data block is a data block with a back storage address, the first mirror program is a program to be upgraded, and the second mirror program is an upgrade program of the first mirror program.

3. The system according to claim 2, characterized in that The first mirror program includes a first file, a second file, a third file and a fourth file, the first file is a startup program of the radar signal processing system, the second file is a startup program of a field programmable gate array, the third file is a startup program of the first processor, and the fourth file is a startup program of the second processor; The radar signal processing system is used to load the first file and the second file in sequence; When it is detected that the serial port of the field programmable gate array receives an update signal, the second mirror program is loaded to update the first mirror program.

4. The system according to claim 3, characterized in that The radar signal processing system is further configured to: load the third file and the fourth file in sequence when it is not detected that the serial port of the field programmable gate array receives an update signal.

5. The system according to claim 3, characterized in that The radar signal processing system is also used to: load the second mirror program when detecting that the serial port of the field programmable gate array receives an update signal, receive update information sent by a computer, and update the first mirror program based on the second mirror program and the update information.

6. The system according to claim 2, characterized in that The non-volatile memory also stores operating parameter information of the radar signal processing system.

7. The system according to claim 6, characterized in that The ARM processor and the field programmable gate array are also used for: Loading the operating parameter information from the non-volatile memory; The field programmable gate array is further used to configure the working state based on the first parameter information in the working parameter information; The ARM processor is also used to perform working state configuration based on the second parameter information in the working parameter information.

8. The system according to claim 6, characterized in that When the radar signal processing system receives a first instruction to modify a parameter in operation, the radar signal processing system obtains the operating parameter information loaded in the non-volatile memory based on the first instruction, and modifies the operating parameter information loaded in the non-volatile memory to obtain a first parameter; determining a target data segment in a working procedure based on the first parameter; The target data segment is modified based on the first parameter.

9. The system according to claim 6, characterized in that When the radar signal processing system receives a modification instruction for loading the operating parameter information in the non-volatile memory, the radar signal processing system modifies the operating parameter information based on the modification instruction and rewrites the modified operating parameter information into the non-volatile memory.

10. A radar signal processing method, characterized in that: The radar echo signal is detected by the radar signal processing system according to any one of claims 1 to 9.

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