Molecular clock, manufacturing method thereof and electronic equipment

Abstract

The invention provides a molecular clock, a manufacturing method thereof and electronic equipment, an oscillator can be manufactured in a first film layer structure of a source chip through a micro electro mechanical system processing technology, a molecular waveguide structure can be manufactured in a second film layer structure of a waveguide chip, the size of the oscillator and the size of the molecular waveguide structure can reach the chip level, and the size of the molecular clock is reduced. Compared with an oscillator and a molecular waveguide structure manufactured in the prior art, the size of the molecular clock is reduced, so that the size of the molecular clock is reduced, and the problem that the size of the molecular clock is large due to the fact that the sizes of the molecular waveguide structure and the oscillator are large in the prior art is solved.

Description

Technical Field

[0001] The present application relates to the field of time and frequency technology, and in particular to a molecular clock, a manufacturing method thereof, and an electronic device. Background Art

[0002] In terms of high-performance clock benchmarks, existing technologies mainly include atomic clocks, molecular clocks and oscillators. Molecular clocks generally include: external oscillators, high-frequency generation circuits, high-frequency receiving circuits, low-frequency processing circuits and molecular waveguide structures. Among them, molecular waveguide structures are generally made of metal materials through high-precision machining, and are generally large in size, in the range of cm. 3 The external oscillator is usually made of a quartz crystal encapsulated in a ceramic tube, which is generally large in size. This results in a large overall size of the molecular clock. Therefore, how to reduce the size of the molecular clock has become an urgent problem to be solved. Summary of the invention

[0003] The present application provides a molecular clock, a manufacturing method thereof and an electronic device, which are used to reduce the volume of the molecular clock.

[0004] In the first aspect, the embodiment of the present application provides a molecular clock, which may include: a source chip, a processing chip and a waveguide chip, the source chip includes: a first substrate, a first film layer structure arranged on the first substrate and an oscillator, the oscillator is arranged in the first film layer structure; the waveguide chip includes: a second substrate, a second film layer structure arranged on the second substrate and a molecular waveguide structure, the molecular waveguide structure is arranged in the second film layer structure, and the molecular waveguide structure includes an inlet and an outlet; the oscillator is used to provide a source signal (such as a clock signal) to the processing chip, the processing chip processes the source signal into a corresponding first radio frequency signal and then transmits it to the inlet of the molecular waveguide structure, so that the first radio frequency signal is transmitted in the molecular waveguide structure, and the processing chip then receives the second radio frequency signal output from the outlet of the molecular waveguide structure from the outlet of the molecular waveguide structure, and can process the second radio frequency signal and output a clock signal with a fixed period and a stable phase, thereby realizing the function of the molecular clock. The clock signal can be a sine wave signal, a square wave signal or other forms of signal, which are not limited here.

[0005] Among them, the manufacturing materials of the first substrate and the second substrate can be the same or different, as long as the materials can realize the function of the substrate, they can be applicable in this application; the first film layer structure and the second film layer structure can both include multiple conductive layers and multiple dielectric layers, so that an oscillator can be manufactured in the first film layer structure through micro-electromechanical system processing technology, and a molecular waveguide structure can be manufactured in the second film layer structure, so that the volume of the oscillator and the molecular waveguide structure can reach the chip level, compared with the oscillator and molecular waveguide structure manufactured in the prior art, the volume can be effectively reduced, thereby reducing the volume of the molecular clock, so that the volume of the molecular clock is tens of mm 3 Even a few mm 3 , which solves the problem in the prior art that the molecular clock has a large volume due to the large volume of the molecular waveguide structure and the oscillator.

[0006] Further explanation: the period and phase of the clock signal output by the oscillator are unstable, which may be due to the influence of factors such as the ambient temperature of the oscillator, the fluctuation of the external power supply received, and electronic interference. If timing is performed based on this, it may lead to inaccurate timing. By processing the chip and the molecular waveguide structure, the frequency and phase of the clock signal output by the oscillator can be adjusted, and a clock signal with a fixed period and stable phase can be output, thereby improving the stability and accuracy of the output clock signal, so that the timing accuracy can be effectively improved when timing is performed based on the clock signal. In addition, polar gas molecules, such as but not limited to polar gas molecules such as ammonia and carbonyl sulfide, can be provided in the molecular waveguide structure, and the gas pressure in the molecular waveguide structure can be set to 0.1Pa to 50Pa. When the first radio frequency signal propagates in the molecular waveguide result, the polar gas molecules absorb the energy of the first radio frequency signal. When the center frequency of the first radio frequency signal is close to the center frequency of the molecular rotation spectrum, the polar gas molecules absorb the most energy, resulting in the energy of the second radio frequency signal emitted from the molecular waveguide structure reaching the lowest. The processing chip can obtain the frequency and phase of the second radio frequency signal with the lowest energy transmitted from the molecular waveguide structure, and compare it with the reference signal with the reference frequency and reference phase to calculate the deviation signal, and then adjust the frequency and phase of the clock signal output by the oscillator based on the deviation signal, so that the clock signal output by the molecular clock has a fixed period and a stable phase, realizing the function of the molecular clock. Therefore, the energy of the first radio frequency signal and the second radio frequency signal is different, and the energy of the first radio frequency signal is higher than the energy of the second radio frequency signal.

[0007] It should be understood that the source chip may include other structures besides the oscillator. Similarly, the waveguide chip may include other structures besides the molecular waveguide structure. The other structures in the source chip and the waveguide chip may be configured according to actual conditions and are not limited here.

[0008] Exemplarily, the source chip, the processing chip and the waveguide chip can be stacked, or the source chip and the processing chip are both arranged on the surface of the waveguide chip, and then the source chip, the processing chip and the waveguide chip are packaged, so as to further reduce the volume of the molecular clock. Specifically, the arrangement and packaging methods may include the following:

[0009] The first type: the source chip, processing chip and waveguide chip can be stacked, which can make full use of the space in the thickness direction of the chip, thereby reducing the occupied area of ​​the molecular clock, further reducing the volume of the molecular clock, and also improving the centralization of the molecular clock. Among them, when stacking, there can be the following stacking methods:

[0010] Stacking method 1: The processing chip is arranged between the source chip and the waveguide chip, and the processing chip is respectively arranged in contact with the waveguide chip and the source chip, wherein the processing chip, the source chip and the waveguide chip have no electrical connection relationship at the position where they contact each other, and the source chip and the processing chip are electrically connected through a wire, thereby reducing the height of the molecular clock.

[0011] Stacking method 2: The processing chip is arranged between the source chip and the waveguide chip, the processing chip and the waveguide chip are arranged in contact with each other without electrical connection, there is a certain gap between the source chip and the processing chip, a first connection pad is arranged on the surface of the source chip facing the processing chip, and a second connection pad is also arranged on the surface of the processing chip facing the source chip, the first connection pad of the source chip and the second connection pad of the processing chip are arranged one by one, a solder ball is arranged between the first connection pad of the source chip and the second connection pad of the processing chip, the source chip and the processing chip are electrically connected through the solder ball, wherein the solder ball can not only play a role of electrical connection, but also play a role of fixing, fixing the source chip on the surface of the processing chip, and avoiding the relative position between the source chip and the processing chip from shifting.

[0012] Stacking method 3: The source chip is arranged between the processing chip and the waveguide chip. When the area of ​​the processing chip is larger than that of the source chip, since the area of ​​the source chip arranged in the middle is smaller, a support structure can be arranged on the side of the processing chip facing the waveguide chip. The support structure can maintain a gap between the processing chip and the waveguide chip, provide a storage space for the source chip, reduce the pressure of the processing chip on the source chip, and thus avoid adverse effects on the performance of the oscillator in the source chip. Among them, a plurality of support structures can be arranged, and each support structure can be dispersed at various positions on the surface of the processing chip to balance the support force of each support structure on each position in the processing chip, avoid a certain position in the processing chip being subjected to a smaller support force, and a certain position being subjected to a larger support force, thereby maintaining the stability of the processing chip. In addition, each support structure can include: a support pad and a support column, the support pad is arranged on the surface of the chip, and the support column is arranged between two support pads. Taking one of the support structures disposed between the processing chip and the waveguide chip as an example, a support pad (which may be referred to as a first support pad) is disposed on the surface of the processing chip facing the waveguide chip, and a support pad (which may be referred to as a second support pad) is disposed on the surface of the waveguide chip facing the processing chip. A support column is disposed between the first support pad of the processing chip and the second support pad of the waveguide chip, so as to prevent the support column from causing damage to the chip. Of course, the support structure may also not include a support pad, in which case the contact surface between the support structure and the chip may be specially treated, such as but not limited to increasing the area of ​​the contact surface, etc., to reduce damage to the chip surface caused by the contact surface.

[0013] Furthermore, when the source chip is respectively arranged in contact with the waveguide chip and the processing chip, each support structure is arranged between the processing chip and the waveguide chip, which can not only reduce the height of the molecular clock, and thus reduce the volume of the molecular clock, but also prevent the source chip from being subjected to greater pressure, wherein the processing chip, the source chip and the waveguide chip have no electrical connection relationship at the position where they contact each other, and the source chip is electrically connected to the processing circuit through a wire. Alternatively, when the processing chip and the source chip are arranged non-contactingly, and the source chip and the waveguide chip are arranged non-contactingly, that is, there is a certain gap between the processing chip and the source chip, and there is also a certain gap between the source chip and the waveguide chip, each support structure is arranged between the processing chip and the waveguide chip, and connection pads are arranged on the source chip and the processing chip, and solder balls are arranged between the connection pads of the source chip and the connection pads of the processing chip, and they are electrically connected and fixed through the solder balls. Alternatively, when the processing chip and the source chip are arranged in non-contact, and the source chip is arranged on the surface of the waveguide chip so that the source chip and the waveguide chip are arranged in contact, when all the supporting structures are divided into at least one first supporting structure and at least one second supporting structure, each first supporting structure can be arranged between the source chip and the processing chip, and a gap can be maintained between the source chip and the processing chip through the first supporting structure, and the second supporting structure can be arranged between the processing chip and the waveguide chip to maintain a gap between the processing chip and the waveguide chip. In addition, at least part of the first supporting structure can be made of conductive material with supporting capacity, so as to facilitate the electrical connection between the processing chip and the source chip, and then the source signal provided by the oscillator of the source chip can be transmitted to the processing chip to realize the function of the molecular clock. Alternatively, a groove may be provided on the surface of the waveguide chip facing the source chip, the source chip may be provided in the groove, and the processing chip and the source chip are provided in a non-contact manner. In this case, the first support structure is provided between the source chip and the processing chip, and at least part of the first support structure electrically connects the source chip and the processing chip, and the second support structure is provided between the processing chip and the waveguide chip, so that the height of the molecular clock can be effectively reduced, thereby further reducing the volume of the molecular clock. The support structure can be made of an insulating material or a conductive material with supporting capacity, and can be specifically provided according to the location of the installation and the function to be achieved, and is not strictly required here.

[0014] Of course, in the first packaging method mentioned above, in addition to the above three stacking methods, other stacking methods can also be used, such as but not limited to the waveguide chip being arranged between the source chip and the processing chip. As long as the processing chip, source chip and waveguide chip are stacked and arranged in a manner that satisfies the requirements, they are all within the protection scope of the embodiments of the present application.

[0015] The second type: the source chip and the processing chip are both arranged on the surface of the waveguide chip, and the source chip and the processing chip can be connected by wires, which can effectively reduce the height of the molecular clock, thereby further reducing the volume of the molecular clock, and can also improve the centralization of the molecular clock. Among them, if the function of the processing chip is to be realized, it can generally include a processing circuit, a signal transmitter and a signal receiver, and the processing circuit, the signal transmitter and the signal receiver can all be arranged in the same chip to form a processing chip, which can increase the degree of integration of the circuit, thereby improving the degree of integration of the molecular clock. Alternatively, when the processing chip includes a first chip and a second chip both arranged on the surface of the waveguide chip, the first chip includes a signal transmitter, and the second chip includes a signal receiver, the source chip can be arranged between the first chip and the second chip, or arranged at other positions, as long as the source chip, the first chip and the second chip are all arranged on the waveguide chip. Furthermore, the processing chip may generally include: a signal transmitter, a signal receiver, and a processing circuit, etc. The processing circuit is electrically connected to the oscillator, the signal transmitter, and the signal receiver, respectively. Therefore, when the processing circuit is provided in the first chip, the oscillator in the source chip is electrically connected to the processing circuit in the first chip; when the processing circuit is provided in the second chip, the oscillator in the source chip is electrically connected to the processing circuit in the second chip. Of course, a part of the processing circuit may be provided in the first chip, and another part of the processing circuit may be provided in the second chip. In this case, the processing circuit in the first chip is electrically connected to the processing circuit in the second chip, thereby realizing the function of the processing circuit.

[0016] In summary, the first or second method mentioned above can be used to package the source chip, processing chip and waveguide chip, so that the molecular clock can be highly integrated through semiconductor packaging technology, making the volume of the entire molecular clock within mm 3 The order of magnitude reaches the chip-level volume. Of course, in actual situations, other packaging methods can also be used to package the source chip, processing chip and waveguide chip, which can be designed according to actual needs and are not limited here. It should be understood that when making source chips, processing chips and waveguide chips, taking the source chip as an example, it is usually possible to make multiple chips on a wafer that are deployed in an array and have the function of a source chip, and the wafer with multiple chips is cut. Each chip after cutting is a source chip. At this time, the source chip can be called a die-level chip, and the wafer with multiple chips before cutting can be called a wafer-level chip. Therefore, when stacking the source chip, processing chip and waveguide chip, it can be a stack of die-level chips, or a stack of wafer-level chips, or a stack of die-level chips and wafer-level chips, but which of the source chip, processing chip and waveguide chip is a die-level chip and which is a wafer-level chip can be designed according to actual conditions and is not required here.

[0017] Exemplarily, the signal transmitter may include but is not limited to a transmitting antenna, and the signal receiver may include but is not limited to a receiving antenna. The first radio frequency signal may be transmitted through the transmitting antenna so that the first radio frequency signal enters the molecular waveguide structure, and the receiving antenna may receive the second radio frequency signal transmitted from the molecular waveguide structure. Among them, the transmitting antenna may be arranged at the entrance of the molecular waveguide structure so that the first radio frequency signal may enter the molecular waveguide structure through the transmitting antenna, and the receiving antenna may be arranged at the exit of the molecular waveguide structure so that the receiving antenna may effectively receive the second radio frequency signal transmitted from the molecular waveguide structure, thereby realizing the function of the molecular clock. It should be understood that the specific implementation of the transmitting antenna and the receiving antenna may be any structure that can realize the transmission and reception of radio frequency signals, and no strict requirements are made here.

[0018] In a possible implementation, the processing circuit may include: a first frequency increase processor, a second frequency increase processor, an error detector, a frequency divider and an adjustment module. The first frequency increase processor may be connected between a signal transmitter and an adjustment module, the second frequency increase processor may be connected between a signal receiver and an adjustment module, the error detector is connected to the signal receiver and the adjustment module respectively, and the frequency divider is connected to the adjustment module. At this time, in addition to receiving the second RF signal, the signal receiver may also receive a reference signal output from the second frequency increase processor, and perform difference processing on the second RF signal and the reference signal before outputting a deviation signal; wherein, since the reference signal and the first RF signal have different frequencies, and the first RF signal and the second RF signal have the same frequency, the deviation signal between the two may be determined by comparing the second RF signal and the reference signal. The error detector can determine whether the deviation signal is within a preset range. If it is, it means that the frequencies of the two are close and there is no need to adjust the source signal. If it is not, it means that the frequencies of the two are very different and the source signal needs to be adjusted again. Therefore, the adjustment module can make preliminary adjustments to the frequency and phase of the source signal based on the judgment result output by the error detector, and output the source signal after preliminary adjustment to the first frequency increase processor, the second frequency increase processor and the frequency divider converter respectively. The first frequency increase processor performs a first frequency increase processing on the source signal after preliminary adjustment by the adjustment module to generate a first radio frequency signal, so that the center frequency of the first radio frequency signal is close to the center frequency of the rotation spectrum of the polar gas molecules in the molecular waveguide structure; the second frequency increase processor performs a second frequency increase processing on the source signal after preliminary adjustment by the adjustment module to generate a reference signal, so that the frequency of the reference signal is different from the first radio frequency signal, so that the calculated deviation signal is not zero. Of course, the frequencies of the first radio frequency signal and the reference signal can also be set to be the same, so that the calculated deviation signal is zero. It can be designed according to actual conditions and is not strictly required here. When the frequency division converter generates a clock signal according to the adjusted source signal, the adjusted source signal can be further adjusted according to the frequency and phase required by the external device, so that the generated clock signal meets the frequency and phase requirements of the external device for use by the external device. It should be understood that the preset range can be set according to factors such as the adjustment capability of the adjustment module and the accuracy requirements of the clock signal output by the molecular clock, and is not strictly required here.

[0019] The configuration of the adjustment module may include but is not limited to the following three methods:

[0020] The first type: the adjustment module may include: a phase-locked loop, a first fractional frequency divider and a second fractional frequency divider, the phase-locked loop is respectively connected to the oscillator, the first fractional frequency divider, the second fractional frequency divider and the error detector, the first fractional frequency divider is also respectively connected to the first frequency up-conversion processor and the frequency division converter, and the second fractional frequency divider is also connected to the second frequency up-conversion processor. The phase-locked loop can be used to receive the source signal and the judgment result, and according to the judgment result, adjust the frequency and phase of the source signal and then output it. At this time, the adjustment of the frequency by the phase-locked loop can be regarded as the first frequency up-conversion processing of the source signal. After that, the first fractional frequency divider performs the first fractional multiple frequency division processing on the signal output by the phase-locked loop, that is, performs the fractional multiple frequency reduction processing on the frequency of the signal output by the phase-locked loop to achieve fine-tuning of the signal frequency, and then outputs the fine-tuned signal to the first frequency up-conversion processor, and the first frequency up-conversion processor performs the second frequency up-conversion processing on the fine-tuned signal, so that the center frequency of the first radio frequency signal is increased to the center frequency of the rotating spectrum of the polar gas molecules in the molecular waveguide structure. When the frequency of the source signal is relatively small and the center frequency of the rotation spectrum of the polar gas molecules in the molecular waveguide structure is relatively large, the center frequency of the source signal can be increased to the center frequency of the rotation spectrum of the polar gas molecules in the molecular waveguide structure through the processing of the phase-locked loop, the first decimal divider and the first frequency increase processor. The function of the second decimal divider is similar to that of the first decimal divider, both of which perform decimal frequency division processing on the frequency of the adjusted source signal, but the degree of decimal frequency division processing is different, resulting in the frequency of the signal processed by the first decimal divider being different from the frequency of the signal processed by the second decimal divider, thereby achieving the frequency of the first radio frequency signal being different from the frequency of the reference signal. In this way, the preliminary adjustment of the source signal can be achieved, and due to the setting of the first decimal divider and the second decimal divider, the adjustment can be made more accurate, which is conducive to achieving the center frequency of the first radio frequency signal close to the center frequency of the rotation spectrum of the polar gas molecules in the molecular waveguide structure, achieving the adjustment of the source signal based on the molecule, and realizing the function of the molecular clock.

[0021] The second type: the adjustment module may include: a regulator, a first phase-locked loop and a second phase-locked loop, the first phase-locked loop is connected to the first frequency-increasing processor, the regulator and the frequency-dividing converter respectively, the second phase-locked loop is connected to the regulator and the second frequency-increasing processor respectively; the regulator is connected to the error detector and the frequency-dividing converter respectively. The regulator may be arranged inside or outside the oscillator. The regulator may be used to receive the source signal and the judgment result, and according to the judgment result, adjust the frequency and phase of the source signal and output them to the first phase-locked loop, the second phase-locked loop and the frequency-dividing converter respectively, so that the first phase-locked loop can perform the first frequency-increasing adjustment on the frequency of the adjusted source signal and output it to the first frequency-increasing processor, the second phase-locked loop can perform the second frequency-increasing adjustment on the frequency of the adjusted source signal and output it to the second frequency-increasing processor, and the frequency-dividing converter can generate a clock signal based on the adjusted source signal. Among them, the frequency adjustment of the regulator can be regarded as the first frequency adjustment, and the frequency adjustment of the first phase-locked loop and the second phase-locked loop can be regarded as the second frequency adjustment, and the preliminary adjustment of the source signal can be completed by two adjustments. Furthermore, when the frequencies of the first RF signal and the reference signal are different, the difference between the first frequency increase adjustment performed by the first phase-locked loop and the second frequency increase adjustment performed by the second phase-locked loop at least includes a different degree of adjustment of the frequency, so that the frequency of the signal output to the first frequency increase processor is different from that of the signal output to the second frequency increase processor. Of course, if the frequencies of the first RF signal and the reference signal are the same, the degree of adjustment of the frequency in the first frequency increase adjustment performed by the first phase-locked loop and the second frequency increase adjustment performed by the second phase-locked loop can be the same, so that the frequency of the signal output to the first frequency increase processor is the same as that of the signal output to the second frequency increase processor.

[0022] The third type: the adjustment module may include: a first phase-locked loop and a second phase-locked loop, the first phase-locked loop is respectively connected to the error detector, the first frequency-up processor, the oscillator and the frequency-dividing converter, the second phase-locked loop is respectively connected to the error detector, the oscillator and the second frequency-up processor; the frequency-dividing converter is also connected to the first frequency-up processor. At this time, the first phase-locked loop can be used to receive the source signal and the judgment result, and according to the judgment result, the frequency and phase of the source signal are adjusted for the first time and then output to the frequency-dividing converter and the first frequency-up processor respectively; the second phase-locked loop can be used to receive the source signal and the judgment result, and according to the judgment result, the frequency and phase of the source signal are adjusted for the second time and then output to the second frequency-up processor. That is to say, in the third setting mode, only the first phase-locked loop and the second phase-locked loop in the adjustment module adjust the frequency of the source signal, which reduces the number of adjustments and the number of components included in the adjustment module, making the structure of the adjustment module more concise, thereby making the structure of the molecular clock more concise.

[0023] Of course, the structure of the processing chip is not limited to the embodiments described above, and items may be added or removed according to actual conditions. As long as the structure can realize the functions of the processing chip, it belongs to the protection scope of the embodiments of the present application.

[0024] In the second aspect, the embodiment of the present application also provides a method for manufacturing a molecular clock, which can be used to prepare the molecular clock in the first aspect and any possible implementation of the first aspect, and the method for manufacturing the molecular clock can include: forming a source chip, the source chip includes: a first substrate, a first film layer structure arranged on the first substrate and an oscillator, the oscillator is arranged in the first film layer structure; forming a waveguide chip, the waveguide chip includes: a second substrate, a second film layer structure arranged on the second substrate and a molecular waveguide structure, the molecular waveguide structure is arranged in the second film layer structure; the molecular waveguide structure includes an inlet and an outlet; forming a processing chip, the oscillator is connected to the processing chip. In this way, the molecular waveguide structure can be arranged in the second film layer structure of the waveguide chip to reduce the volume of the molecular waveguide structure, and the oscillator can be arranged in the first film layer structure of the source chip, which can also reduce the volume of the oscillator, so that the volume of the oscillator and the molecular waveguide structure reaches the chip level, and the volume is reduced compared with the oscillator and the molecular waveguide structure made in the prior art, thereby reducing the volume of the molecular clock, and solving the problem of the molecular clock having a large volume due to the large volume of the molecular waveguide structure and the oscillator in the prior art.

[0025] Exemplarily, when forming a source chip, the source chip can be made by using, but not limited to, micro-electromechanical system processing technology, that is, the oscillator can be made by using micro-electromechanical system processing technology, so that the oscillator can reach the volume of the chip level, thereby reducing the volume of the molecular clock. Similarly, when forming a waveguide chip, the waveguide chip can be made by using, but not limited to, micro-electromechanical system processing technology, that is, the molecular waveguide structure can be made by using micro-electromechanical system processing technology, so that the molecular waveguide structure can reach the volume of the chip level, thereby reducing the volume of the molecular clock. Among them, the specific process of making the source chip and the waveguide chip can be any process that can make the source chip and the waveguide chip known to those skilled in the art, and will not be described in detail here.

[0026] Furthermore, after the source chip, the processing chip and the waveguide chip are manufactured separately, the source chip, the processing chip and the waveguide chip can be stacked, or the source chip and the processing chip can be arranged on the surface of the waveguide chip, and then packaged using semiconductor packaging technology, so that the molecular clock can be highly integrated through semiconductor packaging technology, so that the volume of the entire molecular clock is less than mm 3 The volume of the chip is of the order of magnitude. When packaging, the specific configuration of the source chip, the processing chip and the waveguide chip can refer to the relevant description in the first aspect above, and the repeated parts will not be repeated.

[0027] In the third aspect, the embodiment of the present application further provides an electronic device, which may include: a circuit board and a molecular clock as described in the first aspect and any possible implementation of the first aspect. Since the molecular clock can reach a chip-level volume, the molecular clock can be arranged on the circuit board, thereby realizing the application of the molecular clock on board-level devices and broadening the application scope of the molecular clock. Among them, since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the aforementioned molecular clock, the implementation and technical effects of the electronic device can refer to the implementation and technical effects of the aforementioned molecular clock, and the repeated parts will not be repeated. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0029] Figure 2 It is a schematic diagram of the structure of a molecular clock in the prior art;

[0030] Figure 3 A schematic diagram of the structure of a molecular clock provided in an embodiment of the present application;

[0031] Figure 4 A schematic diagram of a structure of a packaging method for each chip provided in an embodiment of the present application;

[0032] Figure 5 A schematic structural diagram of another packaging method of each chip provided in an embodiment of the present application;

[0033] Figure 6 A schematic diagram of the structure of a processing circuit provided in an embodiment of the present application;

[0034] Figure 7 A structural schematic diagram of another processing circuit provided in an embodiment of the present application;

[0035] Figure 8 A schematic diagram of the structure of another processing circuit provided in an embodiment of the present application;

[0036] Fig. 9 A schematic structural diagram of another chip packaging method provided in an embodiment of the present application;

[0037] Fig.10 A schematic diagram of a structure of another packaging method of each chip provided in an embodiment of the present application;

[0038] Fig.11 A schematic diagram of a structure of another packaging method of each chip provided in an embodiment of the present application;

[0039] Fig.12A schematic diagram of a structure of another packaging method of each chip provided in an embodiment of the present application;

[0040] Fig.13 A schematic diagram of a structure of another packaging method of each chip provided in an embodiment of the present application;

[0041] Fig.14 A flowchart of a method for making a molecular clock provided in an embodiment of the present application.

[0042] Reference numerals:

[0043] 10-source chip, 11-first substrate, 12-first film layer structure, 13-oscillator, 20-processing chip, 21-third substrate, 22-third film layer structure, 23-processing circuit, 24-signal transmitter, 25-signal receiver, 20a-first chip, 20b-second chip, 30-waveguide chip, 31-second substrate, 32-second film layer structure, 33-molecular waveguide structure, 34-inlet, 35-outlet, 36-groove, 40-wire, 51-connection pad, 52-solder ball, 60-support structure, 61-support pad, 62-support column, 601-first support structure, 602-second support structure, 201-phase-locked loop, 202-first fractional frequency divider, 203-first frequency increase processor, 204-second fractional frequency divider, 205-second frequency increase processor, 206-error detector, 207-frequency division converter, 208-regulator, 2011-first phase-locked loop, 2012-second phase-locked loop, 100-housing, 200-circuit board, 300-molecular clock, 301-high frequency generating circuit, 302-high frequency receiving circuit, 303-low frequency processing circuit. DETAILED DESCRIPTION

[0044] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings.

[0045] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be changed as needed, and the changes are included in the protection scope of this application. The drawings of this application are only used to illustrate the relative position relationship and do not represent the true proportion.

[0046] In order to facilitate understanding of the technical solution provided by the embodiments of the present application, its application scenario is first described below.

[0047] The molecular clock provided in the embodiment of the present application can be widely used in electronic devices, and the electronic devices may include various terminal devices and electronic devices. Among them, the terminal devices may include but are not limited to: smart phones, smart TVs, smart TV set-top boxes, smart watches, personal computers (PCs), tablet computers, wearable devices, smart broadband, vehicle-mounted devices and other devices. Electronic devices may include but are not limited to: telecommunications equipment and chip modules, memory and other devices, which are not listed here one by one. The clock signal output by the molecular clock can be used as a reference clock to provide a clock reference for timing, stabilize the clock beat, and improve the accuracy of timing, thereby improving the timing performance of electronic devices.

[0048] In current technology, the structure of the molecular clock can be referred to Figure 1 As shown, the molecular clock 300 may generally include: an external oscillator 13, a high-frequency generating circuit 301, a high-frequency receiving circuit 302, a low-frequency processing circuit 303 and a molecular waveguide structure 33. The external oscillator 13 provides a clock signal as a source signal to the low-frequency processing circuit 303. The low-frequency processing circuit 303 processes the clock signal as the source signal and transmits it to the high-frequency generating circuit 301, so that the high-frequency generating circuit 301 generates a high-frequency first radio frequency signal, and the center frequency of the first radio frequency signal is close to the center frequency of the molecular rotation spectrum in the molecular waveguide structure 33, so that the first radio frequency signal can be propagated in the molecular waveguide structure 33. The high-frequency receiving circuit 302 receives the second radio frequency signal propagated from the molecular waveguide structure 33 and transmits it to the low-frequency processing circuit 303 after processing, so that the low-frequency processing circuit 303 outputs a clock signal with a fixed period and a stable phase.

[0049] The molecular waveguide structure 33 is a gas cavity filled with polar gas molecules. The molecular waveguide structure 33 is generally made of metal materials through high-precision machining and is generally large in size, about cm. 3 The external oscillator 13 is usually made of a quartz crystal packaged in a ceramic shell, and is generally large in size. This results in a larger overall volume of the molecular clock.

[0050] Based on this, the embodiment of the present application provides a molecular clock, which can reduce the volume of the molecular clock. In addition, the molecular clock provided by the embodiment of the present application can be applied to various electronic devices with circuit boards, and such electronic devices with circuit boards can be called board-level devices. Figure 2 The schematic diagram of the structure of the molecular clock when it is used in an electronic device is shown as an example. Figure 2 As shown, the electronic device may include a housing 100 and a circuit board 200 disposed in the housing 100 , and the molecular clock 300 may be disposed on the circuit board 200 .

[0051] Figure 3 The schematic diagram of the structure of the molecular clock in the first embodiment of the present application is shown as an example. Figure 3 As shown, the molecular clock may include: a source chip 10, a processing chip 20 and a waveguide chip 30, the source chip 10 includes: a first substrate 11, a first film layer structure 12 arranged on the first substrate 11 and an oscillator 13, the oscillator 13 is arranged in the first film layer structure 12; the waveguide chip 30 includes: a second substrate 31, a second film layer structure 32 arranged on the second substrate 31 and a molecular waveguide structure 33, the molecular waveguide structure 33 is arranged in the second film layer structure 32, and the molecular waveguide structure 33 includes an inlet 34 and an outlet 35. The processing chip 20 includes a signal transmitter 24, a signal receiver 25 and a processing circuit 23. The processing chip 20 also includes: a third substrate 21, and a third membrane layer structure 22 arranged on the third substrate 21. The processing circuit 23 is arranged in the third membrane layer structure 22. At least one of the signal transmitter 24 and the signal receiver 25 can be arranged in the third membrane layer structure 22 or on the surface of the third membrane layer structure 22. The inlet 34 is arranged corresponding to the signal transmitter 24, and the outlet 35 is arranged corresponding to the signal receiver 25. The oscillator 13 provides a source signal (such as a clock signal) S0 to the processing circuit 23. After the processing circuit 23 processes the source signal S0 into a corresponding first radio frequency signal, it is incident on the entrance 34 of the molecular waveguide structure 33 through the signal transmitter 24. The first radio frequency signal propagates in the molecular waveguide structure 33, and then the signal receiver 25 can receive the second radio frequency signal transmitted from the exit 35. The signal receiver 25 transmits the received second radio frequency signal to the processing circuit 23. After the processing circuit 23 processes the signal, it outputs a clock signal with a fixed period and a stable phase. The clock signal can be a sine wave signal, a square wave signal or other forms of signals, which are not strictly required here.

[0052] In the embodiment of the present application, the molecular waveguide structure 33 can be manufactured in the second film layer structure 32 by using micro-electromechanical system processing technology, and the oscillator 13 can be manufactured in the first film layer structure 12 by using micro-electromechanical system processing technology, so as to reduce the volume of the molecular waveguide structure 33 and the oscillator 13, so that the volume of the oscillator 13 and the molecular waveguide structure 33 can reach the chip level, and compared with the oscillator 13 and the molecular waveguide structure 33 manufactured in the prior art, the volume of the molecular clock can be effectively reduced, and the problem of the molecular clock being larger in the prior art due to the larger volume of the molecular waveguide structure 33 and the oscillator 13 is solved. It should be understood that the specific implementation of the signal transmitter 24 and the signal receiver 25 can be any structure that can realize the transmission and reception of radio frequency signals, and is not limited here.

[0053] When the source chip 10, the processing chip 20 and the waveguide chip 30 are arranged and packaged to obtain a complete molecular clock, the source chip 10, the processing chip 20 and the waveguide chip 30 can be stacked, so that the space in the thickness direction of the chip can be fully utilized, thereby reducing the occupied area of ​​the molecular clock, further reducing the volume of the molecular clock, and also improving the centralization degree of the molecular clock.

[0054] Among them, refer to Figure 4 As shown, (b) is a cross-sectional view along the x1-x2 direction in (a), the processing chip 20 is arranged between the source chip 10 and the waveguide chip 30, and the processing chip 20 is respectively arranged in contact with the waveguide chip 30 and the source chip 10, and the source chip 10 and the processing chip 20 can be electrically connected through the wire 40, so that the height of the molecular clock can be reduced.

[0055] Or, refer to Figure 5 As shown, (b) is a cross-sectional view shown along the x1-x2 direction in (a), the processing chip 20 is arranged between the source chip 10 and the waveguide chip 30, the processing chip 20 and the waveguide chip 30 are contacted but have no electrical connection, there is a certain gap between the source chip 10 and the processing chip 20, a connection pad 51 (which can be called a first connection pad) is provided on the side surface of the source chip 10 facing the processing chip 20, and a connection pad 51 (which can be called a second connection pad) is also provided on the side surface of the processing chip 20 facing the source chip 10, the first connection pad of the source chip 10 and the second connection pad of the processing chip 20 are arranged in a one-to-one correspondence, a solder ball 52 is arranged between the first connection pad of the source chip 10 and the second connection pad of the processing chip 20, the source chip 10 and the processing chip 20 are electrically connected through the solder ball 52, wherein the solder ball 52 can not only play a role of electrical connection, but also play a role of fixing, fixing the source chip 10 on the surface of the processing chip 20, to avoid the relative position between the source chip 10 and the processing chip 20 from being offset.

[0056] Reference Figure 6 As shown, the processing circuit 23 in the processing chip 20 may include: a first frequency increase processor 203, a second frequency increase processor 205, an error detector 206, a frequency divider 207, a phase-locked loop 201, a first fractional frequency divider 202 and a second fractional frequency divider 204, wherein the phase-locked loop 201, the first fractional frequency divider 202 and the second fractional frequency divider 204 may constitute an adjustment module (as shown in the dotted line box 1). The specific processing process of each device may include:

[0057] The oscillator 13 provides a source signal to the phase-locked loop 201, and the source signal may be a clock signal. The phase-locked loop 201 extracts information such as frequency and phase from the source signal, performs frequency up-conversion processing on the source signal, and transmits the processed source signal to the first fractional frequency divider 202. The first fractional frequency divider 202 performs a first fractional frequency division processing on the signal output by the phase-locked loop 201 to achieve fine adjustment of the signal frequency, and then outputs the adjusted signal to the first frequency up-conversion processor 203. The first frequency up-conversion processor 203 performs frequency up-conversion processing on the adjusted signal to generate a high-frequency first radio frequency signal RF, and the signal transmitter 24 transmits the first radio frequency signal RF to the entrance 34 of the molecular waveguide structure 33, so that the first radio frequency signal propagates in the molecular waveguide structure 33. The signal receiver 25 obtains the propagated second RF signal from the exit 35 of the molecular waveguide structure 33, and obtains a deviation signal by subtracting the second RF signal from the reference signal LO output by the second frequency up-conversion processor 205 and transmits it to the error detector 206. The error detector 206 judges the deviation signal and outputs the judgment result to the phase-locked loop 201. The phase-locked loop 201 adjusts the frequency and phase of the source signal output by the oscillator 13 according to the judgment result and outputs it to the first fractional frequency divider 202 again, so that the first fractional frequency divider 202 continues to fine-tune the signal output by the phase-locked loop 201 and outputs it to the first frequency up-conversion processor 203, and repeats the above process.

[0058] Among them, the signal output from the first fractional frequency divider 202 will not only be transmitted to the first frequency increase processor 203, but also to the frequency divider 207. Therefore, as long as the oscillator 13 continues to provide the source signal, the frequency divider 207 will continue to output the clock signal, but the period and phase of the clock signal output in the initial stage may fluctuate. When the judgment result is that the deviation signal is small, the period and phase of the clock signal output by the frequency divider 207 tend to be stable. In addition, when the judgment result is that the deviation signal is small, the signal processed by the phase-locked loop 201 and the first fractional frequency divider 202 will still be transmitted to the first frequency increase processor 203, and the first radio frequency signal will continue to be generated, thereby repeating the process of transmitting the first radio frequency signal in the molecular waveguide structure 33, determining the deviation signal, adjusting based on the deviation signal, outputting the clock signal, and generating the first radio frequency signal. In other words, as long as the oscillator 13 continues to provide the source signal, the signal output from the first fractional frequency divider 202 will always be transmitted to the first frequency increase processor 203 and the frequency divider 207.

[0059] In addition, after the phase-locked loop 201 adjusts the frequency and phase of the source signal, it can also be transmitted to the second fractional frequency divider 204. The second fractional frequency divider 204 fine-tunes the frequency of the signal output by the phase-locked loop 201 and outputs it to the second frequency up-conversion processor 205. The second frequency up-conversion processor 205 generates a reference signal LO based on the fine-tuned signal. The first fractional frequency divider 202 and the second fractional frequency divider 204 have similar functions, both of which perform fractional frequency division processing on the frequency of the adjusted source signal, but the degree of fractional frequency division processing is different, resulting in the frequency of the signal processed by the first fractional frequency divider 202 being different from the frequency of the signal processed by the second fractional frequency divider 204, so that the first radio frequency signal RF and the reference signal LO have different frequencies, so that the calculated deviation signal is not zero. Of course, the frequencies of the first radio frequency signal RF and the reference signal LO can also be the same, so that the calculated deviation signal may be zero, which can be set according to actual conditions and is not limited here.

[0060] Exemplarily, the error detector 206 may be implemented by a lock detector or an analog to digital converter (ADC) and the like. The specific configuration may be based on actual conditions and is not strictly required herein.

[0061] Figure 7 The schematic diagram of the structure of the molecular clock in the second embodiment of the present application is shown as an example. Figure 7 As shown, the structure of the molecular clock in the second embodiment is basically the same as that in the first embodiment, except that the specific structure of the adjustment module is different. The adjustment module in the second embodiment is different from the adjustment module in the first embodiment in the following aspects:

[0062] (1) Remove the first fractional frequency divider and the second fractional frequency divider, and increase the number of phase-locked loops. That is, set the first phase-locked loop 2011 and the second phase-locked loop 2012, the first phase-locked loop 2011 is electrically connected between the oscillator 13 and the first frequency increase processor 203, and the second phase-locked loop 2012 is electrically connected between the oscillator 13 and the second frequency increase processor 205.

[0063] (2) The regulator 208 is provided, and the regulator 208 is provided in the oscillator 13 .

[0064] (3) The error detector 206 outputs the judgment result to the regulator 208 in the oscillator 13, so that the regulator 208 can adjust the frequency and phase of the source signal provided by the oscillator 13 based on the judgment result and output them to the first phase-locked loop 2011, the second phase-locked loop 2012 and the frequency divider 207 respectively, so that the first phase-locked loop 2011 can perform a first frequency increase adjustment on the frequency of the adjusted source signal and output it to the first frequency increase processor 203, the second phase-locked loop 2012 can perform a second frequency increase adjustment on the frequency of the adjusted source signal and output it to the second frequency increase processor 205, and the frequency divider 207 can generate a clock signal based on the adjusted source signal. In addition, the first phase-locked loop 2011 and the second phase-locked loop 2012 have different degrees of frequency adjustment, so that the frequencies of the signals output from the first phase-locked loop 2011 and the second phase-locked loop 2012 are different, so that the first radio frequency signal RF and the reference signal LO have different frequencies.

[0065] (4) The frequency division converter 207 is connected to the oscillator 13 and the first phase-locked loop 2011 respectively, so that the signal adjusted by the regulator 208 in the oscillator 13 is processed by the frequency division converter 207 to output a clock signal with a fixed period and a stable phase.

[0066] Among them, the similarities between the second embodiment and the first embodiment regarding the structure of the molecular clock can be found in the description of the first embodiment, and the repeated parts will not be repeated here.

[0067] Figure 8 The schematic diagram of the structure of the molecular clock in the third embodiment of the present application is shown as an example. Figure 8 As shown, the structure of the molecular clock in the third embodiment is basically the same as that in the first embodiment, except that the specific structure of the adjustment module is different. The adjustment module in the third embodiment is different from the adjustment module in the first embodiment in the following aspects:

[0068] (1) Remove the first fractional frequency divider and the second fractional frequency divider, and increase the number of phase-locked loops. That is, set the first phase-locked loop 2011 and the second phase-locked loop 2012, the first phase-locked loop 2011 is electrically connected between the oscillator 13 and the first frequency increase processor 203, and the second phase-locked loop 2012 is electrically connected between the oscillator 13 and the second frequency increase processor 205.

[0069] (2) The error detector 206 outputs the judgment result to the first phase-locked loop 2011 and the second phase-locked loop 2012, and the first phase-locked loop 2011 and the second phase-locked loop 2012 respectively adjust the frequency and phase of the source signal output by the oscillator 13 based on the judgment result. The first phase-locked loop 2011 and the second phase-locked loop 2012 have different degrees of frequency adjustment, so that the frequencies of the signals output from the first phase-locked loop 2011 and the second phase-locked loop 2012 are different, so that the first radio frequency signal RF and the reference signal LO have different frequencies.

[0070] (3) The frequency division converter 207 is connected to the first phase-locked loop 2011 and the first frequency up-conversion processor 203 respectively, so that the signal adjusted by the first phase-locked loop 2011 is processed by the frequency division converter 207 to output a clock signal with a fixed period and a stable phase.

[0071] It should be understood that the similarities between the third embodiment and the aforementioned first embodiment regarding the structure of the molecular clock can be found in the description of the aforementioned first embodiment, and the repeated parts will not be repeated here.

[0072] Figures 9 to 11 The schematic diagram of the structure of the molecular clock in the fourth embodiment of the present application is shown as an example. Figures 9 to 11 As shown, the structure of the molecular clock in the fourth embodiment is basically the same as that in the first embodiment, except that the source chip 10, the processing chip 20 and the waveguide chip 30 are arranged and packaged in different ways. The arrangement and packaging of the source chip 10, the processing chip 20 and the waveguide chip 30 in the fourth embodiment include:

[0073] Reference Figures 9 to 11 As shown, the source chip 10 is disposed between the processing chip 20 and the waveguide chip 30. When the area of ​​the processing chip 20 is larger than that of the source chip 10, since the area of ​​the source chip 10 disposed in the middle is smaller, a support structure 60 can be disposed on the side of the processing chip 20 facing the waveguide chip 30. The support structure 60 can maintain a gap between the processing chip 20 and the waveguide chip 30, provide an accommodation space for the arrangement of the source chip 10, reduce the pressure of the processing chip 20 on the source chip 10, and thus avoid adverse effects on the performance of the oscillator in the source chip 10. Among them, a plurality of support structures 60 can be disposed, and each support structure 60 can be dispersed at various positions on the surface of the processing chip 20 to balance the support force of each support structure 60 on each position in the processing chip 20, and avoid a certain position in the processing chip 20 being subjected to a smaller support force, while a certain position being subjected to a larger support force, thereby maintaining the stability of the processing chip 20.

[0074] Reference Fig. 9As shown, each support structure 60 may include: a support pad 61 and a support column 62, the support pad 61 is respectively arranged on the surface of the processing chip 20 and the waveguide chip 30, and the support column 62 is arranged between the two support pads 61 respectively arranged on the surface of the processing chip 20 and the waveguide chip 30. Taking one of the support structures 60 arranged between the processing chip 20 and the waveguide chip 30 as an example, a support pad 61 (which can be called a first support pad) is arranged on the surface of the processing chip 20 facing the waveguide chip 30, and a support pad 61 (which can be called a second support pad) is arranged on the surface of the waveguide chip 30 facing the processing chip 20, and a support column 62 is arranged between the first support pad on the processing chip 20 and the second support pad on the waveguide chip 30, so that the support column 62 can avoid damage to the processing chip 20 and the waveguide chip 30. Of course, the support structure 60 may also not include the support pad 61, in which case the contact surface between the support structure 60 and the chip can be specially treated, such as but not limited to increasing the area of ​​the contact surface, etc., to reduce the damage of the contact surface to the chip surface.

[0075] Exemplarily, when the source chip 10 is respectively arranged in contact with the waveguide chip 30 and the processing chip 20, each support structure 60 can be evenly arranged between the processing chip 20 and the waveguide chip 30 (not shown in the figure). This can not only reduce the height of the molecular clock and thus reduce the volume of the molecular clock, but also prevent the source chip 10 from being subjected to greater pressure.

[0076] Or, refer to Fig. 9 As shown, (b) is a cross-sectional view along the x1-x2 direction in (a). When the processing chip 20 and the source chip 10 are arranged non-contact, and the source chip 10 and the waveguide chip 30 are arranged non-contact, that is, there is a certain gap between the processing chip 20 and the source chip 10, and there is also a certain gap between the source chip 10 and the waveguide chip 30, each supporting structure 60 is arranged between the processing chip 20 and the waveguide chip 30, and a plurality of connection pads 51 (which can be referred to as first connection pads) are also arranged on the side surface of the source chip 10 facing the processing chip 20, and a plurality of connection pads 51 (which can be referred to as second connection pads) are also arranged on the side surface of the processing chip 20 facing the source chip 10. The first connection pads in the source chip 10 and the second connection pads in the processing chip 20 are arranged one by one, and the first connection pads in the source chip 10 and the second connection pads in the processing chip 20 can be electrically connected through solder balls 52.

[0077] Or, refer to Fig.10As shown, (b) is a cross-sectional view along the x1-x2 direction in (a). When the processing chip 20 and the source chip 10 are arranged in non-contact, and the source chip 10 is arranged on the surface of the waveguide chip 30, so that the source chip 10 and the waveguide chip 30 are arranged in contact, when all the support structures 60 are divided into at least one first support structure 601 and at least one second support structure 602, each first support structure 601 can be arranged between the source chip 10 and the processing chip 20, and a gap can be maintained between the source chip 10 and the processing chip 20 through the first support structure 601, and the second support structure 602 can be arranged between the processing chip 20 and the waveguide chip 30 to maintain a gap between the processing chip 20 and the waveguide chip 30. In addition, at least part of the first support structure 601 can be made of a conductive material with supporting capacity to electrically connect the processing chip 20 and the source chip 10, so that the source signal provided by the oscillator of the source chip 10 can be transmitted to the processing chip 20 to realize the function of a molecular clock. Fig.10 In order to avoid making the structure in the figure too complicated, the support pads and support columns in the support structure are not shown.

[0078] Or, refer to Fig.11 As shown, a groove 36 may be provided on one side of the waveguide chip 30 facing the source chip 10, and the source chip 10 may be arranged in the groove 36. The processing chip 20 and the source chip 10 are arranged in a non-contact manner. At this time, the first support structure 601 ( Fig.11 The first support structure 601 (not shown) is disposed between the source chip 10 and the processing chip 20, and at least part of the first support structure 601 electrically connects the source chip 10 and the processing chip 20, and the second support structure 602 is disposed between the processing chip 20 and the waveguide chip 30, which can effectively reduce the height of the molecular clock, thereby further reducing the volume of the molecular clock. Among them, the length of the groove 36 in the z direction is the depth of the groove 36, and the height of the source chip 10 in the z direction is the thickness of the source chip 10. The thickness of the source chip 10 can be greater than or equal to the depth of the groove 36, which can be specifically set according to actual conditions and is not limited here. Fig.10 and Fig.11 In order to avoid making the structure in the figure too complicated, the support pads and support columns in the support structure 60 are not shown.

[0079] It should be understood that the similarities between the fourth embodiment and the first embodiment regarding the structure of the molecular clock can be found in the description of the first embodiment, and the repeated parts will not be repeated.

[0080] Fig.12 and Fig.13 The schematic diagram of the structure of the molecular clock in the fifth embodiment of the present application is shown as an example. Fig.12 and Fig.13As shown, the structure of the molecular clock in the fifth embodiment is basically the same as that in the first embodiment, except that the source chip 10, the processing chip 20 and the waveguide chip 30 are arranged and packaged in different ways. The arrangement and packaging of the source chip 10, the processing chip 20 and the waveguide chip 30 in the fifth embodiment include:

[0081] The source chip 10 and the processing chip 20 are both disposed on the surface of the waveguide chip 30, and the source chip 10 and the processing chip 20 can be connected by a wire 40, which can effectively reduce the height of the molecular clock, thereby further reducing the volume of the molecular clock, and can also improve the centralization of the molecular clock. Fig.12 As shown, the processing chip 20 may be provided with one, in which case the signal transmitter 24, the signal receiver 25 and the processing circuit 23 are all provided in the processing chip, thereby improving the centralization of the chip and even the molecular clock. Alternatively, see Fig.13 As shown, when the processing chip 20 includes a first chip 20a and a second chip 20b both disposed on the surface of the waveguide chip 30, the first chip 20a includes a signal transmitter 24, and the second chip 20b includes a signal receiver 25, the source chip 10 can be disposed between the first chip 20a and the second chip 20b, or disposed at other positions, as long as the source chip 10, the first chip 20a and the second chip 20b are all disposed on the waveguide chip 30. Furthermore, when the processing circuit 23 is disposed on the first chip 20a, the source chip 10 is electrically connected to the processing circuit 23 in the first chip 20a; when the processing circuit 23 is disposed on the second chip 20b, the source chip 10 is electrically connected to the processing circuit 23 in the second chip 20b. Of course, a part of the processing circuit 23 can be arranged in the first chip 20a, and another part of the processing circuit 23 can be arranged in the second chip 20b. In this case, the processing circuit 23 in the first chip 20a is electrically connected to the processing circuit 23 in the first chip 20a and the processing circuit 23 in the second chip 20b, so as to realize the function of the processing circuit. In addition, the similarities between the fifth embodiment and the first embodiment regarding the structure of the molecular clock can be referred to the description of the first embodiment, and the repeated parts will not be repeated.

[0082] Fig.14 A schematic diagram of a method for making a molecular clock in a sixth embodiment of the present application is exemplarily shown. The method can be used to make the above Figures 3 to 13 A molecular clock of any structure shown in Fig.14 As shown, the method for making a molecular clock may include:

[0083] S1401. A source chip may be manufactured by, but is not limited to, using a micro-electromechanical system processing technology, and the source chip includes: a first substrate, a first film layer structure disposed on the first substrate, and an oscillator, wherein the oscillator is disposed in the first film layer structure;

[0084] S1402. A waveguide chip may be manufactured by using, but is not limited to, a micro-electromechanical system processing technology, and the waveguide chip includes: a second substrate, a second film layer structure and a molecular waveguide structure disposed on the second substrate, wherein the molecular waveguide structure is disposed in the second film layer structure; the molecular waveguide structure includes an inlet and an outlet;

[0085] S1403. The processing chip may be manufactured by using, but is not limited to, complementary metal oxide semiconductor (CMOS) technology, and the processing chip includes a processing circuit, and the oscillator is connected to the processing circuit;

[0086] S1404, stacking the source chip, the processing chip and the waveguide chip and packaging them.

[0087] When the source chip, the processing chip and the waveguide chip are stacked, the source chip can be arranged between the processing chip and the waveguide chip, or the processing chip can be arranged between the source chip and the waveguide chip, and when the source chip is arranged between the processing chip and the waveguide chip, if the area of ​​the processing chip is larger than the area of ​​the source chip, a support structure can be arranged on the side of the processing chip facing the source chip, so that there is a certain distance between the processing chip and the waveguide chip, so as to accommodate the source chip. For the specific arrangement of the support structure, please refer to the fourth embodiment above, which will not be described in detail here.

[0088] In this way, an oscillator can be made in the first film layer structure of the source chip, and a molecular waveguide structure can be made in the second film layer structure of the waveguide chip through micro-electromechanical system processing technology, so that the volumes of the oscillator and the molecular waveguide structure can reach the chip level, which is smaller than the oscillator and molecular waveguide structure made in the prior art, thereby reducing the volume of the molecular clock, solving the problem in the prior art that the molecular clock has a larger volume due to the larger volume of the molecular waveguide structure and the oscillator.

[0089] The present application embodiment provides a method for making a molecular clock of the seventh embodiment, which is basically the same as the method for making the sixth embodiment, except that: S1404 in the sixth embodiment can be adjusted to: both the source chip and the processing chip are arranged on the surface of the waveguide chip and packaged. The specific arrangement of the source chip and the processing chip can be referred to the fifth embodiment, which will not be described in detail here. This can effectively reduce the height of the molecular clock, thereby further reducing the volume of the molecular clock, and can also improve the centralization of the molecular clock.

[0090] It should be understood that the similarities between the seventh embodiment and the sixth embodiment regarding the method for manufacturing a molecular clock can be found in the description of the sixth embodiment, and the repeated parts will not be repeated.

[0091] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0092] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A molecular clock, characterized in that: include: Source chip, processing chip and waveguide chip; The source chip comprises: a first substrate, a first film layer structure disposed on the first substrate, and an oscillator, wherein the oscillator is disposed in the first film layer structure; The waveguide chip comprises: a second substrate, a second film layer structure and a molecular waveguide structure arranged on the second substrate, the molecular waveguide structure is arranged in the second film layer structure, and the molecular waveguide structure comprises an inlet and an outlet; The oscillator is used to provide a source signal; The processing chip is connected to the oscillator and is used to: process the source signal into a first radio frequency signal and transmit it to the entrance, so that the first radio frequency signal is transmitted in the molecular waveguide structure; receive a second radio frequency signal output from the exit, and obtain a clock signal after processing the second radio frequency signal, and output the clock signal.

2. The molecular clock according to claim 1, characterized in that The source chip, the processing chip and the waveguide chip are stacked.

3. The molecular clock according to claim 1 or 2, characterized in that: The processing chip is arranged between the source chip and the waveguide chip, and the processing chip is arranged in contact with the waveguide chip and the source chip respectively.

4. The molecular clock according to claim 1 or 2, characterized in that: The source chip is arranged between the processing chip and the waveguide chip, the area of ​​the processing chip is larger than the area of ​​the source chip, and a support structure is provided on the side of the processing chip facing the waveguide chip, and the support structure is used to maintain a gap between the processing chip and the waveguide chip.

5. The molecular clock according to claim 4, characterized in that The source chip is arranged on the surface of the waveguide chip.

6. The molecular clock according to claim 4, characterized in that A surface of the waveguide chip facing the source chip has a groove, and the source chip is arranged in the groove.

7. The molecular clock according to claim 5 or 6, characterized in that Part of the support structure is disposed between the source chip and the processing chip, and the support structure disposed between the source chip and the processing chip electrically connects the source chip and the processing chip.

8. The molecular clock according to claim 1, characterized in that The source chip and the processing chip are both arranged on the surface of the waveguide chip.

9. The molecular clock according to claim 8, characterized in that The processing chip comprises a first chip and a second chip disposed on the surface of the waveguide chip, and the source chip is disposed between the first chip and the second chip; The first chip includes a signal transmitter, and the signal transmitter is used to: transmit the first radio frequency signal to the entrance; The second chip includes a signal receiver, and the signal receiver is used to receive the second radio frequency signal output from the outlet.

10. The molecular clock according to any one of claims 1 to 9, characterized in that: The processing chip includes: a signal transmitter, a signal receiver, a first frequency-upgrading processor, a second frequency-upgrading processor, a frequency-division converter, an error detector, and an adjustment module; The signal transmitter is used to transmit the first radio frequency signal; The signal receiver is used to: receive the second radio frequency signal and a reference signal, perform difference processing on the second radio frequency signal and the reference signal, and then output a deviation signal; The error detector is used to: receive the deviation signal, determine whether the deviation signal is within a preset range, and output the determination result; The adjustment module is used to: adjust the frequency and phase of the source signal according to the judgment result, and output the adjusted source signal; The first frequency up-conversion processor is used to: perform a first frequency up-conversion process on the source signal adjusted by the adjustment module to generate the first radio frequency signal; The second frequency up-conversion processor is used to: perform a second frequency up-conversion process on the source signal adjusted by the adjustment module to generate the reference signal; The frequency division converter is used to generate the clock signal according to the adjusted source signal.

11. The molecular clock according to claim 10, characterized in that The adjustment module comprises: a phase-locked loop, a first fractional frequency divider and a second fractional frequency divider, wherein the phase-locked loop is connected to the oscillator, the first fractional frequency divider, the second fractional frequency divider and the error detector respectively, the first fractional frequency divider is also connected to the first frequency increase processor and the frequency divider converter respectively, and the second fractional frequency divider is also connected to the second frequency increase processor; The phase-locked loop is used to: receive the source signal and the judgment result; and adjust the frequency and phase of the source signal according to the judgment result and then output it; The first fractional frequency divider is used to: divide the frequency of the adjusted source signal by a first fractional multiple and output the resultant frequency to the frequency division converter and the first frequency up-conversion processor respectively; The second fractional frequency divider is used to divide the frequency of the adjusted source signal by a second fractional multiple and output the resultant signal to the second frequency up-conversion processor.

12. The molecular clock according to claim 10, characterized in that The adjustment module includes: a regulator, a first phase-locked loop and a second phase-locked loop, wherein the first phase-locked loop is respectively connected to the first frequency-increasing processor, the regulator and the frequency-dividing converter, and the second phase-locked loop is respectively connected to the regulator and the second frequency-increasing processor; the regulator is respectively connected to the error detector and the frequency-dividing converter; The regulator is used to: receive the source signal and the judgment result, and according to the judgment result, adjust the frequency and phase of the source signal and output them to the first phase-locked loop, the second phase-locked loop and the frequency division converter respectively; The first phase-locked loop is used to: perform a first frequency increase adjustment on the frequency of the adjusted source signal and then output the adjusted frequency to the first frequency increase processor; The second phase-locked loop is used to perform a second frequency increase adjustment on the frequency of the adjusted source signal and then output the result to the second frequency increase processor.

13. The molecular clock according to claim 12, characterized in that The regulator is arranged in the oscillator.

14. The molecular clock according to claim 10, wherein: The adjustment module includes: a first phase-locked loop and a second phase-locked loop, wherein the first phase-locked loop is respectively connected to the error detector, the first frequency-increasing processor, the oscillator and the frequency-dividing converter, and the second phase-locked loop is respectively connected to the error detector, the oscillator and the second frequency-increasing processor; the frequency-dividing converter is also connected to the first frequency-increasing processor; The first phase-locked loop is used to: receive the source signal and the judgment result, and according to the judgment result, perform a first adjustment on the frequency and phase of the source signal and output them to the frequency division converter and the first frequency increase processor respectively; The second phase-locked loop is used to receive the source signal and the judgment result, and according to the judgment result, perform a second adjustment on the frequency and phase of the source signal and output the result to the second frequency increase processor.

15. A method for preparing a molecular clock as claimed in any one of claims 1 to 14, characterized in that: include: forming a source chip, the source chip comprising: a first substrate, a first film layer structure disposed on the first substrate, and an oscillator, the oscillator being disposed in the first film layer structure; A waveguide chip is formed; the waveguide chip comprises: a second substrate, a second film layer structure and a molecular waveguide structure arranged on the second substrate, the molecular waveguide structure being arranged in the second film layer structure; the molecular waveguide structure comprises an inlet and an outlet; A processing chip is formed, and the oscillator is connected to the processing chip.

16. The method of claim 15, wherein: Forming the source chip includes: using micro-electromechanical system processing technology to manufacture the source chip.

17. The method of claim 15, wherein: Forming the waveguide chip includes: using micro-electromechanical system processing technology to manufacture the waveguide chip.

18. The production method according to any one of claims 15 to 17, characterized in that: Also includes: The source chip, the processing chip and the waveguide chip are stacked and packaged.

19. The production method according to any one of claims 15 to 17, characterized in that: Also includes: The source chip and the processing chip are both arranged on the surface of the waveguide chip and packaged.

20. An electronic device, characterized in that: include: A circuit board and a molecular clock as described in any one of claims 1 to 14, wherein the molecular clock is arranged on the circuit board.

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