A low-dropout linear regulator with switchable output mode

Abstract

The application belongs to the technical field of integrated circuits, and particularly relates to a low-dropout linear voltage regulator with switchable output modes, which comprises a SET network, an EA network and a feedback network, the EA network comprises a first error amplifier circuit, a second error amplifier circuit and a third error amplifier circuit, the feedback network comprises a fixed feedback resistor network and an adjustable resistor feedback network, and when the SET network selects the first error amplifier circuit or the second error amplifier circuit and the third error amplifier circuit, a loop of the low-dropout linear voltage regulator is formed with the feedback circuit. The dual-mode switchable output device provided by the application can realize the free switching of the fixed and adjustable output working modes, and the switching between the fixed output and the adjustable output can be realized by operating a switching switch, that is, the one-to-many working mode is realized, which brings great convenience to use and saves the cost of the separate design of the fixed and adjustable output power supplies.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and relates to a power management chip, in particular to a low-dropout linear regulator with switchable output modes. BACKGROUND

[0002] The low-dropout linear regulator (LDO) is widely applied to complete machines as a secondary power supply due to its good current capacity and ripple suppression capacity. In actual application, it can be divided into fixed output and adjustable output from the characteristics of the output end. However, in some applications, the adjustable output and the fixed output are different chips, and in the process of upgrading the complete machine, the same chip may be used, but a power supply with different output modes is needed, so the IC design company needs to modify the output mode and reflow, which consumes manpower and material resources and wastes time. SUMMARY

[0003] In order to solve the problems in the prior art, the application provides a low-dropout linear regulator with switchable output modes, which comprises a SET network, an EA network and a feedback network, the EA network comprises a first error amplifier circuit, a second error amplifier circuit and a third error amplifier circuit, the feedback network comprises a fixed feedback resistor network and an adjustable resistor feedback network, when the SET network selects the first error amplifier circuit or the second error amplifier circuit and the third error amplifier circuit, the feedback circuit forms a loop of the low-dropout linear regulator, when the first error amplifier circuit and the third error amplifier circuit and the fixed feedback resistor network form a loop of the low-dropout linear regulator, the output of the low-dropout linear regulator is in an adjustable mode, and when the second error amplifier circuit and the third error amplifier circuit and the adjustable resistor feedback network form a loop of the low-dropout linear regulator, the output of the low-dropout linear regulator is in a fixed mode.

[0004] Further, the SET network is realized by a comparator circuit and an inverter, a reference signal is taken as the inverting input end of the comparator circuit, the low-dropout linear regulator is in different working modes when the negative input of the comparator circuit is connected with different signals, the output signal of the comparison circuit is d6, and the signal d6 passes through an inverter to obtain a signal d5.

[0005] Further, the SET network is realized by a comparator circuit and an inverter, a reference signal is taken as the inverting input end of the comparator circuit, the low-dropout linear regulator is in different working modes when the negative input of the comparator circuit is connected with different signals, the output signal of the comparison circuit is d6, and the signal d6 passes through an inverter to obtain a signal d5.

[0006] Furthermore, a first switch tube is set between the negative input terminal of the first error amplifier circuit and the positive input terminal of the third error amplifier circuit to control the on-off between the two, and the adjustable resistor feedback network controls whether to be connected between the negative input terminal of the first error amplifier circuit and the positive input terminal of the third error amplifier circuit through the third switch tube; a second switch tube is set between the negative input terminal of the second error amplifier circuit and the positive input terminal of the third error amplifier circuit to control the on-off between the two, and the fixed feedback resistor network controls whether to be connected between the negative input terminal of the second error amplifier circuit and the positive input terminal of the third error amplifier circuit through the fourth switch tube.

[0007] Furthermore, the on / off of the first switch tube and the third switch tube is controlled by the signal d6; the on / off of the second switch tube and the fourth switch tube is controlled by the signal d5.

[0008] Furthermore, the SET network is composed of first to fourth P-type MOS transistors, first to second N-type MOS transistors, first to second inverters, and a first resistor, wherein:

[0009] The source power supply terminals of the first P-type MOS transistor and the second P-type MOS transistor are connected, the gate terminals of the first P-type MOS transistor and the second P-type MOS transistor are connected to the bias voltage terminal, and the drain terminal of the first P-type MOS transistor is connected to one end of the first resistor and the source terminal of the third P-type MOS transistor;

[0010] The drain of the second P-type MOS transistor, the drain of the second N-type MOS transistor, and the input end of the first inverter are connected together;

[0011] The gate of the third P-type MOS transistor serves as the inverting input terminal of the SET network, and the drain of the third P-type MOS transistor is connected to the drain and gate of the first N-type MOS transistor and the gate of the second N-type MOS transistor;

[0012] The other end of the first resistor is connected to the source of the fourth P-type MOS transistor, the gate of the fourth P-type MOS transistor serves as the non-inverting input end of the SET network, and the drain of the fourth P-type MOS transistor is grounded;

[0013] The sources of the first N-type MOS transistor and the second N-type MOS transistor are grounded;

[0014] The first inverter and the second inverter are cascaded, and the first inverter outputs a signal d6 and the second inverter outputs a signal d5.

[0015] Furthermore, the size ratio between the first P-type MOS transistor and the second P-type MOS transistor is 1:1; the size ratio between the first N-type MOS transistor and the second N-type MOS transistor is 1:2.

[0016] Further, the EA network is composed of the fifth to seventh P-type MOS transistors, the third to tenth N-type MOS transistors, wherein:

[0017] The source of the fifth to seventh P-type MOS transistors is connected to the power supply terminal, the source and the gate of the fifth P-type MOS transistor, the gate of the sixth P-type MOS transistor, the drain of the third N-type MOS transistor and the fourth N-type MOS transistor are connected together;

[0018] The drain of the sixth P-type MOS transistor is connected to the gate of the seventh P-type MOS transistor, the gate of the fifth N-type MOS transistor and the sixth N-type MOS transistor;

[0019] The drain of the seventh P-type MOS transistor is connected to the drain of the tenth N-type MOS transistor and is connected to the output terminal of the EA network and the feedback network;

[0020] The gate of the third N-type MOS transistor and the fourth N-type MOS transistor is connected to the second reference power supply terminal, the source of the third N-type MOS transistor is connected to the drain of the seventh N-type MOS transistor, the source of the fifth N-type MOS transistor;

[0021] The source of the fourth N-type MOS transistor is connected to the source of the sixth N-type MOS transistor, the drain of the eighth N-type MOS transistor;

[0022] The gate of the fifth N-type MOS transistor is connected to the first voltage signal fed back by the feedback network, the gate of the sixth N-type MOS transistor is connected to the second voltage signal fed back by the feedback network;

[0023] The gate of the seventh N-type MOS transistor is connected to the signal d5, the source of the seventh N-type MOS transistor is connected to the source of the eighth N-type MOS transistor, the drain of the ninth N-type MOS transistor;

[0024] The gate of the eighth N-type MOS transistor is connected to the signal d6;

[0025] The source of the ninth N-type MOS transistor and the ninth N-type MOS transistor is grounded, the gate of the ninth N-type MOS transistor and the tenth N-type MOS transistor is connected to the second bias voltage terminal.

[0026] Further, the feedback network includes the eleventh N-type MOS transistor, the eighth P-type MOS transistor, the first on-chip feedback resistor and the second on-chip feedback resistor in series, the first off-chip feedback resistor and the second off-chip feedback resistor in series, wherein:

[0027] The gate of the eighth P-type MOS transistor is connected to the output terminal of the EA network as the input terminal of the feedback network, the source of the eighth P-type MOS transistor is connected to the power supply terminal, and the gate is connected to the first on-chip feedback resistor and the first off-chip feedback resistor;

[0028] The voltage between the first on-chip feedback resistor and the second on-chip feedback resistor is used as the first voltage signal fed back by the feedback network, and the voltage between the first off-chip feedback resistor and the second off-chip feedback resistor is used as the second voltage signal fed back by the feedback network;

[0029] The drain of the eleventh N-type MOS transistor is connected to one end of the second on-chip feedback resistor, the source of the eleventh N-type MOS transistor is connected to one end of the second off-chip feedback resistor, and the gate of the eleventh N-type MOS transistor is connected to the signal d5.

[0030] The present invention selects one of the modes through the SET port to obtain an adjustable output or a fixed output. In the present invention, when the SET voltage is at a high level, the output is in the adjustable output mode. When the SET voltage is at a low level, different feedback resistor networks are selected through an internal switch circuit to achieve the fixed output mode. This ensures that a low-voltage dropout linear regulator with two output modes is implemented in the same chip, improving the integration compatibility of a single chip. This can save manpower and material resources on the circuit design side, and can meet different application environments of the same chip on the application side, achieving a win-win situation in the supply and demand relationship. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 The circuit topology diagrams of conventional fixed output and adjustable output in the prior art are shown;

[0032] Figure 2 A topological diagram of a low-dropout linear regulator with switchable output modes according to the present invention;

[0033] Figure 3 A circuit schematic diagram of a low-dropout linear regulator with switchable output modes according to the present invention;

[0034] Figure 4 The present invention provides a low voltage difference linear regulator with switchable output mode, wherein the Set signal and the V ADJ Simulation diagram when the terminals are short-circuited. OUT 1.2V;

[0035] Figure 5 The present invention is a simulation diagram of a low voltage difference linear regulator with switchable output mode when the Set signal is short-circuited with the ground terminal. During the simulation, V OUT 5V;

[0036] Among them, MN1 is a first N-type MOS transistor; MN2 is a second N-type MOS transistor; MN3 is a third N-type MOS transistor; MN4 is a fourth N-type MOS transistor; MN5 is a fifth N-type MOS transistor; MN6 is a sixth N-type MOS transistor; MN7 is a seventh N-type MOS transistor; MN8 is an eighth N-type MOS transistor;

[0037] MN9, the ninth N-type MOS transistor; MN10, the tenth N-type MOS transistor; MN11, the eleventh N-type MOS transistor;

[0038] MP1, first P-type MOS transistor; MP2, second P-type MOS transistor; MP3, third P-type MOS transistor; MP4, fourth P-type MOS transistor; MP5, fifth P-type MOS transistor; MP6, sixth P-type MOS transistor; MP7, seventh P-type MOS transistor; MP8, eighth P-type MOS transistor;

[0039] R1 represents the first resistor;

[0040] INV1, first inverter; INV2, second inverter;

[0041] R FIX1 , the first on-chip feedback resistor; R FIX2 , the second on-chip feedback resistor;

[0042] R ADJ1 , the first off-chip feedback resistor; R ADJ 2. Second off-chip feedback resistor;

[0043] NMOS1, the first switching tube; NMOS2, the second switching tube; NMOS3, the third switching tube; NMOS4, the fourth switching tube; NMOS5, the fifth switching tube. DETAILED DESCRIPTION

[0044] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0045] The present invention provides a low-voltage dropout linear regulator with switchable output modes, comprising a SET network, an EA network, and a feedback network. The EA network comprises a first error amplifier circuit, a second error amplifier circuit, and a third error amplifier circuit. The feedback network comprises a fixed feedback resistor network and an adjustable resistor feedback network. When the SET network selects the first error amplifier circuit or the second error amplifier circuit to form a loop of the low-voltage dropout linear regulator with the third error amplifier circuit and the feedback circuit, and when the first error amplifier circuit, the third error amplifier circuit, and the fixed feedback resistor network form the loop of the low-voltage dropout linear regulator, the output of the low-voltage dropout linear regulator is in an adjustable mode. When the second error amplifier circuit, the third error amplifier circuit, and the adjustable resistor feedback network form the loop of the low-voltage dropout linear regulator, the output of the low-voltage dropout linear regulator is in a fixed mode.

[0046] Figure 1 The circuit topology is a traditional fixed output and adjustable output circuit topology, mainly composed of an error amplifier EA, a P-type MOS transistor MP, a first on-chip feedback resistor R FIX1 and a second on-chip feedback resistor R FIX2 (fixed output), a first off-chip feedback resistor R ADJ1 and a second off-chip feedback resistor R ADJ2 (output adjustable), when a fixed voltage output is required, the internal circuit of the chip is modified to point A, when a adjustable output voltage is required, the feedback end of the internal circuit of the chip is designed as a port connected to point B, and different resistors are connected to achieve an adjustable output voltage. The above scheme of changing the circuit can meet the application requirements of different outputs, but since different chips need to be designed to meet the application, the compatibility of the product after the application upgrade is limited.

[0047] In view of the problems in the prior art, the present application provides a dual-mode switching low-dropout linear regulator circuit, the topology of which is shown in Figure 1 , and includes a SET network, an EA network and a feedback network. The EA network includes a first error amplifier circuit, a second error amplifier circuit and a third error amplifier circuit. The feedback network includes a fixed feedback resistor network and an adjustable resistor feedback network. The SET network is realized by a comparator circuit and an inverter, and a reference signal is used as the inverting input of the comparator circuit. When the negative input of the comparator circuit is connected to different signals, the low-dropout linear regulator is in different working modes. The output signal of the comparator circuit is d6, and the signal d6 is obtained through an inverter to obtain a signal d5.

[0048] A first MOS transistor is arranged between the negative input of the first error amplifier circuit and the positive input of the third error amplifier circuit to control the on-off between the two. The adjustable resistor feedback network controls whether to access the negative input of the first error amplifier circuit and the positive input of the third error amplifier circuit through a third MOS transistor. A second MOS transistor is arranged between the negative input of the second error amplifier circuit and the positive input of the third error amplifier circuit to control the on-off between the two. The fixed feedback resistor network controls whether to access the negative input of the second error amplifier circuit and the positive input of the third error amplifier circuit through a fourth MOS transistor.

[0049] As Figure 2 , in this embodiment, the reference signal of the positive input of the comparator of the input SET network is set to V ref 1, and the mode of the low-dropout linear regulator is controlled by the Set signal of the inverting input of the comparator of the input SET network, which specifically includes:

[0050] When the Set signal is set to be higher than the reference signal V ref1, the signal d6 outputted by the comparator of the SET network is high level, the signal d5 obtained after the signal d6 passing through the inverter is low level, at this time the first switch tube NMOS1 and the third switch tube NMOS3 are turned on, the first error amplifier circuit EA1 is selected, at this time the loop of the LDO is constituted by the first error amplifier circuit EA1, the third error amplifier circuit EA3 and the adjustable resistance feedback network, at this time the chip is in the output adjustable mode, and the output voltage can be obtained by connecting different feedback resistances in the periphery;

[0051] When the Set signal is set to be lower than the reference signal V ref 1, the signal d6 outputted by the comparator of the SET network is low level, the signal d5 obtained after the signal d6 passing through the inverter is high level, at this time the second switch tube NMOS2, the fourth switch tube NMOS4 and the fifth switch tube NMOS5 are turned on, the second error amplifier circuit EA2 is selected, at this time the loop of the LDO is constituted by the second error amplifier circuit EA2, the third error amplifier circuit EA3 and the fixed feedback resistance network, at this time the chip is in the fixed output mode, and the fixed output voltage can be obtained by designing different output feedback resistances in the periphery.

[0052] The embodiment also provides an implementation scheme of a low-dropout linear voltage regulator with switchable output mode, which is mainly realized by MOS tubes.

[0053] As shown in Figure 3 , the SET network is constituted by the first to fourth P-type MOS tubes, the first to second N-type MOS tubes, the first to second inverters and the first resistance, wherein:

[0054] The source power supply end of the first P-type MOS tube MP1 and the source power supply end of the second P-type MOS tube MP1 are connected, the gate of the first P-type MOS tube and the gate of the second P-type MOS tube are connected with the bias voltage end, the drain of the first P-type MOS tube is connected with one end of the first resistance and the source of the third P-type MOS tube MP3;

[0055] The drain of the second P-type MOS tube MN1, the drain of the second N-type MOS tube MN2 and the input end of the first inverter INV1 are connected together;

[0056] The gate of the third P-type MOS tube is used as the inverting input end of the SET network, the drain of the third P-type MOS tube is connected with the drain and the gate of the first N-type MOS tube and the gate of the second N-type MOS tube;

[0057] The other end of the first resistance R1 is connected with the source of the fourth P-type MOS tube, the gate of the fourth P-type MOS tube MP4 is used as the non-inverting input end of the SET network, and the drain of the fourth P-type MOS tube is grounded;

[0058] The source of the first N-type MOS and the second N-type MOS is grounded.

[0059] The first inverter and the second inverter INV2 are cascaded, and the first inverter outputs a signal d6 and the second inverter outputs a signal d5.

[0060] As an optional embodiment, the size ratio between the first P-type MOS and the second P-type MOS is 1:1, and the size ratio between the first N-type MOS and the second N-type MOS is 1:2.

[0061] As shown in Figure 3 The EA network is composed of the fifth to seventh P-type MOS, the third to tenth N-type MOS, wherein:

[0062] The source of the fifth to seventh P-type MOS is connected with the power supply end, the source and the gate of the fifth P-type MOS MP5, the gate of the sixth P-type MOS MP6, the drain of the third N-type MOS MN3 and the fourth N-type MOS MN4 are connected together.

[0063] The drain of the sixth P-type MOS is connected with the gate of the seventh P-type MOS MP7, the gate of the fifth N-type MOS MN5 and the sixth N-type MOS MN6.

[0064] The drain of the seventh P-type MOS is connected with the drain of the tenth N-type MOS MN10, and is connected with the feedback network as the output end of the EA network.

[0065] The gate of the third N-type MOS and the fourth N-type MOS is connected with the second reference power supply end, the source of the third N-type MOS is connected with the drain of the seventh N-type MOS MN7 and the source of the fifth N-type MOS.

[0066] The source of the fourth N-type MOS is connected with the source of the sixth N-type MOS and the drain of the eighth N-type MOS MN8.

[0067] The gate of the fifth N-type MOS is connected with the first voltage signal fed back by the feedback network, and the gate of the sixth N-type MOS is connected with the second voltage signal fed back by the feedback network.

[0068] The gate of the seventh N-type MOS is connected with the signal d5, and the source of the seventh N-type MOS is connected with the source of the eighth N-type MOS and the drain of the ninth N-type MOS MN9.

[0069] The gate of the eighth N-type MOS is connected with the signal d6.

[0070] The source of the ninth N-type MOS and the tenth N-type MOS is grounded, and the gate of the ninth N-type MOS and the tenth N-type MOS is connected with the second bias voltage end.

[0071] As Figure 3 , the feedback network comprises an eleventh N-type MOS transistor MN11 and an eighth P-type MOS transistor MP8, a first on-chip feedback resistor and a second on-chip feedback resistor connected in series, a first off-chip feedback resistor and a second off-chip feedback resistor connected in series, wherein:

[0072] The gate of the eighth P-type MOS transistor is connected with the output end of the EA network as the input end of the feedback network, and the source of the eighth P-type MOS transistor is connected with the power supply end, and the gate is connected with the first on-chip feedback resistor and the first off-chip feedback resistor.

[0073] The voltage between the first on-chip feedback resistor and the second on-chip feedback resistor is the first voltage signal fed back by the feedback network, and the voltage between the first off-chip feedback resistor and the second off-chip feedback resistor is the second voltage signal fed back by the feedback network.

[0074] The drain of the eleventh N-type MOS transistor is connected with one end of the second on-chip feedback resistor, the source of the eleventh N-type MOS transistor is connected with one end of the second off-chip feedback resistor, and the gate of the eleventh N-type MOS transistor is connected with the signal d5.

[0075] The embodiment gives a setting example of the Set signal, and the person skilled in the art understands the working mode of the low-dropout linear regulator with switchable output mode according to the embodiment, which specifically comprises:

[0076] When the Set signal is connected with V ADJ , the simulation diagram is as shown in Figure 4 , V ADJ is greater than V ref1 about 600mV, at this time MP4 is cut off, at this time the current of MP1 flows to the branches of MP3 and MN1, at this time the current of MN2 is greater than MP2, at this time the output low level, d6 is high level MN8 is turned on, d5 is low level MN7 and MN11 are cut off, at this time the signal transmission is from MN6→MP7→MP→V ADJ , the output of the first error amplifier circuit EA1 in Figure 2 , the eighth P-type MOS transistor MP8, the first off-chip feedback resistor R ADJ1 and the second off-chip feedback resistor R ADJ2 constitute an adjustable resistance feedback network; the specific function is realized.

[0077] When the Set signal is connected with GND, the simulation diagram is as shown in Figure 5As shown, MP3 is cut off at this time, MP1 current flows to MP4 at this time, MP2 current is greater than MN2 at this time, output high level at this time, d6 is low level MN8 cut off, d5 is high level MN7 is on, at this time the signal transmission from MN5→MP7→MP→V FIX In the operational amplifier pair, MN3 and MN5 are used to form an error operational amplifier pair Figure 2 The second error amplifier circuit EA2, the eighth P-type MOS transistor MP8, the first internal feedback resistor R FIX1 And the second internal feedback resistor R FIX2 Constitute a fixed output mode.

[0078] The above examples, the purpose, technical scheme and advantages of the present application are further described in detail, it should be understood that the above examples are only preferred embodiments of the present application, and are not used to limit the present application, any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application, should be included in the protection scope of the present application.

Claims

1. A low-dropout linear regulator with switchable output mode, characterized in that: The invention comprises a SET network, an EA network and a feedback network, wherein the EA network comprises a first error amplifier circuit, a second error amplifier circuit and a third error amplifier circuit, and the feedback network comprises a fixed feedback resistor network and an adjustable resistor feedback network. When the SET network selects the first error amplifier circuit or the second error amplifier circuit and the third error amplifier circuit and the feedback circuit to form a loop of a low-voltage-dropout linear regulator, when the first error amplifier circuit, the third error amplifier circuit and the fixed feedback resistor network form a loop of the low-voltage-dropout linear regulator, the output of the low-voltage-dropout linear regulator is in an adjustable mode, and when the second error amplifier circuit, the third error amplifier circuit and the adjustable resistor feedback network form a loop of the low-voltage-dropout linear regulator, the output of the low-voltage-dropout linear regulator is in a fixed mode. The SET network is realized by a comparator circuit and an inverter, and a reference signal is used as the inverting input terminal of the comparator circuit. The negative input of the comparator circuit is connected to the negative input terminal of the comparator circuit. When different signals are connected, the low-voltage difference linear regulator is in different working modes. The output signal of the comparison circuit is d6, and the signal d6 is converted into a signal d5 through an inverter; a first switch tube is set between the negative input end of the first error amplifier circuit and the positive input end of the third error amplifier circuit to control the on-off between the two, and the adjustable resistor feedback network controls whether to be connected between the negative input end of the first error amplifier circuit and the positive input end of the third error amplifier circuit through the third switch tube; a second switch tube is set between the negative input end of the second error amplifier circuit and the positive input end of the third error amplifier circuit to control the on-off between the two, and the fixed feedback resistor network controls whether to be connected between the negative input end of the second error amplifier circuit and the positive input end of the third error amplifier circuit through the fourth switch tube; the on-off of the first switch tube and the third switch tube is controlled by the signal d6; the on-off of the second switch tube and the fourth switch tube is controlled by the signal d5.

2. The low-dropout linear regulator with switchable output mode according to claim 1, characterized in that: The SET network is composed of the first to fourth P-type MOS transistors, the first to second N-type MOS transistors, the first to second inverters and the first resistor, wherein: The source power supply terminals of the first P-type MOS transistor and the second P-type MOS transistor are connected, the gate terminals of the first P-type MOS transistor and the second P-type MOS transistor are connected to the bias voltage terminal, and the drain terminal of the first P-type MOS transistor is connected to one end of the first resistor and the source terminal of the third P-type MOS transistor; The drain of the second P-type MOS transistor, the drain of the second N-type MOS transistor, and the input end of the first inverter are connected together; The gate of the third P-type MOS transistor serves as the inverting input terminal of the SET network, and the drain of the third P-type MOS transistor is connected to the drain and gate of the first N-type MOS transistor and the gate of the second N-type MOS transistor; The other end of the first resistor is connected to the source of the fourth P-type MOS transistor, the gate of the fourth P-type MOS transistor serves as the non-inverting input end of the SET network, and the drain of the fourth P-type MOS transistor is grounded; The sources of the first N-type MOS transistor and the second N-type MOS transistor are grounded; The first inverter and the second inverter are cascaded, and the first inverter outputs a signal d6 and the second inverter outputs a signal d5.

3. The low-dropout linear regulator with switchable output modes according to claim 2, wherein: The size ratio between the first P-type MOS transistor and the second P-type MOS transistor is 1:1; the size ratio between the first N-type MOS transistor and the second N-type MOS transistor is 1:

2.

4. The low-dropout linear regulator with switchable output modes according to claim 1, wherein: The EA network is composed of the fifth to seventh P-type MOS transistors and the third to tenth N-type MOS transistors, where: The sources of the fifth to seventh P-type MOS transistors are connected to the power supply terminal, the source and gate of the fifth P-type MOS transistor, the gate of the sixth P-type MOS transistor, and the drains of the third N-type MOS transistor and the fourth N-type MOS transistor are connected together; The drain of the sixth P-type MOS transistor is connected to the gate of the seventh P-type MOS transistor, the gate of the fifth N-type MOS transistor, and the gate of the sixth N-type MOS transistor; The drain of the seventh P-type MOS transistor and the drain of the tenth N-type MOS transistor are connected together and connected to the feedback network as the output end of the EA network; The gates of the third N-type MOS transistor and the fourth N-type MOS transistor are connected to the second reference power supply terminal, and the source of the third N-type MOS transistor is connected to the drain of the seventh N-type MOS transistor and the source of the fifth N-type MOS transistor; The source of the fourth N-type MOS transistor is connected to the source of the sixth N-type MOS transistor and the drain of the eighth N-type MOS transistor; The gate of the fifth N-type MOS transistor is connected to the first voltage signal fed back by the feedback network, and the gate of the sixth N-type MOS transistor is connected to the second voltage signal fed back by the feedback network; The gate of the seventh N-type MOS transistor is connected to the signal d5, and the source of the seventh N-type MOS transistor is connected to the source of the eighth N-type MOS transistor and the drain of the ninth N-type MOS transistor; The gate of the eighth N-type MOS transistor is connected to the signal d6; The sources of the ninth N-type MOS transistor and the ninth N-type MOS transistor are grounded, and the gates of the ninth N-type MOS transistor and the tenth N-type MOS transistor are connected to the second bias voltage terminal.

5. The low-dropout linear regulator with switchable output modes according to claim 4, characterized in that: The feedback network includes an eleventh N-type MOS transistor, an eighth P-type MOS transistor, a first on-chip feedback resistor and a second on-chip feedback resistor connected in series, and a first off-chip feedback resistor and a second off-chip feedback resistor connected in series, wherein: The gate of the eighth P-type MOS transistor is connected to the output end of the EA network as the input end of the feedback network, the source of the eighth P-type MOS transistor is connected to the power supply end, and the gate is connected to one end of the first on-chip feedback resistor and one end of the first off-chip feedback resistor respectively; The voltage between the first on-chip feedback resistor and the second on-chip feedback resistor is used as the first voltage signal fed back by the feedback network, and the voltage between the first off-chip feedback resistor and the second off-chip feedback resistor is used as the second voltage signal fed back by the feedback network; The drain of the eleventh N-type MOS transistor is connected to one end of the second on-chip feedback resistor, the source of the eleventh N-type MOS transistor is connected to one end of the second off-chip feedback resistor, and the gate of the eleventh N-type MOS transistor is connected to the signal d5.

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