Reference signal generation circuit, chip and electronic device

Abstract

This application provides a reference signal generation circuit, chip, and electronic device. The reference signal generation circuit includes an operational amplifier module, a mirror module, and a reference signal adjustment module. The voltage feedback unit generates a feedback voltage based on the initial current and outputs a corresponding reference voltage, which can be adjusted individually. The current adjustment unit can adjust the initial current to calibrate at least one reference current while keeping the reference voltage constant, thereby allowing the reference voltage or reference current to be adjusted individually.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, specifically to a reference signal generation circuit, chip, and electronic device. Background Technology

[0002] A bandgap reference circuit (BGR) is a circuit that generates an output voltage independent of the supply voltage and temperature, and is widely used in various analog circuits. The bandgap reference circuit adds a voltage proportional to absolute temperature and a voltage negatively correlated with absolute temperature to obtain a temperature-independent output voltage.

[0003] Voltages negatively correlated with absolute temperature are generally achieved by generating a base-emitter voltage through a transistor, while voltages positively correlated with absolute temperature are generally achieved by subtracting the base-emitter voltages generated by two transistors. The output voltage of the bandgap reference circuit is clamped by a unity-gain buffer to generate a corresponding reference voltage, which, when divided by the feedback resistor, yields the corresponding reference current.

[0004] However, during the adjustment process, the reference voltage and reference current change synchronously, making it impossible to adjust the reference voltage or reference current independently, thereby reducing the accuracy of the reference voltage or reference current. Summary of the Invention

[0005] In view of the above problems, embodiments of this application provide a reference signal generation circuit, chip, and electronic device to solve the technical problem that the reference voltage or reference current cannot be adjusted independently.

[0006] In a first aspect, embodiments of this application provide a reference signal generation circuit, which includes an operational amplifier module, a mirror module, and a reference signal adjustment module. The operational amplifier module is used to output an operational amplifier signal based on a comparison between a reference voltage and a feedback voltage. The mirror module is used to generate a corresponding initial current under the control of the operational amplifier signal and mirror at least one reference current of a corresponding proportion based on the initial current. The reference signal adjustment module includes a voltage feedback unit and a current adjustment unit. The voltage feedback unit is used to generate a feedback voltage based on the initial current and output a corresponding reference voltage. The current adjustment unit is used to adjust the initial current to calibrate at least one reference current while keeping the reference voltage constant.

[0007] Secondly, embodiments of this application also provide a chip that includes the aforementioned reference signal generation circuit.

[0008] Thirdly, embodiments of this application also provide an electronic device, which includes a device body and the aforementioned reference signal generating circuit or chip disposed on the device body.

[0009] The reference signal generation circuit, chip, and electronic device provided in this application embodiment generate a feedback voltage based on the initial current and output a corresponding reference voltage through a voltage feedback unit. The reference voltage can be adjusted individually, and the current adjustment unit can adjust the initial current to calibrate at least one reference current while keeping the reference voltage constant. Thus, the reference voltage or reference current can be adjusted individually.

[0010] Furthermore, compared to only being able to calibrate one reference current at a time, the current adjustment unit of this application can adjust the initial current to synchronously calibrate the reference current of all paths, thereby improving the calibration efficiency of the reference current.

[0011] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A first schematic block diagram of a reference signal generation circuit provided in an embodiment of this application is shown.

[0014] Figure 2 The schematic diagram of the mirror module is shown.

[0015] Figure 3 The circuit diagram of the first type of initial current generation branch is shown.

[0016] Figure 4 The second circuit diagram of the initial current generation branch is shown.

[0017] Figure 5 The circuit diagram of the mirror current branch is shown.

[0018] Figure 6 The first circuit schematic of the voltage feedback unit is shown.

[0019] Figure 7 The second circuit schematic of the voltage feedback unit is shown.

[0020] Figure 8 The circuit diagram of the current adjustment unit is shown.

[0021] Figure 9 A first circuit schematic diagram of the reference signal generation circuit provided in an embodiment of this application is shown.

[0022] Figure 10 A second circuit schematic diagram of the reference signal generation circuit provided in an embodiment of this application is shown.

[0023] Figure 11 A third circuit schematic diagram of the reference signal generation circuit provided in the embodiments of this application is shown.

[0024] Figure 12 A fourth circuit schematic diagram of the reference signal generation circuit provided in the embodiments of this application is shown.

[0025] Figure 13 A schematic diagram of the chip provided in an embodiment of this application is shown.

[0026] Figure 14 A schematic diagram of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0027] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0028] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0029] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0030] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0031] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0032] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0033] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0034] In the embodiments of this application, the first terminal / first end of each transistor is one of the source and the drain, and the second terminal / second end of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first terminal / first end and the second terminal / second end of the transistor in the embodiments of this application can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first terminal / first end is the source, and the second terminal / second end is the drain; for example, when the transistor is an N-type transistor, the first terminal / first end is the drain, and the second terminal / second end is the source.

[0035] After the bandgap reference circuit is calibrated, it typically outputs a reference voltage that is independent of the power supply voltage and temperature. When the output reference voltage needs to be greater than or less than the reference voltage, it is usually scaled using a unity-gain buffer (operational amplifier) ​​and a resistor divider. Changing the voltage division ratio can change the output reference voltage, and the current flowing through the voltage divider resistors can be used as the reference current output.

[0036] When a high-precision reference current is required, the reference current needs to be calibrated. This is usually done by adding or removing multiple current mirror branches in parallel. However, this method can only calibrate one output reference current at a time, and the accuracy of the reference currents of other outputs remains low. Moreover, the calibration efficiency of the reference current is also low.

[0037] Based on this, embodiments of this application provide a reference signal generation circuit 100, such as... Figure 1 As shown, the reference signal generation circuit 100 includes an operational amplifier module 10, a mirror module 20, and a reference signal adjustment module 30. The reference signal adjustment module 30 includes a voltage feedback unit 31 and a current adjustment unit 32. The voltage feedback unit 31 generates a feedback voltage VFB based on the initial current and outputs a corresponding reference voltage VREF, which can be adjusted individually. The current adjustment unit 32 can adjust the initial current to calibrate at least one reference current IREF while keeping the reference voltage VREF constant, thereby allowing the reference voltage VREF or the reference current IREF to be adjusted individually.

[0038] Moreover, compared to only being able to calibrate one reference current IREF at a time, the current adjustment unit 32 of this application can adjust the initial current to simultaneously calibrate the reference current IREF of all paths, thereby improving the calibration efficiency of the reference current IREF.

[0039] This application provides a reference signal generation circuit 100. Please refer to [link / reference]. Figures 1 to 12 ,like Figure 1 As shown, the reference signal generation circuit 100 includes an operational amplifier module 10, a mirror module 20, a reference signal adjustment module 30, a voltage feedback unit 31, and a current adjustment unit 32. The reference signal adjustment module 30 includes a voltage feedback unit 31 and a current adjustment unit 32. The operational amplifier module 10 is used to output an operational amplifier signal based on the comparison result between the reference voltage VBG and the feedback voltage VFB. The mirror module 20 is used to generate a corresponding initial current under the control of the operational amplifier signal and mirror at least one reference current IREF based on the initial current. The voltage feedback unit 31 is used to generate a feedback voltage VFB based on the initial current and output a corresponding reference voltage VREF. The current adjustment unit 32 is used to adjust the initial current to calibrate at least one reference current IREF while keeping the reference voltage VREF constant.

[0040] It is understood that the reference signal generation circuit 100 provided in this application embodiment generates a feedback voltage VFB based on the initial current through the voltage feedback unit 31 and outputs a corresponding reference voltage VREF. The reference voltage VREF can be adjusted individually. The current adjustment unit 32 can adjust the initial current to calibrate at least one reference current IREF while keeping the reference voltage VREF unchanged. Thus, the reference voltage VREF or the reference current IREF can be adjusted individually.

[0041] Furthermore, compared to only being able to calibrate one reference current IREF at a time, the current adjustment unit 32 of this application can adjust the initial current to simultaneously calibrate the reference current IREF of all paths, thereby improving the calibration efficiency of the reference current IREF.

[0042] It should be noted that the first input terminal of the operational amplifier module 10 is connected to the reference voltage VBG, the second input terminal of the operational amplifier module 10 is connected to the feedback voltage VFB, and the output terminal of the operational amplifier module 10 outputs the operational amplifier signal. The operational amplifier module 10 is connected to the mirror module 20, and the mirror module 20 is connected to the current adjustment unit 32 and the voltage feedback unit 31. The current adjustment unit 32 and the voltage feedback unit 31 are connected in parallel.

[0043] Optionally, such as Figure 2 As shown, the mirror module 20 includes an initial current generation branch 21 and a current mirroring branch 22. The initial current generation branch 21 is used to generate an initial current. The current mirroring branch 22 is connected to the initial current generation branch 21 and is used to mirror at least one reference current based on the initial current.

[0044] It should be noted that the initial current generation branch 21 can be connected to the operational amplifier module 10 to generate an initial current based on the output signal of the operational amplifier module 10. The current mirroring branch 22 can mirror at least one reference current based on the initial current through the current mirroring relationship.

[0045] Optionally, such as Figure 3 As shown, the initial current generation branch 21 includes a first transistor M1. The control terminal of the first transistor M1 is connected to the output terminal of the operational amplifier OP1. The first terminal of the first transistor M1 is connected to the power supply terminal VDD. The second terminal of the first transistor M1 is connected to the voltage feedback unit 31 and the current adjustment unit 32.

[0046] It should be noted that the initial current generation branch 21 can generate the corresponding initial current through the first transistor M1, which simplifies the circuit structure of the initial current generation branch 21.

[0047] Optionally, such as Figure 4 As shown, the initial current generation branch 21 includes a first transistor M1 and a second transistor M3. The first terminal of the first transistor M1 is connected to the power supply terminal VDD, and the control terminal of the first transistor M1 is connected to the second terminal of the first transistor M1. The first terminal of the second transistor M3 is connected to the second terminal of the first transistor M1, and the second terminal of the second transistor M3 is connected to the voltage feedback unit 31 and the current adjustment unit 32. The control terminal of the second transistor M3 is connected to the output terminal of the operational amplifier module 10.

[0048] It should be noted that the initial current generation branch 21 generates the corresponding initial current through the first transistor M1 and the second transistor M3, which helps to improve the accuracy of the initial current.

[0049] Optionally, such as Figure 5 As shown, the current mirror branch 22 includes at least one third transistor M2, the control electrode of the at least one third transistor M2 is connected to the control electrode of the first transistor M1, the first electrode of the at least one third transistor M2 is connected to the power supply terminal VDD, and the second electrode of the at least one third transistor M2 is used to output at least one reference current IREF.

[0050] It should be noted that since the first transistor M1 and at least one third transistor M2 can form a mirror structure, the current flowing through the first transistor M1 is the initial current, and the current flowing through the third transistor M2 is the reference current IREF. As the initial current changes, each reference current IREF will change accordingly, so as to perform synchronous calibration of each reference current IREF.

[0051] Optionally, such as Figure 6 As shown, the voltage feedback unit 31 includes a first adjustable resistor R1 and a second resistor R2. The first adjustable resistor R1 is used to adjust the reference voltage VREF; the second resistor R2 is connected between the first adjustable resistor R1 and the ground terminal GND.

[0052] It should be noted that the reference voltage VREF can be adjusted by changing the value of the first adjustable resistor R1. The reference voltage VREF is less than the base voltage VBG.

[0053] Optionally, such as Figure 6 As shown, one end of the first adjustable resistor R1 is connected to the operational amplifier module 10 and the mirror module 20 respectively, and the other end of the first adjustable resistor R1 is used to output the reference voltage VREF.

[0054] It should be noted that the reference voltage VREF output in this embodiment can be less than the feedback voltage VFB.

[0055] Optionally, such as Figure 7 As shown, one end of the first adjustable resistor R1 is connected to the mirror module 20 and outputs the reference voltage VREF, and the other end of the first adjustable resistor R1 is connected to the operational amplifier module 10.

[0056] It should be noted that the reference voltage VREF output in this embodiment can be greater than the feedback voltage VFB.

[0057] Optionally, such as Figure 8As shown, the current adjustment unit 32 includes a third adjustable resistor R3. One end of the third adjustable resistor R3 is connected to the mirror module 20, and the other end of the third adjustable resistor R3 is connected to the ground terminal GND.

[0058] It should be noted that the third adjustable resistor R3 can be a sliding resistor or a resistor array to achieve adjustable resistance. The third adjustable resistor R3 is used to adjust the initial current and at least one reference current IREF while keeping the reference voltage VREF constant.

[0059] Optionally, such as Figure 9 , Figure 10 , Figure 11 as well as Figure 12 As shown, the reference signal generation circuit 100 also includes a bandgap reference module 60, which is used to output a reference voltage VBG.

[0060] It should be noted that the bandgap reference module 60 is a bandgap reference circuit that can fine-tune the output reference voltage VBG. The bandgap reference module 60 is connected to the operational amplifier OP1 to provide the corresponding reference voltage VBG.

[0061] The operational amplifier module 10 includes an operational amplifier OP1. The first input terminal of the operational amplifier OP1 is connected to the feedback voltage VFB, the second input terminal of the operational amplifier OP1 is connected to the reference voltage VBG, and the output terminal of the operational amplifier OP1 outputs the operational amplifier signal.

[0062] exist Figure 9 , Figure 11 In this configuration, the first input terminal of operational amplifier OP1 is the non-inverting input terminal, and the second input terminal of operational amplifier OP1 is the inverting input terminal. Figure 10 , Figure 12 In this circuit, the first input terminal of operational amplifier OP1 is the inverting input terminal, and the second input terminal of operational amplifier OP1 is the non-inverting input terminal.

[0063] like Figure 9 As shown, the reference voltage VREF output by the reference signal generation circuit 100 is lower than the reference voltage VBG. After the bandgap reference is calibrated, the bandgap reference module 60 of the reference signal generation circuit 100 outputs a reference voltage VBG that is independent of process, power supply voltage, and temperature. Operational amplifier OP1, second transistor M3, first adjustable resistor R1, second resistor R2, and third adjustable resistor R3 form a negative feedback loop. Under the action of the feedback loop, the non-inverting and inverting input terminals of operational amplifier OP1 are virtually shorted, meaning the potential at the non-inverting input terminal of operational amplifier OP1 is equal to the potential at its inverting input terminal. Therefore, the magnitude of the reference voltage VREF can be expressed as the following calculation formula:

[0064] VREF=VFB×R2÷(R1+R2)=VBG×R2÷(R1+R2) (1)

[0065] Where VREF represents the reference voltage VREF. VFB represents the potential at the inverting input of operational amplifier OP1. R1 represents the resistance of the first adjustable resistor R1. R2 represents the resistance of the second resistor R2. VBG represents the reference voltage VBG.

[0066] The drain current of the first transistor M1 is equal to the sum of the currents flowing through the first adjustable resistor R1 and the third resistor. The gate-source voltage, gate length, and gate width of the third transistor M2 are respectively equal to the gate-source voltage, gate length, and gate width of the first transistor M1. This can be achieved by using a corresponding number of smallest units with the same width-to-length ratio to form the first transistor M1 and the third transistor M2, ensuring the current mirror accuracy. The reference current IREF (i.e., the drain current of the third transistor M2) is M times the initial current (i.e., the drain current of the first transistor M1), where M is any number greater than 0. Therefore, the sum of the currents flowing through the first adjustable resistor R1 and the third adjustable resistor R3, i.e., IM3, can be expressed as the following calculation formula:

[0067] IM3=VFB÷[(R1+R2)∥R3]=VBG÷[(R1+R2)∥R3] (2)

[0068] Where R3 represents the resistance value of the third adjustable resistor R3. (R1+R2)∥R3 represents the equivalent resistance of the first adjustable resistor R1 and the second resistor R2 connected in series and then connected in parallel with the third adjustable resistor R3.

[0069] Since both the first transistor M1 and the second transistor M3 are connected in series with the equivalent resistance in the same branch, the current flowing through the equivalent resistance, i.e., IM3, is equal to the current flowing through the first transistor M1 and the second transistor M3. Therefore, the reference current IREF can be expressed as follows:

[0070] IREF=M×IM3=M×VBG÷[(R1+R2)∥R3] (3)

[0071] Where IREF represents the reference current IREF. M is an adjustable coefficient, determined jointly by the first transistor M1 and the third transistor M2.

[0072] Once the output reference voltage VREF is determined, the reference current IREF can be calibrated by changing the resistance value of the third adjustable resistor R3. Figure 10 The formulas for calculating the reference voltage VREF and reference current IREF can be the above formulas (1) and (3).

[0073] Figure 11 The reference signal generation circuit 100 outputs a reference voltage VREF that is higher than the reference voltage VBG. After the bandgap reference is calibrated, a reference voltage VBG that is independent of process, power supply voltage, and temperature is output. Operational amplifier OP1, second transistor M3, first adjustable resistor R1, second resistor R2, and third adjustable resistor R3 form a negative feedback loop. Under the action of the feedback loop, the non-inverting and inverting input terminals of operational amplifier OP1 are virtually shorted, that is, the potential of the non-inverting input terminal of operational amplifier OP1 is equal to the potential of its inverting input terminal. Therefore, the magnitude of the reference voltage VREF can be expressed as the following calculation formula:

[0074] VREF=VFB×(1+R1 / R2)=VBG×(1+R1 / R2) (4)

[0075] Where VREF represents the reference voltage VREF. VFB represents the potential at the inverting input of operational amplifier OP1. R1 represents the resistance of the first adjustable resistor R1. R2 represents the resistance of the second resistor R2. VBG represents the reference voltage VBG.

[0076] The drain current of the first transistor M1 is equal to the sum of the currents flowing through the first adjustable resistor R1 and the third resistor. The gate-source voltage, gate length, and gate width of the third transistor M2 are respectively equal to the gate-source voltage, gate length, and gate width of the first transistor M1. This can be achieved by using a corresponding number of smallest units with the same width-to-length ratio to form the first transistor M1 and the third transistor M2, ensuring the current mirror accuracy. The reference current IREF (i.e., the drain current of the third transistor M2) is M times the initial current (i.e., the drain current of the first transistor M1), where M is any number greater than 0. Therefore, the sum of the currents flowing through the first adjustable resistor R1 and the third adjustable resistor R3, i.e., IM3, can be expressed as the following calculation formula:

[0077] IM3=VREF÷[(R1+R2)∥R3]=VBG÷[(R1+R2)∥R3]×(1+R1 / R2) (5)

[0078] Where R3 represents the resistance value of the third adjustable resistor R3. (R1+R2)∥R3 represents the equivalent resistance of the first adjustable resistor R1 and the second resistor R2 connected in series and then connected in parallel with the third adjustable resistor R3.

[0079] Since both the first transistor M1 and the second transistor M3 are connected in series with the equivalent resistance in the same branch, the current flowing through the equivalent resistance, i.e., IM3, is equal to the current flowing through the first transistor M1 and the second transistor M3. Therefore, the reference current IREF can be expressed as follows:

[0080] IREF=M×IM3=M×VBG÷[(R1+R2)∥R3]×(1+R1 / R2) (6)

[0081] Where IREF represents the current value of the reference current IREF.

[0082] Once the output reference voltage VREF is determined, the reference current IREF can be calibrated by changing the resistance value of the third adjustable resistor R3. Figure 12 The formulas for calculating the reference voltage VREF and reference current IREF can be the above formulas (4) and (6).

[0083] Therefore, it can be seen that by adjusting the resistance value of the first adjustable resistor R1, the output reference voltage VREF can be adjusted. Once the output reference voltage VREF is determined, the output reference current IREF can be calibrated by adjusting the resistance value of the third adjustable resistor R3, without changing the output reference voltage VREF.

[0084] This application embodiment also provides a chip 200, such as Figure 13 As shown, the chip 200 includes the aforementioned reference signal generation circuit 100. The chip 200 is also called an integrated circuit (IC), and the chip 200 may be, but is not limited to, a SOC (System on Chip) chip or a SIP (System in Package) chip.

[0085] It is understood that since the chip 200 provided in this application embodiment includes the above-mentioned reference signal generation circuit 100, it can also generate a feedback voltage VFB based on the initial current through the voltage feedback unit 31 and output a corresponding reference voltage VREF. The reference voltage VREF can be adjusted separately. The current adjustment unit 32 can adjust the initial current to calibrate at least one reference current IREF while keeping the reference voltage VREF unchanged, so that the reference voltage VREF or the reference current IREF can be adjusted separately.

[0086] Furthermore, compared to only being able to calibrate one reference current IREF at a time, the current adjustment unit 32 of this application can adjust the initial current to simultaneously calibrate the reference current IREF of all paths, thereby improving the calibration efficiency of the reference current IREF.

[0087] This application also provides an electronic device 300, such as... Figure 14As shown, the electronic device 300 includes a device body and the aforementioned reference signal generating circuit 100 or chip 200 disposed within the device body. The electronic device 300 may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car center console screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.

[0088] It is understood that since the electronic device 300 provided in this application embodiment includes the above-mentioned reference signal generation circuit 100 or chip 200, it can also generate a feedback voltage VFB based on the initial current through the voltage feedback unit 31 and output a corresponding reference voltage VREF. The reference voltage VREF can be adjusted individually. The current adjustment unit 32 can adjust the initial current to calibrate at least one reference current IREF while keeping the reference voltage VREF unchanged, so that the reference voltage VREF or the reference current IREF can be adjusted individually.

[0089] Furthermore, compared to only being able to calibrate one reference current IREF at a time, the current adjustment unit 32 of this application can adjust the initial current to simultaneously calibrate the reference current IREF of all paths, thereby improving the calibration efficiency of the reference current IREF.

[0090] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A reference signal generation circuit, characterized in that, The reference signal generation circuit includes: An operational amplifier module, which outputs an operational amplifier signal based on the comparison result between a reference voltage and a feedback voltage; A mirroring module is used to generate a corresponding initial current under the control of the operational amplifier signal, and to mirror at least one reference current based on the initial current. A reference signal adjustment module includes a voltage feedback unit and a current adjustment unit. The voltage feedback unit generates a feedback voltage based on the initial current and outputs a corresponding reference voltage. The current adjustment unit adjusts the initial current to calibrate the at least one reference current while keeping the reference voltage constant. The voltage feedback unit includes a first adjustable resistor and a second resistor. The first adjustable resistor is used to adjust the reference voltage, and the second resistor is connected between the first adjustable resistor and the ground terminal. The current adjustment unit includes a third adjustable resistor, one end of which is connected to the mirror module and the other end of which is connected to the ground terminal; the third adjustable resistor is used to adjust the initial current and the at least one reference current while the reference voltage remains unchanged.

2. The reference signal generation circuit as described in claim 1, characterized in that, The mirror module includes: An initial current generating branch is used to generate the initial current. A current mirroring branch is connected to the initial current generating branch and is used to mirror at least one reference current based on the initial current.

3. The reference signal generation circuit as described in claim 2, characterized in that, The initial current generation branch includes a first transistor, the control electrode of the first transistor is connected to the output terminal of the operational amplifier module, the first electrode of the first transistor is connected to the power supply terminal, and the second electrode of the first transistor is connected to the voltage feedback unit and the current adjustment unit.

4. The reference signal generation circuit as described in claim 2, characterized in that, The initial current generation branch includes: The first transistor has its first terminal connected to the power supply terminal and its control terminal connected to its second terminal. The second transistor has its first terminal connected to the second terminal of the first transistor, its second terminal connected to the voltage feedback unit and the current adjustment unit, and its control terminal connected to the output terminal of the operational amplifier module.

5. The reference signal generation circuit as described in claim 3 or 4, characterized in that, The current mirror branch includes at least one third transistor, the control electrode of the at least one third transistor is connected to the control electrode of the first transistor, the first electrode of the at least one third transistor is connected to the power supply terminal, and the second electrode of the at least one third transistor is used to output the at least one reference current.

6. The reference signal generation circuit as described in claim 1, characterized in that, One end of the first adjustable resistor is connected to the mirror module and the operational amplifier module respectively, and the other end of the first adjustable resistor is used to output the reference voltage.

7. The reference signal generation circuit as described in claim 1, characterized in that, One end of the first adjustable resistor is connected to the mirror module and outputs the reference voltage, while the other end of the first adjustable resistor is connected to the operational amplifier module.

8. A chip, characterized in that, The chip includes a reference signal generation circuit as described in any one of claims 1 to 7.

9. An electronic device, characterized in that, The electronic device includes a device body and a chip as described in claim 8 disposed on the device body.

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