A trimming circuit for the reference voltage of a chip

Abstract

The present invention discloses a trimming circuit for the chip reference voltage, comprising: when the enable signal is at a high level, the low-enable discharge module is turned off, and the adjustable buffer unit generates a preset voltage according to an external reference voltage and a voltage regulation signal. The generated preset voltage passes through a low-pass filter network composed of a fast charging path, a slow charging path, and a filter capacitor to generate a reference voltage; the abnormal state detection unit is used for detecting the abnormality of the trimming circuit. If there is an abnormality, the output signal of the abnormal state detection unit is at a high level, controlling the output signal of the fast charging control unit to be at a low level, turning on the fast charging path, controlling the opening time of the fast charging path through the fast charging control unit, and inputting a following speed trimming signal to the fast charging control unit to trim the generated reference voltage to be the same as the preset voltage. The present invention adjusts the performance of the chip reference voltage through a trimming signal, which can meet the performance requirements of the device under different working conditions.

Description

Technical Field

[0001] The present invention relates to the technical fields of analog circuits and semiconductor integrated circuits, and specifically, to a trimming circuit for the reference voltage of a chip. Background Art

[0002] With the progress of information technology and the popularization of 5G networks, it is required that a new generation of high-performance electronic devices can operate at higher frequencies and have a higher signal-to-noise ratio. The noise on the power supply and the intrinsic noise of the device will significantly affect the performance of the electronic device. As the reference voltage of the chip serves as the reference for the entire circuit or system, not only does the reference voltage need to have good anti-interference ability, but also it needs to meet the requirements of the device in different working states. Therefore, it is necessary to trim the performance of the power supply reference voltage.

[0003] Figure 1 Fig. shows a reference voltage generation circuit proposed in the patent with the publication number CN113721690A, titled "Bandgap Reference Circuit and Its Control Method and Power Supply Circuit". By injecting a start-up current into the first-stage reference module through the start-up circuit module, the first-stage reference module is made to get out of the zero state and generate a first-stage reference voltage. The pre-regulated low-dropout linear regulator generates a second voltage signal LVDD that can suppress power supply noise based on the first-stage reference voltage, and at the same time powers the second-stage reference module. Through the way of circuit stacking and cascading, a reference voltage with low noise and high power supply rejection ratio is achieved at the output end of the second-stage reference module. However, this circuit does not have a trimming circuit and cannot trim the performance of the reference voltage according to the specific working state, so it cannot adjust the performance of the chip, cannot meet the requirements of the device, and reduces the yield of the chip. Summary of the Invention

[0004] Aiming at the problems existing in the prior art, the present invention provides a trimming circuit for the reference voltage of a chip, which introduces multiple trimming signals to adjust the performance of the reference voltage of the chip, and can meet the performance requirements of the device in different working states.

[0005] To achieve the above technical purpose, the present invention adopts the following technical solution: A trimming circuit for the reference voltage of a chip, comprising: an adjustable buffer unit, an abnormal state detection unit, a fast charging control unit, a fast charging path, a slow charging path, a filter capacitor C1, and a low-enable discharge module;

[0006] When the enable signal EN is at a high level, the low-enable discharge module is turned off, and the adjustable buffer unit generates a preset voltage V REF according to an external reference voltage V REF_PRE and a voltage regulation signal. The generated preset voltage V REF_PRE generates a reference voltage V REF_RC after passing through a low-pass filter network composed of a fast charging path, a slow charging path, and a filter capacitor C1;

[0007] The abnormal state detection unit is used for abnormal detection of the trimming circuit. If there is an abnormality, the output signal SH of the abnormal state detection unit is at a high level, the output signal ON of the fast charge control unit is at a low level, the fast charge path is opened, the fast charge control unit controls the opening time of the fast charge path, and a following speed trimming signal is input to the fast charge control unit to generate a reference voltage V REF_RC trimmed to be the same as the preset voltage V REF_PRE identical.

[0008] Further, when the enable signal EN is at a low level, the low enable discharge module is turned on, and the charge on the filter capacitor C1 flows through the low enable discharge module to the preset voltage V REF_PRE , and the preset voltage V REF_PRE is discharged to ground by the low enable discharge module.

[0009] Further, when the fast charge path is in an off state, the preset voltage V REF_PRE generates a reference voltage V with low noise and high power supply rejection ratio characteristics through the slow charge path and the filter capacitor C1 that trim the signal of the input filter resistor REF_RC .

[0010] Further, the adjustable buffer unit includes: an operational amplifier A1, a sixth PMOS transistor MP6, a first resistor R1, and an adjustable resistor R2. The non-inverting input terminal of the operational amplifier A1 is respectively connected to one end of the first resistor R1 and one end of the adjustable resistor R2. The other end of the first resistor R1 is grounded. The inverting input terminal of the operational amplifier A1 is connected to an external reference voltage V REF connection. The output terminal of the operational amplifier A1 is connected to the gate of the sixth PMOS transistor MP6. The source of the sixth PMOS transistor MP6 is connected to the power supply voltage VIN. The drain of the sixth PMOS transistor MP6 and the other end of the adjustable resistor R2 are used as the output terminal of the adjustable buffer unit and are connected to the input terminal of the low enable discharge module, the input terminal of the fast charge path, and the input terminal of the slow charge path; the resistance value of the adjustable resistor R2 is controlled by the y-channel voltage regulation signal, and the control terminal of the operational amplifier A1 is connected to the enable signal EN.

[0011] Further, the abnormal state detection unit includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a current source I1, a first capacitor C2, a second capacitor C3, a first Schmitt inverter SMIT1, a first inverter INV1, and an OR gate OR1. The gate of the fourth NMOS transistor MN4 and the input terminal of the first inverter INV1 are both connected to the enable signal EN. The source of the fourth NMOS transistor MN4 is connected to the input terminal of the current source I1, and the output terminal of the current source I1 is grounded. The drain of the fourth NMOS transistor is respectively connected to the gate of the fifth PMOS transistor MP5, the drain of the fifth PMOS transistor MP5, the gate of the fourth PMOS transistor MP4, the gate of the third PMOS transistor MP3, the gate of the second PMOS transistor MP2, and the gate of the first PMOS transistor MP1. The sources of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 are all connected to the power supply voltage VIN. The drain of the fourth PMOS transistor MP4 and the output terminal of the OR gate OR1 are both connected to the fast charge control unit. The drain of the third PMOS transistor MP3 is respectively connected to one end of the second capacitor C3, the input terminal of the first Schmitt inverter SMIT1, and the drain of the third NMOS transistor MN3. The other end of the third capacitor C3 and the source of the third NMOS transistor MN3 are both grounded, and the gate of the third NMOS transistor MN3 is connected to the output terminal of the first inverter INV1. The output terminal of the first Schmitt inverter SMIT1 is connected to the first input terminal of the OR gate OR1. The drain of the second PMOS transistor MP2 is respectively connected to one end of the first capacitor C2, the drain of the second NMOS transistor MN2, and the second input terminal of the OR gate OR1. The other end of the first capacitor C2 and the source of the second NMOS transistor MN2 are both grounded, and the gate of the second NMOS transistor MN2 is connected to the output terminal of the operational amplifier A1 in the adjustable buffer unit. The drain of the first PMOS transistor MP1 is respectively connected to the drain and the gate of the first NMOS transistor MN1, and the source of the first NMOS transistor MN1 is grounded. The third input terminal of the OR gate OR1 is connected to the y-channel voltage regulation signal.

[0012] Further, the fast charging control unit includes: a fifth NMOS transistor MN5, a third capacitor C4, a second Schmitt inverter SMIT2, and a second inverter INV2. The gate of the fifth NMOS transistor MN5 is connected to the output terminal of the OR gate OR1. The drain of the fifth NMOS transistor MN5 is respectively connected to the drain of the fourth PMOS transistor MP4, one end of the third capacitor C4, and the input terminal of the second Schmitt inverter SMIT2. The other end of the third capacitor C4 and the source of the fifth NMOS transistor MN5 are both grounded. The output terminal of the second Schmitt inverter SMIT2 is connected to the input terminal of the second inverter INV2. The output terminal of the second inverter INV2 is connected to the fast charging path.

[0013] Further, the low enable discharge module includes: a sixth NMOS transistor MN6 and a seventh NMOS transistor MN7. The drains of the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 are both connected to the output terminal of the adjustable buffer unit. The source of the sixth NMOS transistor MN6 is grounded. The source of the seventh NMOS transistor MN7 is respectively connected to the output terminal of the fast charging path, the output terminal of the slow charging path, and one end of the filter capacitor C1. The gates of the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 are both connected to the output terminal of the first inverter INV1.

[0014] Further, the fast charging path includes: m + 1 tenth PMOS transistors, m eleventh PMOS transistors, and m + 1 second resistors RA. The gates of the m + 1 tenth PMOS transistors are all connected to the output terminal of the second inverter INV2 in the fast charging control unit. The sources of the m + 1 tenth PMOS transistors are all used as the input terminals of the fast charging path and are connected to the output terminal of the adjustable buffer unit. The drain of the first tenth PMOS transistor is connected to one end of the first second resistor RA. The drains of the subsequent m tenth PMOS transistors are respectively connected to the sources of one eleventh PMOS transistor. The gates of the m eleventh PMOS transistors are respectively connected to a following speed adjustment signal. The drains of the m eleventh PMOS transistors are respectively connected to one end of the subsequent m second resistors RA. The other ends of the m + 1 second resistors RA are all used as the output terminals of the fast charging path to generate a reference voltage V REF_RC , and are connected to one end of the filter capacitor C1.

[0015] Further, the slow charging path includes: a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a third resistor R3, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, n twelfth PMOS transistors, and n tenth NMOS transistors. The sources of the seventh PMOS transistor MP7, the ninth PMOS transistor MP9, and the n twelfth PMOS transistors are all connected to the output end of the adjustable buffer unit as the input end of the slow charging path; the drain of the seventh PMOS transistor MP7 is connected to the source of the eighth PMOS transistor MP8, and the gates of the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, and the drain of the ninth PMOS transistor MP9 are all connected to the drain of the ninth NMOS transistor MN9. The drain of the eighth PMOS transistor MP8 is connected to one end of the third resistor R3, and the other end of the third resistor R3 serves as the output end of the slow charging path to generate a reference voltage V REF_RC , and is connected to one end of the filter capacitor C1; the gates of the ninth NMOS transistor MN9, the eighth NMOS transistor MN8, and the n tenth NMOS transistors are all connected to the gate of the first NMOS transistor MN1 in the abnormal state detection unit. The sources of the ninth NMOS transistor MN9 and the n tenth NMOS transistors are all connected to the drain of the eighth NMOS transistor MN8, and the source of the eighth NMOS transistor MN8 is grounded; the drains of the n tenth NMOS transistors are respectively connected to the drains of one twelfth PMOS transistor, and the gates of the n twelfth PMOS transistors are respectively connected to one filter resistor trimming signal.

[0016] Further, the other end of the filter capacitor C1 is grounded.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] (1) The trimming circuit of the chip reference voltage of the present invention generates a preset voltage according to the adjustable buffer unit of the input voltage regulation signal, and through the introduction of the follow-up speed trimming signal and the filter resistor trimming signal, finely trims the performance such as the noise, power supply rejection ratio, and follow-up speed of the preset voltage to obtain the reference voltage, which can not only meet the performance requirements of the chip in different working states, but also improve the yield of the chip;

[0019] (2) The trimming circuit of the chip reference voltage of the present invention is also provided with an abnormal state detection unit to realize the abnormal detection of the trimming circuit, and open the fast charging path. By controlling the opening time of the fast charging path, the reference voltage is quickly trimmed to be the same as the preset voltage, so that the chip quickly reaches a stable state and ensures the normal operation of the chip;

[0020] (3)The trimming circuit of the reference voltage of the chip of the present invention is further provided with a low-enable discharge module, which provides a discharge path for the reference voltage when the trimming circuit is in low enable, so that there is no reference residual voltage affecting the performance of the subsequent circuit, ensuring the safety and stability of the subsequent circuit. Description of the Drawings

[0021] Figure 1 It is a schematic diagram of a reference voltage generation circuit in the prior art;

[0022] Figure 2 It is a schematic diagram of the trimming circuit of the reference voltage of the chip of the present invention;

[0023] Figure 3 It is a circuit diagram of the abnormal state detection unit and the fast charging control unit in the present invention;

[0024] Figure 4 It is a circuit diagram of the adjustable buffer unit and the low-enable discharge module in the present invention;

[0025] Figure 5 It is a circuit diagram of the low-pass filter network in the present invention. Detailed Embodiment

[0026] The technical solution of the present invention will be further explained below with reference to the drawings.

[0027] As Figure 2 It is a schematic diagram of the trimming circuit of the reference voltage of the chip of the present invention. The trimming circuit includes: an adjustable buffer unit 101, an abnormal state detection unit 102, a fast charging control unit 103, a fast charging path 104, a slow charging path 105, a filter capacitor C1 106, and a low-enable discharge module 107;

[0028] When the enable signal EN is at a high level, the low-enable discharge module 107 is turned off, and the adjustable buffer unit 101 generates a preset voltage V according to the external reference voltage V REF and the voltage regulation signal REF_PRE . The generated preset voltage V REF_PRE generates a reference voltage V REF_RC after passing through the low-pass filter network composed of the fast charging path 104, the slow charging path 105, and the filter capacitor C1 106. Specifically, the fast charging path 104 is a low-impedance path, which is controlled by the output signal ON of the fast charging control unit 103 and is used to quickly charge the filter capacitor C1 106 to quickly establish the reference voltage V REF_RC . After the fast charging path 104 is turned off, the low-pass filter network is composed of the high-impedance slow charging path 105 and the filter capacitor C1 106. The preset voltage V REF_PRE passes through the slow charging path 105 of the input filter resistance trimming signal and the filter capacitor C1 106, so that the preset voltage V REF_PREbecomes a reference voltage V with low noise and high power supply rejection ratio characteristics REF_RC , which can effectively suppress the clutter on the power supply and the intrinsic noise of the device, and improve the anti-interference ability of the chip.

[0029] The abnormal state detection unit 102 is used for abnormal detection of the trimming circuit. If there is an abnormality, the output signal SH of the abnormal state detection unit 102 is at a high level, and the output signal ON of the fast charge control unit 103 is at a low level. The fast charge path 104 is opened, and the fast charge control unit 103 controls the opening time of the fast charge path 104, and inputs a following speed trimming signal to the fast charge control unit 103 to ensure that the reference voltage V REF_RC can quickly follow the preset voltage V REF_PRE changes and is fully stabilized to the preset voltage V REF_PRE .

[0030] When the enable signal EN is at a low level, the low enable discharge module 107 is turned on, and the charge on the filter capacitor C1 106 flows through the low enable discharge module 107 to the preset voltage V REF_PRE , and the preset voltage V REF_PRE is discharged to ground by the low enable discharge module 107, so that there is no reference residual voltage that affects the performance of the subsequent circuit, and unknown risks to the chip are avoided.

[0031] The trimming circuit based on the chip reference voltage of the present invention introduces a variety of trimming signals to adjust the performance of the reference voltage, which can not only meet the performance requirements of the chip in different working states, but also improve the yield of the chip.

[0032] For example Figure 4 , the adjustable buffer unit 101 includes: an operational amplifier A1, a sixth PMOS transistor MP6, a first resistor R1, and an adjustable resistor R2. The non-inverting input terminal of the operational amplifier A1 is respectively connected to one end of the first resistor R1 and one end of the adjustable resistor R2. The other end of the first resistor R1 is grounded. The inverting input terminal of the operational amplifier A1 is connected to the external reference voltage V REF . The output terminal of the operational amplifier A1 is connected to the gate of the sixth PMOS transistor MP6. The source of the sixth PMOS transistor MP6 is connected to the power supply voltage VIN. The drain of the sixth PMOS transistor MP6 and the other end of the adjustable resistor R2 are used as the output terminal of the adjustable buffer unit 101 and are connected to the input terminals of the low enable discharge module 107, the fast charge path 104, and the slow charge path 105. The resistance value of the adjustable resistor R2 is controlled by the y-channel voltage regulation signal. The control terminal of the operational amplifier A1 is connected to the enable signal EN. By setting the voltage regulation signal, the adjustable buffer unit 101 can output a high-precision preset voltage V REF_PRE , V REF_PRE = [1+(R2) / (R1)]×V REF .

[0033] As Figure 3 shown in Figure 3 , the abnormal state detection unit 102 includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a current source I1, a first capacitor C2, a second capacitor C3, a first Schmitt inverter SMIT1, a first inverter INV1, and an OR gate OR1. The gate of the fourth NMOS transistor MN4 and the input terminal of the first inverter INV1 are both connected to the enable signal EN. The source of the fourth NMOS transistor MN4 is connected to the input terminal of the current source I1, and the output terminal of the current source I1 is grounded. The drain of the fourth NMOS transistor is respectively connected to the gate of the fifth PMOS transistor MP5, the drain of the fifth PMOS transistor MP5, the gate of the fourth PMOS transistor MP4, the gate of the third PMOS transistor MP3, the gate of the second PMOS transistor MP2, and the gate of the first PMOS transistor MP1. The sources of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 are all connected to the power supply voltage VIN. The drain of the fourth PMOS transistor MP4 and the output terminal of the OR gate OR1 are both connected to the fast charge control unit 103. The drain of the third PMOS transistor MP3 is respectively connected to one end of the second capacitor C3, the input terminal of the first Schmitt inverter SMIT1, and the drain of the third NMOS transistor MN3. The other end of the third capacitor C3 and the source of the third NMOS transistor MN3 are both grounded. The gate of the third NMOS transistor MN3 is connected to the output signal ENL of the output terminal of the first inverter INV1. The output terminal of the first Schmitt inverter SMIT1 is connected to the first input terminal of the OR gate OR1. The drain of the second PMOS transistor MP2 is respectively connected to one end of the first capacitor C2, the drain of the second NMOS transistor MN2, and the second input terminal of the OR gate OR1. The other end of the first capacitor C2 and the source of the second NMOS transistor MN2 are both grounded. The output signal PGATE of the gate of the second NMOS transistor MN2 is connected to the output terminal of the operational amplifier A1 in the adjustable buffer unit 101. The drain of the first PMOS transistor MP1 is respectively connected to the drain and the gate of the first NMOS transistor MN1, and the source of the first NMOS transistor MN1 is grounded. The third input terminal of the OR gate OR1 is connected to the y-channel voltage regulation signal.

[0034] The abnormal state detection unit 102 is capable of detecting three abnormal states:

[0035] The first case is that the enable signal EN flips from low to high: when the enable signal EN is low, the fourth NMOS transistor MN4 is turned off, and the current mirror composed of the first PMOS transistor MP1 to the fifth PMOS transistor MP5 is turned off, and no current charges the second capacitor C3; at the same time, the third NMOS transistor MN3 is turned on, and the second capacitor C3 discharges through the third NMOS transistor MN3, making the input signal of the first Schmitt inverter SMIT1 be 0; after the enable signal EN flips from low to high, the third NMOS transistor MN3 is turned off, the fourth NMOS transistor MN4 is turned on, and the current mirror charges the second capacitor C3, but it takes a certain delay for the first Schmitt inverter SMIT1 to reach the flip threshold. Therefore, during this period, the input signal of the first Schmitt inverter SMIT1 is still 0, so that the output signal SH of the NOR gate is high level, that is, an abnormal state is detected by the abnormal state detection unit 102.

[0036] The second case is that the power supply voltage VIN is lower than the preset voltage V output by the adjustable buffer unit 101 REF_PRE : In this state, the output voltage of the operational amplifier A1 is 0, the second NMOS transistor MN2 is turned off, and the current mirror charges the first capacitor C2, quickly pulling the end connected to the first capacitor C2, the drain of the second NMOS transistor MN2, and the drain of the second PMOS transistor MP2 to a high level, so that the output signal SH of the NOR gate is high level, that is, an abnormal state is detected by the abnormal state detection unit 102.

[0037] The third case is that any change occurs in the voltage regulation signal: when any change occurs in the y-channel voltage regulation signal, a high-level pulse signal is output, so that the output signal SH of the NOR gate is high level, that is, an abnormal state is detected by the abnormal state detection unit 102.

[0038] Such as Figure 3, the fast charging control unit 103 includes: a fifth NMOS transistor MN5, a third capacitor C4, a second Schmitt inverter SMIT2, and a second inverter INV2. The gate of the fifth NMOS transistor MN5 is connected to the output terminal of the OR gate OR1. The drain of the fifth NMOS transistor MN5 is respectively connected to the drain of the fourth PMOS transistor MP4, one end of the third capacitor C4, and the input terminal of the second Schmitt inverter SMIT2. The other end of the third capacitor C4 and the source of the fifth NMOS transistor MN5 are both grounded. The output terminal of the second Schmitt inverter SMIT2 is connected to the input terminal of the second inverter INV2. The output terminal of the second inverter INV2 is connected to the fast charging path 104. When an abnormal state is detected, the output signal SH of the abnormal state detection unit 102 is at a high level, the fifth NMOS transistor MN5 is turned on, and the charge on the third capacitor C4 is quickly discharged to the ground through the fifth NMOS transistor MN5. Then, after passing through the second Schmitt inverter SMIT2 and the second inverter INV2, the output signal ON is at a low level, so as to open the fast charging path 104. When the abnormal state ends, the output signal SH of the abnormal state detection unit 102 is at a low level, the fifth NMOS transistor MN5 is turned off, and the third capacitor C4 is charged through the fourth PMOS transistor MP4. When the level on the third capacitor C4 reaches the switching threshold of the second Schmitt inverter SMIT2, the second Schmitt inverter SMIT2 outputs a low level, and the output terminal signal ON of the second inverter INV2 is at a high level, so that the fast charging path 104 is turned off. The present invention controls the magnitude of the charging current through the third capacitor C4 and the fourth PMOS transistor MP4, and can control the opening time of the fast charging path 104, so as to ensure that the reference voltage V REF_RC is fully stabilized to the preset voltage V REF_PRE .

[0039] For example Figure 4 , the low enable discharge module 107 includes: a sixth NMOS transistor MN6 and a seventh NMOS transistor MN7. The drains of the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 are both connected to the output terminal of the adjustable buffer unit 101. The source of the sixth NMOS transistor MN6 is grounded. The source of the seventh NMOS transistor MN7 is respectively connected to the output terminal of the fast charging path 104, the output terminal of the slow charging path 105, and one end of the filter capacitor C1 106. The gates of the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 are both connected to the output signal ENL of the output terminal of the first inverter INV1. When the enable signal EN is at a low level, the signal ON output by the fast charging control unit 103 is also at a low level, controlling the fast charging path 104 to open. Although at this time the preset voltage V REF_PRE and the reference voltage V REF_RCThey are connected through the fast charging path 104. However, due to the large capacitance value of the filter capacitor C1 106, after the enable signal EN changes from high to low, it takes a long time for the filter capacitor C1 106 to completely discharge the charge through the low-resistance path. The residual voltage on the filter capacitor C1 106 will deteriorate the performance of the subsequent circuit. The present invention adds a low-enable discharge module 107. When the enable signal EN is at a low level, the signal output after passing through the first inverter INV1 is at a high level, and the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 are turned on, and the preset voltage V REF_PRE is discharged to ground through the sixth NMOS transistor MN6; as the preset voltage V REF_PRE decreases, the charge on the filter capacitor C1 106 will flow through the seventh NMOS transistor MN7 to the preset voltage V REF_PRE , and finally is discharged to ground. Since both the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 are switching transistors and their impedance is close to zero, therefore, the charge on the filter capacitor C1 106 will be quickly discharged. When the enable signal EN becomes high, the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 are turned off, which will not affect the normal operation of the trimming circuit.

[0040] As Figure 5 , the fast charging path 104 includes: m + 1 tenth PMOS transistors AP, m eleventh PMOS transistors BP, m + 1 second resistors RA. The gates of the m + 1 tenth PMOS transistors AP are all connected to the output terminal of the second inverter INV2 in the fast charging control unit 103. The sources of the m + 1 tenth PMOS transistors AP are all used as the input terminals of the fast charging path 104 and are connected to the output terminal of the adjustable buffer unit 101; the drain of the first tenth PMOS transistor AP is connected to one end of the first second resistor RA, and the drains of the subsequent m tenth PMOS transistors AP are respectively connected to the sources of one eleventh PMOS transistor BP. The gates of the m eleventh PMOS transistors BP are respectively connected to a following speed trimming signal, and the drains of the m eleventh PMOS transistors BP are respectively connected to one ends of the subsequent m second resistors RA; the other ends of the m + 1 second resistors RA are all used as the output terminals of the fast charging path 104 to generate a reference voltage V REF_RC , and are connected to one end of the filter capacitor C1 106, and the other end of the filter capacitor C1 106 is grounded. When the abnormal state detection unit 102 detects an abnormal state, the output signal SH of the abnormal state detection unit 102 is at a high level, and the fifth NMOS transistor MN5 is turned on, and then the output signal ON of the fast charging control unit is set low, so that the low-resistance fast charging path 104 between the preset voltage V REF_PRE and the reference voltage V REF_RC is opened, and the reference voltage V REF_RC can quickly follow the preset voltage V REF_PREThe change, specifically, the equivalent impedance of the fast charging path 104 is determined by m + 1 second resistors RA. m eleventh PMOS transistors BP are controlled by m path following speed trimming signals. By setting the following speed trimming signals, the change speed of the reference voltage V REF_RC with the preset voltage V REF_PRE can be changed. The more PMOS transistors that are turned on in the eleventh PMOS transistor BP controlled by the following speed trimming signal, the more second resistors RA are connected in parallel to the circuit, and the smaller the equivalent impedance of the fast charging path 104, making the reference voltage V REF_RC change with the preset voltage V REF_PRE faster. For different application scenarios, the trimming speed of the reference voltage V REF_RC can be adjusted by adjusting the following speed trimming signal, so as to meet different application requirements. After all abnormal states end, the output signal SH of the abnormal state detection unit 102 is set to 0, the fifth NMOS transistor MN5 is turned off, and the fourth PMOS transistor MP4 charges the fourth capacitor C4. By setting a reasonable delay, it is ensured that when the output signal ON of the fast charging control unit is at a high level, that is, when the fast charging path 104 is turned off, the reference voltage V REF_RC has been fully stabilized to the preset voltage V REF_PRE .

[0041] For example Figure 5 , the slow charging path 105 includes: a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a third resistor R3, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, n twelfth PMOS transistors CP, and n tenth NMOS transistors CN. The sources of the seventh PMOS transistor MP7, the ninth PMOS transistor MP9, and the n twelfth PMOS transistors CP are all used as the input end of the slow charging path 105 and are connected to the output end of the adjustable buffer unit 101; the drain of the seventh PMOS transistor MP7 is connected to the source of the eighth PMOS transistor MP8, and the gates of the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, and the drain of the ninth PMOS transistor MP9 are all connected to the drain of the ninth NMOS transistor MN9. The drain of the eighth PMOS transistor MP8 is connected to one end of the third resistor R3, and the other end of the third resistor R3 serves as the output end of the slow charging path 105 to generate the reference voltage V REF_RCand is connected to one end of the filter capacitor C1 106; the gates of the ninth NMOS transistor MN9, the eighth NMOS transistor MN8, and the gates of the n tenth NMOS transistors CN are all connected to the output signal VBN of the gate of the first NMOS transistor MN1 in the abnormal state detection unit 102. The sources of the ninth NMOS transistor MN9 and the n tenth NMOS transistors CN are all connected to the drain of the eighth NMOS transistor MN8, and the source of the eighth NMOS transistor MN8 is grounded; the drains of the n tenth NMOS transistors CN are respectively connected to the drains of an n twelfth PMOS transistors CP, and the gates of the n twelfth PMOS transistors CP are respectively connected to a filter resistor trimming signal. When the fast-pass path 104 is in the off state, the low-pass filter network is only composed of the high-resistance slow-charge path 105 and the large filter capacitor C1 106 connected in series, and the preset voltage V REF_PRE After passing through this low-pass filter network, a reference voltage V with the characteristics of low noise and high power supply rejection ratio can be obtained REF_RC , specifically, the current of the eighth NMOS transistor MN8 is continuously copied by the external current source I1, and its value is I. The n twelfth PMOS transistors CP are controlled by the n-channel filter resistor trimming signals. By setting the filter resistor trimming signals, the equivalent resistance value of the slow-charge path 105 can be changed, and the total aspect ratio of the n tenth NMOS transistors CN connected to the circuit is (W / L) CN , and the current flowing through the ninth PMOS transistor MP9 operating in the saturation region is:

[0042]

[0043]

[0044] where K represents the process constant, represents the gate-source voltage difference of the ninth PMOS transistor MP9, represents the threshold voltage of the PMOS transistor;

[0045] The seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 operate in the linear region, and V GS,MP7 = V GS,MP8 = V GS,MP9 , and the impedances of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 are respectively:

[0046]

[0047]

[0048] Therefore, the equivalent impedance R of the slow-charge path eff =R MP7 + R MP8+R3. The more PMOS transistors in the twelfth PMOS transistor CP are turned on, the more the corresponding tenth NMOS transistor CN is connected to the circuit, and the larger the (W / L) CN dimension is, that is, the smaller the current flowing through the ninth PMOS transistor MP9 is, the larger the equivalent resistance value of the slow charging path 105 is, and the better the filtering performance is.

[0049] Based on the reference voltage trimming circuit of the present invention, by introducing various trimming signals, the performance of the reference voltage is finely trimmed, which can not only meet the performance requirements of the chip in different working states, but also improve the yield of the chip. Among them, the resistance value of the adjustable resistor R2 is controlled by the y-channel voltage regulation signal. By setting the voltage regulation signal, the adjustable buffer unit 101 can output a high-precision preset voltage V REF_PRE ; m eleventh PMOS transistors BP are controlled by m path following speed trimming signals. By setting the following speed trimming signals, the change speed of the reference voltage V REF_RC with respect to the preset voltage V REF_PRE can be changed. The more PMOS transistors in the eleventh PMOS transistor BP are turned on, the smaller the equivalent impedance of the fast charging path 104 is, and the faster the change speed of the reference voltage V REF_RC with respect to the preset voltage V REF_PRE is. n twelfth PMOS transistors CP are controlled by n path filtering resistor trimming signals. By setting the filtering resistor trimming signals, the equivalent resistance value of the slow charging path 105 can be changed. The more PMOS transistors in the twelfth PMOS transistor CP are turned on, the smaller the current flowing through the ninth PMOS transistor MP9 is, and the larger the equivalent resistance value of the slow charging path 105 is, and the better the filtering performance is.

[0050] The above is only the preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiment. All technical solutions within the idea of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements should be regarded as the protection scope of the present invention.

Claims

1. A chip reference voltage trimming circuit, characterized in that: include: An adjustable buffer unit (101), an abnormal state detection unit (102), a fast charging control unit (103), a fast charging path (104), a slow charging path (105), a filter capacitor C1 (106) and a low-enable discharge module (107); When the enable signal EN is at a high level, the low enable discharge module (107) is turned off, and the adjustable buffer unit (101) is adjusted according to the external reference voltage V REF and the voltage regulation signal to generate a preset voltage V REF_PRE , the preset voltage V REF_PRE A reference voltage V is generated after passing through a low-pass filter network composed of a fast charging path (104), a slow charging path (105) and a filter capacitor C1 (106). REF_RC ; When the enable signal EN is at a low level, the low enable discharge module (107) is turned on, and the charge on the filter capacitor C1 (106) flows to the preset voltage V through the low enable discharge module (107). REF_PRE , and the preset voltage V REF_PRE Discharging to ground by a low enable discharge module (107); The abnormal state detection unit (102) is used for detecting abnormalities of the adjustment circuit. If an abnormality exists, the output signal SH of the abnormal state detection unit (102) is high level, the output signal ON of the fast charge control unit (103) is controlled to be low level, the fast charge path (104) is opened, the opening time of the fast charge path (104) is controlled by the fast charge control unit (103), and a follow speed adjustment signal is input to the fast charge control unit (103), so that the generated reference voltage V REF_RC Adjust to the preset voltage V REF_PRE same; The adjustable buffer unit (101) comprises: an operational amplifier A1, a sixth PMOS transistor MP6, a first resistor R1, and an adjustable resistor R2, wherein the in-phase input terminal of the operational amplifier A1 is respectively connected to one end of the first resistor R1 and one end of the adjustable resistor R2, the other end of the first resistor R1 is grounded, and the inverting input terminal of the operational amplifier A1 is connected to an external reference voltage V REF The output end of the operational amplifier A1 is connected to the gate of the sixth PMOS tube MP6, the source of the sixth PMOS tube MP6 is connected to the power supply voltage VIN, the drain of the sixth PMOS tube MP6 and the other end of the adjustable resistor R2 are connected as the output end of the adjustable buffer unit (101) to the low-enable discharge module (107), the input end of the fast charging path (104) and the input end of the slow charging path (105); the resistance value of the adjustable resistor R2 is controlled by the y-path voltage regulation signal, and the control end of the operational amplifier A1 is connected to the enable signal EN; The abnormal state detection unit (102) comprises: a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a current source I1, a first capacitor C2, a second capacitor C3, a first Schmidt inverter SMIT1, a first inverter INV1 and an OR gate OR1, the gate of the fourth NMOS tube MN4 and the input end of the first inverter INV1 are both connected to an enable signal EN, and the fourth NMOS tube MN4 is connected to an enable signal EN. The source of the MOS tube MN4 is connected to the input end of the current source I1, and the output end of the current source I1 is grounded; the drain of the fourth NMOS tube MN4 is respectively connected to the gate of the fifth PMOS tube MP5, the drain of the fifth PMOS tube MP5, the gate of the fourth PMOS tube MP4, the gate of the third PMOS tube MP3, the gate of the second PMOS tube MP2, and the gate of the first PMOS tube MP1; the source of the first PMOS tube MP1, the source of the second PMOS tube MP2, the source of the third PMOS tube MP3, the source of the fourth PMOS tube MP4, and the source of the fifth PMOS tube MP5 are all connected to the current source I1. The source voltage VIN is connected; the drain of the fourth PMOS tube MP4 and the output end of the OR gate OR1 are both connected to the fast charging control unit (103); the drain of the third PMOS tube MP3 is respectively connected to one end of the second capacitor C3, the input end of the first Schmitt inverter SMIT1, and the drain of the third NMOS tube MN3; the other end of the second capacitor C3 and the source of the third NMOS tube MN3 are both grounded; the gate of the third NMOS tube MN3 is connected to the output end of the first inverter INV1; the output end of the first Schmitt inverter SMIT1 is connected to the first input end of the OR gate OR1; the second The drain of the PMOS transistor MP2 is respectively connected to one end of the first capacitor C2, the drain of the second NMOS transistor MN2, and the second input end of the OR gate OR1; the other end of the first capacitor C2 and the source of the second NMOS transistor MN2 are both grounded; the gate of the second NMOS transistor MN2 is connected to the output end of the operational amplifier A1 in the adjustable buffer unit (101); the drain of the first PMOS transistor MP1 is respectively connected to the drain of the first NMOS transistor MN1 and the gate of the first NMOS transistor MN1; the source of the first NMOS transistor MN1 is grounded; the third input end of the OR gate OR1 is connected to the y-channel voltage regulation signal; The fast charging control unit (103) comprises: a fifth NMOS tube MN5, a third capacitor C4, a second Schmidt inverter SMIT2 and a second inverter INV2, the gate of the fifth NMOS tube MN5 is connected to the output end of the OR gate OR1, the drain of the fifth NMOS tube MN5 is respectively connected to the drain of the fourth PMOS tube MP4, one end of the third capacitor C4 and the input end of the second Schmidt inverter SMIT2, the other end of the third capacitor C4 and the source of the fifth NMOS tube MN5 are both grounded, the output end of the second Schmidt inverter SMIT2 is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is connected to the fast charging path (104); The low-enable discharge module (107) comprises: a sixth NMOS tube MN6 and a seventh NMOS tube MN7, wherein the drain of the sixth NMOS tube MN6 and the drain of the seventh NMOS tube MN7 are both connected to the output end of the adjustable buffer unit (101); the source of the sixth NMOS tube MN6 is grounded, and the source of the seventh NMOS tube MN7 is respectively connected to the output end of the fast charging path (104), the output end of the slow charging path (105), and one end of the filter capacitor C1 (106); and the gate of the sixth NMOS tube MN6 and the gate of the seventh NMOS tube MN7 are both connected to the output end of the first inverter INV1.

2. A chip reference voltage trimming circuit according to claim 1, characterized in that: When the fast charging path (104) is in the off state, the preset voltage V REF_PRE The slow charging path (105) of the input filter resistor trimming signal and the filter capacitor C1 (106) generate a reference voltage V with low noise and high power supply rejection ratio characteristics. REF_RC .

3. The chip reference voltage trimming circuit according to claim 1, characterized in that: The fast charging path (104) comprises: m+1 tenth PMOS tubes, m eleventh PMOS tubes, and m+1 second resistors RA; the gates of the m+1 tenth PMOS tubes are connected to the output end of the second inverter INV2 in the fast charging control unit (103); the sources of the m+1 tenth PMOS tubes are connected to the output end of the adjustable buffer unit (101) as the input end of the fast charging path (104); the drain of the first tenth PMOS tube is connected to one end of the first second resistor RA; the drains of the next m tenth PMOS tubes are respectively connected to the source of an eleventh PMOS tube; the gates of the m eleventh PMOS tubes are respectively connected to a follow-up speed adjustment signal; the drains of the m eleventh PMOS tubes are respectively connected to one end of the next m second resistors RA; the other ends of the m+1 second resistors RA are used as the output end of the fast charging path (104) to generate a reference voltage V REF_RC , and connected to one end of the filter capacitor C1 (106).

4. The chip reference voltage trimming circuit according to claim 1, characterized in that: The slow charging path (105) comprises: a seventh PMOS tube MP7, an eighth PMOS tube MP8, a ninth PMOS tube MP9, a third resistor R3, an eighth NMOS tube MN8, a ninth NMOS tube MN9, n twelfth PMOS tubes and n tenth NMOS tubes; the source of the seventh PMOS tube MP7, the source of the ninth PMOS tube MP9 and the source of the n twelfth PMOS tubes are all connected to the output end of the adjustable buffer unit (101) as the input end of the slow charging path (105); the drain of the seventh PMOS tube MP7 is connected to the source of the eighth PMOS tube MP8; the gate of the seventh PMOS tube MP7, the gate of the eighth PMOS tube MP8, the gate of the ninth PMOS tube MP9 and the drain of the ninth PMOS tube MP9 are all connected to the drain of the ninth NMOS tube MN9; the drain of the eighth PMOS tube MP8 is connected to one end of the third resistor R3; the other end of the third resistor R3 is used as the output end of the slow charging path (105) to generate a reference voltage V REF_RC , and connected to one end of the filter capacitor C1 (106); the gate of the ninth NMOS tube MN9, the gate of the eighth NMOS tube MN8 and the gates of the n tenth NMOS tubes are all connected to the gate of the first NMOS tube MN1 in the abnormal state detection unit (102); the source of the ninth NMOS tube MN9 and the source of the n tenth NMOS tubes are all connected to the drain of the eighth NMOS tube MN8, and the source of the eighth NMOS tube MN8 is grounded; the drains of the n tenth NMOS tubes are respectively connected to the drain of a twelfth PMOS tube, and the gates of the n twelfth PMOS tubes are respectively connected to a filter resistance adjustment signal.

5. The chip reference voltage trimming circuit according to claim 1, characterized in that: The other end of the filter capacitor C1 (106) is grounded.

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