Memory management method and storage device

Abstract

The present invention provides a memory management method and a storage device. The method comprises: obtaining a first read count corresponding to a first physical unit in a first physical management unit; obtaining an average read count corresponding to the first physical management unit; obtaining a first evaluation value corresponding to the first physical management unit according to the first read count and the average read count, wherein the first evaluation value reflects the uneven degree of read operations respectively performed on multiple physical units in the first physical management unit; and performing a read verification operation on the first physical management unit if the first evaluation value is greater than a triggering threshold value. Thus, the accuracy of triggering the read verification operation on the physical management unit can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory management method and a storage device. Background Art

[0002] Digital cameras, mobile phones and MP3s have grown rapidly in the past few years, which has led to a rapid increase in consumer demand for storage media. Rewritable non-volatile memory is most suitable for portable electronic products such as laptops because of its characteristics of data non-volatility, power saving, small size, no mechanical structure, and fast read and write speed. For example, a solid-state drive is a memory storage device that uses a fast memory module as a storage medium. Therefore, the fast memory industry has become a very popular part of the electronics industry in recent years.

[0003] In general, a rewritable non-volatile memory module usually includes multiple physical erase units, and each physical erase unit includes multiple physical programming pages. When the data stored in a physical programming unit in a physical erase unit is read multiple times (for example, 100,000 to 1 million times), the data stored in this physical programming unit is also likely to generate error bits or loss due to the applied read voltage, and may even cause the data stored in other physical programming units in the same physical erase unit to generate error bits or loss. This phenomenon is called "read disturbance". "Read Disturb" refers to a phenomenon that may affect the integrity of the data in the storage unit. When a storage unit is frequently read, this read operation may interfere with the adjacent storage units, which may cause the data of those storage units that are not directly accessed to change or be damaged. Specifically, in the NAND Flash structure, data is read and written in pages, while erasure needs to be performed in blocks. Each page is connected by a word line (WL), and the pages are physically closely adjacent to each other. When a page is read multiple times, the floating gate voltage around it may indirectly affect the floating gate voltage state of the adjacent pages, causing a slight change in the amount of charge in those pages. If this change accumulates to a certain extent, it may cause the originally stored data bit to flip, that is, from 1 to 0 or from 0 to 1, resulting in data errors.

[0004] Based on this problem, various manufacturers must develop various memory management methods to effectively suppress the probability of read disturbance. Summary of the invention

[0005] The present invention provides a memory management method and a storage device, which can effectively improve the accuracy of triggering a read verification operation on a physical management unit.

[0006] An embodiment of the present invention provides a memory management method, which is used for a storage device, wherein the storage device includes a memory module, the memory module includes multiple physical management units, the multiple physical management units include a first physical management unit, the first physical management unit includes multiple physical units, and the memory management method includes: obtaining a first read count corresponding to a first physical unit among the multiple physical units, wherein the first read count reflects the total number of times the first physical unit is subjected to a read operation; obtaining an average read count corresponding to the first physical management unit, wherein the average read count reflects the average number of times the read operation is performed on the multiple physical units; obtaining a first evaluation value corresponding to the first physical management unit based on the first read count and the average read count, wherein the first evaluation value reflects the degree of imbalance of the read operations being performed on the multiple physical units respectively; and if the first evaluation value is greater than a trigger critical value, performing a read verification operation on the first physical management unit.

[0007] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes a plurality of physical management units, the plurality of physical management units include a first physical management unit, the first physical management unit includes a plurality of physical units, and the memory controller is used to: obtain a first read count corresponding to a first physical unit among the plurality of physical units, wherein the first read count reflects the total number of times the first physical unit is subjected to a read operation; obtain an average read count corresponding to the first physical management unit, wherein the average read count reflects the average number of times the read operation is performed on the plurality of physical units; obtain a first evaluation value corresponding to the first physical management unit according to the first read count and the average read count, wherein the first evaluation value reflects the degree of imbalance of the read operations performed on the plurality of physical units; and if the first evaluation value is greater than a trigger threshold value, perform a read verification operation on the first physical management unit.

[0008] Based on the above, a first read count of a first entity unit in a first entity management unit and an average read count corresponding to the first entity management unit can be obtained. In particular, the first read count can reflect the total number of times a read operation is performed on the first entity unit, and the average read count can reflect the average number of times a read operation is performed on multiple entity units in the first entity management unit. According to the first read count and the average read count, a first evaluation value corresponding to the first entity management unit can be obtained. In particular, the first evaluation value can reflect the degree of imbalance of the read operations performed on multiple entity units in the first entity management unit. If the first evaluation value is greater than the trigger critical value, a read verification operation can be performed on the first entity management unit. Thereby, the accuracy of triggering the read verification operation on the entity management unit can be effectively improved.

[0009] In particular, for certain situations that cannot be effectively detected conventionally, such as only a small portion of physical units in certain physical management units having serious read disturbance problems, the present invention can still accurately trigger the read verification operations on these physical management units. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0011] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0012] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0013] Figure 4 is a schematic diagram of managing entity units through entity management units according to an embodiment of the present invention;

[0014] Figure 5 is a flowchart of a memory management method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0016] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1, the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 may include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0017] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (embedded Multi-Media Card, eMMC), a universal flash storage (Universal Flash Storage, UFS), a fast peripheral component interconnect (Peripheral Component Interconnect Express, PCIExpress), a fast non-volatile memory (Non-Volatile Memory Express, NVM express), a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA), a universal serial bus (Universal Serial Bus, USB) or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 via the connection interface 121 (for example, exchange signals, instructions and / or data).

[0018] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also called threshold voltage). For example, the memory module 122 may include a single level cell (SLC) NAND type flash memory module, a multi level cell (MLC) NAND type flash memory module, a triple level cell (TLC) NAND type flash memory module, a quad level cell (QLC) NAND type flash memory module and / or other memory modules having the same or similar characteristics.

[0019] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the entire or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application-specific integrated circuits (ASIC), programmable logic devices (PLD) or other similar devices or combinations of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0020] The memory controller 123 may send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 may send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 may send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 may send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 may also send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited by the present invention. The memory module 122 may receive the command sequence from the memory controller 123 and access the storage unit inside the memory module 122 according to the command sequence.

[0021] Figure 2 FIG. 1 is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22 and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0022] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may be used to control or manage the whole or part of the operation of the memory controller 123. For example, the memory control circuit 23 may communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0023] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0024] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on the data to ensure the correctness of the data. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits, etc.), which are not limited by the present invention.

[0025] Figure 3 FIG. 1 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B). Each physical unit includes a plurality of storage cells and is used for non-volatile storage of data.

[0026] In one embodiment, a physical unit may include one or more physical erase units. In addition, a physical unit may include multiple sub-physical units. For example, a sub-physical unit may include one or more physical programming units.

[0027] In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (Bytes, B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0028] In one embodiment, a physical programming unit is a minimum unit for synchronously writing data in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0029] In one embodiment, a physical erase unit may include a plurality of physical programming units. The plurality of physical programming units in a physical erase unit may be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to the plurality of physical programming units in the physical erase unit to change the threshold voltage of at least some of the storage cells in the physical programming units. By performing an erase operation on a physical erase unit, the data stored in the physical erase unit may be cleared.

[0030] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) to the data area 31 and the idle area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the idle area 32 do not store data (e.g., valid data).

[0031] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated with the idle area 32. In addition, the physical unit in the idle area 32 can be erased to clear the data in the physical unit. In one embodiment, the physical unit in the idle area 32 is also called an idle physical unit. In one embodiment, the idle area 32 is also called an idle pool.

[0032] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cell, the physical cell may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0033] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., the physical units 301(1)-301(A)) in the data area 31. For example, a logical unit may correspond to a logical block address (LBA) or other logical management units. A logical unit may be mapped to one or more physical units.

[0034] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit does not currently store any valid data.

[0035] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing or erasing according to the information in the management table (i.e., the logical-to-physical mapping table).

[0036] In one embodiment, the memory control circuit 23 may manage at least some of the physical units (e.g., physical units 301(1) to 301(B)) in the memory module 122 through a plurality of physical management units. Each physical management unit may include a plurality of physical units. In one embodiment, a physical management unit is also referred to as a virtual unit. In one embodiment, the memory control circuit 23 may manage or access a plurality of physical units in the physical management unit using a physical management unit as a basic unit. For example, a plurality of physical units included in the same physical management unit may be accessed synchronously or sequentially (e.g., read data, write data, or erase).

[0037] Figure 4 FIG. 1 is a schematic diagram showing how to manage entity units through entity management units according to an embodiment of the present invention. Figure 4 In one embodiment, the memory module 122 includes physical management units 41 (1) to 41 (D). The total number of physical management units 41 (1) to 41 (D) can be set or adjusted according to practical needs, and the present invention is not limited thereto.

[0038] Each of entity management units 41(1) to 41(D) may include multiple entity units. For example, entity management unit 41(1) includes entity units 401(1) to 401(E), and entity management unit 41(D) includes entity units 402(1) to 402(E). For example, entity units 401(1) to 401(E) and 402(1) to 402(E) may be included in Figure 3 In addition, the total number of entity units included in each entity management unit can be set or adjusted according to practical needs, and the present invention is not limited thereto.

[0039] In one embodiment, the memory control circuit 23 may select a certain entity management unit (also referred to as a first entity management unit) from the entity management units 41 (1) to 41 (D). For example, the first entity management unit may be the entity management unit 41 (i), and i is an integer between 1 and D. Then, the memory control circuit 23 may determine (e.g., select) a entity unit (also referred to as a first entity unit) from the first entity management unit. The first entity unit may be one of the multiple entity units included in the first entity management unit. For example, assuming that the first entity management unit is the entity management unit 41 (1), the first entity unit may be one of the entity units 401 (1) to 401 (E). Alternatively, assuming that the first entity management unit is the entity management unit 41 (D), the first entity unit may be one of the entity units 402 (1) to 402 (E).

[0040] In one embodiment, the memory control circuit 23 may determine one of the multiple physical units included in the first physical management unit as the first physical unit according to a preset rule. For example, the memory control circuit 23 may determine one of the multiple physical units included in the first physical management unit as the first physical unit at different time points by alternation or the like.

[0041] In one embodiment, the memory control circuit 23 may execute a random algorithm to determine the first physical unit. For example, the memory control circuit 23 may randomly determine one of the multiple physical units included in the first physical management unit as the first physical unit according to the operation result of the random algorithm. For example, the memory control circuit 23 may input a seed into the random algorithm. The random algorithm may generate an output value in response to the seed. The memory control circuit 23 may randomly determine one of the multiple physical units included in the first physical management unit as the first physical unit according to the output value.

[0042] In one embodiment, according to different output values ​​of the random algorithm, the memory control circuit 23 may randomly determine different physical units in the first physical management unit as the first physical unit. For example, according to a certain output value (also referred to as the first output value) of the random algorithm, the memory control circuit 23 may determine a certain physical unit (also referred to as the first candidate unit) in the first physical management unit as the first physical unit. Alternatively, according to another output value (also referred to as the second output value) of the random algorithm, the memory control circuit 23 may determine another physical unit (also referred to as the second candidate unit) in the first physical management unit as the first physical unit. The first candidate unit and the second candidate unit are different physical units in the first physical management unit.

[0043] In one embodiment, after determining the first physical unit from the first physical management unit, the memory control circuit 23 may obtain a read count (also referred to as a first read count) corresponding to the first physical unit. The first read count may reflect the total number of times the read operation is performed on the first physical unit. For example, the read operation performed on the first physical unit is used to read data from the first physical unit. For example, assuming that the total number of times the read operation is performed on the first physical unit in the past period of time is "40", the first read count may be "40". Specifically, the memory control circuit 23 only records the latest and largest read count corresponding to the first physical unit.

[0044] In one embodiment, the memory control circuit 23 may also obtain an average read count corresponding to the first entity management unit. This average read count reflects the average number of times a read operation is performed on multiple entity units in the first entity management unit. For example, assuming that this average read count is "50", it means that an average of "50" read operations have been performed on multiple entity units in the first entity management unit in the past period of time. However, in reality, the total number of read operations performed on each entity unit in the first entity management unit in the past period of time may be higher or lower than this average number. Specifically, the memory control circuit 23 only records the latest and largest read count corresponding to the first entity management unit.

[0045] In detail, the purpose of the memory control circuit 23 recording only the latest and largest read counts corresponding to the first physical unit and the first physical management unit is to reduce the storage space required for storing the above read counts.

[0046] In one embodiment, the memory control circuit 23 may first obtain the total read count corresponding to the first physical management unit. This total read count reflects the total number of times the read operation is performed on the first physical management unit. For example, assuming that the total number of times the read operation is performed on the first physical management unit in the past period of time is "1000", then this total read count may be "1000". Then, the memory control circuit 23 may obtain the average read count based on this total read count and the total number of multiple physical units included in the first physical management unit. For example, assuming that the total read count is "1000" and the total number of multiple physical units included in the first physical management unit is "20", the memory control circuit 23 may divide the total read count (e.g., "1000") by the total number of multiple physical units included in the first physical management unit (e.g., "20") to obtain the average read count (e.g., "50").

[0047] In one embodiment, the memory control circuit 23 may obtain an evaluation value (also referred to as a first evaluation value) corresponding to the first physical management unit according to the first read count and the average read count. The first evaluation value may reflect the unevenness of the read operations performed on the multiple physical units in the first physical management unit. Alternatively, from another perspective, the first evaluation value may reflect whether the read operations were performed evenly on the multiple physical units in the first physical management unit over a period of time.

[0048] In one embodiment, the memory control circuit 23 may compare the first evaluation value with a critical value (also referred to as a trigger critical value). If the first evaluation value is greater than the trigger critical value, the memory control circuit 23 may perform a read verification operation on the first entity management unit. For example, in the case where the first evaluation value is greater than the trigger critical value (or in response to the first evaluation value being greater than the trigger critical value), the memory control circuit 23 may perform the read verification operation on all entity units in the first entity management unit one by one. For example, the read verification operation may be used to ensure or improve the correctness of at least part of the data currently stored in the first entity management unit. However, if the first evaluation value is not greater than (e.g., less than or equal to) the trigger critical value, the memory control circuit 23 may not perform the read verification operation on the first entity management unit. Thus, unnecessary waste of system resources can be avoided.

[0049] In one embodiment, the memory control circuit 23 may obtain an evaluation factor (also referred to as a balance evaluation factor) based on the first read count and the average read count. This balance evaluation factor is related to the degree of imbalance of the read operations being performed on the multiple physical units in the first physical management unit. For example, this balance evaluation factor may be positively correlated to the degree of imbalance of the read operations being performed on the multiple physical units in the first physical management unit. That is, if this balance evaluation factor is larger, it means that in the past period of time, the multiple physical units in the first physical management unit have been executed The degree of imbalance is higher (equivalent to the fact that in the past period of time, the multiple physical units in the first physical management unit have been read less evenly). Conversely, if this balance evaluation factor is smaller, it means that in the past period of time, the multiple physical units in the first physical management unit have been executed. The degree of imbalance is lower (equivalent to the fact that in the past period of time, the multiple physical units in the first physical management unit have been read more evenly).

[0050] In one embodiment, the memory control circuit 23 may obtain the balance evaluation factor according to the following formula (1).

[0051] t=|(B(i)-AVG) / AVG| (1)

[0052] In formula (1), B(i) represents the first read count, AVG represents the average read count, and t represents the balance evaluation factor. According to formula (1), the calculated t (i.e., the balance evaluation factor) is positively correlated with the difference (which can be a positive or negative value) between B(i) (i.e., the first read count) and AVG (i.e., the average read count). That is, the larger the difference between B(i) and AVG, the larger the calculated t. It should be noted that formula (1) can also be set or adjusted according to practical needs, and the present invention is not limited thereto.

[0053] In one embodiment, after obtaining the balance evaluation factor, the memory control circuit 23 may obtain a first evaluation value according to the average read count and the balance evaluation factor. For example, the first evaluation value may be positively correlated with the average read count and the balance evaluation factor.

[0054] In one embodiment, the memory control circuit 23 may obtain the first evaluation value according to the following formula (2).

[0055] EV=AVG×(1+t) (2)

[0056] In formula (2), EV represents the first evaluation value. According to formula (2), if AVG (i.e., the average read count) and / or t (i.e., the balance evaluation factor) is larger, the calculated EV (i.e., the first evaluation value) is also larger. It should be noted that formula (2) can also be set or adjusted according to practical needs, and the present invention is not limited thereto.

[0057] In one embodiment, if the first evaluation value is greater than the trigger threshold value, it means that in the past period of time, the unevenness of the read operations performed on the multiple physical units in the first physical management unit is relatively high (i.e., the difference between the read counts corresponding to the multiple physical units in the first physical management unit is large). Therefore, by comparing the first evaluation value with the trigger threshold value, it is possible to effectively detect the physical management unit that is likely to cause access errors in the future due to uneven use of the multiple physical units inside the physical management unit (for example, only some physical units have severe read interference).

[0058] On the other hand, if the first evaluation value is not greater than the trigger threshold value, it means that in the past period of time, the imbalance degree of performing read operations on multiple physical units in the first physical management unit is relatively low (i.e., the difference between the read counts corresponding to the multiple physical units in the first physical management unit is small). In this case, the memory control circuit 23 may not perform the read verification operation on the first physical management unit to avoid unnecessary waste of system resources.

[0059] In one embodiment, the memory control circuit 23 may also compare the first read count with the trigger critical value. If the first read count is greater than the trigger critical value, the memory control circuit 23 may directly perform a read verification operation on the first physical management unit. For example, in the case where the first read count is greater than the trigger critical value (or in response to the first read count being greater than the trigger critical value), the memory control circuit 23 may perform the read verification operation on all physical units in the first physical management unit one by one to ensure or improve the correctness of at least part of the data currently stored in the first physical management unit. However, if the first read count is not greater than (e.g., less than or equal to) the trigger critical value, the memory control circuit 23 may not perform the read verification operation on the first physical management unit to avoid unnecessary waste of system resources.

[0060] In one embodiment, during the read verification operation, the memory control circuit 23 may instruct the memory module 122 to read data (also referred to as first data) from the first physical management unit. For example, the first data may include data read from at least one physical unit in the first physical management unit.

[0061] In one embodiment, the step of reading data from at least one physical unit in the first physical management unit includes an operation of first selecting a target physical unit from the first physical management unit. Specifically, the operation of the memory control circuit 23 selecting a target physical unit from the first physical management unit is to first select a physical unit with the largest number of erase times as the target physical unit.

[0062] In one embodiment, after a physical unit with the largest number of erase times is selected as a target physical unit, all physical programming units in the physical unit are traversed to read data.

[0063] In one embodiment, all physical programming units are not traversed to read data, because this is time-consuming. Instead, after selecting the target physical unit, at least two physical programming units are randomly selected from the target physical unit, but the word lines (Word Lines, WL) to which the two physical programming units belong are adjacent word lines (Word Lines, WL). For example, the first physical programming unit belongs to WL0, and the second physical programming unit belongs to WL1; and WL0 and WL1 are adjacent word lines (Word Lines, WL). And the first read voltage required to read the data in the first physical programming unit and the second read voltage value required to read the data in the second physical programming unit are the same. Preferably, the first read voltage and the second read voltage value must be stored in a re-read voltage table pre-burned into the storage device 12.

[0064] In one embodiment, at least two physical programming units are randomly selected from the target physical unit, wherein the first physical programming unit is randomly selected, and the second physical programming unit in an adjacent word line (WL) relationship is also randomly selected.

[0065] In one embodiment, the operation of selecting at least two physical programming units from the target physical unit is not random, but first reads the physical programming unit with the largest physical address value. If the physical programming unit is not the target physical programming unit, then select the physical programming unit with half the maximum value of the physical address to determine whether it is the target physical programming unit. If not, continue to use half of this value to determine whether the next round of physical programming units is the target physical programming unit. Exemplarily, if a physical unit includes 100 physical programming units, the first round searches for the physical programming unit of page99. If not, the second round searches for the physical programming unit of page49, and so on. If the target physical programming unit is page 24, only three rounds of searches are needed to find the target physical programming unit, which is faster than traversing to find the target physical programming unit.

[0066] In one embodiment, the memory control circuit 23 constructs a table of physical programming units that successfully read data in response to a data read instruction, and uses a sorting algorithm to manage the table. The physical address values ​​of the physical programming units with the largest data error bit values ​​during historical read operations are arranged at the head of the table, and the subsequent selection of the target physical programming unit is made based on the table.

[0067] In one embodiment, the memory control circuit 23 may construct the physical programming unit table according to the data error bit value corresponding to at least one physical programming unit detected during the historical read operation. For example, the physical programming unit table may be constructed using the LRU-K algorithm or other algorithms. For example, the memory control circuit 23 may add the physical address value of the physical programming unit whose corresponding data error bit value is greater than the threshold to this physical programming unit table. For example, the data error bit value may be positively correlated to the bit error rate of the physical programming unit. Thereafter, the memory control circuit 23 may select a target physical programming unit from this physical programming unit table, so that the data error bit value corresponding to the selected target physical programming unit must be greater than the threshold.

[0068] In one embodiment, after obtaining the first data, the memory control circuit 23 may determine whether the first data meets the update condition. If the first data meets the update condition, the memory control circuit 23 may re-store the first data to another physical management unit (also referred to as the second physical management unit) in the memory module 122. Figure 4 For example, assuming that the first physical management unit is the physical management unit 41 (i), the second physical management unit may be the physical management unit 41 (j). i and j may be integers between 1 and D, and i is different from j. However, if the first data does not meet the update condition, the memory control circuit 23 may not re-store the first data to the second physical management unit.

[0069] In one embodiment, after obtaining the first data, the decoding circuit 25 may perform a decoding operation on the first data. This decoding operation may be used to detect and attempt to correct error bits in the first data. Based on the result of this decoding operation, the memory control circuit 23 may determine whether the total number of error bits in the first data is greater than a preset value. If the total number of error bits is greater than the preset value, the memory control circuit 23 may determine that the first data meets the update condition. However, if the total number of error bits is not greater than the preset value, the memory control circuit 23 may determine that the first data does not meet the update condition.

[0070] In one embodiment, by re-storing the first data originally containing relatively more error bits into the second physical management unit, the correctness of the re-stored first data can be improved. On the other hand, re-storing the first data into the second physical management unit can also reduce the total number of error bits contained in the first data subsequently read from the second physical management unit.

[0071] In one embodiment, after performing a decoding operation on the first data, the memory control circuit 23 may also determine whether the first data is successfully decoded according to the result of the decoding operation. If the first data cannot be successfully decoded (for example, the first data includes data that cannot be corrected or error bits), the memory control circuit 23 may determine that the first data meets the update condition. However, if the first data can be successfully decoded (for example, all data or error bits in the first data can be corrected), the memory control circuit 23 may determine that the first data does not meet the update condition.

[0072] In one embodiment, after restoring the first data to the second physical management unit, the memory control circuit 23 may reset the read count information corresponding to the first physical management unit. For example, the read count information may include the total read count and / or the average read count corresponding to the first physical management unit. In one embodiment, the read count information may also include the read count corresponding to any physical unit in the first physical management unit. In one embodiment, in response to restoring the first data to the second physical management unit, the memory control circuit 23 may reset the total read count corresponding to the first physical management unit, the average read count corresponding to the first physical management unit, and / or the read count corresponding to any physical unit in the first physical management unit to zero (or restore to an initial value).

[0073] In one embodiment, after re-storing the first data to the second physical management unit, the memory control circuit 23 may also re-associate the first physical management unit (including all physical units in the first physical management unit) to Figure 3 In one embodiment, after restoring the first data to the second physical management unit, the memory control circuit 23 may also erase all physical units in the first physical management unit.

[0074] Figure 5 FIG. 1 is a flowchart of a memory management method according to an embodiment of the present invention. Figure 5In step S501, a first read count corresponding to a first entity unit in a first entity management unit is obtained, wherein the first read count reflects the total number of times a read operation is performed on the first entity unit. In step S502, an average read count corresponding to the first entity management unit is obtained, wherein the average read count reflects the average number of times a read operation is performed on multiple entity units in the first entity management unit. In step S503, a first evaluation value corresponding to the first entity management unit is obtained based on the first read count and the average read count, wherein the first evaluation value reflects the degree of imbalance of the read operations performed on the multiple entity units. In step S504, it is determined whether the first evaluation value is greater than the trigger critical value. If the first evaluation value is greater than the trigger critical value, in step S505, a read verification operation is performed on the first entity management unit. However, if the first evaluation value is not greater than the trigger critical value, in step S506, a read verification operation is not performed on the first entity management unit.

[0075] However, Figure 5 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Figure 5 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 5 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0076] In summary, the memory management method and storage device proposed in the embodiments of the present invention can effectively improve the accuracy of triggering the read verification operation on the physical management unit. In particular, for certain conditions that cannot be effectively detected traditionally, such as only a small number of physical units in some physical management units have serious read interference problems, the present invention can still accurately trigger the read verification operation on these physical management units. As a result, the operational stability of the storage device can be effectively improved.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that: For a storage device, wherein the storage device comprises a memory module, the memory module comprises a plurality of entity management units, the plurality of entity management units comprises a first entity management unit, the first entity management unit comprises a plurality of entity units, and the memory management method comprises: Obtaining a first read count corresponding to a first physical unit among the plurality of physical units, wherein the first read count reflects a total number of times a read operation is performed on the first physical unit; Obtaining an average read count corresponding to the first physical management unit, wherein the average read count reflects an average number of times the read operation is performed on the plurality of physical units; Obtaining a first evaluation value corresponding to the first physical management unit according to the first read count and the average read count, wherein the first evaluation value reflects the degree of imbalance in the read operations being performed on the plurality of physical units; and If the first evaluation value is greater than the trigger threshold, a read verification operation is performed on the first physical management unit.

2. The memory management method according to claim 1, further comprising: If the first read count is greater than the trigger threshold, the read verification operation is performed on the first physical management unit.

3. The memory management method according to claim 1, further comprising: According to the operation result of the random algorithm, one of the plurality of entity units is randomly determined as the first entity unit.

4. The memory management method according to claim 1, wherein the step of obtaining the first evaluation value corresponding to the first physical management unit according to the first read count and the average read count comprises: Obtaining a balance evaluation factor according to the first read count and the average read count, wherein the balance evaluation factor is positively correlated to the imbalance degree; The first evaluation value is obtained according to the average read count and the balance evaluation factor.

5. The memory management method according to claim 4, wherein the step of obtaining the balance evaluation factor according to the first read count and the average read count comprises: According to the following formula, the balance evaluation factor is obtained: t=|(B(i)-AVG) / AVG| Wherein, B(i) represents the first read count, AVG represents the average read count, and t represents the balance evaluation factor.

6. The memory management method according to claim 1, wherein the read verification operation comprises: Reading first data from the first entity management unit; Determining whether the first data meets the update condition; as well as If the first data meets the update condition, the first data is stored again in a second physical management unit among the plurality of physical management units. 7 . The memory management method according to claim 6 , wherein the first data comprises data read from at least one of the plurality of physical units.

8. The memory management method according to claim 6, wherein the step of determining whether the first data meets the update condition comprises: performing a decoding operation on the first data; According to the result of the decoding operation, determining whether the total number of error bits in the first data is greater than a preset value; as well as If the total number of the error bits is greater than the preset value, it is determined that the first data meets the update condition.

9. The memory management method according to claim 6, wherein the step of determining whether the first data meets the update condition comprises: performing a decoding operation on the first data; Determining, based on a result of the decoding operation, whether the first data is successfully decoded; as well as If the first data cannot be successfully decoded, it is determined that the first data meets the update condition.

10. The memory management method according to claim 6, further comprising: After the first data is stored again in the second physical management unit, the read count information corresponding to the first physical management unit is reset.

11. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory module includes a plurality of physical management units, the plurality of physical management units include a first physical management unit, the first physical management unit includes a plurality of physical units, and the memory controller is used to: Obtaining a first read count corresponding to a first physical unit among the plurality of physical units, wherein the first read count reflects a total number of times a read operation is performed on the first physical unit; Obtaining an average read count corresponding to the first physical management unit, wherein the average read count reflects an average number of times the read operation is performed on the plurality of physical units; Obtaining a first evaluation value corresponding to the first physical management unit according to the first read count and the average read count, wherein the first evaluation value reflects the degree of imbalance of the read operations being performed on the plurality of physical units; as well as If the first evaluation value is greater than the trigger threshold, a read verification operation is performed on the first physical management unit.

12. The storage device according to claim 11, wherein the memory controller is further configured to: If the first read count is greater than the trigger threshold, the read verification operation is performed on the first physical management unit.

13. The storage device according to claim 11, wherein the memory controller is further configured to: According to the operation result of the random algorithm, one of the plurality of entity units is randomly determined as the first entity unit.

14. The storage device according to claim 11, wherein the operation of the memory controller obtaining the first evaluation value corresponding to the first physical management unit according to the first read count and the average read count comprises: Obtaining a balance evaluation factor according to the first read count and the average read count, wherein the balance evaluation factor is positively correlated to the imbalance degree; The first evaluation value is obtained according to the average read count and the balance evaluation factor.

15. The storage device according to claim 14, wherein the operation of the memory controller obtaining the balance evaluation factor according to the first read count and the average read count comprises: According to the following formula, the balance evaluation factor is obtained: t=|(B(i)-AVG) / AVG| Wherein, B(i) represents the first read count, AVG represents the average read count, and t represents the balance evaluation factor.

16. The memory device of claim 11, wherein the read verification operation comprises: Reading first data from the first entity management unit; Determining whether the first data meets the update condition; as well as If the first data meets the update condition, the first data is stored again in a second physical management unit among the plurality of physical management units. 17 . The storage device according to claim 16 , wherein the first data comprises data read from at least one of the plurality of physical units.

18. The storage device according to claim 16, wherein the operation of the memory controller determining whether the first data meets the update condition comprises: performing a decoding operation on the first data; According to the result of the decoding operation, determining whether the total number of error bits in the first data is greater than a preset value; as well as If the total number of the error bits is greater than the preset value, it is determined that the first data meets the update condition.

19. The storage device according to claim 16, wherein the operation of the memory controller determining whether the first data meets the update condition comprises: performing a decoding operation on the first data; Determining, based on a result of the decoding operation, whether the first data is successfully decoded; as well as If the first data cannot be successfully decoded, it is determined that the first data meets the update condition.

20. The storage device according to claim 16, wherein the memory controller is further configured to: After the first data is stored again in the second physical management unit, the read count information corresponding to the first physical management unit is reset.

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