Simulation data transmission control method and device based on multi-chip memory

Abstract

The embodiment of the present application provides a simulation data transmission control method and device based on multi-chip memory, the method comprising: receiving the operation data of the simulation device, sequentially and cyclically storing the operation data according to a plurality of preset memory chips, determining the corresponding simulation data, and sending the simulation data to the data receiving end in sequence according to the set optimal transmission parameters, so that after the data receiving end receives the simulation data, it determines the corresponding response signal according to the secondary sequence number in the simulation data; receiving the response signal, determining whether the response signal is repeated, if repeated, pausing the sending operation according to the preset blocking window, and performing data retransmission operation on the data receiving end according to the response signal and the simulation data stored in the memory chip, if not repeated, performing sequential sending operation according to the preset sliding window and the response signal until the data transmission is completed. The present application can improve the efficiency and flexibility of simulation data transmission.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a simulation data transmission control method and device based on multi-chip memory. Background Art

[0002] With the development of simulation technology, real-time simulation systems are increasingly used in different fields, such as aerospace, automotive engineering, electronic design, etc.

[0003] In real-time simulation systems, efficient data communication protocols are key factors in ensuring simulation accuracy and real-time performance. Traditional data communication protocols use fixed window sizes or feedback mechanisms based on packet loss rates to adjust the sending rate, but this approach responds slowly when the network environment changes dynamically and is prone to network oscillation. When faced with complex and changing network environments and simulation devices with different performance, it is often difficult to ensure the efficiency and reliability of data transmission.

[0004] In real-time simulation systems, simulation data usually has large data volumes and high real-time requirements. Traditional storage technologies often have difficulty meeting these requirements, resulting in reduced simulation performance. Moreover, during the simulation data transmission process, when abnormal conditions (such as packet loss, network congestion, etc.) are detected, how to quickly respond and resume transmission is an important issue. Today's solutions cannot meet the requirements of efficient transmission and smooth storage of simulation data. Summary of the invention

[0005] In view of the problems in the prior art, the present application provides a simulation data transmission control method and device based on multi-chip memory, which can improve the efficiency and flexibility of simulation data transmission.

[0006] In order to solve at least one of the above problems, the present application provides the following technical solutions:

[0007] In a first aspect, the present application provides a simulation data transmission control method based on multiple memory chips, comprising:

[0008] Receive the operation data of the simulation device, and perform sequential cyclic storage operations on the operation data according to a plurality of preset memory slices to determine corresponding simulation data, wherein the simulation data includes a primary sequence number and a secondary sequence number, the primary sequence number is used to identify a complete data block of the simulation data, and the secondary sequence number is used to identify the position of each data packet in the complete data block;

[0009] The simulation data is sequentially sent to the data receiving end according to the set optimal transmission parameters, so that after receiving the simulation data, the data receiving end determines a corresponding response signal according to the secondary sequence number in the simulation data, and sends the response signal, wherein the response signal is used to indicate the secondary sequence number of the next data packet that the data receiving end expects to receive;

[0010] Receive the response signal, determine whether the response signal is repeated, if it is repeated, suspend the sending operation according to a preset blocking window, and resend the data to the data receiving end according to the response signal and the simulation data stored in the memory chip; if it is not repeated, perform sequential sending operations according to the preset sliding window and the response signal until the data transmission is completed.

[0011] Furthermore, before the operation of sending the simulation data to the data receiving end in sequence according to the set optimal transmission parameters comprises:

[0012] Receiving preset initial transmission parameters sent by the data receiving end;

[0013] A communication test operation is performed on the data receiving end according to the initial transmission parameters, so that the data receiving end determines the corresponding optimal transmission parameters according to the set algorithm model.

[0014] Further, performing a communication test operation on the data receiving end according to the initial transmission parameters so that the data receiving end determines the corresponding optimal transmission parameters according to a set algorithm model includes:

[0015] Determine a corresponding plurality of transmission parameter sample combinations according to the initial transmission parameter and a preset sample threshold;

[0016] Data transmission operations are performed on the data receiving end respectively according to the multiple transmission parameter sample combinations, so that the data receiving end determines the corresponding optimal transmission parameters according to the multiple groups of test data obtained after the data transmission operation and the preset communication comprehensive performance indicator model.

[0017] Further, the operation of setting the optimal transmission parameters and sending the simulation data to the data receiving end in sequence includes:

[0018] Determine whether the maximum transmission unit value in the optimal transmission parameter is greater than a preset value, and if so, perform a check data adding operation on the simulation data according to a preset cyclic redundancy check algorithm, and send the simulation data obtained after the check data adding operation to the data receiving end in sequence according to the frame interval in the optimal transmission parameter;

[0019] If it is not greater than, the simulation data is sent to the data receiving end in sequence according to the frame interval in the optimal transmission parameter.

[0020] Further, the determining the corresponding response signal according to the secondary sequence number in the simulation data includes:

[0021] Determine whether the secondary sequence numbers in the simulation data are continuous, and if so, perform a response signal generation operation in increasing order to determine a corresponding response signal;

[0022] If not, a response signal generation operation is performed according to the secondary sequence number missing in the simulation data to determine the corresponding response signal.

[0023] Further, after receiving the response signal, the method further includes:

[0024] Determining whether the response signal is continuous;

[0025] If not, a data retransmission operation is performed on the data receiving end according to the largest response signal and the simulation data stored in the memory chip.

[0026] Further, the sequentially cyclically storing the operating data according to the plurality of preset memory slices to determine the corresponding simulation data includes:

[0027] According to a preset response signal rule, determining whether the historical operation data in a plurality of preset memory slices has been successfully transmitted;

[0028] If so, performing a data overwriting operation on the historical operation data according to the received operation data of the simulation device to determine the corresponding simulation data;

[0029] If not, the corresponding simulation data is determined according to the response signal rule and the historical operation data.

[0030] In a second aspect, the present application provides a simulation data transmission control device based on multiple memory chips, comprising:

[0031] a simulation data determination module, configured to receive the operation data of the simulation device, and to perform sequential cyclic storage operations on the operation data according to a plurality of preset memory slices to determine corresponding simulation data, wherein the simulation data includes a primary sequence number and a secondary sequence number, the primary sequence number is used to identify a complete data block of the simulation data, and the secondary sequence number is used to identify the position of each data packet in the complete data block;

[0032] A response signal determination module, used for sending the simulation data to the data receiving end in sequence according to the set optimal transmission parameters, so that after receiving the simulation data, the data receiving end determines the corresponding response signal according to the secondary sequence number in the simulation data, and sends the response signal, wherein the response signal is used to indicate the secondary sequence number of the next data packet that the data receiving end expects to receive;

[0033] The cumulative response transmission module is used to receive the response signal and determine whether the response signal is repeated. If it is repeated, the sending operation is suspended according to a preset blocking window, and the data receiving end is retransmitted according to the response signal and the simulation data stored in the memory chip. If it is not repeated, a sequential sending operation is performed according to a preset sliding window and the response signal until the data transmission is completed.

[0034] In a third aspect, the present application provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the multi-chip memory-based simulation data transmission control method when executing the program.

[0035] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the simulated data transmission control method based on multi-chip memories.

[0036] In a fifth aspect, the present application provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the simulation data transmission control method based on multi-chip memory.

[0037] It can be seen from the above technical scheme that the present application provides a simulation data transmission control method and device based on multi-chip memory, which receives the operating data of the simulation device, sequentially and cyclically stores the operating data according to multiple preset memory chips, determines the corresponding simulation data, and sends the simulation data to the data receiving end in sequence according to the set optimal transmission parameters, so that after the data receiving end receives the simulation data, it determines the corresponding response signal according to the secondary sequence number in the simulation data; receives the response signal, determines whether the response signal is repeated, and if so, suspends the sending operation according to the preset blocking window, and retransmits the data to the data receiving end according to the response signal and the simulation data stored in the memory chip; if not, performs sequential sending operations according to the preset sliding window and the response signal until the data transmission is completed, thereby improving the efficiency and flexibility of simulation data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 This is one of the flow charts of the simulation data transmission control method based on multiple memory chips in the embodiment of the present application;

[0040] Figure 2 This is a second flow chart of a simulation data transmission control method based on multiple memory chips in an embodiment of the present application;

[0041] Figure 3 The third flowchart of the simulation data transmission control method based on multiple memory chips in the embodiment of the present application;

[0042] Figure 4 This is a fourth flow chart of a simulation data transmission control method based on multiple memory chips in an embodiment of the present application;

[0043] Figure 5 This is a fifth flow chart of a simulation data transmission control method based on multiple memory chips in an embodiment of the present application;

[0044] Figure 6 This is a sixth flow chart of a simulation data transmission control method based on multiple memory chips in an embodiment of the present application;

[0045] Figure 7 FIG7 is a flow chart of a method for controlling simulated data transmission based on multiple memory chips in an embodiment of the present application;

[0046] Figure 8 It is a structural diagram of a simulation data transmission control device based on multiple memory chips in an embodiment of the present application;

[0047] Fig. 9 It is a schematic diagram of the structure of an electronic device in an embodiment of the present application.

[0048] Reference numerals:

[0049] Electronic device 9600, central processing unit 9100, memory 9140, communication module 9110, input unit 9120, audio processor 9130, display 9160, power supply 9170, buffer memory 9141, application / function storage unit 9142, data storage unit 9143, driver program storage unit 9144, antenna 9111, speaker 9131, microphone 9132. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0051] The acquisition, storage, use, and processing of data in the technical solution of this application comply with the relevant provisions of national laws and regulations.

[0052] Considering that the existing simulation data transmission method cannot meet the requirements of the real-time simulation system for efficient transmission and smooth storage of simulation data. The present application provides a simulation data transmission control method and device based on multi-chip memory, which receives the operation data of the simulation device, sequentially and cyclically stores the operation data according to multiple preset memory chips, determines the corresponding simulation data, and sends the simulation data to the data receiving end in sequence according to the set optimal transmission parameters, so that after the data receiving end receives the simulation data, it determines the corresponding response signal according to the secondary sequence number in the simulation data; receives the response signal, determines whether the response signal is repeated, if repeated, suspends the sending operation according to the preset blocking window, and performs data retransmission operation on the data receiving end according to the response signal and the simulation data stored in the memory chip, if not repeated, performs sequential sending operation according to the preset sliding window and the response signal until the data transmission is completed, thereby improving the efficiency and flexibility of simulation data transmission.

[0053] In order to improve the efficiency and flexibility of simulated data transmission, the present application provides an embodiment of a simulated data transmission control method based on multiple memory chips, see Figure 1 The simulation data transmission control method based on multiple memory chips specifically includes the following contents:

[0054] Step S101: receiving the operation data of the simulation device, and performing sequential cyclic storage operations on the operation data according to a plurality of preset memory slices to determine corresponding simulation data, wherein the simulation data includes a primary sequence number and a secondary sequence number, the primary sequence number is used to identify a complete data block of the simulation data, and the secondary sequence number is used to identify the position of each data packet in the complete data block;

[0055] Optionally, in this embodiment, the purpose of this step is to avoid frame loss of simulation data by using an adaptive cache mechanism and sequentially cyclically storing simulation data using an overwritable memory.

[0056] Optionally, in this embodiment, the preset memory chip uses DDR SDRAM. The simulation data sending end A has multiple DDR SDRAMs, which are used to send simulation data to the simulation data receiving end B, that is, the simulation host.

[0057] Optionally, in this embodiment, sequential loop storage is performed.

[0058] The multiple DDR SDRAMs of the simulation data transmitter A respectively store the historical simulation data transmitted by the upstream simulation device, and send these simulation data to the simulation data receiver B in sequence. Under normal circumstances, after the simulation data is sent successfully, the new data will sequentially replace the successfully sent data.

[0059] However, when packet loss occurs, the sender A determines that it needs to stop sending data to the receiver B, but the upstream simulation device is still transmitting new data to be sent to the sender A; when the sender A receives the running data of the device to be sent, the onboard multi-chip DDR SDRAM adopts a sequential overwriting cycle read-write strategy, which determines which DDR SDRAMs belong to overwritable memory, and stores these data to be sent in the overwritable memory in sequence as simulation data to be sent to the receiver B. In terms of effect, through the adaptive cache mechanism, the simulation data frame loss is avoided in the case of network transmission congestion, the simulation data flow from the front-end simulation device to the receiving host is smoothed, and the accuracy and integrity of the data collected by the simulation device are guaranteed.

[0060] Optionally, in this embodiment, simulation data is stored as a data block in a DDR SDRAM. If you want to transmit this complete data block, divide it into several data payload packets. When transmitting a data block, first transmit the payload packet of this data packet, then transmit several data payload packets in sequence, and finally transmit the tail packet. These three packets have their own secondary sequence numbers. The first-level sequence number indicates the current data block to which it belongs, and the second-level sequence number indicates the number of the data packet to which it belongs. The data payload packets are collected by the simulation device CPU from various types of simulation modules at the front end and stored in the DDR SDRAM. The head packet and the tail packet are generated by the CPU according to the current transmission data block grouping.

[0061] For example, simulation device A (sender) generates a frame of simulation data, the data packet sequence number is from 0 to N+1, N+2 data packets, of which the 0th data packet is the head packet and the N+2th data packet is the tail packet. The middle 1 to N data packets are the main data blocks.

[0062] Step S102: sending the simulation data to the data receiving end in sequence according to the set optimal transmission parameters, so that after receiving the simulation data, the data receiving end determines a corresponding response signal according to the secondary sequence number in the simulation data, and sends the response signal, wherein the response signal is used to indicate the secondary sequence number of the next data packet that the data receiving end expects to receive;

[0063] Optionally, in this embodiment, optimal transmission parameters are set, and the communicating parties conduct pre-negotiation before formal transmission, and the data receiving end B determines the optimal transmission parameters. This process takes into account the actual conditions of the network and the real-time processing capabilities of the terminal equipment, thereby achieving more flexible and adaptable communication.

[0064] The optimal transmission parameters include the application layer maximum transmission unit MTU and the frame interval IFG. After the data receiving end B determines the optimal transmission parameters, the transmitting end A transmits the simulation data to the data receiving end B according to the application layer maximum transmission unit MTU and the frame interval IFG in the parameters.

[0065] Optionally, in this embodiment, during the sending process, the sending end A increases the accuracy of data transmission based on the variable packet header technology.

[0066] Specifically, under different terminal devices and network media conditions, the proportion of application layer data headers can vary, and bandwidth utilization can be maximized while ensuring data transmission accuracy under different network transmission environments. Because MTU is determined based on the pre-negotiation test results, the value of MTU is a number of discrete points that are integer multiples of 128 bytes.

[0067] When the MTU is 128 bytes, the protocol overhead is removed, the data volume is small enough, setting the checksum part is less cost-effective, and there is no CRC check part in the packet header;

[0068] When the MTU is greater than 128 bytes and less than 1024 bytes, a 16-bit CRC check is set in the packet header;

[0069] When the MTU is greater than 1024 bytes, a 32-bit CRC check unit is set in the packet header.

[0070] As the data volume increases, the length of the CRC check section is increased, greatly improving the accuracy of the check with a smaller protocol overhead.

[0071] Optionally, in this embodiment, the sending end A continuously sends simulation data according to the frame interval IFG negotiated in the previous stage, and the receiving end B returns a response signal each time it receives a data packet. The response signal includes the secondary sequence number of the next data packet expected to be received. The sending end A will accept the expected response signal from the receiving end B, and continuously push the sliding blocking window forward according to the sequence number, thereby allowing the sending end to send new data packets.

[0072] Receiver B maintains an expected response sequence number register ERSN REGISTER (Expect responseserial number register). Whenever receiver B receives a data packet, register ERSN enters the logic of determining whether to self-increment. Receiver B returns a response signal based on register ERSN, which contains the secondary sequence number of the next data packet to be received. In other words, receiver B will only accept data packets that arrive in sequence, store the data in the receiving buffer in turn, and inform sender A of the sequence number of the next data packet expected to be received through a response signal. If receiver B finds that the sequence of data packets is not continuous, it will not generate the next secondary sequence number, but will continue to generate the lost secondary sequence number.

[0073] For example:

[0074] The receiving end B receives data packets with sequence numbers T, T+1, and T+2 in sequence. The expected response sequence number maintained by register ERSN increases to T+3 in sequence, and the expected sequence numbers contained in the returned response packets are T+1, T+2, and T+3 in sequence. If data packets with sequence numbers T, T+2, and T+3 are received in sequence, the data packet with sequence number T+1 is lost. The judgment process of the receiving end is analyzed as follows: the expected response sequence number maintained by register ERSN increases to T+1 when the data packet with sequence number T is received, and the response packet with expected sequence number T+1 is returned. Then the receiving end B receives a data packet with sequence number T+2, which is inconsistent with the expected data packet. The register ERSN does not increase, and the expected response packet with expected sequence number T+1 is sent again. At the same time, the receiving end B stores the T+2 data packet. During the transmission of the entire data block, the sending end can send the lost packet. At this point, the receiving end A will receive two identical response packets, and determine that the data packet with sequence number T+1 is lost, so it organizes retransmission.

[0075] Step S103: Receive the response signal, determine whether the response signal is repeated, if it is repeated, suspend the sending operation according to the preset blocking window, and resend the data to the data receiving end according to the response signal and the simulation data stored in the memory chip, if it is not repeated, perform sequential sending operations according to the preset sliding window and the response signal until the data transmission is completed.

[0076] Optionally, in this embodiment, the transmitting end A needs to determine whether the response signal is missing or repeated.

[0077] Optionally, if the response signal is discontinuous (missing), it means that the response packet may be lost, resulting in the sender A not receiving the expected response. When the sender A finds that the response packet is lost, it will start to monitor the sequence numbers in the subsequent response packets received. The sender A will record and compare the sequence numbers in each response packet to find the largest sequence number. By comparing the maximum sequence number with the sequence number range of the sent data packets, the sender A can infer the data packet sequence number corresponding to the response packet that may be lost.

[0078] For example, assume that sender A has sent the following data packets in order, with sequence numbers 1, 2, 3, 4, and 5:

[0079] Data packet 1 (sequence number 1) is successfully received, and receiver B sends a response packet, expecting to receive data packet with sequence number 2.

[0080] Packet 2 (sequence number 2) is also received successfully, but the corresponding ACK packet is lost.

[0081] Data packet 3 (sequence number 3) and data packet 4 (sequence number 4) are successfully received, and receiver B sends a response packet. However, since the response packet for data packet 2 is lost, sender A only receives the response packets with expected sequence numbers 3 and 4.

[0082] Packet 5 (sequence number 5) is also sent, but at this point sender A notices a problem: it has not received the response packet for sequence number 2, but has received the response packets for sequence numbers 3 and 4.

[0083] In this case, sender A will begin to suspect that the response packet of data packet 2 may be lost. To confirm this, it will continue to monitor the subsequent response packets received. If it does not receive the response packet with the expected sequence number 2, but directly receives the response packet with the expected higher sequence number (such as sequence number 6 or higher), then sender A can determine that the response packet of data packet 2 is indeed lost.

[0084] Once the acknowledgement packet is confirmed to be lost, sender A can take appropriate measures, such as resending data packet 2, to ensure the integrity and order of the data. In this way, even when the network is unstable or the acknowledgement packet may be lost, sender A can effectively manage the data transmission process and ensure the accurate delivery of data.

[0085] Optionally, if the response signal is repeated, it means that the simulation data packet may be lost. When the sender receives two identical expected response packets, it is judged as an abnormal situation such as data packet loss or network congestion. At this time, the sender will read back the missing data according to the response signal and retransmit it.

[0086] After detecting an abnormal situation, the sliding blocking window stops sliding and performs the blocking function. The sequential sending logic of the data packet automatically enters the PAUSE state until the retransmission ends and continues to send the data sequentially. The blocking window limits the sender A from uncontrolled burst transmission of data when the receiver B is congested, avoiding the cumulative congestion of the flow channel.

[0087] During the retransmission logic, the upstream simulation device may continue to send new data to the transmitter A. In order to prevent this data from accumulating in the DDR SDRAM and causing insufficient storage space, the transmitter A adopts an overwrite strategy. This means that if a data packet in a certain DDR SDRAM has been successfully sent and received a correct response from the simulation host, the space in this DDR SDRAM can be overwritten and used by the newly incoming data. In this way, even if device A is processing the retransmission logic, it can ensure that the newly incoming simulation data will not be discarded, thereby avoiding the frame loss of simulation data.

[0088] Specifically, in the correct response mode, the sending end A receives the header packet ACK of the next data block of a certain simulation data block of the receiving end B, which means that the receiving end B has completely received the simulation data block, and the DDR SDRAM storing this data block can be overwritten by the new simulation input data.

[0089] This example demonstrates how this embodiment implements simulated data transmission through communication pre-negotiation, variable packet header, sliding blocking window mechanism, adaptive cache and cumulative response mechanism, thereby increasing the efficiency and flexibility of simulated data transmission.

[0090] From the above description, it can be seen that the simulation data transmission control method based on multi-chip memory provided in the embodiment of the present application can receive the operating data of the simulation device, sequentially and cyclically store the operating data according to multiple preset memory chips, determine the corresponding simulation data, and send the simulation data to the data receiving end in sequence according to the set optimal transmission parameters, so that after the data receiving end receives the simulation data, it determines the corresponding response signal according to the secondary sequence number in the simulation data; receives the response signal, determines whether the response signal is repeated, and if so, suspends the sending operation according to the preset blocking window, and retransmits the data to the data receiving end according to the response signal and the simulation data stored in the memory chip; if not, performs sequential sending operations according to the preset sliding window and the response signal until the data transmission is completed, thereby improving the efficiency and flexibility of the simulation data transmission.

[0091] In one embodiment of the multi-chip memory-based simulated data transmission control method of the present application, see Figure 2 , and can also include the following:

[0092] Step S201: receiving preset initial transmission parameters sent by the data receiving end;

[0093] Step S202: performing a communication test operation on the data receiving end according to the initial transmission parameters, so that the data receiving end determines the corresponding optimal transmission parameters according to a set algorithm model.

[0094] Optional, communication pre-negotiation process, in order to ensure efficient communication under different devices and network conditions, for different terminal devices and network media, various parameters such as network delay and host processing capacity are random. In order to improve the adaptability and robustness of the protocol, this solution can automatically adjust the MTU and IFG values ​​according to the network conditions of this communication and the responsiveness of the terminal device through pre-negotiation. Under high-latency or unstable network conditions, the protocol adopts a more conservative data transmission strategy. In a high-speed and stable network environment, more radical optimization measures are adopted.

[0095] Specifically, first, the sender A sends a communication request, and the receiver B responds with the initial parameters. Then, in the test phase, the sender A starts to send test data packets in groups according to the initial parameters until all are sent. Finally, the receiver B obtains the optimal communication parameters through algorithm processing and informs the sender A. The sender A sends simulation data to the receiver B according to the optimal communication parameters.

[0096] Through step S202, this embodiment achieves more flexible and efficient communication by determining the optimal communication parameters.

[0097] In one embodiment of the multi-chip memory-based simulated data transmission control method of the present application, see Figure 3 , and can also include the following:

[0098] Step S301: determining a plurality of corresponding transmission parameter sample combinations according to the initial transmission parameters and a preset sample threshold;

[0099] Step S302: performing data transmission operations on the data receiving end respectively according to the multiple transmission parameter sample combinations, so that the data receiving end determines the corresponding optimal transmission parameters according to the multiple groups of test data obtained after the data transmission operation and the preset communication comprehensive performance indicator model.

[0100] Optionally, in this embodiment, the initial value of the maximum transmission unit MTU test of the application layer data packet is the maximum multiple of 128 bytes contained by half of the maximum value of the receiving end buffer. For example, if the receiving end buffer is 4096 bytes, the initial value of the maximum transmission unit MTU test of the application layer data packet is 2048.

[0101] Optionally, in this embodiment, the Ethernet standard IEEE 802.3 stipulates that the minimum frame interval is 12 bytes, and the initial value of the frame interval IFG is 12.

[0102] Optionally, in this embodiment, the sample M value of the maximum transmission unit MTU of the application layer data packet is taken, that is, with 128 bytes as the step size, the MTU gradually decreases and the minimum size is 128 bytes, and each MTU value is taken as sample M.

[0103] Optionally, in this embodiment, the value of sample g of the frame interval IFG increases in the range of 12 bytes to 20 bytes, and each IFG value is taken as sample g.

[0104] Construct sample combinations (M, g), and test each group (M, g) 216 times to obtain the throughput and packet loss rate.

[0105] It is understandable that actual tests have shown that the impact of frame intervals in the range of 12 bytes to 20 bytes on network throughput and latency is significant. A smaller frame interval can improve throughput, but a too small frame interval will increase the probability of collision; a larger frame interval will increase latency, but can reduce device processing pressure and packet loss rate. 20 bytes, as a relatively large value, can provide enough data points to evaluate the impact of different frame intervals on network performance, while avoiding waste of resources caused by excessive frame intervals. Therefore, it is scientific and reasonable to choose a range of 12 bytes to 20 bytes for testing.

[0106] Through communication testing, the receiving end B can obtain corresponding communication indicators, including throughput T, packet loss rate L, transmission efficiency E, delay D and processing capacity D.

[0107] The receiving end B builds two models, the comprehensive performance indicator model Y0:

[0108]

[0109] Total indicator model Y1:

[0110]

[0111] According to the entropy weight method, the weight E of the above total index model Y1 is calculated T and W L Since the dimensions of throughput T and packet loss rate L are not consistent, the range transformation method is used to normalize them before calculation to make heterogeneous indicators homogeneous. For positive indicators such as throughput T, negative indicators such as packet loss rate L are treated differently.

[0112] After normalization, the weight of the j-th indicator sample value is calculated in turn, the entropy value of the j-th indicator is calculated, and the weight of each indicator is calculated according to the information entropy of each indicator to obtain the weight W Tand W L After that, the specific Y1 formula can be obtained.

[0113] After obtaining the specific Y1 formula, the value of Y1 under a certain sample (M, g) can be calculated by the Y1 formula according to the actual test data. Within a certain range, Y0 and Y1 can be considered equivalent, and the value of Y1 is assigned to Y0. The corresponding data matrix and target vector constructed by the comprehensive performance indicator model Y0 are as follows:

[0114] Construct a data matrix from the statistical samples:

[0115]

[0116] The target vector Y0 is constructed from the statistical samples.

[0117] When the following conditions are met, the specific value of the weight is obtained:

[0118]

[0119] At this time, the expression of Y0 can minimize the sum of squared errors. The sum of squared errors is:

[0120]

[0121] At this point, the objective function has a specific form, namely the comprehensive performance formula:

[0122]

[0123] The comprehensive performance formula is iterated according to a preset gradient ascent algorithm to determine the corresponding optimal comprehensive performance index. At this time, Y0 is the optimal comprehensive performance index, which is the optimal value after comprehensively considering transmission efficiency, delay and processing capacity. According to Y0 at this time, the corresponding MTU value and IFG value are obtained, and the receiving end sends the MTU value and IFG value at this time to the sending end, so that the sending end communicates with the optimal MTU value and IFG value.

[0124] Through step S302, this embodiment realizes the calculation of the optimal transmission parameters, laying a foundation for the subsequent realization of flexible communication.

[0125] In one embodiment of the multi-chip memory-based simulated data transmission control method of the present application, see Figure 4 , and can also include the following:

[0126] Step S401: determining whether the maximum transmission unit value in the optimal transmission parameter is greater than a preset value; if so, performing a check data adding operation on the simulation data according to a preset cyclic redundancy check algorithm, and sending the simulation data obtained after the check data adding operation to the data receiving end in sequence according to the frame interval in the optimal transmission parameter;

[0127] Step S402: If it is not greater than, sending the simulation data to the data receiving end in sequence according to the frame interval in the optimal transmission parameter.

[0128] Optionally, in this embodiment, in order to ensure data transmission accuracy under different network transmission environments while maximizing bandwidth utilization, the header information of the application layer data packet can be dynamically adjusted, and a dynamic CRC check mechanism (Cyclic Redundancy Check) is added.

[0129] Specifically, when the MTU is 128 bytes, the protocol overhead is removed, the data volume is small enough, setting the checksum part is less cost-effective, and the packet header has no CRC check part;

[0130] When the MTU is greater than 128 bytes and less than 1024 bytes, a 16-bit CRC check is set in the packet header;

[0131] When the MTU is greater than 1024 bytes, a 32-bit CRC check part is set in the packet header. As the data volume increases, the length of the CRC check part is increased, greatly improving the accuracy of the check with a smaller protocol overhead.

[0132] It can be understood that CRC checksum generates a checksum and appends it to the data packet. The receiving end verifies the integrity of the data by recalculating the checksum. It can effectively detect data errors caused by noise, interference or other transmission problems. In terms of effect, the complexity of CRC checksum is dynamically adjusted according to the pre-negotiated network parameters and device capabilities to achieve a balance between reliability and performance.

[0133] Through step S402, this embodiment successfully implements dynamic verification of variable packet headers and balances the performance and reliability of simulation communications.

[0134] In one embodiment of the multi-chip memory-based simulated data transmission control method of the present application, see Figure 5 , and can also include the following:

[0135] Step S501: determining whether the secondary sequence numbers in the simulation data are continuous, and if so, performing a response signal generation operation in ascending order to determine a corresponding response signal;

[0136] Step S502: If it is not continuous, then a response signal generation operation is performed according to the secondary sequence number missing in the simulation data to determine a corresponding response signal.

[0137] Optionally, in this embodiment, in this step, the receiving end B detects whether the secondary sequence of the simulated data packet sent by the sending end A is continuous.

[0138] Receiver B maintains an expected response sequence number register ERSN REGISTER (Expect responseserial number register). Whenever receiver B receives a data packet, register ERSN enters the logic of determining whether to self-increment. Receiver B returns a response signal based on register ERSN, which contains the secondary sequence number of the next data packet to be received. In other words, receiver B will only accept data packets that arrive in sequence, store the data in the receiving buffer in turn, and inform sender A of the sequence number of the next data packet expected to be received through a response signal. If receiver B finds that the sequence of data packets is not continuous, it will not generate the next secondary sequence number, but will continue to generate the lost secondary sequence number.

[0139] For example, the sender sends data packet 1, data packet 2, data packet 3 in sequence...

[0140] The receiving end first receives data packet 1, and then it returns a response signal to the sending end, which contains the expected data packet sequence number 2 (that is, the next sequence number of data packet 1).

[0141] After receiving the response signal, the sender knows that data packet 1 has been successfully received, so it continues to send data packet 2.

[0142] If for some reason (such as network delay or packet loss), data packet 2 does not arrive at the receiving end immediately, but the receiving end still expects to receive data packet 2 (sequence number 2), it will not increment itself, but continue to send requests for the expected data packet sequence number 2 until data packet 2 is received and stored.

[0143] This process continues until all packets are received correctly and in sequence.

[0144] Through step S502, this embodiment successfully increases the reliability and stability of data transmission by accumulating responses.

[0145] In one embodiment of the multi-chip memory-based simulated data transmission control method of the present application, see Figure 6 , and can also include the following:

[0146] Step S601: Determine whether the response signal is continuous;

[0147] Step S602: If it is not continuous, resending the data to the data receiving end according to the largest response signal and the simulation data stored in the memory chip.

[0148] Optionally, in this embodiment, in this step, the transmitting end A detects whether the expected secondary sequence in the response signal of the receiving end B is continuous.

[0149] If the expected secondary sequence in the response signal is not continuous, it means that the response packet may be lost, resulting in the sender A not receiving the expected response. When the sender A finds that the response packet is lost, it will start to monitor the sequence numbers in the subsequent response packets received. The sender A will record and compare the sequence numbers in each response packet to find the largest sequence number. By comparing the maximum sequence number with the sequence number range of the sent data packets, the sender A can infer the data packet sequence number corresponding to the response packet that may be lost.

[0150] For example, assume that sender A has sent the following data packets in order, with sequence numbers 1, 2, 3, 4, and 5:

[0151] Data packet 1 (sequence number 1) is successfully received, and receiver B sends a response packet, expecting to receive data packet with sequence number 2.

[0152] Packet 2 (sequence number 2) is also received successfully, but the corresponding ACK packet is lost.

[0153] Data packet 3 (sequence number 3) and data packet 4 (sequence number 4) are successfully received, and receiver B sends a response packet. However, since the response packet for data packet 2 is lost, sender A only receives the response packets with expected sequence numbers 3 and 4.

[0154] Packet 5 (sequence number 5) is also sent, but at this point sender A notices a problem: it has not received the response packet for sequence number 2, but has received the response packets for sequence numbers 3 and 4.

[0155] In this case, sender A will begin to suspect that the response packet of data packet 2 may be lost. To confirm this, it will continue to monitor the subsequent response packets received. If it does not receive the response packet with the expected sequence number 2, but directly receives the response packet with the expected higher sequence number (such as sequence number 6 or higher), then sender A can determine that the response packet of data packet 2 is indeed lost.

[0156] Once the acknowledgement packet is confirmed to be lost, sender A can take appropriate measures, such as resending data packet 2, to ensure the integrity and order of the data. In this way, even when the network is unstable or the acknowledgement packet may be lost, sender A can effectively manage the data transmission process and ensure the accurate delivery of data.

[0157] Through step S602, this embodiment successfully increases the reliability of data transmission and improves the transmission efficiency by accumulating responses.

[0158] In one embodiment of the multi-chip memory-based simulated data transmission control method of the present application, see Figure 7 , and can also include the following:

[0159] Step S701: judging whether the historical operation data in the plurality of preset memory slices has been successfully transmitted according to the preset response signal rule;

[0160] Step S702: If yes, then performing a data overwriting operation on the historical operation data according to the received operation data of the simulation device to determine the corresponding simulation data;

[0161] Step S703: If not, determining corresponding simulation data according to the response signal rule and the historical operation data.

[0162] Optionally, in this embodiment, this step applies an adaptive caching mechanism to avoid simulation data frame loss in the event of network transmission congestion, smooth the simulation data flow from the front-end simulation device to the receiving host, and ensure the accuracy and completeness of the data collected by the simulation device.

[0163] Specifically, in the above steps, the transmitter A is sending simulation data to the receiver B in sequence. At this time, the multiple DDR SDRAMs of the transmitter A respectively store the historical simulation data transmitted by the upstream simulation device, and are repeatedly reading and writing. When the situation in step S4 occurs, the sequential sending logic of the data packets between A and B automatically enters the PAUSE state.

[0164] During the retransmission logic, the upstream simulation device may continue to send new data to the transmitter A. In order to prevent this data from accumulating in the DDR SDRAM and causing insufficient storage space, the transmitter A adopts an overwrite strategy. This means that if a data packet in a certain DDR SDRAM has been successfully sent and received a correct response from the simulation host, the space in this DDR SDRAM can be overwritten and used by the newly incoming data. In this way, even if device A is processing the retransmission logic, it can ensure that the newly incoming simulation data will not be discarded, thereby avoiding the frame loss of simulation data.

[0165] Specifically, in the correct response mode, the sending end A receives the header packet ACK of the next data block of a certain simulation data block of the receiving end B, which means that the receiving end B has completely received the simulation data block, and the DDR SDRAM storing this data block can be overwritten by the new simulation input data.

[0166] Through step S703, this embodiment successfully ensures the accuracy and integrity of the data collected by the simulation device based on the adaptive cache mechanism.

[0167] In order to improve the efficiency and flexibility of simulated data transmission, the present application provides an embodiment of a simulated data transmission control device based on a multi-chip memory for implementing all or part of the contents of the simulated data transmission control method based on a multi-chip memory, see Figure 8 The simulation data transmission control device based on multiple memory chips specifically includes the following contents:

[0168] The simulation data determination module 10 is used to receive the operation data of the simulation device, and perform sequential cyclic storage operations on the operation data according to a plurality of preset memory slices to determine the corresponding simulation data, wherein the simulation data includes a primary sequence number and a secondary sequence number, the primary sequence number is used to identify a complete data block of the simulation data, and the secondary sequence number is used to identify the position of each data packet in the complete data block;

[0169] The response signal determination module 20 is used to send the simulation data to the data receiving end in sequence according to the set optimal transmission parameters, so that after the data receiving end receives the simulation data, it determines the corresponding response signal according to the secondary sequence number in the simulation data, and sends the response signal, wherein the response signal is used to indicate the secondary sequence number of the next data packet that the data receiving end expects to receive;

[0170] The cumulative response transmission module 30 is used to receive the response signal and determine whether the response signal is repeated. If it is repeated, the sending operation is suspended according to the preset blocking window, and the data receiving end is retransmitted according to the response signal and the simulation data stored in the memory chip. If it is not repeated, a sequential sending operation is performed according to the preset sliding window and the response signal until the data transmission is completed.

[0171] From the above description, it can be seen that the simulation data transmission control device based on multi-chip memory provided in the embodiment of the present application can receive the operating data of the simulation device, sequentially and cyclically store the operating data according to multiple preset memory chips, determine the corresponding simulation data, and send the simulation data to the data receiving end in sequence according to the set optimal transmission parameters, so that after the data receiving end receives the simulation data, it determines the corresponding response signal according to the secondary sequence number in the simulation data; receives the response signal, determines whether the response signal is repeated, and if so, suspends the sending operation according to the preset blocking window, and resends the data to the data receiving end according to the response signal and the simulation data stored in the memory chip; if not, performs sequential sending operations according to the preset sliding window and the response signal until the data transmission is completed, thereby improving the efficiency and flexibility of the simulation data transmission.

[0172] From the hardware level, in order to improve the efficiency and flexibility of simulated data transmission, the present application provides an embodiment of an electronic device for implementing all or part of the contents of the simulated data transmission control method based on multiple memory chips, and the electronic device specifically includes the following contents:

[0173] Processor, memory, communication interface and bus; wherein the processor, memory and communication interface communicate with each other through the bus; the communication interface is used to realize information transmission between the simulation data transmission control method based on multiple memory chips and related devices such as core business systems, user terminals and related databases; the logic controller can be a desktop computer, a tablet computer and a mobile terminal, etc., but the present embodiment is not limited thereto. In the present embodiment, the logic controller can be implemented with reference to the embodiment of the simulation data transmission control method based on multiple memory chips and the embodiment of the simulation data transmission control method based on multiple memory chips in the embodiment, and the contents thereof are incorporated herein, and the repeated parts are not repeated.

[0174] It is understandable that the user terminal may include a smart phone, a tablet electronic device, a network set-top box, a portable computer, a desktop computer, a personal digital assistant (PDA), a vehicle-mounted device, a smart wearable device, etc. Among them, the smart wearable device may include smart glasses, a smart watch, a smart bracelet, etc.

[0175] In practical applications, part of the simulation data transmission control method based on multiple memory chips can be executed on the electronic device side as described above, or all operations can be completed in the client device. The selection can be made based on the processing capability of the client device and the limitations of the user's usage scenario. This application does not limit this. If all operations are completed in the client device, the client device may also include a processor.

[0176] The client device may have a communication module (i.e., a communication unit) that can communicate with a remote server to achieve data transmission with the server. The server may include a server on the task scheduling center side, and other implementation scenarios may also include a server on an intermediate platform, such as a server on a third-party server platform that has a communication link with the task scheduling center server. The server may include a single computer device, or a server cluster consisting of multiple servers, or a server structure of a distributed device.

[0177] Fig. 9 FIG. 9 is a schematic block diagram of the system structure of the electronic device 9600 according to an embodiment of the present application. Fig. 9 As shown, the electronic device 9600 may include a central processor 9100 and a memory 9140; the memory 9140 is coupled to the central processor 9100. It is worth noting that Fig. 9 is exemplary; other types of structures may also be used to supplement or replace this structure to implement telecommunication functions or other functions.

[0178] In one embodiment, the function of the simulation data transmission control method based on multiple memory chips can be integrated into the central processing unit 9100. The central processing unit 9100 can be configured to perform the following control:

[0179] Step S101: receiving the operation data of the simulation device, and performing sequential cyclic storage operations on the operation data according to a plurality of preset memory slices to determine corresponding simulation data, wherein the simulation data includes a primary sequence number and a secondary sequence number, the primary sequence number is used to identify a complete data block of the simulation data, and the secondary sequence number is used to identify the position of each data packet in the complete data block;

[0180] Step S102: sending the simulation data to the data receiving end in sequence according to the set optimal transmission parameters, so that after receiving the simulation data, the data receiving end determines a corresponding response signal according to the secondary sequence number in the simulation data, and sends the response signal, wherein the response signal is used to indicate the secondary sequence number of the next data packet that the data receiving end expects to receive;

[0181] Step S103: Receive the response signal, determine whether the response signal is repeated, if it is repeated, suspend the sending operation according to the preset blocking window, and resend the data to the data receiving end according to the response signal and the simulation data stored in the memory chip, if it is not repeated, perform sequential sending operations according to the preset sliding window and the response signal until the data transmission is completed.

[0182] From the above description, it can be seen that the electronic device provided in the embodiment of the present application receives the operating data of the simulation device, sequentially and cyclically stores the operating data according to multiple preset memory chips, determines the corresponding simulation data, and sends the simulation data to the data receiving end in sequence according to the set optimal transmission parameters, so that after the data receiving end receives the simulation data, it determines the corresponding response signal according to the secondary sequence number in the simulation data; receives the response signal, determines whether the response signal is repeated, and if so, suspends the sending operation according to the preset blocking window, and resends the data to the data receiving end according to the response signal and the simulation data stored in the memory chip; if not, performs sequential sending operations according to the preset sliding window and the response signal until the data transmission is completed, thereby improving the efficiency and flexibility of the simulation data transmission.

[0183] In another embodiment, the simulated data transmission control method based on multi-chip memories can be configured separately from the central processing unit 9100. For example, the simulated data transmission control method based on multi-chip memories can be configured as a chip connected to the central processing unit 9100, and the function of the simulated data transmission control method based on multi-chip memories can be realized through the control of the central processing unit.

[0184] like Fig. 9 As shown, the electronic device 9600 may also include: a communication module 9110, an input unit 9120, an audio processor 9130, a display 9160, and a power supply 9170. It is worth noting that the electronic device 9600 does not necessarily have to include Fig. 9 In addition, the electronic device 9600 may also include Fig. 9 For components not shown, reference may be made to the prior art.

[0185] like Fig. 9 As shown, the central processing unit 9100 is sometimes also referred to as a controller or an operation control, and may include a microprocessor or other processor device and / or logic device. The central processing unit 9100 receives input and controls the operation of various components of the electronic device 9600.

[0186] The memory 9140 may be, for example, one or more of a cache, a flash memory, a hard drive, a removable medium, a volatile memory, a non-volatile memory or other suitable devices. The above-mentioned information related to the failure may be stored, and a program for executing the relevant information may also be stored. The CPU 9100 may execute the program stored in the memory 9140 to implement information storage or processing, etc.

[0187] The input unit 9120 provides input to the central processing unit 9100. The input unit 9120 is, for example, a key or a touch input device. The power supply 9170 is used to provide power to the electronic device 9600. The display 9160 is used to display display objects such as images and texts. The display may be, for example, an LCD display, but is not limited thereto.

[0188] The memory 9140 may be a solid-state memory, such as a read-only memory (ROM), a random access memory (RAM), a SIM card, etc. It may also be a memory that saves information even when the power is off, can be selectively erased, and is provided with more data, examples of which are sometimes referred to as EPROMs, etc. The memory 9140 may also be some other type of device. The memory 9140 includes a buffer memory 9141 (sometimes referred to as a buffer). The memory 9140 may include an application / function storage unit 9142, which is used to store application programs and function programs or processes for executing the operation of the electronic device 9600 through the central processor 9100.

[0189] The memory 9140 may also include a data storage unit 9143 for storing data, such as contacts, digital data, pictures, sounds, and / or any other data used by the electronic device. The driver storage unit 9144 of the memory 9140 may include various drivers for communication functions of the electronic device and / or for executing other functions of the electronic device (such as messaging applications, address book applications, etc.).

[0190] The communication module 9110 is a transmitter / receiver that sends and receives signals via the antenna 9111. The communication module 9110 is coupled to the central processor 9100 to provide input signals and receive output signals, which may be the same as the case of a conventional mobile communication terminal.

[0191] Based on different communication technologies, multiple communication modules 9110 may be provided in the same electronic device, such as a cellular network module, a Bluetooth module and / or a wireless local area network module, etc. The communication module 9110 is also coupled to a speaker 9131 and a microphone 9132 via an audio processor 9130 to provide an audio output via the speaker 9131 and receive an audio input from the microphone 9132, thereby realizing a common telecommunication function. The audio processor 9130 may include any suitable buffer, decoder, amplifier, etc. In addition, the audio processor 9130 is also coupled to the central processor 9100, so that recording can be performed on the machine through the microphone 9132, and the sound stored on the machine can be played through the speaker 9131.

[0192] The embodiment of the present application also provides a computer-readable storage medium capable of implementing all the steps in the method for controlling simulated data transmission based on multiple memory chips in the above embodiment, where the execution subject is a server or a client. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, all the steps in the method for controlling simulated data transmission based on multiple memory chips in the above embodiment are implemented. For example, when the processor executes the computer program, the following steps are implemented:

[0193] Step S101: receiving the operation data of the simulation device, and performing sequential cyclic storage operations on the operation data according to a plurality of preset memory slices to determine corresponding simulation data, wherein the simulation data includes a primary sequence number and a secondary sequence number, the primary sequence number is used to identify a complete data block of the simulation data, and the secondary sequence number is used to identify the position of each data packet in the complete data block;

[0194] Step S102: sending the simulation data to the data receiving end in sequence according to the set optimal transmission parameters, so that after receiving the simulation data, the data receiving end determines a corresponding response signal according to the secondary sequence number in the simulation data, and sends the response signal, wherein the response signal is used to indicate the secondary sequence number of the next data packet that the data receiving end expects to receive;

[0195] Step S103: Receive the response signal, determine whether the response signal is repeated, if it is repeated, suspend the sending operation according to the preset blocking window, and resend the data to the data receiving end according to the response signal and the simulation data stored in the memory chip, if it is not repeated, perform sequential sending operations according to the preset sliding window and the response signal until the data transmission is completed.

[0196] From the above description, it can be seen that the computer-readable storage medium provided in the embodiment of the present application receives the operating data of the simulation device, sequentially and cyclically stores the operating data according to multiple preset memory chips, determines the corresponding simulation data, and sends the simulation data to the data receiving end in sequence according to the set optimal transmission parameters, so that after the data receiving end receives the simulation data, it determines the corresponding response signal according to the secondary sequence number in the simulation data; receives the response signal, determines whether the response signal is repeated, and if so, suspends the sending operation according to the preset blocking window, and resends the data to the data receiving end according to the response signal and the simulation data stored in the memory chip; if not, performs sequential sending operations according to the preset sliding window and the response signal until the data transmission is completed, thereby improving the efficiency and flexibility of the simulation data transmission.

[0197] The embodiment of the present application also provides a computer program product capable of implementing all the steps in the simulation data transmission control method based on multiple memory chips in the above embodiment, where the execution subject is a server or a client. When the computer program / instruction is executed by a processor, the steps of the simulation data transmission control method based on multiple memory chips are implemented. For example, the computer program / instruction implements the following steps:

[0198] Step S101: receiving the operation data of the simulation device, and performing sequential cyclic storage operations on the operation data according to a plurality of preset memory slices to determine corresponding simulation data, wherein the simulation data includes a primary sequence number and a secondary sequence number, the primary sequence number is used to identify a complete data block of the simulation data, and the secondary sequence number is used to identify the position of each data packet in the complete data block;

[0199] Step S102: sending the simulation data to the data receiving end in sequence according to the set optimal transmission parameters, so that after receiving the simulation data, the data receiving end determines a corresponding response signal according to the secondary sequence number in the simulation data, and sends the response signal, wherein the response signal is used to indicate the secondary sequence number of the next data packet that the data receiving end expects to receive;

[0200] Step S103: Receive the response signal, determine whether the response signal is repeated, if it is repeated, suspend the sending operation according to the preset blocking window, and resend the data to the data receiving end according to the response signal and the simulation data stored in the memory chip, if it is not repeated, perform sequential sending operations according to the preset sliding window and the response signal until the data transmission is completed.

[0201] From the above description, it can be seen that the computer program product provided in the embodiment of the present application receives the running data of the simulation device, sequentially and cyclically stores the running data according to multiple preset memory chips, determines the corresponding simulation data, and sends the simulation data to the data receiving end in sequence according to the set optimal transmission parameters, so that after the data receiving end receives the simulation data, it determines the corresponding response signal according to the secondary sequence number in the simulation data; receives the response signal, determines whether the response signal is repeated, and if so, suspends the sending operation according to the preset blocking window, and resends the data to the data receiving end according to the response signal and the simulation data stored in the memory chip; if not, performs sequential sending operations according to the preset sliding window and the response signal until the data transmission is completed, thereby improving the efficiency and flexibility of the simulation data transmission.

[0202] It should be understood by those skilled in the art that embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0203] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (apparatus), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0204] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0205] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0206] The present invention uses specific embodiments to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A simulation data transmission control method based on multi-chip memory, characterized in that: Applied to a data sending end, the data sending end is communicatively connected with a preset data receiving end and a preset simulation device, the method comprises: Receive the operation data of the simulation device, and perform sequential cyclic storage operations on the operation data according to a plurality of preset memory slices to determine corresponding simulation data, wherein the simulation data includes a primary sequence number and a secondary sequence number, the primary sequence number is used to identify a complete data block of the simulation data, and the secondary sequence number is used to identify the position of each data packet in the complete data block; The simulation data is sequentially sent to the data receiving end according to the set optimal transmission parameters, so that after receiving the simulation data, the data receiving end determines a corresponding response signal according to the secondary sequence number in the simulation data, and sends the response signal, wherein the response signal is used to indicate the secondary sequence number of the next data packet that the data receiving end expects to receive; Receive the response signal, determine whether the response signal is repeated, if it is repeated, suspend the sending operation according to a preset blocking window, and resend the data to the data receiving end according to the response signal and the simulation data stored in the memory chip; if it is not repeated, perform sequential sending operations according to the preset sliding window and the response signal until the data transmission is completed.

2. The method for controlling simulated data transmission based on multiple memory chips according to claim 1, characterized in that: Before the operation of sending the simulation data to the data receiving end in sequence according to the set optimal transmission parameters, the method includes: Receiving preset initial transmission parameters sent by the data receiving end; A communication test operation is performed on the data receiving end according to the initial transmission parameters, so that the data receiving end determines the corresponding optimal transmission parameters according to the set algorithm model.

3. The method for controlling simulated data transmission based on multiple memory chips according to claim 2, characterized in that: The performing a communication test operation on the data receiving end according to the initial transmission parameters so that the data receiving end determines the corresponding optimal transmission parameters according to a set algorithm model includes: Determine a corresponding plurality of transmission parameter sample combinations according to the initial transmission parameter and a preset sample threshold; Data transmission operations are performed on the data receiving end respectively according to the multiple transmission parameter sample combinations, so that the data receiving end determines the corresponding optimal transmission parameters according to the multiple groups of test data obtained after the data transmission operation and the preset communication comprehensive performance indicator model.

4. The method for controlling simulated data transmission based on multiple memory chips according to claim 1, characterized in that: The operation of setting the optimal transmission parameters and sending the simulation data to the data receiving end in sequence includes: Determine whether the maximum transmission unit value in the optimal transmission parameter is greater than a preset value, and if so, perform a check data adding operation on the simulation data according to a preset cyclic redundancy check algorithm, and send the simulation data obtained after the check data adding operation to the data receiving end in sequence according to the frame interval in the optimal transmission parameter; If it is not greater than, the simulation data is sent to the data receiving end in sequence according to the frame interval in the optimal transmission parameter.

5. The method for controlling simulated data transmission based on multiple memory chips according to claim 1, characterized in that: The determining a corresponding response signal according to the secondary sequence number in the simulation data comprises: Determine whether the secondary sequence numbers in the simulation data are continuous, and if so, perform a response signal generation operation in increasing order to determine a corresponding response signal; If not, a response signal generation operation is performed according to the secondary sequence number missing in the simulation data to determine the corresponding response signal.

6. The method for controlling simulated data transmission based on multiple memory chips according to claim 1, characterized in that: After receiving the response signal, the method further includes: Determining whether the response signal is continuous; If not, a data retransmission operation is performed on the data receiving end according to the largest response signal and the simulation data stored in the memory chip.

7. The method for controlling simulated data transmission based on multiple memory chips according to claim 1, characterized in that: The step of performing sequential cyclic storage operations on the operating data according to a plurality of preset memory slices to determine corresponding simulation data includes: According to a preset response signal rule, determining whether the historical operation data in a plurality of preset memory slices has been successfully transmitted; If so, performing a data overwriting operation on the historical operation data according to the received operation data of the simulation device to determine the corresponding simulation data; If not, the corresponding simulation data is determined according to the response signal rule and the historical operation data.

8. A simulation data transmission control device based on multiple memory chips, characterized in that: The device is arranged at a data transmitting end, the data transmitting end is communicatively connected with a preset data receiving end and a preset simulation device, and the device comprises: a simulation data determination module, configured to receive the operation data of the simulation device, and to perform sequential cyclic storage operations on the operation data according to a plurality of preset memory slices to determine corresponding simulation data, wherein the simulation data includes a primary sequence number and a secondary sequence number, the primary sequence number is used to identify a complete data block of the simulation data, and the secondary sequence number is used to identify the position of each data packet in the complete data block; A response signal determination module, used for sending the simulation data to the data receiving end in sequence according to the set optimal transmission parameters, so that after receiving the simulation data, the data receiving end determines the corresponding response signal according to the secondary sequence number in the simulation data, and sends the response signal, wherein the response signal is used to indicate the secondary sequence number of the next data packet that the data receiving end expects to receive; The cumulative response transmission module is used to receive the response signal and determine whether the response signal is repeated. If it is repeated, the sending operation is suspended according to a preset blocking window, and the data receiving end is retransmitted according to the response signal and the simulation data stored in the memory chip. If it is not repeated, a sequential sending operation is performed according to a preset sliding window and the response signal until the data transmission is completed.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of the simulation data transmission control method based on multi-chip memory according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the simulation data transmission control method based on multi-chip memories described in any one of claims 1 to 7 are implemented.

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