Inter-board Synchronization Trigger Method for Microinstructions and Microinstruction Control Test System

Abstract

The present application relates to an inter-board synchronous triggering method for microinstructions and a microinstruction control test system. The method includes: receiving a synchronous clock signal sent by the communication board card, and starting cyclic counting based on the synchronous clock signal to obtain a clock count value; expanding each test instruction into one or more microinstructions in sequence based on the sorting of multiple test instructions pre-loaded into the buffer; receiving a start instruction sent by the communication board card, where the start instruction includes a start count value; comparing the start count value with the clock count value, and when the clock count value is equal to the start count value for the first time, triggering the operation of the microinstructions, which solves the problem that communication time is required for synchronous triggering of microinstructions and the real-time performance is poor.

Description

Technical Field

[0001] This application relates to the field of chip testing, and particularly to a method for inter-board synchronous triggering of microinstructions and a microinstruction control test system. Background Art

[0002] A semiconductor chip ATE (Automatic Test Equipment) is used to detect the integrity of the functions and performance of integrated circuits, and is an important device for ensuring the quality of integrated circuits in the integrated circuit production and manufacturing process. The testing of integrated circuits usually goes through four steps: test program design, program compilation, vector loading, and test execution, and the PATTERN (test vector) file runs through each step of the integrated circuit testing. The main content contained in the PATTERN file is the symbol combination of input levels and expected output levels, and also contains microinstructions for implementing certain complex functions. During the testing process, multiple resource boards need to cooperate, and it is required that microinstructions can be synchronously triggered between different boards. However, the existing triggering method usually parses the trigger (TRIGGER) microinstruction when the digital board (DIO) runs the PATTERN, and sends the TRIGGER message to the communication bus. After other boards receive this instruction, they complete the corresponding operations. This method takes communication time and has poor real-time performance. Summary of the Invention

[0003] In this embodiment, a method for inter-board synchronous triggering of microinstructions and a microinstruction control test system are provided to solve the problem in the related art that communication time is required for multi-board microinstruction synchronous triggering and the real-time performance is poor.

[0004] In a first aspect, in this embodiment, a method for inter-board synchronous triggering of microinstructions is provided. The method is applied to a resource board in a microinstruction control test system. The system includes a host computer, a communication board communicatively connected to the host computer, and a plurality of resource boards connected to the communication board. The method includes:

[0005] Receiving a synchronous clock signal sent by the communication board, and starting cyclic counting based on the synchronous clock signal to obtain a clock count value;

[0006] Based on the sorting of multiple test instructions pre-loaded into the buffer, expanding each test instruction into one or more microinstructions in sequence;

[0007] Receiving a start instruction sent by the communication board, where the start instruction includes a start count value;

[0008] Comparing the start count value with the clock count value, and when the clock count value is equal to the start count value for the first time, triggering the operation of the microinstruction.

[0009] In some of these embodiments, the micro-instruction includes an execution cycle serial number, and the triggering of the operation of the micro-instruction when the clock count value first equals the start count value includes:

[0010] When the clock count value first equals the start count value, start counting based on the synchronous clock signal and a pre-configured execution cycle factor to obtain an execution cycle count value;

[0011] Sequentially obtain the execution cycle serial numbers of each of the micro-instructions and compare them with the execution cycle count value;

[0012] When the execution cycle serial number equals the execution cycle count value, execute the micro-instruction until all the micro-instructions in the cache have been executed.

[0013] In some of these embodiments, the micro-instruction further includes an event type and event parameters, and the execution of the micro-instruction includes:

[0014] Based on the event type and the event parameters, obtain the instruction information of the micro-instruction;

[0015] Based on the event parameters, determine the sending object of the micro-instruction;

[0016] Send the instruction information to the sending object.

[0017] In some of these embodiments, the sending of the instruction information to the sending object includes:

[0018] In the case where the sending object is a waveform generator or a waveform collector, perform clock domain conversion on the instruction information and distribute it to the waveform generator or the waveform collector;

[0019] In the case where the sending object is a controller, based on the communication protocol with the controller, send the instruction information to the controller.

[0020] In some of these embodiments, the obtaining of the instruction information of the micro-instruction based on the event type and the event parameters includes:

[0021] In the case where the event type of the micro-instruction is instruction loading, based on the loading address in the event parameters, read the corresponding instruction information from the memory;

[0022] In the case where the event type of the micro-instruction is not instruction loading, generate the corresponding instruction information based on the event parameters.

[0023] In some of these embodiments, the micro-instruction further includes a valid channel, and when the execution cycle number is equal to the execution cycle count value, executing the micro-instruction includes:

[0024] Determining whether the micro-instruction is valid for the resource board based on the valid channel of the micro-instruction;

[0025] If it is valid, execute the micro-instruction;

[0026] If it is invalid, ignore the micro-instruction and read the next micro-instruction.

[0027] In some of these embodiments, the test instruction includes a valid channel, a line difference, an opcode, and function information. Based on the sorting of multiple test instructions pre-loaded into the cache, sequentially expanding each test instruction into one or more micro-instructions includes:

[0028] Obtaining the number of execution cycles corresponding to the test instruction based on the opcode and the function information;

[0029] Obtaining the execution cycle numbers of the respective micro-instructions corresponding to the test instruction based on the line difference and the number of execution cycles;

[0030] Generating one or more micro-instructions corresponding to the test instruction based on the valid channel, the execution cycle number, the opcode, and the function information.

[0031] In some of these embodiments, when the execution cycle number is equal to the execution cycle count value, executing the micro-instruction includes:

[0032] Determining whether the micro-instruction is a delay compensation micro-instruction, and the delay compensation micro-instruction includes a number of delay cycles;

[0033] If so, obtaining the difference between the execution cycle numbers of the respective micro-instructions after the delay compensation micro-instruction and the number of delay cycles;

[0034] Comparing the difference with the execution cycle count value, and when the difference is equal to the execution cycle count value, executing the corresponding micro-instruction.

[0035] In some of these embodiments, before sequentially expanding each test instruction into one or more micro-instructions based on the sorting of multiple test instructions pre-loaded into the cache, the method further includes:

[0036] Sequentially reading multiple test instructions into the cache based on the received pre-loading instruction and the storage address and length of the test instructions;

[0037] Set a preloading flag based on the length of the test instruction, the number of test instructions read into the cache, and the maximum storage capacity of the cache.

[0038] When the value of the preloading flag is equal to a preset value, expand each test instruction into one or more microinstructions in sequence based on the sorting of the test instructions in the cache.

[0039] In a second aspect, a microinstruction control test system is provided in this embodiment. The system includes a host computer, a communication board card communicatively connected to the host computer, and a plurality of resource board cards connected to the communication board card. The resource board card includes a microinstruction controller, and the microinstruction controller includes:

[0040] A service decoding module for receiving a synchronous clock signal and a start instruction sent by the communication board card and forwarding them to the microinstruction control module. The start instruction includes a start count value.

[0041] A test instruction cache module for expanding each test instruction into one or more microinstructions in sequence based on the sorting of a plurality of preloaded test instructions and sending them to the microinstruction control module.

[0042] A microinstruction control module for starting cyclic counting based on the synchronous clock signal to obtain a clock count value; and comparing the start count value with the clock count value, and triggering the execution of the microinstruction when the clock count value first equals the start count value.

[0043] In some of these embodiments, the microinstruction controller further includes a parameter control module, and the microinstruction control module is further configured to:

[0044] When the clock count value first equals the start count value, start counting based on the synchronous clock signal and a preconfigured execution cycle factor to obtain an execution cycle count value.

[0045] Sequentially obtain the execution cycle serial numbers of each microinstruction and compare them with the execution cycle count value.

[0046] When the execution cycle serial number equals the execution cycle count value, determine whether the microinstruction is valid for the resource board card based on the effective channel of the microinstruction.

[0047] If it is valid, send the microinstruction to the parameter control module.

[0048] If it is invalid, ignore the microinstruction and read the next microinstruction.

[0049] In some of these embodiments, the micro-instruction controller further includes a loading control module and a parameter selection module. The micro-instructions include an event type and event parameters.

[0050] The parameter control module is configured to, when the event type in the micro-instruction is instruction loading, parse the corresponding loading instruction based on the micro-instruction and send it to the loading control module.

[0051] When the event type of the micro-instruction is not instruction loading, generate instruction information of the micro-instruction based on the event type and the event parameters, and send the instruction information to the parameter selection module.

[0052] The loading control module is configured to read the corresponding instruction information based on the loading instruction and send it to the parameter selection module.

[0053] In some of these embodiments, the micro-instruction controller further includes a cross-clock domain control module and a controller transmission module.

[0054] The parameter selection module is configured to send the instruction information to the cross-clock domain control module or the controller transmission module based on the event type of the instruction information.

[0055] The cross-clock domain control module is configured to perform clock domain conversion on the instruction information and distribute it to the waveform generator or the waveform collector.

[0056] The controller transmission module is configured to send the instruction information to the controller based on the communication protocol with the controller.

[0057] In some of these embodiments, the micro-instruction controller further includes an instruction request module. The instruction request module is configured to:

[0058] Based on the storage addresses and lengths of the pre-loading instruction and the test instructions received, sequentially read multiple test instructions into the test instruction cache module; set a pre-loading flag based on the length of the test instructions, the number of test instructions read into the test instruction cache module, and the maximum storage capacity of the test instruction cache module.

[0059] Compared with the related art, in the method for inter-board synchronous triggering of microinstructions provided in this embodiment, the resource board receives the synchronous clock signal sent by the communication board and starts cyclic counting based on the synchronous clock signal to obtain the clock count value, providing a unified counting time for multiple resource boards to run microinstructions synchronously; by sorting multiple test instructions pre-loaded into the cache and expanding each test instruction into one or more microinstructions in sequence, each microinstruction is stored in the cache in sequence according to the execution cycle number generated during expansion to prepare for subsequent execution; the execution of the microinstructions is started by receiving the start instruction sent by the communication board, and the reception times of the start instructions of each resource board are not synchronized; by comparing the start count value in the start instruction with the clock count value, when the clock count value is equal to the start count value for the first time, the running of the microinstructions is triggered, and each resource board determines the triggering timing of the microinstructions according to the same start count value, ensuring that each resource board starts running the microinstructions at the same time, without the need to spend communication time, improving the control accuracy, synchronization accuracy and real-time performance of the instructions.

[0060] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects, and advantages of this application more concise and understandable. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] The drawings described herein are used to provide a further understanding of this application and constitute a part of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an improper limitation of this application. In the drawings:

[0062] Figure 1 is a structural block diagram of a microinstruction control test system according to some embodiments of this application;

[0063] Figure 2 is a flowchart of a method for inter-board synchronous triggering of microinstructions according to some embodiments of this application;

[0064] Figure 3 is a flowchart of microinstruction expansion according to some embodiments of this application;

[0065] Figure 4 is a flowchart of triggering the running of microinstructions according to some embodiments of this application;

[0066] Figure 5 is a flowchart of microinstruction execution according to some embodiments of this application;

[0067] Figure 6 is a flowchart of microinstruction validity determination according to some embodiments of this application;

[0068] Figure 7 is a flowchart of microinstruction delay compensation according to some embodiments of this application;

[0069] Figure 8 It is a flowchart of test instruction preloading in some embodiments of the present application;

[0070] Figure 9 It is a structural block diagram of a microinstruction control test system in some embodiments of the present application;

[0071] Figure 10 It is a structural block diagram of a microinstruction control test system in some other embodiments of the present application;

[0072] Figure 11 It is a structural block diagram of a microinstruction control test system in some other embodiments of the present application;

[0073] Figure 12 It is a structural block diagram of a microinstruction control test system in some other embodiments of the present application;

[0074] Figure 13 It is a structural block diagram of a microinstruction control test system in some preferred embodiments of the present application. Detailed implementation manners

[0075] For a clearer understanding of the purpose, technical solution and advantages of the present application, the present application is described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0076] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meanings understood by those with ordinary skills in the technical field to which this application belongs. In this application, words such as "a", "an", "one kind", "the", "these", etc. do not indicate a limitation in quantity, and they can be singular or plural. The terms "including", "containing", "having" and any variants thereof involved in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product or device including a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent in these processes, methods, products or devices. The similar words such as "connected", "coupled" involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. Usually, the character " / " indicates that the objects associated before and after are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application only distinguish similar objects and do not represent a specific sorting of the objects.

[0077] The inter-board synchronous triggering method of microinstructions provided by the embodiments of this application can be executed in the resource boards in the microinstruction control test system. Figure 1 It is a structural block diagram of the microinstruction control test system of some embodiments of this application. As Figure 1 shown, the microinstruction control test system includes a host computer 10, a communication board 20 communicatively connected to the host computer 10, and a plurality of resource boards 30 (3 are shown in the figure) connected to the communication board 20. Those of ordinary skill in the art can understand that Figure 1 the structure shown is only schematic and does not limit the structure of the above microinstruction control test system. For example, the microinstruction control test system may also include more or fewer components than Figure 1 shown, or have a different configuration from Figure 1 shown.

[0078] In this embodiment, an inter-board synchronous triggering method of microinstructions is provided. Figure 2 It is a flowchart of the inter-board synchronous triggering method of microinstructions of some embodiments of this application. As Figure 2 shown, the process includes the following steps:

[0079] Step S201: Receive the synchronous clock signal sent by the communication board card, and start cyclic counting based on this synchronous clock signal to obtain a clock count value.

[0080] In the micro-instruction control test system, the resource board card is used to provide different types of test resources to the chip under test. The types of multiple resource board cards can be the same or different. The communication board card connects the host computer and the resource board card, and is used to send the test instructions and configuration information of the host computer to the corresponding resource board card, and send the status information of the resource board card to the host computer. The communication board card and the resource board card can be located in different slots of the test machine and are electrically connected through the backplane.

[0081] To ensure the coordinated operation of multiple resource board cards, the communication board card sends a synchronous clock signal MASTER_CLK to multiple resource board cards as the clock reference for the synchronous operation of multiple resource board cards. After all resource board cards are powered on, the communication board card starts to send the synchronous clock signal MASTER_CLK and sets the effective time of the synchronous clock signal. Specifically, the first rising edge of MASTER_CLK can be made effective.

[0082] When each resource board card receives the first rising edge of the synchronous clock signal, it starts cyclic counting, and the maximum value of this cyclic counting can be preset in advance.

[0083] Furthermore, when it is necessary to change the clock frequency of the synchronous clock signal, the output of the synchronous clock signal can be stopped first. When each resource board card cannot receive the synchronous clock signal within a preset time period, the cyclic counter is cleared until the first rising edge of the synchronous clock signal is received next time to start counting. At this time, it can be ensured that all board cards are synchronized in terms of counting time.

[0084] Step S202: Based on the sorting of multiple test instructions pre-loaded into the cache, expand each test instruction into one or more micro-instructions in sequence.

[0085] Multiple test instructions (PATTERN) to be executed are pre-loaded into the cache of the resource board card, and the cache can be a FIFO. Specifically, a preset number of test instructions can be loaded from the DDR into the FIFO based on the pre-loaded instructions, and the pre-loaded instructions include the address and length of the test instructions.

[0086] The test instructions of this embodiment may only include instructions for controlling the execution time and order of statements, as well as instructions for controlling external devices, without including specific chip pin IO operation information. Specifically, the instructions for controlling the execution time and order of statements may include REPAET (single-line loop), LOOP (block loop), ENDLOOP, and TRIG (trigger function test) statements, and the instructions for controlling external devices may include EVENT_AD statements. Among them, the EVENT_AD statement is a collection of multiple microinstructions.

[0087] According to the sorting of multiple test instructions in the cache, each test instruction is expanded in sequence. For example, a test instruction that executes in a loop can be expanded into multiple repeated microinstructions according to the number of executions, and the EVENT_AD statement can also be decoded based on a preset rule to obtain the corresponding microinstructions.

[0088] Step S203: Receive a start instruction sent by the communication board card. The start instruction includes a start count value.

[0089] When preparing to start the operation of the microinstructions, the host computer sends a start instruction to the communication board card, and the communication board card then forwards the start instruction to each resource board card. The time when each resource board card receives the start instruction may not be exactly the same.

[0090] In some embodiments, a counter may be provided on the communication board card. The counter also counts based on the synchronous clock signal MASTER_CLK, takes the count value when the start instruction is received as the start count value, adds it to the start instruction, and forwards it to each resource board card.

[0091] Step S204: Compare the start count value with the clock count value. When the clock count value is equal to the start count value for the first time, trigger the operation of the microinstructions.

[0092] Each resource board card compares the start count value with its own clock count value. When the clock count value is equal to the start count value for the first time, trigger the operation of the microinstructions. Since the clock counting of each resource board card is executed synchronously in a loop, the moment when the clock count value of each resource board card is equal to the start count value for the first time is the same. At this time, trigger the operation of the microinstructions to achieve the synchronous operation of the microinstructions.

[0093] In some embodiments, the start count value is equal to the count value when the communication board card receives the start instruction. Therefore, when each resource board card receives the start instruction, the clock count value of each resource board card must be greater than the start count value. At this time, wait for the next cycle count of each resource board card to reach the start count value, and then trigger the operation of the microinstructions.

[0094] Through steps S201 to S204, by receiving the synchronous clock signal sent by the communication board card and starting cyclic counting based on the synchronous clock signal to obtain the clock count value, it provides a unified counting time for multiple resource board cards to synchronously execute microinstructions; by sorting multiple test instructions pre-loaded into the cache and expanding each test instruction into one or more microinstructions in sequence, each microinstruction is stored in the cache in sequence according to the execution cycle sequence number generated during expansion to prepare for subsequent execution; by receiving the start instruction sent by the communication board card to start the execution of microinstructions, the reception times of the start instructions of each resource board card are not synchronized; by comparing the start count value in the start instruction with the clock count value, when the clock count value is equal to the start count value for the first time, the operation of the microinstruction is triggered, and each resource board card determines the trigger timing of the microinstruction according to the same start count value, ensuring that each resource board card starts to execute the microinstruction at the same time, without spending communication time, and improving the control accuracy, synchronization accuracy and real-time performance of the instruction.

[0095] In some embodiments, Figure 3 is a flowchart of microinstruction expansion in some embodiments of the present application, as Figure 3 shown, this process includes the following steps:

[0096] Step S301, based on the operation code and function information, obtain the number of execution cycles corresponding to the test instruction.

[0097] Specifically, the test instruction includes a valid channel Ch_enable, a line difference Vector_num, an operation code Opcode, and function information Operand.

[0098] Among them, the valid channel Ch_enable is used to identify which resource board cards the test instruction is valid for. Each resource board card corresponds to a channel number, and each bit can identify a channel. The line difference Vector_num is used to represent the line difference between this test instruction and the previous test instruction. The operation code Opcode is the instruction statement, including REPAET, LOOP, ENDLOOP, TRIG, and EVENT_AD statements. For other test instructions except EVENT_AD, the function information Operand is used to record the number of executions of this test instruction. For the EVENT_AD test instruction, the function information Operand is used to record the control object, event type, and event parameters of this test instruction according to preset rules.

[0099] In a specific embodiment, the control objects of the EVENT_AD test instruction can be any arbitrary waveform generator (AWG) and waveform collector (DGT). The event types can include controlling the connection, disconnection, startup, stop, and micro-instruction loading of the AWG and DGT, and the event parameters can be the configuration parameters required during the control of the AWG and DGT.

[0100] When the operation code of the test instruction is TRIG, the corresponding number of execution cycles is 1.

[0101] When the operation codes of the test instruction are REPAET, LOOP, and ENDLOOP, obtain the corresponding number of execution cycles of the test instruction according to the corresponding function information. Among them, the LOOP and ENDLOOP test instructions support multi-level nesting, for example, three-level nesting is supported. Since the LOOP and ENDLOOP instructions need to execute a section of test instructions in a loop, the RAM can be used to store the test instructions.

[0102] Step S302: Based on the line difference and the number of execution cycles, obtain the execution cycle numbers of each micro-instruction corresponding to the test instruction.

[0103] According to the line difference and the number of execution cycles of each test instruction, determine the execution cycle numbers of each micro-instruction corresponding to the test instruction. The starting value of the execution cycle number of the test instruction is equal to the sum of the end value of the execution cycle number of the previous test instruction and the line difference.

[0104] Step S303: Based on the valid channels, execution cycle numbers, operation codes, and function information, generate one or more micro-instructions corresponding to the test instruction.

[0105] Specifically, the micro-instruction format corresponding to the test instruction is as follows:

[0106] Execution cycle number + operation code (Opcode) + function information (Operand).

[0107] Furthermore, in the case of supporting the maximum operating rate, each test instruction can be expanded using one system clock. When the operation code of the test instruction is LOOP, while expanding one test instruction, read out the next test instruction and determine whether the next data is an ENDLOOP instruction and whether the loop count has been reached at this time, so as to generate the corresponding micro-instruction.

[0108] Through steps S301 to S303, by based on the operation code and function information, obtain the number of execution cycles corresponding to the test instruction, that is, the number of executions of the test instruction; based on the line difference and the number of execution cycles, obtain the execution cycle sequence numbers of each micro-instruction corresponding to the test instruction, and strictly correspond the execution order of each micro-instruction with the execution time; by based on the valid channel, execution cycle sequence number, operation code and function information, generate one or more micro-instructions corresponding to the test instruction, convert the repeatedly executed test instruction into sequentially executed micro-instructions, and obtain the execution time of each micro-instruction, improving the control precision and synchronization precision of the test instruction.

[0109] In some embodiments, Figure 4 is a flowchart for triggering the operation of micro-instructions in some embodiments of the present application, as Figure 4 shown, this process includes the following steps:

[0110] Step S401, when the clock count value first equals the start count value, start counting based on the synchronous clock signal and the pre-configured execution cycle factor to obtain the execution cycle count value.

[0111] When the clock count value of the resource board first equals the start count value, start the execution cycle counting to determine whether the execution time of each micro-instruction is correct. Specifically, the execution time of the micro-instruction = execution cycle factor × the period of the synchronous clock signal. The execution cycle factor is pre-configured by the host computer and sent to each resource board. Therefore, the resource board counts according to the synchronous clock signal and the execution cycle factor to obtain the execution cycle count value.

[0112] Step S402, sequentially obtain the execution cycle sequence numbers of each micro-instruction and compare them with the execution cycle count value.

[0113] Each micro-instruction includes a corresponding execution cycle sequence number. Before sequentially executing the micro-instructions, compare the execution cycle sequence number in the micro-instruction with the execution cycle count value.

[0114] Step S403, when the execution cycle sequence number equals the execution cycle count value, execute the micro-instruction until all the micro-instructions in the cache are executed.

[0115] According to the table content in step S303, due to the existence of row difference, the execution cycle numbers of each micro-instruction can be continuous or discontinuous. Before executing a micro-instruction, first determine whether the execution cycle count value is equal to the execution cycle number of this micro-instruction. If they are equal, execute this micro-instruction and read the next micro-instruction at the same time. If the execution cycle count value is less than the execution cycle number, wait until the execution cycle count value is equal to the execution cycle number before executing. If the execution cycle count value is greater than the execution cycle number, the micro-instruction execution is abnormal and the process terminates. According to this process, all the micro-instructions in the cache are executed in sequence, and an execution completion signal is output. At the same time, the execution cycle count value can also be output to determine whether the micro-instruction is executed normally.

[0116] Through steps S401 to S403, after triggering the micro-instruction to run, start counting based on the synchronous clock signal and the pre-configured execution cycle factor to obtain the execution cycle count value, which is used as the time reference for determining whether the execution time of the micro-instruction is correct. By sequentially obtaining the execution cycle numbers of each micro-instruction and comparing them with the execution cycle count value, and when the execution cycle number is equal to the execution cycle count value, execute this micro-instruction until all the micro-instructions in the cache are executed. Each micro-instruction is executed based on the correct execution time, ensuring the time accuracy of each micro-instruction execution.

[0117] In some embodiments, Figure 5 is the flowchart of the micro-instruction execution in some embodiments of the present application, as Figure 5 shown, this process includes the following steps:

[0118] Step S501, based on the event type and event parameters, obtain the instruction information of the micro-instruction.

[0119] For the EVENT_AD test instruction, its function information Operand can be divided into two parts: event type EVENT_TYPE and event parameter SIGNAL_NAME. The format of the event type EVENT_TYPE can be control object_operation type. Among them, the control object can be any arbitrary waveform generator AWG and waveform collector DGT, and the operation type can be connection, disconnection, start, stop, trigger, instruction loading. The event parameter can be the configuration parameter required in the process of controlling the AWG and DGT.

[0120] For operation types such as connection, disconnection, start, and stop, the instruction information of the micro-instruction can be the control signal for the AWG and DGT, and this control signal can be generated based on the event type and event parameters;

[0121] In some embodiments, when the event type of the micro-instruction is instruction loading, corresponding instruction information is read from the memory based on the loading address in the event parameters; when the event type of the micro-instruction is not instruction loading, corresponding instruction information is generated based on the event parameters.

[0122] Specifically, when the event type of the micro-instruction is instruction loading, a loading operation is performed, corresponding control signals are loaded according to the event parameters, and waveform files, FIR (finite impulse response) coefficients, etc. stored in the DDR are read.

[0123] When the event type of the micro-instruction is not instruction loading, the event types of the micro-instruction may include connection, disconnection, start, and stop. According to the event type and event parameters, corresponding control signals can be generated, such as start signals, stop signals, connection signals, etc. of the AWG or DGT.

[0124] Step S502, determine the sending object of the micro-instruction based on the event parameters.

[0125] According to the event parameters of the micro-instruction and with reference to the pre-acquired parameter information, determine the sending object of the instruction information. The sending objects include the AWG, DGT, and the controller FPGA. The controller FPGA is also connected to the AWG and DGT. The FPGA can further process the received instruction information and then send it to the AWG and DGT. Therefore, it should be noted that the sending object is not exactly the same as the control object in the micro-instruction. In this embodiment, the control objects are the AWG and DGT, while the sending objects also include the controller FPGA.

[0126] Step S503, send the instruction information to the sending object.

[0127] Specifically, when the sending object is a waveform generator or a waveform collector, clock domain conversion is performed on the instruction information and it is distributed to the waveform generator or the waveform collector. When the sending object is a controller, based on the communication protocol with the controller, the instruction information is sent to the controller.

[0128] Among them, clock domain conversion refers to converting the MASTER_CLK clock domain to the SYS_CLK system clock domain.

[0129] When the sending object is the controller FPGA, it is encoded in a custom protocol format and the instruction information is sent to the FE FPGA through the corresponding transmission channel.

[0130] Through steps S501 to S503, by based on the event type and event parameters, obtain the instruction information of the micro-instruction, generate or read the corresponding control signal; by based on the event parameters, determine the sending object of the micro-instruction, and send the instruction information to the sending object, realizing flexible control of the test equipment and improving the automation control level of the test equipment.

[0131] In some embodiments, Figure 6 is a flowchart for determining the validity of micro-instructions in some embodiments of the present application, as Figure 6 shown, this process includes the following steps:

[0132] Step S601, determine whether the micro-instruction is valid for this resource board based on the valid channel of the micro-instruction.

[0133] When the execution cycle number in step S403 is equal to the execution cycle count value, execute this micro-instruction. Before execution, first determine whether the micro-instruction is valid for this resource board based on the valid channel of the micro-instruction. Compare the valid channel of the test instruction with the channel number of this resource board to determine whether the micro-instruction is valid for this resource board.

[0134] Step S602, in the case of being valid, execute the micro-instruction.

[0135] If it is a valid micro-instruction, send this micro-instruction to the parameter control module for executing the micro-instruction.

[0136] Step S603, in the case of being invalid, ignore this micro-instruction and read the next micro-instruction.

[0137] If it is an invalid micro-instruction, then ignore it and read the next micro-instruction in the cache FIFO, and loop to compare the execution cycle number with the execution cycle count value.

[0138] Through steps S601 to S603, by based on the valid channel of the micro-instruction, determine whether the micro-instruction is valid for this resource board. In the case of being valid, execute the micro-instruction. In the case of being invalid, ignore the micro-instruction and read the next micro-instruction, and execute the corresponding micro-instruction for different resource boards, improving the flexibility of micro-instruction execution.

[0139] In some embodiments, Figure 7 is a flowchart for micro-instruction delay compensation in some embodiments of the present application, as Figure 7 shown, this process includes the following steps:

[0140] Step S701, determine whether the micro-instruction is a delay compensation micro-instruction, and this delay compensation micro-instruction includes the number of delay cycles.

[0141] Among the microinstructions included in the EVENT_AD test instruction, in addition to the microinstructions such as the connection, disconnection, startup, stop, and microinstruction loading of the AWG and DGT in the above embodiments, there is also a delay compensation microinstruction RESYNC. This delay compensation microinstruction is used to provide the number of delay cycles, and this number of delay cycles is used to compensate for the trigger delay of the signal after the startup microinstruction runs.

[0142] In this embodiment, the trigger delay of the signal may include:

[0143] 1) The trigger delay of logical processing. After the logic receives the operation trigger instruction of the microinstruction, it still needs to perform other service processes and cannot perform the trigger action immediately. There will be a delay here, and the delay time is related to the system clock. It is denoted as N system clocks here.

[0144] 2) The trigger delay of data processing. After the trigger instruction actually takes effect, there is a delay for the data triggered and output to reach the IO of the DAC. The delay time is related to the sampling clock. It is denoted as M sampling clocks here.

[0145] 3) After the data is input into the DAC chip, the DAC chip needs to convert it into an analog signal for output. There is an inherent delay in the chip here, which cannot be ignored. The delay time is related to the sampling clock. It is denoted as T sampling clocks here.

[0146] Therefore, in the case of no compensation, the actual trigger is after receiving the trigger signal with a delay of N × system clock + (M + T) × sampling clock. This delay is a fixed delay. In this embodiment, the sampling clock period is known, so this delay time is also fixed. Convert this delay time into the number of delay cycles for compensation, where the number of delay cycles = (N × system clock + (M + T) × sampling clock) / MASTER_CLK. Rounding can be used here, and the precision loss is controlled within the range of 1 MASTER_CLK.

[0147] In this embodiment, before running other microinstructions, the host computer sends the number of delay cycles to be compensated to the resource board through the delay compensation microinstruction RESYNC. When the resource board runs other microinstructions, all microinstructions are advanced based on this number of delay cycles.

[0148] Step S702, if yes, obtain the difference between the execution cycle number corresponding to each microinstruction after the delay compensation microinstruction and the number of delay cycles.

[0149] If the microinstruction is a delay compensation microinstruction, obtain the number of delay cycles and calculate the difference between the execution cycle number of each microinstruction after the delay compensation microinstruction and the number of delay cycles.

[0150] Step S703: Compare the difference with the execution cycle count value. When the difference is equal to the execution cycle count value, execute the corresponding micro-instruction.

[0151] In a specific embodiment, assume that the execution cycle serial number of a micro-instruction is 100. Without delay compensation, this micro-instruction should be executed when the execution cycle count value is equal to 100. When receiving the delay compensation micro-instruction RESYNC and the number of delay cycles in RESYNC is 30, this micro-instruction should be executed when the execution cycle count value is equal to 100 - 30 = 70. That is, each micro-instruction after the delay compensation micro-instruction is executed 30 delay cycles in advance.

[0152] Through steps S701 to S703, by determining whether a micro-instruction is a delay compensation micro-instruction, it is determined whether subsequent micro-instructions need delay compensation; by obtaining the difference between the execution cycle serial number and the number of delay cycles corresponding to each micro-instruction after the delay compensation micro-instruction, the time length of the delay compensation is determined; by comparing the difference with the execution cycle count value and executing the corresponding micro-instruction when the difference is equal to the execution cycle count value, the time accuracy of the early execution of the micro-instruction is ensured, and the trigger accuracy of the micro-instruction operation is improved.

[0153] In some embodiments, Figure 8 is a flowchart of the test instruction preloading in some embodiments of the present application. As Figure 8 shown, this process includes the following steps:

[0154] Step S801: Based on the received preloading instruction, the storage addresses and lengths of the test instructions, read multiple test instructions into the cache in sequence.

[0155] After receiving the preloading instruction, the resource board reads the corresponding test instructions from the DDR into the cache of the resource board according to the storage addresses and lengths of the test instructions in the preloading instruction. The cache can be a FIFO.

[0156] Step S802: Set a preloading flag based on the length of the test instruction, the number of test instructions read into the cache, and the maximum storage capacity of the cache.

[0157] During the loading process, determine whether the loading is completed according to the number of test instructions read into the cache and the length of the test instructions to be loaded.

[0158] Specifically, a loading length threshold can be preset in advance, and the loading length threshold can be equal to the maximum number of microinstructions that the cache space can store. When the length of the test instruction to be loaded is less than the loading length threshold, it is determined whether the number of test instructions read into the cache is equal to the length of the test instruction to be loaded. When the two are equal, it is determined that the loading is completed, and the preloading flag is set to a preset value. For example, the preloading flag is set to 1. When the length of the test instruction to be loaded is greater than or equal to the loading length threshold, it is determined whether the number of test instructions read into the cache is equal to the loading length threshold. When the two are equal, it is determined that the loading is completed, and the preloading flag is set to the preset value.

[0159] Step S803, when the value of the preloading flag is equal to the preset value, based on the sorting of the test instructions in the cache, each test instruction is sequentially expanded into one or more microinstructions.

[0160] The value of the preloading flag being equal to the preset value indicates that the loading of the test instructions is completed. At this time, each test instruction in the cache can be expanded into one or more microinstructions. When a test instruction is completely expanded, there is remaining storage space in the cache space. At this time, the preloading flag can be set to 0 again, and the loading of the test instructions can continue until all the remaining test instructions are loaded into the cache.

[0161] Through steps S801 to S803, by based on the received preloading instruction, the storage address and length of the test instruction, multiple test instructions are sequentially read into the cache for subsequent expansion of the test instructions; by based on the length of the test instruction, the number of test instructions read into the cache, and the maximum storage capacity of the cache, the preloading flag is set, and the loading stops when the loading quantity of the test instructions reaches the maximum value that the cache can store, preventing data overflow; by when the value of the preloading flag is equal to the preset value, based on the sorting of the test instructions in the cache, each test instruction is sequentially expanded into one or more microinstructions, ensuring the orderly asynchronous execution of the loading and expansion of the test instructions.

[0162] Some embodiments of the present application also provide a microinstruction control test system. Figure 9 is a structural block diagram of the microinstruction control test system of some embodiments of the present application, as Figure 9 shown. The microinstruction control test system includes a host computer 10, a communication board 20 communicatively connected to the host computer 10, and a plurality of resource boards 30 (one is shown in the figure) connected to the communication board. The resource board 30 includes a microinstruction controller 100, and the microinstruction controller includes:

[0163] A service decoding module 101, configured to receive a synchronous clock signal and a start instruction sent by the communication board and forward them to the microinstruction control module 105. The start instruction includes a start count value.

[0164] The test instruction cache module 104 is configured to expand each test instruction into one or more microinstructions in sequence based on the sorting of multiple pre-loaded test instructions and send them to the microinstruction control module 105;

[0165] The microinstruction control module 105 is configured to start cyclic counting based on the synchronous clock signal to obtain a clock count value; and compare the start count value with the clock count value, and when the clock count value is equal to the start count value for the first time, trigger the execution of the microinstruction.

[0166] In the microinstruction control test system of this embodiment, the test instruction cache module 104 caches the test instructions in an orderly manner, and the microinstruction control module 105 performs synchronous counting, providing a unified counting time for multiple resource boards to execute microinstructions synchronously. When the clock count value is equal to the start count value for the first time, the execution of the microinstruction is triggered. Each resource board determines the trigger timing of the microinstruction according to the same start count value, ensuring that each resource board starts to execute the microinstruction at the same moment, without spending communication time, improving the control precision, synchronization accuracy, and real-time performance of the instructions.

[0167] In some embodiments, Figure 10 is the structural block diagram of the microinstruction control test system in other embodiments of the present application. As Figure 10 shown, the microinstruction controller 100 further includes a parameter control module 106, and the microinstruction control module 105 is further configured to:

[0168] When the clock count value is equal to the start count value for the first time, start counting based on the synchronous clock signal and a pre-configured execution cycle factor to obtain an execution cycle count value;

[0169] Sequentially obtain the execution cycle numbers of each microinstruction and compare them with the execution cycle count value;

[0170] When the execution cycle number is equal to the execution cycle count value, determine whether the microinstruction is valid for the resource board based on the effective channel of the microinstruction;

[0171] If it is valid, send the microinstruction to the parameter control module 106;

[0172] If it is invalid, ignore the microinstruction and read the next microinstruction.

[0173] In the microinstruction control test system of this embodiment, the execution cycle count value is obtained through the microinstruction control module 105 as the time reference for determining whether the execution time of the microinstruction is correct. When the execution cycle number is equal to the execution cycle count value, the microinstruction is executed, ensuring the time accuracy of each microinstruction execution; corresponding microinstructions are executed for different resource boards, improving the flexibility of microinstruction execution.

[0174] In some embodiments, Figure 11 is a structural block diagram of a micro-instruction control test system according to still other embodiments of the present application. As Figure 11 shown, the micro-instruction controller 100 further includes a load control module 107 and a parameter selection module 108. The micro-instruction includes an event type and event parameters.

[0175] The parameter control module 106 is configured to, when the event type in the micro-instruction is instruction loading, parse the corresponding load instruction based on the micro-instruction and send it to the load control module 107;

[0176] when the event type of the micro-instruction is not instruction loading, generate instruction information of the micro-instruction based on the event type and event parameters, and send the instruction information to the parameter selection module 108;

[0177] The load control module 107 is configured to read the corresponding instruction information based on the load instruction and send it to the parameter selection module 108.

[0178] The micro-instruction control test system of this embodiment generates or reads a control signal for controlling a test device through the parameter control module 106 and the load control module 107 and sends it to the parameter selection module, realizing flexible control of the test device and improving the automatic control level of the test device.

[0179] In some embodiments, Figure 12 is a structural block diagram of a micro-instruction control test system according to still other embodiments of the present application. As Figure 12 shown, the micro-instruction controller further includes a cross-clock domain control module 109 and a controller transmission module 110.

[0180] The parameter selection module 108 is configured to send the instruction information to the cross-clock domain control module 109 or the controller transmission module 110 based on the event type of the instruction information;

[0181] The cross-clock domain control module 109 is configured to perform clock domain conversion on the instruction information and distribute it to a waveform generator or a waveform collector;

[0182] The controller transmission module 110 is configured to send the instruction information to the controller based on the communication protocol with the controller.

[0183] The micro-instruction control test system of this embodiment sends the instruction information to a functional module corresponding to a control object through the parameter selection module 108, realizes clock domain conversion of the instruction information through the cross-clock domain control module 109, and realizes packet transmission of the instruction information through the controller transmission module 110, ensuring correct transmission of the instruction information to the test device and the controller.

[0184] In some embodiments, asFigure 12 As shown in the figure, the micro-instruction controller further includes an instruction request module 103, and the instruction request module 103 is used for:

[0185] Based on the storage addresses and lengths of the received preloading instructions and test instructions, sequentially read multiple test instructions into the test instruction cache module 104; set a preloading flag based on the length of the test instructions, the number of test instructions read into the test instruction cache module 104, and the maximum storage capacity of the test instruction cache module.

[0186] In the micro-instruction control test system of this embodiment, the instruction request module 103 sequentially reads multiple test instructions into the test instruction cache module 104 and sets a preloading flag, and stops loading when the loading quantity of the test instructions reaches the maximum value that the cache can store, preventing data overflow and ensuring the orderly asynchronous execution of the loading and expansion of the test instructions.

[0187] The micro-instruction control test system of this embodiment will be described and illustrated below through preferred embodiments. The micro-instruction control test system includes a host computer, a communication board card communicatively connected to the host computer, and multiple resource board cards connected to the communication board card. The resource board cards include micro-instruction controllers. Figure 13 It is a structural block diagram of the micro-instruction controller of some preferred embodiments of this application. As Figure 13 shown, the micro-instruction controller includes: a service decoding module 101, a DDR control module 102, an instruction request module 103, a test instruction cache module 104, a micro-instruction control module 105, a parameter control module 106, a loading control module 107, a parameter selection module 108, a cross-clock domain control module 109, a controller transmission module 110, an AWG control module 111, a DGT control module 112, and a GTX-to-FE transmission control module 113.

[0188] Service decoding module 101: Its main function is to decode the data sent by the host computer according to the communication protocol, convert the decoded data from the SYS_CLK system clock domain to the MASTER_CLK micro-instruction clock domain, and at the same time send the decoded parameters to the corresponding modules, including the DDR control module 102, the instruction request module 103, the test instruction cache module 104, and the micro-instruction control module 105. The main parameters include DDR read and write instructions, start instructions, execution cycle factors of test instructions, addresses and lengths of test instructions stored in the DDR, information such as preloading instructions of test instructions, status clearing instructions of test instructions, etc.

[0189] DDR control module 102: Executes the read and write functions of the DDR and supports multiple DDRs to initiate read and write requests simultaneously.

[0190] Instruction Request Module 103: Initiate a request to the DDR based on the preloading instruction of the test instruction and information such as the address and length stored in the DDR of the test instruction, read the test instruction stored in the DDR, and send it to the Test Instruction Cache Module 104; at the same time, judge whether the preloading status bit SET_UP is completed according to the length of the test instruction stored in the DDR and the number sent to the Test Instruction Cache Module 104; the judgment condition is that when the length is less than 2000, the SET_UP status is completed when the number of data sent is equal to the length, otherwise it is not completed; when the length is greater than or equal to 2000, the SET_UP status is completed when the number of data sent is equal to 2000, otherwise it is not completed.

[0191] Test Instruction Cache Module 104: After the SET_UP status is completed, decode the test instruction received in 128-bit format, expand the test instruction according to the operation code OPCODE of the test instruction, restore it to the micro-instructions corresponding to each execution cycle, each micro-instruction with its own execution cycle sequence number, and issue it to the Micro-instruction Control Module 105 in the format of valid channel_execution cycle sequence number_operation code_function information; the main purpose is to expand instructions such as REPEAT\LOOP\ENDLOOP\TRIG, convert the original test instruction into an instruction with independent execution time information for each one, store it in the Micro-instruction Control Module 105, and wait for the micro-instruction to be triggered and take effect to perform the actual micro-instruction operation.

[0192] Micro-instruction Control Module 105: Generate an actual valid RUN_TRIG instruction according to the start instruction and the start count value TRIG_GST_CNT, and a counter that starts clock cycling counting when powered on; start running micro-instructions according to the RUN_TRIG instruction, start CYCLE counting after the RUN_TRIG instruction takes effect, and the MASTER_CLK performs CYCLE counting according to the execution cycle factor (every time the execution cycle factor of MASTER_CLK clocks pass, the CYCLE_CNT is incremented by 1). When the actual CYCLE_CNT count reaches the execution cycle sequence number in the micro-instruction, judge whether the valid channel in this micro-instruction includes this board. If it is a valid micro-instruction, issue it to the Parameter Control Module 106, otherwise ignore this micro-instruction, and at the same time read the next micro-instruction in the cache FIFO and continue to judge whether the CYCLE_CNT is equal to the execution cycle sequence number; when all the data in the cache FIFO of the Micro-instruction Control Module 105 is processed, output the RUN_VECTOR_DONE signal, indicating that the test instruction operation is completed, and at the same time output the CYCLE_COUNT count for judging whether the test instruction runs normally.

[0193] Parameter control module 106: Decode the micro-instructions to obtain corresponding control signals, including AWG_TRIG, AWG_STOP, AWG_LOADSEETING, AWG_CONNECT, AWG_DISCONNECT, DGT_TRIG, DGT_STOP, DGT_LOADSEETING, DGT_CONNECT, DGT_DISCONNECT, etc. Send the control signals to the load control module 107 or the parameter selection module 108, where AWG_LOADSEETING and DGT_LOADSEETING are sent to the load control module 107, and the remaining 8 signals are sent to the parameter selection module 108.

[0194] Load control module 107: Request DDR data according to the AWG_LOADSEETING and DGT_LOADSEETING instructions and the SIGNAL addresses they carry, read out the SIGNAL information stored in the DDR, and send the read data to the parameter selection module 108 for data selection.

[0195] Parameter selection module 108: Determine which parameters need to be transmitted to the AWG module, DGT module, and peripheral chips of the FE FPGA according to the preset parameter information. After determination, send the data of the AWG module and DGT module to the cross-clock domain control module 109 for cross-clock preprocessing; send the data to be transmitted to the peripheral chips of the FE FPGA to the controller transmission module 110.

[0196] Cross-clock domain control module 109: Perform clock domain conversion through the FIFO, convert the data of the AWG module and DGT module from the MASTER_CLK clock domain to the SYS_CLK system clock domain, and then distribute them to the AWG control module 111 and the DGT control module 112.

[0197] Controller transmission module 110: Transmit the data to be transmitted to the FE FPGA to the FE FPGA according to the self-defined protocol format, encode the data according to the transmission type, form 64-bit wide data, and transmit it to the FE FPGA through the GTX bus of the GTX to FE transmission control module 113.

[0198] The micro-instruction control test system of this embodiment receives a synchronous clock signal and a start instruction through the service decoding module 101 and forwards them to the micro-instruction control module 105; reads multiple test instructions from the DDR to the test instruction cache module 104 in sequence through the instruction request module 103, and sets a preloading flag. When the loading quantity of the test instructions reaches the maximum value that the cache can store, the loading is stopped to prevent data overflow, ensuring the orderly asynchronous execution of the loading and expansion of the test instructions; caches the test instructions through the test instruction cache module 104, and performs synchronous counting through the micro-instruction control module 105, providing a unified counting time for multiple resource boards to run micro-instructions synchronously. When the clock count value is equal to the start count value for the first time, the operation of the micro-instruction is triggered, ensuring that each resource board starts running the micro-instruction at the same moment and improving the synchronization accuracy of the instructions; when the execution cycle serial number is equal to the execution cycle count value, the micro-instruction is executed, ensuring the time accuracy of the execution of each micro-instruction; generates or reads control signals for controlling the test equipment through the parameter control module 106 and the loading control module 107, sends the instruction information to the function module corresponding to the control object through the parameter selection module 108, realizes the clock domain conversion of the instruction information through the cross-clock domain control module 109, and realizes the packet transmission of the instruction information through the controller transmission module 110, ensuring the correct transmission of the instruction information to the test equipment and the controller.

[0199] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiment and the optional implementation manners, and will not be elaborated in this embodiment.

[0200] It should be understood that the specific embodiments described here are only used to explain this application, rather than to limit it. According to the embodiments provided by this application, all other embodiments obtained by those of ordinary skill in the art without creative work belong to the protection scope of this application.

[0201] Obviously, the drawings are only some examples or embodiments of this application. For those of ordinary skill in the art, this application can also be applied to other similar situations based on these drawings without creative work. In addition, it can be understood that although the work done during the development process here may be complex and time-consuming, for those of ordinary skill in the art, some design, manufacturing, or production changes based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient disclosure of this application.

[0202] The term "embodiment" in this application means that the specific features, structures or characteristics described in connection with the embodiments may be included in at least one embodiment of this application. The fact that this phrase appears in various positions in the specification does not necessarily mean the same embodiment, nor does it mean that it is independent or alternative to other embodiments and mutually exclusive. Those of ordinary skill in the art can clearly or implicitly understand that the embodiments described in this application can be combined with other embodiments without conflict.

[0203] The above-described embodiments merely represent several implementation manners of this application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of patent protection. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can still be made, and these all fall within the protection scope of this application. Therefore, the protection scope of this application shall be subject to the appended claims.

Claims

1. A method for synchronously triggering microinstructions between boards, characterized in that: The method is applied to a resource board in a microinstruction control test system, wherein the system comprises a host computer, a communication board connected to the host computer for communication, and a plurality of resource boards connected to the communication board, and the method comprises: Receiving a synchronous clock signal sent by the communication board, and starting cyclic counting based on the synchronous clock signal to obtain a clock count value; Based on the order of multiple test instructions preloaded into the cache, each test instruction is sequentially expanded into one or more microinstructions; the test instructions include instructions for controlling the execution time and execution order of statements, and instructions for controlling external devices, but do not include chip pin IO operation information; Receiving a startup instruction sent by the communication board, wherein the startup instruction includes a startup count value; Comparing the startup count value with the clock count value, and triggering the execution of the microinstruction when the clock count value is equal to the startup count value for the first time; The microinstruction includes an execution cycle number, and when the clock count value is equal to the start count value for the first time, triggering the execution of the microinstruction includes: When the clock count value is equal to the start count value for the first time, counting starts based on the synchronous clock signal and a preconfigured execution cycle factor to obtain an execution cycle count value; Obtaining the execution cycle sequence number of each of the microinstructions in sequence and comparing it with the execution cycle count value; When the execution cycle sequence number is equal to the execution cycle count value, the microinstruction is executed until all microinstructions in the cache are executed.

2. The method according to claim 1, characterized in that: The microinstruction also includes an event type and event parameters, and executing the microinstruction includes: Based on the event type and the event parameters, obtaining instruction information of the microinstruction; Based on the event parameters, determining a sending object of the microinstruction; The instruction information is sent to the sending object.

3. The method according to claim 2, characterized in that The sending of the instruction information to the sending object comprises: In the case where the sending object is a waveform generator or a waveform collector, performing clock domain conversion on the instruction information and distributing it to the waveform generator or the waveform collector; When the sending object is a controller, the instruction information is sent to the controller based on a communication protocol with the controller.

4. The method according to claim 2, characterized in that: The acquiring the instruction information of the microinstruction based on the event type and the event parameter comprises: In the case where the event type of the microinstruction is instruction loading, reading corresponding instruction information from a memory based on a loading address in the event parameter; When the event type of the microinstruction is not instruction loading, corresponding instruction information is generated based on the event parameters.

5. The method according to claim 1, characterized in that The microinstruction also includes a valid channel, and when the execution cycle sequence number is equal to the execution cycle count value, executing the microinstruction includes: Determining whether the microinstruction is valid for the resource board based on the valid channel of the microinstruction; If valid, executing the microinstruction; In the invalid case, the microinstruction is ignored and the next microinstruction is fetched.

6. The method according to claim 1, characterized in that The test instruction includes a valid channel, a row difference, an operation code and function information, and the sequence of the multiple test instructions preloaded into the cache is based on the order in which each test instruction is sequentially expanded into one or more microinstructions, including: Based on the operation code and the function information, obtaining the number of execution cycles corresponding to the test instruction; Based on the row difference and the number of execution cycles, obtaining the execution cycle sequence number of each microinstruction corresponding to the test instruction; Based on the valid channel, execution cycle number, operation code and function information, one or more microinstructions corresponding to the test instruction are generated.

7. The method according to claim 1, characterized in that When the execution cycle sequence number is equal to the execution cycle count value, executing the microinstruction includes: Determining whether the microinstruction is a delay compensation microinstruction, wherein the delay compensation microinstruction includes a delay cycle number; If so, obtaining the difference between the execution cycle number corresponding to each microinstruction after the delay compensation microinstruction and the delay cycle number; The difference is compared with the execution cycle count value, and when the difference is equal to the execution cycle count value, the corresponding microinstruction is executed.

8. The method according to claim 1, characterized in that Before sequentially expanding each test instruction into one or more microinstructions based on the order of the plurality of test instructions preloaded into the cache, the method further includes: Based on the received storage addresses and lengths of the preload instructions and the test instructions, the plurality of test instructions are sequentially read into the cache; Setting a preload flag based on the length of the test instruction, the number of test instructions read into the cache, and the maximum storage quantity of the cache; When the value of the preload flag is equal to a preset value, each test instruction is sequentially expanded into one or more microinstructions based on the order of the test instructions in the cache.

9. A microinstruction control test system, characterized in that: The system includes a host computer, a communication board connected to the host computer, and a plurality of resource boards connected to the communication board, wherein the resource board includes a microinstruction controller, and the microinstruction controller includes: A service decoding module, used for receiving the synchronous clock signal and the start instruction sent by the communication board and forwarding them to the microinstruction control module, wherein the start instruction includes a start count value; A test instruction cache module is used to expand each test instruction into one or more microinstructions in sequence and send them to the microinstruction control module based on the order of the pre-loaded multiple test instructions; the test instructions include instructions for controlling the execution time and execution order of statements, and instructions for controlling external devices, but do not include chip pin IO operation information; A microinstruction control module, configured to start cyclic counting based on the synchronous clock signal to obtain a clock count value; and to compare the start count value with the clock count value, and to trigger the execution of the microinstruction when the clock count value is equal to the start count value for the first time; A parameter control module is used to start counting based on the synchronous clock signal and a pre-configured execution cycle factor to obtain an execution cycle count value when the clock count value is equal to the start count value for the first time; sequentially obtain the execution cycle sequence number of each microinstruction and compare it with the execution cycle count value; when the execution cycle sequence number is equal to the execution cycle count value, execute the microinstruction until all microinstructions in the cache are executed.

10. The system according to claim 9, characterized in that The parameter control module is also used for: Determining whether the microinstruction is valid for the resource board based on the valid channel of the microinstruction; If valid, sending the microinstruction to the parameter control module; In the invalid case, the microinstruction is ignored and the next microinstruction is fetched.

11. The system according to claim 10, characterized in that The microinstruction controller also includes a loading control module and a parameter selection module. The microinstruction includes an event type and an event parameter. The parameter control module is used for parsing the corresponding load instruction based on the microinstruction and sending it to the load control module when the event type in the microinstruction is instruction loading; In the case where the event type of the microinstruction is not instruction loading, generating instruction information of the microinstruction based on the event type and the event parameter, and sending the instruction information to the parameter selection module; The loading control module is used to read corresponding instruction information based on the loading instruction and send it to the parameter selection module.

12. The system according to claim 11, characterized in that The microinstruction controller also includes a cross-clock domain control module and a controller transmission module. The parameter selection module is used to send the instruction information to the cross-clock domain control module or the controller transmission module based on the event type of the instruction information; The cross-clock domain control module is used to perform clock domain conversion on the instruction information and distribute it to the waveform generator or waveform collector; The controller transmission module is used to send the instruction information to the controller based on the communication protocol with the controller.

13. The system according to claim 9, characterized in that The microinstruction controller further comprises an instruction request module, wherein the instruction request module is used for: Based on the storage address and length of the received preload instructions and test instructions, multiple test instructions are read into the test instruction cache module in sequence; based on the length of the test instructions, the number of test instructions read into the test instruction cache module and the maximum storage quantity of the test instruction cache module, a preload flag is set.

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