Device and method for SSD (Solid State Disk) master control to co-process NAND instruction

Abstract

The invention relates to the field of storage, in particular to a device and method for an SSD master control to co-process an NAND instruction. The device comprises main instruction slots and co-processing instruction slots, each main instruction slot comprises an NAND operation type, an NAND main operation instruction, resources needed by NAND operation and a co-processing instruction slot number, each co-processing instruction slot comprises an NAND operation instruction and a matched main instruction slot number, one NAND main instruction slot represents a complete NAND operation, and the NAND main instruction slot represents a non-complete NAND operation. If the NAND main instruction slot cannot complete a complete NAND operation sequence, the co-processing instruction slot needs to be matched to complete the complete NAND operation sequence. On the basis of the device, NAND operations such as fixed instruction expansion and multi-instruction expansion can be flexibly realized, the software design participation degree and complexity are greatly reduced, the compatibility of SSD master control to different manufacturers and different models is expanded, and the effect of meeting the design purpose by using a small number of hardware resources is achieved.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to a first device and method for SSD master control to assist in processing NAND instructions. Background Art

[0002] There are two NAND protocols: ONFI and Toggle. However, many NAND chip manufacturers have different technologies. When implementing the same protocol, some commands may have different implementation methods. For example, for Read operations, some manufacturers need to add a Page number before the Read command, while some manufacturers have the Page number in the address bytes between Read commands. On the other hand, commands may also be different between different models of the same manufacturer, and newer versions of NAND support more commands.

[0003] SSD controllers need to support NAND Flash of multiple manufacturers and models. However, during the development process, they can only fully support the current NAND operation commands. Subsequent commands may not be fully supported. For example, for Write operations, due to the increase in the number of stacked layers, a manufacturer adds the number of Planes and Pages after the first Write operation instruction. This has changed the operation instructions of the manufacturer's previous NAND models, and the SSD controller cannot support the operations of the new model.

[0004] There is another type of NAND operation that requires multiple instructions to be completed in sequence. No other operation instructions can be inserted between these instructions. Therefore, these instructions need to be regarded as one instruction in the SSD master control and sent to the NAND Flash in sequence according to the preset order. Summary of the invention

[0005] In view of the defects of the prior art, the present invention provides a device and method for SSD master control to assist in processing NAND instructions. Based on this method, various operations of NAND of different models from different manufacturers can be completed.

[0006] In order to solve the technical problem, the technical solution adopted by the present invention is: a device for SSD master co-processing NAND instructions, including a NAND main instruction slot unit and a NAND co-processing instruction slot unit, the NAND main instruction slot unit includes multiple main instruction slots, each main instruction slot stores a NAND operation type, a NAND main operation instruction, resources required for the NAND operation and a co-processing instruction slot number; the NAND co-processing instruction slot unit is used to supplement or expand the NAND main instruction slot operation, the NAND co-processing instruction slot unit includes multiple co-processing instruction slots, each co-processing instruction slot stores a NAND operation instruction and a matching main instruction slot number.

[0007] Furthermore, when the main instruction slot cannot complete a complete NAND operation sequence, it is completed by the co-processing instruction slot. The main instruction slot is configured with the number and number of the co-processing instruction slots and the running order of the co-processing instructions. The SSD master controller regards the main instruction and the co-processing instruction as one NAND operation. The co-processing instruction slot is configured with the co-processing operation instruction and the main instruction slot number to be matched.

[0008] Furthermore, the execution order of the co-processing instruction is to send it to NAND before the main instruction or to send it after the main instruction receives feedback from NAND.

[0009] Furthermore, after the main instruction is sent to the NAND, the main instruction slot and the co-processing instruction slot are released.

[0010] Furthermore, for fixed NAND instructions, the co-processing instruction slot is set to a fixed mode without binding the main instruction slot, the main instruction slot is configured with the co-processing instruction slot number and execution order, and only the main instruction slot is released after the instruction is issued.

[0011] Furthermore, NAND operation types include SLC, TLC, and QLC.

[0012] Furthermore, the NAND main operation instructions include write operations and read operations.

[0013] Furthermore, the resources required for NAND operations include memory resources and DMA resources.

[0014] The present invention also discloses a method for SSD master control to assist in processing NAND instructions, comprising the following steps: S01. Apply for an idle main instruction slot, and configure the instruction type, specific instructions, and hardware resources required for the operation of the main instruction slot: S02, determine whether the main instruction slot needs a co-processing instruction, if not, execute step S07, if yes, continue to determine whether the main instruction slot needs a fixed NAND instruction, if a fixed NAND instruction is needed, execute step S03, if not, execute step S05; S03, applying for an idle co-processing instruction slot, setting the co-processing instruction slot as a fixed instruction slot, and not releasing the co-processing instruction slot after the command is successfully sent; S04, configure the co-processing instruction slot number and the co-processing instruction execution order that the main instruction slot needs to match, send the main instruction and the co-processing execution to NAND in the predetermined sending order, release the main instruction slot after the instruction is successfully sent, and end; S05, configuring the co-processing instruction slot number that the main instruction slot needs to match, the execution order of each co-processing instruction, and configuring the co-processing instruction slot instruction and the main instruction slot number; S06, sending the main instruction and the co-processing instruction in sequence according to the preset execution order, releasing the main instruction slot and the co-processing instruction slot after the instruction is successfully executed, and ending; S07, immediately send the command to NAND, release the main command slot after successful sending, and end.

[0015] Beneficial effects of the present invention: The device described in the present invention includes a main instruction slot and a co-processing instruction slot. The co-processing instruction slot is used to supplement or expand the NAND main instruction slot operation. Therefore, based on this device, NAND operations such as fixed instruction extension and multiple instruction extension can be flexibly implemented, which greatly reduces the software design participation and complexity, expands the compatibility of the SSD master control with different manufacturers and different models, and achieves the effect of using a small amount of hardware resources to meet the design purpose. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a flow chart of the method described in Example 2. DETAILED DESCRIPTION

[0017] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0018] Example 1 The present embodiment discloses a device for SSD master co-processing NAND instructions, including a NAND main instruction slot unit and a NAND co-processing instruction slot unit. The NAND main instruction slot unit includes multiple main instruction slots, each of which stores a NAND operation type, a NAND main operation instruction, resources required for the NAND operation, and a co-processing instruction slot number.

[0019] A NAND main instruction slot represents a complete NAND operation. You need to configure the NAND operation type to SLC, TLC, or QLC, and then write NAND main operation instructions such as write (Write) and read (Read) into the main instruction slot. If the NAND main instruction slot cannot complete the operation alone, you need to configure the number and number of co-processing instruction slots, and the order of co-processing instruction execution. In addition, set the software and hardware resources required for the operation according to the operation type, such as memory resources, DMA resources, etc.

[0020] The main function of the NAND co-processing instruction slot unit is to supplement or expand the NAND main instruction slot operation. The unit includes multiple co-processing instruction slots, each of which includes a NAND operation instruction and a matching main instruction slot number.

[0021] If the NAND main instruction slot cannot complete a complete NAND operation sequence, the co-processing instruction slot is required to complete it. The main instruction slot needs to be configured with the number and number of the co-processing instruction slots and the running order of the co-processing instructions. The co-processing instruction can be sent to NAND before the main instruction, or it can be sent after the main instruction receives feedback from NAND. The SSD master controls the main instruction and the co-processing instruction as one NAND operation. The co-processing instruction slot needs to be configured with the operation instruction and the main instruction slot number to be matched. The main instruction slot and the co-processing instruction slot can be released after the main instruction slot is sent to NAND.

[0022] For a certain type of fixed NAND instruction, the co-processing instruction slot can be set to a fixed mode without binding the main instruction slot. The main instruction slot is configured with the co-processing instruction slot number and execution order, and there is no need to release the co-processing instruction slot after issuing it.

[0023] The main instruction slot and the co-processing instruction slot can be used together to adapt to complex multi-instruction operations and multi-instruction operations with strict operation order, which expands the NAND adaptability range of the SSD master control and simplifies the software design caused by complex NAND operation instructions.

[0024] Example 2 This embodiment discloses a method for SSD master control to assist in processing NAND instructions. Figure 1 As shown, the method comprises the following steps: S01. Apply for an idle main instruction slot, and configure the instruction type, specific instructions, and hardware resources required for the operation of the main instruction slot: S02, determine whether the main instruction slot needs a co-processing instruction, if not, execute step S07, if yes, continue to determine whether the main instruction slot needs a fixed NAND instruction, if a fixed NAND instruction is needed, execute step S03, if not, execute step S05; S03, applying for an idle co-processing instruction slot, setting the co-processing instruction slot as a fixed instruction slot, and not releasing the co-processing instruction slot after the command is successfully sent; S04, configure the co-processing instruction slot number and the co-processing instruction execution order that the main instruction slot needs to match, send the instructions to NAND in sequence according to the predetermined sending order, release the main instruction slot after the instruction is successfully sent, and end; S05, configuring the co-processing instruction slot number that the main instruction slot needs to match, the execution order of each co-processing instruction, and configuring the co-processing instruction slot instruction and the main instruction slot number; S06, sending the main instruction and the auxiliary instruction in sequence according to the preset execution order, releasing the main instruction slot and the auxiliary instruction slot after the instruction is successfully executed, and ending; S07, immediately send the command to NAND, release the main command slot after successful sending, and end.

[0025] Through the method described in this embodiment, NAND operations such as fixed instruction extension and multiple instruction extension can be flexibly implemented, which greatly reduces the involvement and complexity of software design, expands the compatibility of SSD master control with different manufacturers and different models, and achieves the effect of using a small amount of hardware resources to meet the design purpose.

[0026] The above description is only the basic principle and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention belong to the protection scope of the present invention.

Claims

1. A device for SSD master control co-processing NAND instructions, characterized in that: It includes a NAND main instruction slot unit and a NAND co-processing instruction slot unit. The NAND main instruction slot unit includes multiple main instruction slots, each of which stores a NAND operation type, a NAND main operation instruction, resources required for the NAND operation, and a co-processing instruction slot number. The NAND co-processing instruction slot unit is used to supplement or expand the NAND main instruction slot operation. The NAND co-processing instruction slot unit includes multiple co-processing instruction slots, each of which stores a NAND operation instruction and a matching main instruction slot number.

2. The device for SSD master control co-processing NAND instructions according to claim 1, characterized in that: When the main instruction slot cannot complete a complete NAND operation sequence, the co-processing instruction slot cooperates to complete it. The main instruction slot is configured with the number and number of co-processing instruction slots and the running order of co-processing instructions. The SSD master controller regards the main instruction and co-processing instruction as a NAND operation. The co-processing instruction slot is configured with the co-processing operation instruction and the main instruction slot number to be matched.

3. The device for SSD master control co-processing NAND instructions according to claim 2, characterized in that: The execution order of the co-processing instructions is to send them to NAND before the main instructions or to send them after the main instructions receive feedback from NAND.

4. The device for SSD master control co-processing NAND instructions according to claim 2, characterized in that: After the main instruction is sent to NAND, the main instruction slot and the co-processing instruction slot are released.

5. The device for SSD master control co-processing NAND instructions according to claim 1, characterized in that: For fixed NAND instructions, the co-processing instruction slot is set to a fixed mode without binding the main instruction slot. The main instruction slot is configured with the co-processing instruction slot number and execution order. After the instruction is issued, only the main instruction slot is released.

6. The device for SSD master control co-processing NAND instructions according to claim 1, characterized in that: NAND operation types include SLC, TLC, and QLC.

7. The device for SSD master control co-processing NAND instructions according to claim 1, characterized in that: the NAND master operation instructions include write operations and read operations.

8. The device for SSD master control co-processing NAND instructions according to claim 1, characterized in that: The resources required for NAND operations include memory resources and DMA resources.

9. A method for SSD master control to assist in processing NAND instructions, characterized in that: The following steps are involved: S01. Apply for an idle main instruction slot, and configure the instruction type, specific instructions, and hardware resources required for the operation of the main instruction slot: S02, determine whether the main instruction slot needs a co-processing instruction, if not, execute step S07, if yes, continue to determine whether the main instruction slot needs a fixed NAND instruction, if a fixed NAND instruction is needed, execute step S03, if not, execute step S05; S03, applying for an idle co-processing instruction slot, setting the co-processing instruction slot as a fixed instruction slot, and not releasing the co-processing instruction slot after the command is successfully sent; S04, configure the co-processing instruction slot number and the co-processing instruction execution order that the main instruction slot needs to match, send the main instruction and the co-processing instruction to NAND in the predetermined sending order, release the main instruction slot after the instruction is successfully sent, and end; S05, configuring the co-processing instruction slot number that the main instruction slot needs to match, the execution order of each co-processing instruction, and configuring the co-processing instruction slot instruction and the main instruction slot number; S06, sending the main instruction and the co-processing instruction in sequence according to the preset execution order, releasing the main instruction slot and the co-processing instruction slot after the instruction is successfully executed, and ending; S07, immediately send the command to NAND, release the main command slot after successful sending, and end.

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