Register processing method and device, electronic equipment and storage medium

Abstract

The invention provides a register processing method, and relates to the technical field of artificial intelligence, in particular to the technical field of chip, simultaneous multithreading and vector operation. According to the specific implementation scheme, a to-be-processed instruction is transmitted according to a first number of architecture registers required by the to-be-processed instruction and a second number of idle physical registers, the second number is determined from a plurality of physical registers shared by a plurality of threads, and the to-be-processed instruction is an instruction of a target thread in the plurality of threads; and in response to a received release instruction corresponding to the to-be-processed instruction, releasing the physical register occupied by the to-be-processed instruction. The invention further provides a register processing device, electronic equipment and a storage medium.

Description

Technical Field

[0001] The present disclosure relates to the field of artificial intelligence technology, and in particular to the technical fields of chips, simultaneous multi-threading (SMT), vector operations, etc. More specifically, the present disclosure provides a register processing method, device, electronic device, and storage medium. Background Art

[0002] With the development of artificial intelligence technology, the application scenarios of vector computing are increasing. The vector computing unit can be a vector computing unit that supports simultaneous multi-threading. Based on simultaneous multi-threading technology, the vector computing unit can support multiple threads to process data simultaneously. Summary of the invention

[0003] The present disclosure provides a register processing method, apparatus, device and storage medium.

[0004] According to one aspect of the present disclosure, a register processing method is provided, the method comprising: emitting instructions to be processed based on a first number of architectural registers required for the instructions to be processed and a second number of free physical registers, wherein the second number is determined from a plurality of physical registers shared by a plurality of threads, and the instructions to be processed are instructions of a target thread among the plurality of threads; in response to receiving a release instruction corresponding to the instructions to be processed, releasing the physical registers occupied by the instructions to be processed.

[0005] According to another aspect of the present disclosure, a register processing device is provided, the device comprising: a plurality of physical registers configured to be shared by a plurality of threads; a register mapping unit configured to: provide indication information to an instruction fetch unit according to a first number of architectural registers required for an instruction to be processed and a second number of free physical registers, wherein the second number is determined from a plurality of physical registers shared by a plurality of threads, and the instruction to be processed is an instruction of a target thread among the plurality of threads; the instruction fetch unit configured to: in response to determining that the indication information corresponding to the instruction to be processed is the first indication information, emit the instruction to be processed; the register mapping unit is further configured to: in response to receiving a release instruction corresponding to the instruction to be processed, release the physical register occupied by the instruction to be processed

[0006] According to another aspect of the present disclosure, a register processing device is provided. The device includes the register processing apparatus provided by the present disclosure.

[0007] According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method provided according to the present disclosure.

[0008] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided. The computer instructions are used to cause a computer to execute the method provided according to the present disclosure.

[0009] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the method provided according to the present disclosure is implemented.

[0010] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0012] Figure 1 is a schematic flow chart of a register processing method according to an embodiment of the present disclosure;

[0013] Figure 2 is a schematic diagram of a register processing method according to an embodiment of the present disclosure;

[0014] Figure 3 is a schematic diagram of a register mapping table according to an embodiment of the present disclosure;

[0015] Figure 4 is a schematic diagram of a release instruction according to an embodiment of the present disclosure;

[0016] Figure 5 is a schematic block diagram of a register processing device according to an embodiment of the present disclosure;

[0017] Figure 6 is a schematic block diagram of a register processing device according to an embodiment of the present disclosure; and

[0018] Figure 7 is a block diagram of an electronic device to which a register processing method can be applied according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0020] Based on simultaneous multi-threading technology, the vector computing unit can support multiple threads to execute multiple vector instructions at the same time to process data simultaneously, thereby improving the operating efficiency of artificial intelligence-related applications. However, in order to achieve simultaneous data processing by multiple threads, multiple vector registers need to be allocated to each thread, making it difficult to reduce the chip area overhead and further optimize the chip power consumption.

[0021] The data bit width of the vector register can be 256 bits. In this case, a larger vector register stack space is also required. If the vector computing unit supports 8 threads to execute instructions simultaneously, 32 vector registers can be set for each of the 8 threads, for a total of 256 vector registers, which makes it difficult to effectively optimize the chip area and function.

[0022] Therefore, in order to reduce chip area overhead and power consumption, the present disclosure provides a register processing method, which will be described below.

[0023] Figure 1 is a schematic flow chart of a register processing method according to an embodiment of the present disclosure.

[0024] like Figure 1 As shown, method 100 may include operations S110 to S120.

[0025] In operation S110 , a pending instruction is issued according to a first number of architectural registers required by the pending instruction and a second number of free physical registers.

[0026] In the embodiment of the present disclosure, the instruction to be processed may be an instruction of a target thread among the multiple threads. For example, the multiple threads may be, for example, 8 threads. The target thread may be any thread among the multiple threads.

[0027] In the embodiments of the present disclosure, the architecture register may also be referred to as a logical register. For example, taking the instruction to be processed as an addition instruction, the addition instruction indicates to add the value of the first architecture register and the value of the second architecture register, and write the addition result to the third architecture register. The first number of architecture registers required by the addition instruction may be 3.

[0028] In the disclosed embodiment, the second number of free physical registers may be determined from the physical registers shared by multiple threads. For example, taking 8 threads as an example, 64 to 224 physical registers may be set for the 8 threads. The physical registers may be the above-mentioned vector registers. Thus, the number of physical registers may be reduced by 12.5% ​​to 75%.

[0029] In the embodiment of the present disclosure, the instruction to be processed may be sent to the decoding unit. For example, when the first number is greater than 0 and the second number is greater than 0, the instruction fetch unit may send the instruction to be processed to the decoding unit.

[0030] In operation S120 , in response to receiving a release instruction corresponding to the pending instruction, a physical register occupied by the pending instruction is released.

[0031] In the embodiment of the present disclosure, the release instruction may be received after the pending instruction is executed. The physical register occupied by the pending instruction is released so as to be occupied by other instructions.

[0032] Through the disclosed embodiment, before providing the instruction to the decoding unit, the number of architectural registers and the number of free physical registers of the instruction to be processed are determined, and the instruction can be continued to be executed when there are free physical registers, so that multiple threads can share multiple physical registers. After receiving the release instruction, the occupied registers are released, and when multiple threads share multiple physical registers, the number of physical registers can be effectively reduced, thereby effectively reducing the chip area overhead and the power consumption.

[0033] Taking the simultaneous multithreaded computing unit (SMT8) supporting 8 threads as an example, if 128 vector registers are set for 8 threads, the chip area can be reduced by about 20%. In addition, for the simultaneous multithreaded computing unit supporting 8 threads, about 5 threads are busy at the same time due to waiting for memory access results and other reasons. Therefore, reducing 128 vector registers will hardly cause the performance of the vector computing unit to decrease. If more than 128 vector registers (for example, 160) are set, the chip area can be effectively reduced without changing the performance of the vector computing unit.

[0034] It can be understood that the method of the present disclosure is described above, and the method of the present disclosure will be further described below.

[0035] Figure 2 is a schematic diagram of a register processing method according to an embodiment of the present disclosure.

[0036] like Figure 2 As shown, the above method 100 can be implemented based on the register mapping unit 210 and the instruction fetch unit 220. The instruction fetch unit 220 can obtain the instruction of one thread among multiple threads from the instruction cache (icache) ic20. The thread can be used as the target thread. The instruction can be used as a to-be-processed instruction.

[0037] In the disclosed embodiment, the instruction fetch unit 220 may include a register quantity determination module. The register quantity determination module may determine the number of architectural registers required for the instruction to be processed. For example, the instruction fetch unit 220 may include a simple decoding module. The decoding module may determine the number of architectural registers required for the instruction to be processed, and may serve as a register quantity determination module. It is understood that the decoding module is mainly used to determine the number of architectural registers required for the instruction, which is different from the decoding unit. After the instruction fetch unit transmits the instruction to the decoding unit, the decoding unit may decode the instruction.

[0038] In an embodiment of the present disclosure, the instruction fetch unit 220 may send a first request to the register mapping unit 210. The first request may indicate the number of architectural registers required for the instruction to be processed.

[0039] In some embodiments, register mapping unit 210 may determine whether a first number of architectural registers required for a pending instruction is less than or equal to a second number of free physical registers.

[0040] In some embodiments, in some implementations of the above operation S110, in response to determining that the first number is less than or equal to the second number, the register mapping unit 210 may provide the first indication information to the instruction fetch unit 220. The first indication information may instruct the instruction fetch unit 220 to transmit the pending instruction to the decoding unit. In the case where the number of free physical registers is large, the pending instruction may continue to be executed. Through the embodiments of the present disclosure, before providing the instruction to the decoding unit, the number of architectural registers and the number of free physical registers of the pending instruction are determined, and the instruction may continue to be executed efficiently when there are sufficient free physical registers, so as to realize multiple threads sharing multiple physical registers.

[0041] In some embodiments, the method may further include: in response to determining that the first number is greater than the second number, the register mapping unit 210 may provide second indication information to the instruction fetch unit 220. The second indication information may instruct the instruction fetch unit 220 to stop fetching instructions related to the target thread. In the case where the number of free physical registers is small, the pending instruction may be blocked and the instruction fetch of the target thread may be stopped. It is understood that when the instruction fetch unit stops fetching the target thread, it may fetch instructions of other threads.

[0042] In some embodiments, the method may further include: in response to receiving a release instruction of at least one thread other than the target thread among the multiple threads, determining whether the first number is less than or equal to a third number of free physical registers after receiving the release instruction. For example, at least one thread other than the target thread among the multiple threads may include a first thread and a second thread. If the instruction fetch unit 220 obtains the release instruction of the first thread, the instruction fetch unit 220 may provide the release instruction to the register mapping unit 210. The register mapping unit 210 may release the physical registers occupied by the instructions of the first thread. As a result, the number of free physical registers increases, for example, from the second number to the third number. Next, the register mapping unit 210 may determine whether the first number of architectural registers required for the instruction to be processed is less than or equal to the third number of free physical registers. At this time, if the first number of architectural registers required for the instruction to be processed is less than or equal to the third number of free physical registers, the instruction to be processed may be provided to the decoding unit, and the instruction of the target thread may be retrieved again.

[0043] According to the embodiments of the present disclosure, when there are few free physical registers, instruction fetching of the target thread can be stopped, and instructions of other threads can be obtained to improve instruction processing efficiency.

[0044] It can be understood that some methods of issuing instructions to be processed are described above, and the register mapping unit will be further described below.

[0045] In some embodiments, the register mapping unit may include a register mapping table. Figure 3 Provide explanation.

[0046] Figure 3 is a schematic diagram of a register mapping table according to an embodiment of the present disclosure.

[0047] In the embodiment of the present disclosure, the register mapping table may include multiple entries. Figure 3 As shown, the register mapping table regmap30 may include N entries. N may be an integer greater than 1. N may be 128, for example.

[0048] In the embodiment of the present disclosure, multiple entries correspond to multiple physical registers respectively. Figure 3 As shown, N entries may correspond to N physical registers. Each entry may correspond to one physical register.

[0049] In an embodiment of the present disclosure, an entry may include a validity field (valid) and a physical register identification field (pid). The value of the validity field may indicate whether the physical register is busy. The physical register identification field may indicate a physical register. Figure 3As shown, the value of the physical register identification field of entry e3000 is p12, which can indicate the physical register numbered 12. The value of the effectiveness field of entry e3001 is 1, which can indicate that the physical register p12 is busy. Figure 3 As shown, the value of the validity field of entry e3127 is 0, indicating that there is an idle physical register among the multiple physical registers. It can be understood that when the value of the validity field of entry e3127 is 0, the value of the physical register identification field of entry e3127 can be empty or the number of a physical register.

[0050] In the embodiment of the present disclosure, the entry may further include an architecture register identification field. The architecture register identification field may indicate the thread occupying the physical register and the architecture register corresponding to the physical register. Figure 3 As shown, the value of the architectural register identification field of entry e3000 is {0, r9}, which can represent the architectural register r9 of thread 0. An instruction of thread 0 occupies physical register p12. The architectural register r9 of thread 0 is renamed to physical register p12. In addition, the value of the architectural register identification field of entry e3001 is {2, r0}, which can represent the architectural register r0 of thread 2. An instruction of thread 2 occupies physical register p0. The architectural register r0 of thread 2 is renamed to physical register p0.

[0051] In the embodiment of the present disclosure, the number of free physical registers can be determined from multiple physical registers through a register mapping table. For example, when determining whether the first number of architectural registers required for the instruction to be processed is less than or equal to the number of free physical registers, the register mapping unit can look up the table to determine the number of entries with a value of 0 in the effectiveness field in the register mapping table regmap30 as the number of free physical registers.

[0052] Through the embodiment of the present disclosure, a register mapping table is set so that multiple physical registers can be efficiently used by multiple threads. The register mapping unit can quickly determine the number of free physical registers based on the register mapping table, thereby improving instruction processing efficiency.

[0053] It can be understood that the register mapping table of the present disclosure is described above, and the release instruction of the present disclosure will be described below.

[0054] Figure 4 is a schematic diagram of a release instruction according to an embodiment of the present disclosure.

[0055] like Figure 4 As shown, the release instruction ri40 can be a 32-bit instruction. Bits 0 to 14 of the release instruction ri40 can be an operation code.

[0056] In some embodiments, the release instruction may include a reference register identifier. Figure 4 As shown, the values ​​of bits 15 to 19 of the release instruction ri40 can be used as a reference register identifier. For example, the reference register identifier can be r5, which can represent the fourth architecture register of the target thread.

[0057] In some embodiments, the release instruction may further include indication information of the physical register to be released. The indication information of the physical register to be released may include multiple indication values. The multiple indication values ​​may be valid values ​​or invalid values. Figure 4 As shown, the value of the 20th to 31st bits of the release instruction ri40 can be used as the indication information of the physical register to be released. For example, the value [31:20] of the 31st to 20th bits of the release instruction ri40 can be 000100001010. The 21st, 23rd and 28th bits are valid values ​​1.

[0058] In some embodiments, in some implementations of the above operation S120, releasing the physical register occupied by the pending instruction may include: determining at least one to-be-released register identifier corresponding to at least one valid value among the multiple indication values ​​based on the target register identifier corresponding to the target indication value among the multiple indication values.

[0059] In the disclosed embodiment, the target register identifier is determined based on the reference register identifier. Figure 4As shown, the target indication value can be any indication value of multiple indication values. For example, the indication value of the 20th bit can be preset as the target indication value, and the indication value of the 20th bit can be preset to correspond to the reference register identifier. Thus, the reference register identifier can be used as the target register identifier. The indication value of the 20th bit corresponds to the architecture register identifier r5. Next, the architecture register identifier corresponding to the indication value can be determined according to the offset between the multiple indication values ​​and the target indication value. The indication value of the 21st bit corresponds to the architecture register identifier r6. The indication value of the 22nd bit corresponds to the architecture register identifier r7. The indication value of the 23rd bit corresponds to the architecture register identifier r8. The indication value of the 24th bit corresponds to the architecture register identifier r9. The indication value of the 25th bit corresponds to the architecture register identifier r10. The indication value of the 26th bit corresponds to the architecture register identifier r11. The indication value of the 27th bit corresponds to the architecture register identifier r12. The indication value of the 28th bit corresponds to the architecture register identifier r13. The indication value of the 29th bit corresponds to the architecture register identifier r14. The indication value of the 30th bit corresponds to the architecture register identifier r15. The 31st bit of the indication value corresponds to the architecture register identifier r16. It can be understood that in this embodiment, the lowest bit (the 20th bit) of the multiple indication values ​​is used as the target indication value, but the present disclosure is not limited thereto, and the highest bit (for example, the 31st bit) of the multiple indication values ​​may be used as the target indication value, or any bit of the indication values ​​may be used as the target indication value.

[0060] In the disclosed embodiment, at least one register identifier to be released corresponding to at least one valid value among the multiple indication values ​​can be determined. As described above, the 21st bit, the 23rd bit, and the 28th bit are valid values. The architecture register identifier r6 corresponding to the 21st bit, the architecture register identifier r8 corresponding to the 23rd bit, and the architecture register identifier r13 corresponding to the 28th bit can be used as register identifiers to be released, respectively. It can be understood that the architecture register identifier r6, the architecture register identifier r8, and the architecture register identifier r13 can represent the fifth architecture register identifier, the sixth architecture register, and the seventh architecture register of the target thread.

[0061] In some embodiments, in some implementations of the above operation S120, releasing the physical registers occupied by the pending instruction may include: releasing at least one physical register corresponding to at least one register identifier to be released. For example, the release instruction ri40 may be an instruction of the target thread. By querying the register mapping table, three physical registers corresponding to the architecture register identifier r6, the architecture register identifier r8, and the architecture register identifier r13 of the target thread may be determined, and these three physical registers may be released. And the value of the validity field of the entry corresponding to these three physical registers is adjusted to an invalid value of 0.

[0062] Through the disclosed embodiment, a customized release instruction is provided, which can quickly release occupied physical registers. When multiple threads share multiple physical registers, it can effectively avoid threads being blocked due to a small number of free physical registers, and can fully improve instruction processing efficiency.

[0063] It is understood that the above description uses the vector computing unit supporting 8 threads as an example to illustrate the present disclosure. However, the present disclosure is not limited thereto, and a simultaneous multi-thread computing unit (SMT4) supporting 4 threads may also apply the above method. It is also understood that the number of threads in the present disclosure may be any value.

[0064] It is understood that during execution, the instruction may be processed by multiple functional units. The multiple functional units may include the above-mentioned instruction fetch unit. In addition to the instruction fetch unit, the functional unit may also send a second request to the storage unit to obtain data.

[0065] It can be understood that the method of the present disclosure is described above, and the device of the present disclosure will be described below.

[0066] Figure 5 is a schematic block diagram of a register processing device according to an embodiment of the present disclosure.

[0067] like Figure 5 As shown, the apparatus 500 may include a plurality of physical registers 501 , a register mapping unit 510 and an instruction fetch unit 520 .

[0068] The multiple physical registers 501 can be configured to be shared by multiple threads. For example, the multiple threads can be 8, and 128 shared physical registers can be set for the 8 threads.

[0069] The register mapping unit 510 may be configured to provide indication information to the instruction fetch unit according to a first number of architectural registers required for the instruction to be processed and a second number of free physical registers.

[0070] In the embodiments of the present disclosure, the architecture register may also be referred to as a logical register. For example, taking the instruction to be processed as an addition instruction, the addition instruction indicates to add the value of the first architecture register and the value of the second architecture register, and write the addition result to the third architecture register. The first number of architecture registers required by the addition instruction may be 3.

[0071] In the embodiment of the present disclosure, the second number of free physical registers may be determined from a plurality of physical registers shared by a plurality of threads. For example, taking 8 threads as an example, 64 to 224 physical registers may be set for the 8 threads. The physical registers may be the above-mentioned vector registers. Thus, the number of physical registers may be reduced by 12.5% ​​to 75%.

[0072] In the embodiment of the present disclosure, the instruction to be processed is an instruction of a target thread among multiple threads. For example, the target thread may be any thread among the multiple threads.

[0073] The instruction fetch unit 520 may be configured to: in response to determining that the indication information corresponding to the instruction to be processed is the first indication information, transmit the instruction to be processed.

[0074] In the embodiment of the present disclosure, the instruction to be processed may be sent to the decoding unit. For example, when the first number is greater than 0 and the second number is greater than 0, the instruction fetch unit 520 may send the instruction to be processed to the decoding unit.

[0075] The register mapping unit 510 may also be configured to: in response to receiving a release instruction corresponding to the instruction to be processed, release the physical register occupied by the instruction to be processed.

[0076] In the embodiment of the present disclosure, the release instruction may be received after the pending instruction is executed. The physical register occupied by the pending instruction is released so as to be occupied by other instructions.

[0077] Through the disclosed embodiment, before providing the instruction to the decoding unit, the number of architectural registers of the instruction to be processed and the number of free physical registers are determined, and the instruction can be continued to be executed when there are free physical registers, so that multiple threads can share multiple physical registers. After receiving the release instruction, the occupied registers are released, and when multiple threads share multiple physical registers, the number of physical registers can be effectively reduced, thereby effectively reducing the chip area overhead and reducing power consumption.

[0078] In some embodiments, the instruction fetch unit may include a register quantity determination module. The register quantity determination module may be configured to: determine the number of architectural registers required for the instruction to be processed. For example, the above description of the register quantity determination module of the instruction fetch unit 220 is also applicable to the register quantity determination unit of the instruction fetch unit 520, and the present disclosure will not repeat them here.

[0079] In some embodiments, the instruction fetch unit may obtain an instruction of one of the multiple threads from the instruction cache. The thread may be used as a target thread. The instruction may be used as a to-be-processed instruction.

[0080] In some embodiments, the instruction fetch unit may be further configured to: send a first request to the register mapping unit. The first request is used to indicate the number of architecture registers required for the instruction to be processed.

[0081] In some embodiments, the register mapping unit may be configured to determine whether a first number of architectural registers required by the instruction to be processed is less than or equal to a second number of free physical registers.

[0082] In some embodiments, the register mapping unit may be configured as follows: in response to determining that the first number is less than or equal to the second number of free physical registers, the register mapping unit may provide first indication information to the instruction fetch unit. The first indication information may instruct the instruction fetch unit to transmit the pending instruction to the decoding unit. In the case where the number of free physical registers is large, the pending instruction may continue to be executed. Through the embodiments of the present disclosure, before providing the instruction to the decoding unit, the number of architectural registers of the pending instruction and the number of free physical registers are determined, and when there are sufficient free physical registers, the instruction may continue to be executed efficiently to achieve multiple threads sharing multiple physical registers.

[0083] In some embodiments, the register mapping unit may also be configured to: in response to determining that a first number of architectural registers required for the pending instruction is greater than a second number of free physical registers, provide second indication information to the instruction fetch unit. The second indication information may instruct the instruction fetch unit to stop fetching instructions related to the target thread. In the case where the number of free physical registers is small, the pending instruction may be blocked and the fetching of instructions of the target thread may be stopped. It is understood that in the case of stopping fetching instructions of the target thread, the instruction fetch unit may fetch instructions of other threads.

[0084] In some embodiments, the register mapping unit may also be configured to: in response to receiving a release instruction from at least one thread other than the target thread among the multiple threads, determine whether the first number of architectural registers required for the pending instruction is less than or equal to the third number of registers that are free after receiving the release instruction. For example, at least one thread other than the target thread among the multiple threads may include a first thread and a second thread. If the instruction fetch unit obtains the release instruction of the first thread, the instruction fetch unit may provide the release instruction to the register mapping unit. The register mapping unit may release the physical registers occupied by the instructions of the first thread. As a result, the number of free physical registers increases, for example, from the second number mentioned above to the third number. Next, the register mapping unit 210 may determine whether the first number of architectural registers required for the pending instruction is less than or equal to the third number of free physical registers. At this time, if the first number of architectural registers required for the pending instruction is less than or equal to the third number of free physical registers, the pending instruction may be provided to the decoding unit, and the instructions of the target thread may be retrieved again.

[0085] It can be understood that some methods of issuing instructions to be processed are described above, and the register mapping unit will be further described below.

[0086] In some embodiments, the register mapping unit may include a register mapping table.

[0087] In some embodiments, the register mapping table includes multiple entries. The multiple entries correspond to multiple physical registers respectively. The entry includes at least one of a validity field, an architecture register identification field, and a physical register identification field. The value of the physical register identification field is used to represent a physical register. The value of the validity field is used to indicate whether the physical register is busy. The value of the architecture register identification field is used to indicate the thread occupying the physical register and the architecture register corresponding to the physical register. It can be understood that the above description of the register mapping table regmap30 is also applicable to this embodiment, and the present disclosure will not repeat it here.

[0088] In the embodiment of the present disclosure, the number of free physical registers can be determined from multiple physical registers through a register mapping table. For example, when determining whether the first number of architectural registers required for the instruction to be processed is less than or equal to the second number of free physical registers, the register mapping unit can look up the table to determine the number of entries with a value of 0 in the validity field in the register mapping table as the number of free physical registers.

[0089] It can be understood that the register mapping table of the present disclosure is described above, and the release instruction of the present disclosure will be described below.

[0090] In some embodiments, the release instruction includes a reference register identifier and indication information of a physical register to be released, and the indication information of the physical register to be released includes multiple indication values, and the indication values ​​are valid values ​​or invalid values. It can be understood that the above description of the release instruction ri40 is also applicable to this embodiment, and the present disclosure will not repeat them here.

[0091] In some embodiments, the register mapping unit is further configured to perform the following operations to release the physical registers occupied by the pending instruction: according to the target register identifier corresponding to the target indication value in the multiple indication values, determine at least one register identifier to be released corresponding to at least one valid value in the multiple indication values. The target register identifier is determined according to the reference register identifier. Release at least one physical register corresponding to the at least one register identifier to be released. It can be understood that the above description of the register mapping unit releasing the physical register according to the release instruction ri40 is also applicable to this embodiment, and the present disclosure will not repeat it here.

[0092] Figure 6 is a block diagram of a register processing device according to one embodiment of the present disclosure.

[0093] like Figure 6As shown, the device 60 may include a register processing device 600. For example, the register processing device 600 may be the device 500 described above.

[0094] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0095] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0096] Figure 7 A schematic block diagram of an example electronic device 700 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0097] like Figure 7 As shown, the device 700 includes a computing unit 701, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 702 or a computer program loaded from a storage unit 708 to a random access memory (RAM) 703. In the RAM 703, various programs and data required for the operation of the device 700 can also be stored. The computing unit 701, the ROM 702, and the RAM 703 are connected to each other via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0098] A number of components in the device 700 are connected to the I / O interface 705, including: an input unit 706, such as a keyboard, a mouse, etc.; an output unit 707, such as various types of displays, speakers, etc.; a storage unit 708, such as a disk, an optical disk, etc.; and a communication unit 709, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 709 allows the device 700 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0099] The computing unit 701 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSP), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 701 performs the various methods and processes described above, such as the register processing method. For example, in some embodiments, the register processing method may be implemented as a computer software program, which is tangibly included in a machine-readable medium, such as a storage unit 708. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 700 via the ROM 702 and / or the communication unit 709. When the computer program is loaded into the RAM 703 and executed by the computing unit 701, one or more steps of the register processing method described above may be performed. Alternatively, in other embodiments, the computing unit 701 may be configured to execute the register processing method in any other appropriate manner (eg, by means of firmware).

[0100] Various embodiments of the systems and techniques described above herein may be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard parts (ASSPs), system on chip systems (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0101] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0102] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. More specific examples of machine-readable storage media may include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories, read-only memories, erasable programmable read-only memories (EPROM) or flash memories, optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0103] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a cathode ray tube (CRT) display or a liquid crystal display (LCD)) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0104] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a Local Area Network (LAN), a Wide Area Network (WAN), and the Internet.

[0105] A computer system may include clients and servers. Clients and servers are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship to each other.

[0106] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0107] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A register processing method, comprising: Emitting the pending instruction according to a first number of architectural registers required for the pending instruction and a second number of free physical registers, wherein the second number is determined from a plurality of physical registers shared by a plurality of threads, and the pending instruction is an instruction of a target thread among the plurality of threads; In response to receiving a release instruction corresponding to the pending instruction, a physical register occupied by the pending instruction is released.

2. The method according to claim 1, wherein: The transmitting the pending instruction according to the first number of architectural registers required for the pending instruction and the second number of free physical registers comprises: In response to determining that the first number is less than or equal to the second number, the pending instruction is emitted.

3. The method according to claim 1, wherein: The transmitting the pending instruction according to the first number of architectural registers required for the pending instruction and the second number of free physical registers further comprises: In response to determining that the first number is greater than the second number, stopping acquiring instructions of the target thread; In response to receiving a release instruction of at least one of the plurality of threads other than the target thread, it is determined whether the first number is less than or equal to a third number of the free physical registers after receiving the release instruction.

4. The method according to claim 1, wherein: The release instruction includes a reference register identifier and indication information of a physical register to be released, wherein the indication information of the physical register to be released includes a plurality of indication values, and the indication values ​​are valid values ​​or invalid values. The releasing of the physical registers occupied by the pending instructions comprises: Determine, according to a target register identifier corresponding to a target indicator value among the multiple indicator values, at least one register identifier to be released corresponding to at least one valid value among the multiple indicator values, wherein the target register identifier is determined according to the reference register identifier; At least one of the physical registers corresponding to at least one of the to-be-released register identifiers is released.

5. The method according to claim 1, wherein: The number of the free physical registers is determined from the plurality of physical registers through a register mapping table, The register mapping table includes multiple entries, each of which corresponds to the multiple physical registers. The entry includes at least one of a validity field, an architecture register identification field, and a physical register identification field. The physical register identification field is used to represent one of the physical registers. The validity field is used to indicate whether the physical register is busy. The architecture register identification field is used to indicate the thread occupying the physical register and the architecture register corresponding to the physical register.

6. A register processing device, comprising: Multiple physical registers, configured to be shared by multiple threads; a register mapping unit configured to: provide indication information to an instruction fetch unit according to a first number of architectural registers required for the instruction to be processed and a second number of free physical registers, wherein the second number is determined from a plurality of physical registers shared by a plurality of threads, and the instruction to be processed is an instruction of a target thread among the plurality of threads; an instruction fetch unit, configured to: in response to determining that the indication information corresponding to the instruction to be processed is the first indication information, transmit the instruction to be processed; The register mapping unit is further configured to: in response to receiving a release instruction corresponding to the instruction to be processed, release the physical register occupied by the instruction to be processed.

7. The method according to claim 1, wherein: The register mapping unit is further configured to perform the following operations to provide indication information to the instruction fetch unit according to a first number of architectural registers required by the pending instruction and a second number of free physical registers: In response to determining that the first number is less than or equal to the second number, the first indication information is provided to the instruction fetch unit.

8. The device according to claim 6, wherein: The instruction fetch unit comprises a register quantity determination module, The register quantity determination module is configured to: determine the number of architectural registers required for the instruction to be processed; The instruction fetch unit is further configured to: send a first request to the register mapping unit, wherein the first request is used to indicate the number of architecture registers required by the instruction to be processed.

9. The device according to claim 6, wherein: The register mapping unit is further configured to perform at least one of the following operations to provide indication information to the instruction fetch unit according to the first number of architectural registers required by the instruction to be processed and the second number of free physical registers: In response to determining that the first number is greater than the second number, providing second indication information to the instruction fetch unit, wherein the second indication information is used to instruct the instruction fetch unit to stop fetching instructions related to the target thread; In response to receiving a release instruction of at least one of the plurality of threads other than the target thread, it is determined whether the first number is less than or equal to a third number of the free registers after receiving the release instruction.

10. The device according to claim 6, wherein: The release instruction includes a reference register identifier and indication information of a physical register to be released, wherein the indication information of the physical register to be released includes a plurality of indication values, and the indication values ​​are valid values ​​or invalid values. The register mapping unit is further configured to perform the following operations to release the physical registers occupied by the pending instructions: Determine, according to a target register identifier corresponding to a target indicator value among the multiple indicator values, at least one register identifier to be released corresponding to at least one valid value among the multiple indicator values, wherein the target register identifier is determined according to the reference register identifier; At least one of the physical registers corresponding to at least one of the to-be-released register identifiers is released.

11. The device according to claim 6, wherein: The number of the free physical registers is determined from the plurality of physical registers through a register mapping table, The register mapping table includes multiple entries, each of which corresponds to a plurality of the physical registers. The entry includes at least one of a validity field, an architecture register identification field, and a physical register identification field. The value of the physical register identification field is used to represent one of the physical registers. The value of the validity field is used to indicate whether the physical register is busy. The value of the architecture register identification field is used to indicate the thread occupying the physical register and the architecture register corresponding to the physical register.

12. A register processing device, comprising the apparatus according to any one of claims 6 to 11.

13. An electronic device, comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 5.

14. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 5.

15. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 5.

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