PCIe dual-port SSD low-power-consumption control device and method

Abstract

The invention relates to the field of storage, in particular to a PCIe dual-port SSD low power consumption control device and method.The device comprises a load prediction unit and a power consumption control unit, and the load prediction unit takes a judgment result of a PCIe power management module ASPM on a link idle state and a margin value of receiving / sending cache as input; and the power consumption control unit calculates respective load states of the current two ports and outputs a level value of a load level, and the power consumption control unit adjusts the working state of each module of the SSD in time according to the load level output by the load prediction unit, so that the power consumption control of the SSD is realized. According to the method, the service pressure and the load conditions of the two ports are detected, the working state of each module of the SSD is adaptively adjusted, dynamic adjustment of the power consumption of the SSD is realized, and on the premise of ensuring timely and accurate data response, the power consumption of the whole disk is reduced to the greatest extent, and the energy-saving effect of a data center is improved.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to a PCIe dual-port SSD low power consumption control device and method. Background Art

[0002] PCIe dual-port SSDs are often used in data center services of active-active storage systems, and are responsible for data storage, read-write access, and other functions. Active-active storage systems are a widely used redundant storage method that uses a master-slave mechanism to enable two data sites to simultaneously handle user services. When a storage controller service fails, it can quickly switch to another controller to provide data access response for upper-layer services, ensuring high-reliability operation of the system. With the rapid development of data centers today, active-active systems no longer only provide traditional disaster recovery capabilities, but also emphasize the improvement of resource utilization, achieving collaborative work and load balancing of two storage arrays, and maximizing hardware resource utilization. When the PCIe dual-port SSD is in dual-port working mode, both links are working, and the overall power consumption of the SSD is high. How to reduce the power consumption of the SSD is an issue that needs to be improved.

[0003] To ensure the independence, security and reliability of the active-active system, the physical isolation of the data read and write path resources of the two PCIe ports, such as the DMA data transmission engine, is considered when designing the PCIe dual-port SSD system. Therefore, the working status of related hardware resources can be automatically adjusted according to the read and write business conditions of the two ports of the active-active system, and the power consumption can be adaptively adjusted to achieve the goal of optimizing the power consumption of the entire disk. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a PCIe dual-port SSD low power consumption control device and method, which can accurately and efficiently realize the power consumption control of the ports according to the load conditions of the access to the two ports by the active-active storage system in real time, thereby reducing the power consumption of the entire disk.

[0005] In order to solve the technical problem, the technical solution adopted by the present invention is: a PCIe dual-port SSD low power consumption control device, including a load prediction unit, a power consumption control unit and a clock switching unit: The input of the load prediction unit is the judgment result of the PCIe power management module ASPM on the link idle state of port A and / or port B and the margin value of the receiving / transmitting buffer. The load state of port A and / or port B is calculated according to the input, and the load level value is output. Port A and port B represent the two PCIe ports of the PCIe dual-port SSD. The load state calculation method is: when the link does not enter the L0s state within the sampling time interval T and the receiving and sending buffers are more than half full within the sampling time interval T, the load prediction unit determines that the link is in a heavy load state and outputs the load level A; when the number of times the link enters the L0s state within the sampling time interval T reaches the threshold Y0 and the receiving and sending buffers are less than half full within the sampling time interval T, the load prediction unit determines that the link is in a light load state and outputs the load level B; when the number of times the link enters the L1 state within the sampling time interval T reaches the threshold Y1, the load prediction unit determines that the link is in a process of no data transmission and outputs the load level C; The input end of the power consumption control unit is connected to the output end of the load prediction unit. The working state of each SSD module is adjusted according to the load level output by the load prediction unit to realize the power consumption control of the SSD. The working state of each SSD module is adjusted as follows: when the load prediction unit outputs level A, each SSD module is controlled to be in a full-load operation state and operate at the maximum supportable frequency. When the load prediction unit outputs level B, each SSD module is controlled to be in a partially reduced-frequency operation state. When the load prediction unit outputs level C, the power consumption core module is controlled to enter a low-power state and standby.

[0006] Furthermore, when the PCIe link power management module ASPM controls the PCIe LTSSM to exit L1 and enter the recovery state, the load prediction unit updates the level to levelA, so that each module synchronously enters the full-load working state. When the PCIe link power management module ASPM controls the PCIe LTSSM from the L0 state to the L0s state, the load prediction unit updates the level to levelB, so that each hardware unit begins to enter the low power consumption control state. When the PCIe link power management module ASPM controls the PCIe LTSSM from the L0s state to the L1 state, the load prediction unit updates the level to levelC, so that each hardware unit enters the deep low power consumption control state.

[0007] Furthermore, the three load levels output by the load prediction unit have internal flow characteristics, and the load levels are managed by a logic operation state machine.

[0008] Furthermore, it also includes a clock switching unit, the input end of the clock switching unit is connected to the output end of the power consumption control unit, which is used to receive the frequency control signal for each SSD module output by the power consumption control unit and switch the clock frequency of each SSD module according to the frequency control signal.

[0009] Furthermore, the frequency control signal for each SSD module output by the power consumption control unit consists of 2 bits. When the load prediction unit outputs Level A, the frequency control signal is the maximum value 11. When the load prediction unit outputs Level B, the frequency control signal outputs the middle value 10. When the load prediction module outputs Level C, the frequency control signal is the second minimum value 01. When the clock needs to be turned off, the frequency control signal is the minimum value 00 (this state cannot be controlled by the load prediction unit and is a reserved control value).

[0010] Correspondingly, each SSD module has 2 control signals, which are combined into 4 frequency division coefficients. The 4 frequency division coefficients produce 4 clock frequency gears. Gear 3 represents the state of no frequency reduction, which meets the working scenario requirements of level A load. Gear 2 represents the state of partial frequency reduction, which meets the working scenario requirements of level B load. Gear 1 represents the state of deep frequency reduction, which meets the working scenario requirements of level C load. Gear 0 represents the clock stop state.

[0011] Furthermore, when the load prediction unit outputs level B or level C, the power consumption core modules that enter a low power consumption state and standby include an NVMe controller, a DDR controller, an AXI bus, and a CPU.

[0012] The present invention also discloses a PCIe dual-port SSD low power consumption control method, comprising the following steps: S01, enable the PCIe dual-port SSD in dual-port working mode; S02, initializing the sampling time interval T of the load prediction unit, and initializing the number of times the link working state enters L0s and L1 thresholds Y0 and Y1; S03, PCIe dual-port SSD performs business command processing; S04, the load prediction unit determines the state of the workload of the two ports in real time, and provides a load level indication signal for the power consumption control unit. The load levels include levelA, levelB and levelC, and the calculation method is as follows: when the link does not enter the L0s state within the sampling time interval T and the receiving and sending buffers are more than half full within the sampling time interval T, the load prediction unit determines that the link is in a heavy load state and outputs the load level levelA; when the number of times the link enters the L0s state within the sampling time interval T reaches the threshold value Y0 and the receiving and sending buffers are less than half full within the sampling time interval T, the load prediction unit determines that the link is in a light load state and outputs the load level levelB; when the number of times the link enters the L1 state within the sampling time interval T reaches the threshold value Y1, the load prediction unit determines that the link is in a process of no data transmission and outputs the load level levelC; S05. The power consumption control unit uses the load level output by the load prediction unit as input to adjust the working state of each SSD module to realize power consumption control of the SSD. The working state of each SSD module is adjusted as follows: when the load prediction unit outputs level A, each SSD module is controlled to be in a full-load operation state and to operate at the maximum supportable frequency; when the load prediction unit outputs level B, each SSD module is controlled to be in a partially reduced-frequency operation state; when the load prediction unit outputs level C, the power consumption core module is controlled to enter a low-power state and standby.

[0013] Furthermore, step S04 also includes: when the PCIe link power management module ASPM controls the PCIe LTSSM to exit L1 and enter the recovery state, the load prediction unit updates the level to levelA, so that each module synchronously enters the full-load working state; when the PCIe link power management module ASPM controls the PCIe LTSSM from the L0 state to the L0s state, the load prediction unit updates the level to levelB, so that each hardware unit begins to enter a low power consumption control state; when the PCIe link power management module ASPM controls the PCIe LTSSM from the L0s state to the L1 state, the load prediction unit updates the level to levelC, so that each hardware unit enters a deep low power consumption control state.

[0014] Further, in step S05, the power consumption control unit takes the load level output by the load prediction unit as input, obtains and outputs the frequency control signal of each module of the SSD through calculation, sets a clock switching unit, and the clock switching unit receives the frequency control signal output by the power consumption control unit to control the clock frequency of each module of the SSD; The frequency control signal for each SSD module output by the power consumption control unit consists of 2 bits. When the load prediction unit outputs Level A, the frequency control signal is the maximum value 11. When the load prediction unit outputs Level B, the frequency control signal outputs the middle value 10. When the load prediction module outputs Level C, the frequency control signal is the second minimum value 01. When the clock needs to be turned off, the frequency control signal is the minimum value 00 (this state cannot be controlled by the prediction unit and is a reserved control value).

[0015] Correspondingly, each SSD module has 2 control signals, which are combined into 4 frequency division coefficients. The 4 frequency division coefficients produce 4 clock frequency gears. Gear 3 represents the state of no frequency reduction, which meets the working scenario requirements of level A load. Gear 2 represents the state of partial frequency reduction, which meets the working scenario requirements of level B load. Gear 1 represents the state of deep frequency reduction, which meets the working scenario requirements of level C load. Gear 0 represents the clock stop state.

[0016] Beneficial effects of the present invention: The present invention detects the business pressure and load conditions of the two ports, adaptively coordinates and schedules the working status of the hardware modules involved in the two physical paths, such as DMA and NVMe controllers, to achieve dynamic adjustment of SSD power consumption. Under the premise of ensuring timely and accurate data response, the power consumption of the entire disk is reduced to the greatest extent possible, thereby improving the energy saving effect of the data center. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of an SSD equipped with the low power consumption control device described in Example 1; Figure 2 This is a flow chart of the method described in Example 2. DETAILED DESCRIPTION

[0018] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0019] Example 1 This embodiment discloses a PCIe dual-port SSD low power consumption control device, such as Figure 1As shown, the basic hardware units of SSD include PCIe dual-port module, NVMe controller, DDR controller, CPU and bus. PCIe dual-port module is the interface for SSD to communicate with the host. NVMe controller is the functional unit for NVMe protocol parsing, queue management and command processing. DDR controller is the control module of DDR data cache medium. CPU core is the central processing unit module for software operation. Bus is used to connect various hardware units. This device detects the business pressure and load conditions of the two ports, adaptively coordinates and schedules the working status of the hardware modules involved in the two physical paths, such as DMA and NVMe controller, to achieve dynamic adjustment of SSD power consumption. Under the premise of ensuring timely and accurate data response, it can minimize the power consumption of the entire disk and reduce the energy saving effect of the data center.

[0020] Specifically, the device includes a load prediction unit, an adaptive power consumption coordination and clock switching unit. The load prediction unit is used to determine the state of the PCIe port workload, and the input is the PCIe power management module ASPM's judgment result on the link idle state of port A and / or port B and the margin value of the receive / send buffer. The load state of port A and / or port B is calculated based on the input, and the load level value is output. Port A and port B represent the two PCIe ports of the PCIe dual-port SSD.

[0021] In this embodiment, the load state is calculated as follows: when the link does not enter the L0s state within the sampling time interval T and the receiving and sending buffers are in a state of more than half full within the sampling time interval T, the load prediction unit determines that the link is in a heavy load state and outputs a load level A; when the number of times the link enters the L0s state within the sampling time interval T reaches a threshold value Y0 and the receiving and sending buffers are in a state of less than half full within the sampling time interval T, the load prediction unit determines that the link is in a light load state and outputs a load level B; when the number of times the link enters the L1 state within the sampling time interval T reaches a threshold value Y1, the load prediction unit determines that the link is in a process of no data transmission and outputs a load level C. In this embodiment, the three load levels output by the load prediction unit have an internal flow characteristic, that is, the Level levels can flow mutually, the load level is managed by a logic operation state machine, and the switching between the Level levels is controlled by a state machine to ensure effective management of the load level.

[0022] The input end of the power consumption control unit is connected to the output end of the load prediction unit. The load level output by the load prediction unit is used to adjust the working state of each SSD module to realize the power consumption control of the SSD. The working state of each SSD module is adjusted as follows: when the load prediction unit outputs levelA, each SSD module is controlled to be in a full-load operation state and to operate at the maximum frequency that can be supported. When the load prediction unit outputs levelB, each SSD module is controlled to be in a partially reduced frequency operation state. When the load prediction unit outputs levelC, the power consumption core module is controlled to enter a low-power state on standby. When the PCIe link power management module ASPM controls the PCIe LTSSM to exit L1 and enter the recovery state, the load prediction unit updates the level to levelA, so that each module enters the full-load working state synchronously. When the PCIe link power management module ASPM controls the PCIe LTSSM to enter the L0s state from the L0 state, the load prediction unit updates the level to levelB, so that each hardware unit begins to enter the low-power control state. When the PCIe link power management module ASPM controls the PCIe LTSSM to enter the L1 state from the L0s state, the load prediction unit updates the level to level C, so that each hardware unit enters a deep low power consumption control state.

[0023] In this embodiment, the frequency switching of each SSD module is realized by a clock switching unit. The input end of the clock switching unit is connected to the output end of the power consumption control unit, which is used to receive the frequency control signal for each SSD module output by the power consumption control unit, and switch the clock frequency of each SSD module according to the frequency control signal.

[0024] Specifically, the frequency control signal for each SSD module output by the power consumption control unit consists of 2 bits. When the load prediction unit outputs Level A, the frequency control signal is the maximum value 11. When the load prediction unit outputs Level B, the frequency control signal outputs the middle value 10. When the load prediction module outputs Level C, the frequency control signal is the second minimum value 01. When the clock needs to be turned off, the frequency control signal is the minimum value 00 (this state cannot be controlled by the prediction unit and is a reserved control value).

[0025] Correspondingly, each SSD module has 2 control signals, which are combined into 4 frequency division coefficients. The 4 frequency division coefficients generate 4 clock frequency gears to achieve adaptive frequency switching. Gear 3 represents the state of no frequency reduction, which meets the working scene requirements of level A load, gear 2 represents the state of partial frequency reduction, which meets the working scene requirements of level B load, gear 1 represents the state of deep frequency reduction, which meets the working scene requirements of level C load, and gear 0 represents the clock stop state. Through the gear selection of the frequency control signal, the safe switching of the frequency of each module is achieved.

[0026] In this embodiment, when the load prediction unit outputs level B or level C, the power consumption core modules that enter the low power consumption state and standby include the NVMe controller, the DDR controller, the AXI bus and the CPU.

[0027] When changing the frequency of each SSD module, since the PCIe NVMe controller is unique to each port, the frequency of the PCIe NVMe controller can be directly adjusted according to the load level. The AXI bus, DDR controller and CPU core are shared by the two ports, and the power consumption levels of the two ports need to be comprehensively judged to confirm the working status. For example, if the power consumption level of port A is level B and the power consumption level of port B is level C, then the power consumption levels of port A and port B are comprehensively considered, and the AXI bus, DDR controller and CPU core enter the partial frequency reduction state corresponding to level B to ensure the normal operation of port A.

[0028] Example 2 In this embodiment, the frequency control signal output by the power consumption control unit is implemented by the CPU or software, and a clock switching unit is not required. It should be noted that the CPU or software switches the frequency of the SSD module when it is idle.

[0029] Example 3 This embodiment discloses a PCIe dual-port SSD low power consumption control method. Figure 2 As shown, the following steps are included: S01, the SOC chip enables the PCIe dual-port SSD in dual-port working mode by detecting that the DualPortEn# signal of the PCIe gold finger is valid; S02, initializing the sampling time interval T of the load prediction unit, and initializing the number of times the link working state enters L0s and L1 thresholds Y0 and Y1; S03, PCIe dual-port SSD performs business command processing; S04, the load prediction unit determines the state of the workload of the two ports in real time, and provides a load level indication signal for the power consumption control unit. The load levels include levelA, levelB and levelC, and the calculation method is as follows: when the link does not enter the L0s state within the sampling time interval T and the receiving and sending buffers are more than half full within the sampling time interval T, the load prediction unit determines that the link is in a heavy load state and outputs the load level levelA; when the number of times the link enters the L0s state within the sampling time interval T reaches the threshold value Y0 and the receiving and sending buffers are less than half full within the sampling time interval T, the load prediction unit determines that the link is in a light load state and outputs the load level levelB; when the number of times the link enters the L1 state within the sampling time interval T reaches the threshold value Y1, the load prediction unit determines that the link is in a process of no data transmission and outputs the load level levelC; S05. The power consumption control unit uses the load level output by the load prediction unit as input to adjust the working state of each SSD module to realize power consumption control of the SSD. The working state of each SSD module is adjusted as follows: when the load prediction unit outputs level A, each SSD module is controlled to be in a full-load operation state and to operate at the maximum supportable frequency; when the load prediction unit outputs level B, each SSD module is controlled to be in a partially reduced-frequency operation state; when the load prediction unit outputs level C, the power consumption core module is controlled to enter a low-power state and standby.

[0030] In this embodiment, step S04 also includes: when the PCIe link power management module ASPM controls the PCIe LTSSM to exit L1 and enter the recovery state, the load prediction unit updates the level to levelA, so that each module synchronously enters the full-load working state, and when the PCIe link power management module ASPM controls the PCIe LTSSM to enter the L0s state from the L0 state, the load prediction unit updates the level to levelB, so that each hardware unit begins to enter the low power consumption control state. When the PCIe link power management module ASPM controls the PCIe LTSSM to enter the L1 state from the L0s state, the load prediction unit updates the level to levelC, so that each hardware unit enters the deep low power consumption control state.

[0031] In step S05, the power consumption control unit takes the load level output by the load prediction unit as input, obtains and outputs the frequency control signal of each SSD module through calculation, sets a clock switching unit, and the clock switching unit receives the frequency control signal output by the power consumption control unit to control the clock frequency of each SSD module.

[0032] The frequency control signal for each SSD module output by the power consumption control unit consists of 2 bits. When the load prediction unit outputs LevelA, the frequency control signal is the maximum value 11. When the load prediction module outputs LevelC, the frequency control signal is the sub-minimum value 01. The NVMe controller, DDR controller, corresponding AXI bus and CPU and other power-consuming core modules enter a low-power state on standby. When the load prediction unit outputs LevelB, the frequency control signal outputs the middle value 10 to ensure that each functional module works normally and the operating frequency is moderate.

[0033] Correspondingly, each SSD module has two control signals, which are combined into four frequency division coefficients. The four frequency division coefficients generate four clock frequency gears. Gear 3 represents the state of no frequency reduction, which meets the working scene requirements of level A loads, gear 2 represents the state of partial frequency reduction, which meets the working scene requirements of level B loads, and gear 1 represents the state of deep frequency reduction, which meets the working scene requirements of level C loads. The frequency of each module can be safely switched by selecting the gear of the frequency control signal.

[0034] In the above description, PCIe LTSSM represents the PCIe link training state machine, L0s, L0, and L1 are the working states of the PCIe link, and L0 is the normal working state of the PCIe link. In this state, the PCIe link can send and receive TLP, DLLP, and Ordered Sets normally. L0s is the first level low power state, which can be switched to the L0 state in a shorter time. L1 is the second level low power state, which has lower power consumption than L0s, but takes longer to switch to the L0 state. When the PCIe link needs to be retrained (Re-Training), it will enter the Recovery state. In the Recovery state, Bit Lock and Symbol / Block Lock are reestablished.

[0035] The present invention realizes power consumption control of the ports accurately and efficiently according to the load conditions of the access of the two ports by the active-active storage system in real time, thereby reducing the power consumption of the entire disk, promoting the green, low-carbon and energy-saving development of the cloud computing center, and reducing the operating costs of the enterprise.

[0036] The above description is only the basic principle and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention belong to the protection scope of the present invention.

Claims

1. A PCIe dual-port SSD low power consumption control device, characterized in that: Including load prediction unit, power consumption control unit and clock switching unit: The input of the load prediction unit is the judgment result of the link idle state of port A and / or port B and the margin value of the receiving / transmitting buffer by the PCIe power management module ASPM. The load state of port A and / or port B is calculated according to the input, and the load level value is output. Port A and port B represent the two PCIe ports of the PCIe dual-port SSD. The load state is calculated as follows: when the link does not enter the L0s state within the sampling time interval T and the receiving and sending buffers are more than half full within the sampling time interval T, the load prediction unit determines that the link is in a heavy load state and outputs a load level A; When the number of times the link enters the L0s state within the sampling time interval T reaches the threshold value Y0 and the receiving and sending buffers are below the half-full state within the sampling time interval T, the load prediction unit determines that the link is in a light load state and outputs a load level of level B; when the number of times the link enters the L1 state within the sampling time interval T reaches the threshold value Y1, the load prediction unit determines that the link is in a process of no data transmission and outputs a load level of level C; The input end of the power consumption control unit is connected to the output end of the load prediction unit. The working state of each SSD module is adjusted according to the load level output by the load prediction unit to realize the power consumption control of the SSD. The working state of each SSD module is adjusted as follows: when the load prediction unit outputs level A, each SSD module is controlled to be in a full-load operation state and operate at the maximum supportable frequency. When the load prediction unit outputs level B, each SSD module is controlled to be in a partially reduced-frequency operation state. When the load prediction unit outputs level C, the power consumption core module is controlled to enter a low-power state and standby.

2. The PCIe dual-port SSD low power consumption control device according to claim 1, characterized in that: When the PCIe link power management module ASPM controls the PCIe LTSSM to exit L1 and enter the recovery state, the load prediction unit updates the level to levelA. When the PCIe link power management module ASPM controls the PCIe LTSSM to enter the L0s state from the L0 state, the load prediction unit updates the level to levelB, so that each hardware unit begins to enter the low power consumption control state. When the PCIe link power management module ASPM controls the PCIe LTSSM to enter the L1 state from the L0s state, the load prediction unit updates the level to levelC, so that each hardware unit enters a deep low power consumption control state.

3. The PCIe dual-port SSD low power consumption control device according to claim 1, characterized in that: The three load levels output by the load prediction unit have internal flow characteristics, and the load levels are managed by a logic operation state machine.

4. The PCIe dual-port SSD low power consumption control device according to claim 1, characterized in that: It also includes a clock switching unit, the input end of the clock switching unit is connected to the output end of the power consumption control unit, and is used to receive the frequency control signal output by the power consumption control unit for each SSD module, and switch the clock frequency of each SSD module according to the frequency control signal.

5. The PCIe dual-port SSD low power consumption control device according to claim 4, characterized in that: The frequency control signal for each SSD module output by the power consumption control unit consists of 2 bits. When the load prediction unit outputs Level A, the frequency control signal is the maximum value 11; when the load prediction unit outputs Level B, the frequency control signal outputs the middle value 10; when the load prediction module outputs Level C, the frequency control signal is the second minimum value 01; when the clock needs to be turned off, the frequency control signal is the minimum value 00; Correspondingly, each SSD module has two control signals, which are combined into four frequency division coefficients. The four frequency division coefficients generate four clock frequency gears. Gear 3 represents no frequency reduction, which meets the working scenario requirements of level A loads. Gear 2 represents partial frequency reduction, which meets the working scenario requirements of level B loads. Gear 1 represents deep frequency reduction, which meets the working scenario requirements of level C loads. 0 gear position: the clock is stopped.

6. The PCIe dual-port SSD low power consumption control device according to claim 1, characterized in that: When the load prediction unit outputs Level B or Level C, the power-consuming core modules that enter a low-power state and standby include the NVMe controller, DDR controller, AXI bus, and CPU.

7. A PCIe dual-port SSD low power consumption control method, characterized in that: The following steps are involved: S01, enable the PCIe dual-port SSD in dual-port working mode; S02, initializing the sampling time interval T of the load prediction unit, and initializing the number of times the link working state enters L0s and L1 thresholds Y0 and Y1; S03, PCIe dual-port SSD performs business command processing; S04, the load prediction unit determines the state of the workload of the two ports in real time, and provides a load level indication signal to the power consumption control unit. The load levels include level A, level B and level C, and the calculation method is as follows: when the link does not enter the L0s state within the sampling time interval T and the receiving and sending buffers are in a state of more than half full within the sampling time interval T, the load prediction unit determines that the link is in a heavy load state and outputs the load level level A; When the number of times the link enters the L0s state within the sampling time interval T reaches the threshold value Y0 and the receiving and sending buffers are below the half-full state within the sampling time interval T, the load prediction unit determines that the link is in a light load state and outputs a load level of level B; when the number of times the link enters the L1 state within the sampling time interval T reaches the threshold value Y1, the load prediction unit determines that the link is in a process of no data transmission and outputs a load level of level C; S05. The power consumption control unit uses the load level output by the load prediction unit as input to adjust the working state of each SSD module to realize power consumption control of the SSD. The working state of each SSD module is adjusted as follows: when the load prediction unit outputs level A, each SSD module is controlled to be in a full-load operation state and to operate at the maximum supportable frequency; when the load prediction unit outputs level B, each SSD module is controlled to be in a partially reduced-frequency operation state; when the load prediction unit outputs level C, the power consumption core module is controlled to enter a low-power state and standby.

8. The PCIe dual-port SSD low power consumption control method according to claim 7, characterized in that: Step S04 also includes: when the PCIe link power management module ASPM controls the PCIe LTSSM to exit L1 and enter the recovery state, the load prediction unit updates the level to levelA, so that each module synchronously enters the full-load working state; when the PCIe link power management module ASPM controls the PCIe LTSSM from the L0 state to the L0s state, the load prediction unit updates the level to levelB, so that each hardware unit begins to enter a low power consumption control state; when the PCIe link power management module ASPM controls the PCIe LTSSM from the L0s state to the L1 state, the load prediction unit updates the level to levelC, so that each hardware unit enters a deep low power consumption control state.

9. The PCIe dual-port SSD low power consumption control method according to claim 7, characterized in that: In step S05, the power consumption control unit takes the load level output by the load prediction unit as input, obtains and outputs the frequency control signal of each module of the SSD through calculation, sets a clock switching unit, and the clock switching unit receives the frequency control signal output by the power consumption control unit to control the clock frequency of each module of the SSD; The frequency control signal for each SSD module output by the power consumption control unit consists of 2 bits. When the load prediction unit outputs Level A, the frequency control signal is the maximum value 11. When the load prediction unit outputs Level B, the frequency control signal outputs the middle value 10. When the load prediction module outputs Level C, the frequency control signal is the second minimum value 01. When the clock needs to be turned off, the frequency control signal is the minimum value 00. Correspondingly, each SSD module has 2 control signals, which are combined into 4 frequency division coefficients. The 4 frequency division coefficients produce 4 clock frequency gears. Gear 3 represents the state of no frequency reduction, which meets the working scenario requirements of level A load. Gear 2 represents the state of partial frequency reduction, which meets the working scenario requirements of level B load. Gear 1 represents the state of deep frequency reduction, which meets the working scenario requirements of level C load. Gear 0 represents the clock stop state.

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