A RISC-V platform dynamic CPU scheduling method and system

Abstract

The present invention discloses a RISC-V platform dynamic CPU scheduling method and system, which relates to the technical field of resource allocation and scheduling, including: real-time acquisition of hardware performance events and CPU load of the RISC-V platform; feature selection of the collected hardware performance events to construct a prediction data set; using the prediction data set, training a load prediction model based on reinforcement learning to predict the load value of each CPU; adjusting the active state of the CPU based on the load prediction result of the CPU; and reallocating tasks according to the adjusted CPU state to balance the processor load. The present invention combines hardware performance events and load prediction model design, and proposes a RISC-V platform dynamic CPU scheduling method and system, which fully utilizes the fine-grained performance monitoring capability in the architecture, helps to achieve the best balance between performance and energy consumption, and avoids the problem of excessive or insufficient resource allocation due to lag in traditional methods.

Description

Technical Field

[0001] The present disclosure relates to the technical field of resource allocation and scheduling, and in particular to a RISC-V platform dynamic CPU scheduling method and system. Background Art

[0002] As an open source instruction set architecture, RISC-V has attracted widespread attention from academia and industry for its simplicity, efficiency and scalability. Its modular design allows users to tailor or expand the instruction set according to actual needs, making it outstanding in embedded systems, high-performance computing (HPC) and the Internet of Things (IoT). However, compared with traditional x86 or ARM architectures, the RISC-V ecosystem is still in its development stage, and its software and hardware support and optimization tools are not yet mature, especially in the field of multi-core dynamic scheduling, facing many challenges. For example, in RISC-V multi-core systems, there is a lack of unified core scheduling standards and efficient load management algorithms, resulting in system resource utilization and energy consumption performance failing to reach ideal levels.

[0003] As computing demands increase, the RISC-V architecture gradually evolves towards multi-core and even multi-cluster designs. This architecture makes it possible to improve performance and parallel processing capabilities, but it also brings problems such as load imbalance and waste of core resources. In a multi-core environment, how to dynamically adjust the number of active cores according to the real-time load of the system and optimize resource allocation is an important direction for improving system performance and energy efficiency; especially for the RISC-V platform, the implementation of dynamic core adjustment needs to consider the unique characteristics of the architecture, such as low-power design goals, modular expansion of core configuration, and possible heterogeneity of different cores.

[0004] Most of the current mainstream dynamic core tuning technologies are designed for ARM or x86 architectures, and directly porting them to the RISC-V platform may not be efficient; these methods are mainly based on load monitoring and simple threshold judgment, and do not fully consider the combination of load prediction and fine-grained core tuning. In addition, existing core tuning technologies generally rely on kernel support from the operating system, while the RISC-V ecological tool chain (such as performance monitoring and energy optimization tools) is not yet perfect, and has obvious deficiencies in real-time performance and accuracy. Therefore, the existing RISC-V dynamic core tuning methods have the problem of excessive or insufficient resource allocation, and cannot efficiently predict system load. Summary of the invention

[0005] In order to solve the above problems, the present invention proposes a RISC-V platform dynamic CPU scheduling method and system by combining hardware performance events and load prediction model design, which makes full use of the fine-grained performance monitoring capability in the architecture, helps to achieve the best balance between performance and energy consumption, and avoids the problem of excessive or insufficient resource allocation due to lag in traditional methods.

[0006] According to some embodiments, the present disclosure adopts the following technical solutions:

[0007] A RISC-V platform dynamic CPU scheduling method, comprising:

[0008] Obtain hardware performance events and CPU load collected from the RISC-V platform in real time;

[0009] Based on the correlation with CPU load, feature selection is performed on the collected hardware performance events to build a prediction data set;

[0010] Using the prediction data set, the load prediction model based on reinforcement learning is trained to predict the load value of each CPU;

[0011] Based on the CPU load prediction results, determine whether the conditions for adding or reducing cores are met, adjust the CPU activity status, and optimize resource allocation;

[0012] Based on the adjusted CPU status, tasks are reallocated to balance the processor load.

[0013] According to some embodiments, the present disclosure adopts the following technical solutions:

[0014] A RISC-V platform dynamic CPU scheduling system, comprising:

[0015] The data acquisition module is configured to: acquire hardware performance events and CPU load collected from the RISC-V platform in real time;

[0016] The feature selection module is configured to: select features of the collected hardware performance events according to the correlation with the CPU load, and construct a prediction data set;

[0017] The model training module is configured to: train a load prediction model based on reinforcement learning using the prediction data set to predict the load value of each CPU;

[0018] The state adjustment module is configured to: determine whether the conditions for increasing or reducing the number of cores are met based on the CPU load prediction result, adjust the CPU activity state, and optimize resource allocation;

[0019] The task allocation module is configured to: reallocate tasks and balance processor loads according to the adjusted CPU state.

[0020] According to some embodiments, the present disclosure adopts the following technical solutions:

[0021] A computer program product includes a computer program, and when the computer program is executed by a processor, the computer program implements the RISC-V platform dynamic CPU scheduling method.

[0022] According to some embodiments, the present disclosure adopts the following technical solutions:

[0023] A non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium is used to store computer instructions, and when the computer instructions are executed by a processor, a RISC-V platform dynamic CPU scheduling method is implemented.

[0024] According to some embodiments, the present disclosure adopts the following technical solutions:

[0025] An electronic device comprises: a processor, a memory and a computer program; wherein the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device is running, the processor executes the computer program stored in the memory, so that the electronic device executes the RISC-V platform dynamic CPU scheduling method.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] 1. The present invention realizes efficient data collection and reduces the extra occupation of system resources through a lightweight hardware performance event statistics method.

[0028] 2. The load prediction of the present invention is based on reinforcement learning, which captures the complex nonlinear relationship between hardware performance events and load, effectively improves the prediction accuracy, and thus provides a reliable basis for dynamic core adjustment.

[0029] 3. The present invention combines the results of the prediction model to dynamically adjust the processor core state, and through fine-grained core increase or reduction strategies, significantly improves resource utilization efficiency, reduces power consumption, and improves system performance.

[0030] 4. The present invention is optimized based on the characteristics of the RISC-V architecture, is applicable to different hardware implementations and workloads, and can be expanded to multi-core or multi-Cluster architectures to further unleash the potential of the RISC-V platform. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings constituting a part of the present disclosure are used to provide a further understanding of the present disclosure. The illustrative embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation on the present disclosure.

[0032] Figure 1 This is a flow chart of a RISC-V platform dynamic CPU scheduling method according to Example 1.

[0033] Figure 2 This is a flowchart of lightweight perf statistics of hardware performance events in Example 1.

[0034] Figure 3This is the overall architecture diagram of Example 1. DETAILED DESCRIPTION

[0035] The present disclosure is further described below in conjunction with the accompanying drawings and embodiments.

[0036] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present disclosure. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present disclosure belongs.

[0037] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0038] Example 1

[0039] In one embodiment of the present disclosure, a RISC-V platform dynamic CPU scheduling method is provided, including:

[0040] Step 1: Obtain hardware performance events and CPU load collected from the RISC-V platform in real time;

[0041] Step 2: Based on the correlation with the CPU load, feature selection is performed on the collected hardware performance events to build a prediction data set;

[0042] Step 3: Use the prediction data set to train the load prediction model based on reinforcement learning to predict the load value of each CPU;

[0043] Step 4: Based on the CPU load prediction results, determine whether the conditions for adding or reducing cores are met, adjust the CPU activity status, and optimize resource allocation;

[0044] Step 5: Redistribute tasks and balance processor loads based on the adjusted CPU status.

[0045] As an embodiment, in combination with hardware performance events and load prediction model design, a RISC-V platform dynamic CPU scheduling method disclosed in the present invention fully utilizes the fine-grained performance monitoring capability in the architecture, helps to achieve the best balance between performance and energy consumption, and avoids the problem of excessive or insufficient resource allocation caused by lag in traditional methods, such as Figure 1 The specific implementation process is as follows:

[0046] S11: Use the perf tool to collect hardware performance events and CPU load data.

[0047] The process of collecting hardware performance events and CPU load data using the perf tool includes recording the hardware performance event values ​​and the corresponding CPU utilization within the sampling period. Perf obtains the data in the PMU unit hardware performance event counter through system calls. The PMU unit of the RISC-V platform is a module for recording and monitoring hardware performance events. The RISC-V architecture supports monitoring specific hardware events through custom extensions.

[0048] In this embodiment, the RISC-V platform can record 14 types of hardware performance events, including: cpu-cycles (total number of CPU cycles), instructions (number of executed instructions), indirect-branch-instructions (number of indirect branch instructions), branch-misses (number of branch prediction errors), branches (number of branch predictions), cache-references (number of cache accesses), cache-misses (number of cache misses), store-instructions (number of storage instruction executions), tlb-misses (number of address translation cache misses), rf-launch-fail (number of register file launch failures), rf-instructions (number of register file instruction executions), lsu-spec-fail (number of load storage unit speculation failures), lsu-other-stall (number of other load storage unit stalls) and lsu-sq-discard (number of load storage unit storage queue discards), and calculate the CPU utilization by reading the / proc / stat file as a representation of the CPU load.

[0049] Specifically, in order to improve the real-time performance and collection efficiency of performance event data, this embodiment sets the sampling period to 100ms, and uses the sys_perf_event_open interface to create a performance monitoring unit. The hardware performance event value is read and cleared within the sampling period through the read() function, and the CPU utilization within the sampling period is calculated to ensure accurate data collection with low system overhead.

[0050] For further information, see Figure 2 As shown, in this embodiment, a lightweight hardware performance event statistics method is adopted, specifically:

[0051] (1) Create and configure the PMU to monitor the required hardware events, including selecting the event type to monitor, binding hardware performance events, setting the target process number and CPU number to monitor, and choosing to monitor user mode or kernel mode events.

[0052] (2) Create a perf performance event file descriptor through the system call perf_event_open().

[0053] (3) The performance monitoring PMU is started and counting is started through the ioctl() function. During the sampling process, the count value of the PMU is continuously read by cyclically calling the read() function, and is cleared after reading to ensure the accuracy and real-time performance of the statistical data. The 100ms sampling period set in this embodiment not only ensures the real-time performance of data collection, but also significantly reduces the resource overhead of the processor for collection.

[0054] (4) Release the software and hardware resources of the PMU and complete the entire performance event statistics process.

[0055] While collecting performance event statistics, this embodiment also collects CPU load data to evaluate system busyness and operating load status. To this end, read the data in the / proc / stat file and calculate the CPU utilization using the following formula:

[0056]

[0057] in, is the time the CPU is in user mode, is the time the CPU is in system state, The time the CPU is in idle state.

[0058] S12: Perform feature selection on the collected data, select hardware performance events that are strongly related to the CPU load, and standardize the selected features to build a prediction data set.

[0059] Furthermore, feature selection is based on the Pearson correlation coefficient, analyzing the correlation between the feature and the CPU load, and performing feature screening according to a preset correlation threshold, for example, screening feature quantities whose correlation coefficient is greater than a set threshold (such as 0.7).

[0060] The selected features are standardized to eliminate dimensional differences and ensure the uniformity of the data and the training effect of the model.

[0061] Specifically, in this embodiment, the RISC-V platform is usually configured with 32 hardware PMU event counters, including basic counters mcycle (counting CPU cycles) and minstret (counting completed instructions), and extended event counters mhpmcounter3 to mhpmcounter31, and corresponding hardware performance events can be configured for each counter. However, not all monitoring data of hardware performance events contribute significantly to the CPU load prediction model, so these events need to be screened to determine the most relevant input features.

[0062] This embodiment uses Pearson correlation analysis to select hardware performance events with high correlation with CPU load. The Pearson correlation coefficient is calculated as follows:

[0063]

[0064] Among them, x and y are two variables to be calculated, each with n samples. and represents the i-th sample of two variables, and Represents the mean of the sample.

[0065] By setting a correlation threshold (such as an absolute value greater than 0.7), performance events with a high correlation with the CPU load are screened out as input features of the model.

[0066] Finally, four hardware performance events with a strong correlation with CPU load were selected as key features, namely cpu-cycles (total number of CPU cycles), instructions (number of executed instructions), branches (number of branch predictions), and cache-references (number of cache accesses). These hardware events can accurately reflect the operating status of the CPU and effectively support the training and inference of the load prediction model. This not only significantly reduces the complexity of data processing, but also improves the efficiency and accuracy of the prediction model.

[0067] The embodiment of the present application randomly executes the application program in the Unix bench benchmark program to collect data such as load-related input parameters and output labels, thereby constructing an original data set. Since data of different features have different dimensions and units, this difference may have an adverse effect on the data analysis results. In order to eliminate the interference caused by dimensional differences and improve the comparability between features, the collected original data set is standardized to meet the needs of comprehensive comparative evaluation.

[0068] In the data standardization process, this embodiment uses the Min-Max normalization method to scale each feature data to a given range to make it more consistent with the numerical distribution characteristics of the actual load scenario. The Min-Max normalization calculation is as follows:

[0069]

[0070] Among them, a is the minimum value of the range to be scaled, which is 0 here; b is the maximum value of the range to be scaled, which is 1 here; is the maximum value in each dimension. is the maximum value of each dimension of data, is the original data before normalization, is the result of data normalization.

[0071] Considering that the output label of load prediction is usually expressed as a percentage (%), and its value ranges from 0 to 100, in order to simplify analysis and facilitate observation, this embodiment scales the original data of each dimension to the range of [0, 1]. This normalization process maintains the relative relationship between the feature data.

[0072] After the above operations, the original data set is converted into a prediction data set, providing more stable data input for the efficient training of subsequent models.

[0073] S13: A load prediction model is proposed using the reinforcement learning Q-learning method. The model input is the state characteristics of hardware performance events, and the output is the predicted CPU load value. The model gradually updates the Q value by training historical sampling data, optimizes the load prediction strategy, and uses a validation data set to evaluate the model accuracy.

[0074] The Q-learning load forecasting model construction process includes:

[0075] The hardware performance event values ​​(such as the total number of CPU cycles, the number of executed instructions, the number of branch predictions, and the number of cache accesses) are used as state variables, and the action space is defined as the predicted values ​​of different load intervals to describe the dynamic change characteristics of the load.

[0076] Based on the reinforcement learning algorithm, the state transfer is simulated through the collected prediction data set, and the reward function is used to iterate the accuracy of the load prediction. The Q value of the state-action pair is updated to optimize the load prediction decision. That is, during the training process, the reward value is calculated through the sampled data, and the Q value table is gradually updated according to the state, action and reward to optimize the load prediction strategy.

[0077] The trained model is tested using an independent data set, the error between the predicted load value and the actual load value is compared, and its prediction accuracy and convergence speed under different load conditions are evaluated to ensure that the model can adapt to the dynamic load environment and is stable.

[0078] Specifically, in this embodiment, a Q-learning load prediction method based on reinforcement learning is adopted. Through the decision-making ability of reinforcement learning, the load is divided into three categories: low load, medium load and high load, thereby providing a basis for subsequent dynamic core adjustment.

[0079] First, a reinforcement learning environment is established, with hardware performance events and CPU load as state inputs; hardware performance events include instruction execution count, cache hit rate, and branch prediction hit rate, etc. CPU load is classified according to the collected sample data and defined as three load states: low load (<10%), medium load (10%-95%), and high load (>95%). In this environment, the state space consists of hardware performance events and load classifications, and the action space includes three types of predicted actions: predicted as low load, predicted as medium load, and predicted as high load.

[0080] Secondly, the reward mechanism of the Q-learning algorithm is designed; the accuracy of the load prediction determines the size of the reward value. If the prediction result is consistent with the actual load state, a positive reward is given; if the prediction deviates from the actual load state, a negative reward is given. The reward mechanism is expressed by the formula Definition, where To predict the load status, is the actual load state. The smaller the deviation, the higher the reward value.

[0081] Then, the reinforcement learning training method is used to update the Q table by continuously interacting with the environment. The state-action value of the Q table is iteratively updated by the following formula: ;in, is the value of executing action a in the current state s, r is the reward value, s' is the next state, is the learning rate, is the discount factor; in each round of training, the reinforcement learning model selects actions in a way that combines exploration and exploitation, and finally learns the optimal load forecasting strategy.

[0082] Finally, the trained Q-learning model is used to predict the current load state based on the input hardware performance events at the current moment. The output of the model is one of three load states: low load, medium load, or high load. Experimental results show that the reinforcement learning method can capture the dynamic changes of load states, and the prediction accuracy is higher than that of the traditional logistic regression model, especially in complex load scenarios. It has better adaptability.

[0083] This embodiment uses the Q-learning method in reinforcement learning instead of the traditional logistic regression model, avoiding the problem of difficulty in capturing nonlinear feature relationships. At the same time, compared with deep learning algorithms, it has the advantages of low computational overhead and high reliability, significantly improving the accuracy and adaptability of load prediction, and providing more efficient and controllable decision support for subsequent dynamic core adjustment.

[0084] S14: Based on the output value of the reinforcement learning load prediction model, determine whether the predicted load of each processor core (i.e., CPU) meets the conditions for increasing or reducing cores; when the predicted load exceeds a preset core increase threshold, increase the number of active cores of the processor; when the predicted load is lower than a preset core reduction threshold, reduce the number of active cores to save energy consumption.

[0085] Furthermore, the dynamic core adjustment judgment conditions include: when the predicted load of a single core is higher than the set core increase threshold (such as 95%), the core increase operation is triggered, and an active core is added to cope with the high load; when the predicted load of a single core is lower than the set core reduction threshold (such as 10%), the core reduction operation is triggered, and an active core is shut down to save energy; when the predicted load of a single core is between the set threshold range (such as 10%-95%), the current number of cores remains unchanged.

[0086] Specifically, see Figure 3 As shown, this embodiment provides a hierarchical dynamic adjustment method based on Cluster, including multiple steps:

[0087] First, the number of working cores currently required is determined based on the global load. Then, the local load of each CPU core is obtained based on the load prediction model to determine the cores to be turned on or off. Finally, the relevant cores are turned on or off accordingly.

[0088] Dynamic core adjustment technology is an optimization method designed specifically for multi-core processors, which aims to dynamically adjust the number of active CPU cores according to the system operation status. When the system load is low, the clock and power of some CPU cores can be turned off to further reduce energy consumption; when the load increases, the CPU cores that were previously disabled can be re-enabled to improve overall computing performance.

[0089] The design and implementation of the dynamic core scheduling module usually consists of two parts: one is the CPU core management mechanism based on hot plugging, and the other is the dynamic strategy optimization method for scheduling the CPU.

[0090] The hot-swap-based CPU core management mechanism is used to implement the CPU hot-swap function. Four CPU core states are defined in the kernel layer, namely possible, present, online, and active. Specifically, possible refers to the set of CPU cores that may exist in the system. This state is defined when the system boots and indicates the maximum possible number of cores supported by the hardware. The core in this state is not necessarily physically connected or enabled; present refers to the set of CPU cores actually connected to the current system. These cores have been detected by the hardware and may be activated for computing. online means that the current core has been enabled and participates in task scheduling. In this state, the core can run tasks normally and respond to the allocation of the scheduler. active means that the core is not only online, but also participates in load balancing and actual work. The core in this state undertakes computing tasks and is the key to determining whether the core actually performs work during dynamic core adjustment. The CPU hot-swap state is introduced in Linux to refine the management of the switching of the CPU state from the present state to the online state. The CPU hot-plug mechanism defines the CPU hot-plug state through the cpuhp_state enumeration, and binds the callback function that needs to be executed when the CPU is started or shut down for each state in the cpuhp_hp_states array. During the CPU startup process, the startup callback functions bound to all states before this state will be executed in sequence, and the corresponding shutdown callback function will be executed when the CPU is shut down. The RISC-V architecture realizes the dynamic activation or shutdown of the CPU through the joint management of the core state and system control.

[0091] In one example, the RISC-V system completely shuts down static power consumption by shutting down the core power supply, which specifically includes the following steps: before the core is shut down, the core first notifies the SoC that it will perform a power-down operation, shields all interrupt requests, including external interrupts, soft interrupts, and timer interrupts, and at the same time turns off the relevant interrupt enable bits (such as MSTATUS, SSTATUS, etc.) according to the running state. Then, the data prefetch function is turned off, and the data cache (D-Cache) is cleared. The dirty lines are written back to the L2Cache through D-Cache INV&CLR ALL, and then the D-Cache is turned off to ensure that no new storage operations occur after the cache is cleared. The core turns off the SMPEN bit, shields the snoop request to the core, and enters the low power mode (WFI) after executing the synchronization instruction (fence iorw). After the system detects the low power signal, it shields the debug request of the core to be powered off, pulls down the core reset signal, activates the signal clamp and cuts off the core power supply to achieve a complete core shutdown. The core can be restarted only by the reset signal in the power-off state.

[0092] In one example, when the RISC-V system detects that a specific event needs to wake up the core, the following core opening steps are performed: the system sets the reset address of the awakened core, pulls down the core reset signal and turns on the power, while keeping the reset signal from being released to complete the initial power supply initialization. Then, the core output signal clamp and reset signal are released to recover the core from the reset state and execute the initialization program, including enabling the SMPEN bit to allow snoop requests, initializing the memory management unit (MMU) and enabling the data cache (D-Cache) and other necessary operations, so that the core enters the normal operating state and completes the wake-up and resource reallocation.

[0093] The dynamic strategy optimization method for scheduling CPU is to determine the number of CPU cores required to run the current program and the cores to be turned on or off based on the global load and local load (the load of each core). Assuming the current global load is L, the current number of cores is C, the increase threshold is U, and the decrease threshold is D, the current number of cores required can be determined based on the increase core condition L>(C-1)+U and the decrease core condition L<(C-1)-D.

[0094] In a specific embodiment, a RISC-V platform includes 64 cores, and every four cores form a Cluster. In order to achieve dynamic core adjustment, the method of the present invention first determines the required number of active cores based on the global load, and derives the required number of Clusters. Different from directly using the Cluster as the scheduling unit, the present method prioritizes load adjustment between single-core and dual-core, and gradually expands to the Cluster level, thereby achieving more fine-grained dynamic core adjustment.

[0095] During the adjustment process, the global load level is defined as ranging from 0 to 6400% (64 cores, with a maximum load of 100% per core). Taking the change between single-core and dual-core as an example, when the number of active cores is 1, if the global load rises and exceeds 95% of the single-core capacity (i.e., 95%), the core increase operation will be triggered, and the number of active cores will increase from 1 to 2; on the contrary, when the number of active cores is 2, if the global load drops and is lower than 90% of the dual-core capacity (i.e., 90%), the core reduction operation will be triggered, and the number of active cores will decrease from 2 to 1. When the global load level is between 90% and 95% (i.e., the buffer zone), core increase or core reduction is not triggered to avoid performance fluctuations caused by frequent adjustments. At the same time, in order to further stabilize the system behavior, the core reduction operation is only actually performed when the global load is lower than the core reduction threshold for three consecutive sampling periods, thereby strengthening the core reduction condition.

[0096] After determining the required number of cores, the number of cores is further mapped to the number of Clusters. For example, when the required number of cores reaches the upper limit of the Cluster capacity (such as four cores), a complete Cluster will be activated; and when the number of cores needs to be expanded to five, the second Cluster needs to be activated to meet the load requirements. In the adjustment process between Clusters, the present invention adopts a judgment strategy based on global load as the main and local load as the auxiliary, and gives priority to opening Clusters with lower loads to reduce energy consumption; when shutting down Clusters, the Cluster with the lowest load is shut down first, and the Cluster with higher load is retained to ensure performance.

[0097] Furthermore, the embodiments of the present application consider the core adjustment within the Cluster to achieve more fine-grained dynamic core adjustment. When a Cluster is activated, the core with the lowest load is preferentially selected to be turned on to reduce power consumption; and when a Cluster needs to be shut down, the core with higher load is preferentially selected to be retained, and the core with the lowest load is shut down, so as to achieve a balance between power consumption and performance. For example, when a Cluster switches from a four-core state to a two-core state, the two cores with the highest load will be selected to maintain stable performance, while the remaining two cores will be shut down to save energy.

[0098] As can be seen from the above, the embodiment of the present application first determines the required number of cores based on the global load, then derives the required number of clusters, and combines the local load optimization strategy between clusters and within clusters to achieve hierarchical dynamic adjustment from core to cluster. The design of the buffer zone and the enhanced core reduction condition effectively reduces the probability of frequent adjustment, further balances system performance and energy consumption, and makes the method of the present invention applicable to RISC-V platforms with multi-core cluster architectures.

[0099] S15: According to the core number adjustment result, tasks are reallocated to balance processor load and optimize resource utilization; in the process of task migration, the operating system scheduling algorithm is used to ensure system stability and real-time task scheduling.

[0100] The task migration strategy includes: reallocating tasks according to the results of dynamic core adjustment to ensure core load balance and system performance stability. During the migration process, the communication overhead between cores in a multi-core or multi-cluster architecture is considered, a low-overhead task scheduling algorithm is used, and task allocation is optimized to reduce latency and avoid excessive impact on the tasks being executed.

[0101] In summary, this embodiment proposes a load prediction and dynamic core adjustment method based on reinforcement learning, which is suitable for the multi-core and multi-Cluster architecture of the RISC-V platform. First, the Q-learning algorithm in reinforcement learning is used to build a load prediction model. By capturing the dynamic relationship between hardware performance events and load states, the CPU load is accurately divided into three categories: low load, medium load and high load, providing high-precision prediction support for dynamic core adjustment; secondly, based on the global load and local load information of each core, a hierarchical dynamic core adjustment algorithm is designed. The algorithm determines the number of active cores currently required by the system through the global load, and adjusts the opening and closing of specific cores in fine granularity in combination with local load information, while realizing load balancing and energy consumption optimization at the Cluster level; finally, the dynamic activation and shutdown operations of the core are completed through the hot-swap mechanism of the operating system and the user interface, and the stability of the system and the real-time scheduling are ensured during the task migration process. This method effectively improves the resource utilization efficiency of the RISC-V platform, significantly optimizes the system performance and energy consumption balance, and is suitable for a variety of complex workload scenarios.

[0102] Through the above method, this embodiment can realize dynamic core adjustment of the RISC-V platform based on hardware performance events and CPU load prediction values, optimize the resource utilization of multi-core processors, and reduce system energy consumption, which is suitable for a variety of high-performance computing scenarios. Load prediction provides a more intelligent decision-making basis for dynamic core adjustment. By accurately predicting future loads, the problem of excessive or insufficient resource allocation caused by lag in traditional methods can be avoided. On the RISC-V platform, load prediction based on hardware performance events has significant advantages, which can make full use of the fine-grained performance monitoring capabilities in the architecture to provide guarantees for achieving high precision and low latency in dynamic core adjustment. The dynamic core adjustment method combined with load prediction helps to achieve the best balance between performance and energy consumption, and further tap the potential of the RISC-V architecture.

[0103] In summary, the openness and multi-core design of the RISC-V architecture provide new opportunities for system optimization, but also put forward higher requirements for load prediction and dynamic core adjustment technology. It is urgent to combine hardware performance events and load prediction models to design an efficient dynamic core adjustment method suitable for the RISC-V platform in order to give full play to its performance and energy efficiency advantages.

[0104] Example 2

[0105] In one embodiment of the present disclosure, a RISC-V platform dynamic CPU scheduling system is provided, including:

[0106] The data acquisition module is configured to: acquire hardware performance events and CPU load collected from the RISC-V platform in real time;

[0107] The feature selection module is configured to: select features of the collected hardware performance events according to the correlation with the CPU load, and construct a prediction data set;

[0108] The model training module is configured to: train a load prediction model based on reinforcement learning using the prediction data set to predict the load value of each CPU;

[0109] The state adjustment module is configured to: determine whether the conditions for increasing or reducing the number of cores are met based on the CPU load prediction result, adjust the CPU activity state, and optimize resource allocation;

[0110] The task allocation module is configured to: reallocate tasks and balance processor loads according to the adjusted CPU state.

[0111] Example 3

[0112] In one embodiment of the present disclosure, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the computer program implements the RISC-V platform dynamic CPU scheduling method.

[0113] Example 4

[0114] In one embodiment of the present disclosure, a non-transitory computer-readable storage medium is provided, wherein the non-transitory computer-readable storage medium is used to store computer instructions, and when the computer instructions are executed by a processor, the RISC-V platform dynamic CPU scheduling method is implemented.

[0115] Example 5

[0116] In one embodiment of the present disclosure, an electronic device is provided, including: a processor, a memory, and a computer program; wherein the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device is running, the processor executes the computer program stored in the memory, so that the electronic device executes and implements the RISC-V platform dynamic CPU scheduling method.

[0117] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1A device that provides the functions specified in a block or multiple blocks.

[0118] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0119] Although the above describes the specific implementation methods of the present disclosure in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present disclosure. Technical personnel in the relevant field should understand that on the basis of the technical solution of the present disclosure, various modifications or variations that can be made by those skilled in the art without creative work are still within the scope of protection of the present disclosure.

Claims

1. A RISC-V platform dynamic CPU scheduling method, characterized in that: include: Obtain hardware performance events and CPU load collected from the RISC-V platform in real time; According to the correlation with the CPU load, feature selection is performed on the collected hardware performance events to construct a prediction data set; the feature selection of the collected hardware performance events is based on the Pearson correlation coefficient, the correlation between the feature and the CPU load is analyzed, and the feature is screened according to a preset correlation threshold to form a prediction data set with the CPU load; The load prediction model based on reinforcement learning is trained by using the prediction data set to predict the load value of each CPU; the load prediction model based on reinforcement learning is constructed by using the Q-learning algorithm, which takes the hardware performance event as the state variable and defines the action space as the prediction value of different load intervals to describe the dynamic change characteristics of the load; based on the reinforcement learning algorithm, the state transition is simulated by using the prediction data set, the load prediction is iterated by using the reward function, the Q value of the state-action pair is updated, the load prediction decision is optimized, and the final load prediction model is obtained; Based on the CPU load prediction results, determine whether the conditions for adding or reducing cores are met, adjust the CPU activity status, and optimize resource allocation; use a cluster-based hierarchical dynamic adjustment method to adjust the CPU activity status, specifically: determine the required number of active CPUs based on the global load, and derive the required number of clusters; combine the local load optimization strategies between clusters and within the cluster to achieve hierarchical dynamic adjustment from core to cluster; Based on the adjusted CPU status, tasks are reallocated to balance the processor load.

2. A RISC-V platform dynamic CPU scheduling method as claimed in claim 1, characterized in that: The hardware performance events and CPU load are collected by using the perf tool. The hardware performance events include, but are not limited to, the following features: total number of CPU cycles, number of instructions executed, number of indirect branch instructions, number of branch prediction errors, number of branch predictions, number of cache accesses, number of cache misses, number of store instruction executions, number of address translation cache misses, number of register file launch failures, number of register file instruction executions, number of load-store unit speculation failures, number of load-store unit other pauses, and number of load-store unit store queue discards; The CPU load includes but is not limited to CPU utilization.

3. A RISC-V platform dynamic CPU scheduling method as claimed in claim 1, characterized in that: The adjustment of the CPU active state is specifically as follows: When the predicted load of a single CPU is higher than the preset core increase threshold, the core increase operation is triggered, and an active CPU is added to cope with the high load; when the predicted load of a single CPU is lower than the preset core reduction threshold, the core reduction operation is triggered, and an active CPU is shut down to save energy; when the predicted load of a single CPU is between the preset threshold range, the current number of CPUs remains unchanged.

4. A RISC-V platform dynamic CPU scheduling system, characterized in that: include: The data acquisition module is configured to: acquire hardware performance events and CPU load collected from the RISC-V platform in real time; The feature selection module is configured to: perform feature selection on the collected hardware performance events according to the correlation with the CPU load, and construct a prediction data set; the feature selection on the collected hardware performance events is based on the Pearson correlation coefficient, analyzes the correlation between the features and the CPU load, and performs feature screening according to a preset correlation threshold to form a prediction data set with the CPU load; The model training module is configured to: train a load prediction model based on reinforcement learning using a prediction data set to predict the load value of each CPU; the load prediction model based on reinforcement learning is constructed using a Q-learning algorithm, which takes hardware performance events as state variables and defines an action space as predicted values ​​of different load intervals to describe the dynamic change characteristics of the load; based on the reinforcement learning algorithm, simulate state transfer through a prediction data set, use a reward function to iterate the load prediction, update the Q value of the state-action pair, optimize the load prediction decision, and obtain the final load prediction model; The state adjustment module is configured to: determine whether the conditions for adding or reducing cores are met based on the CPU load prediction results, adjust the CPU activity state, and optimize resource allocation; use a cluster-based hierarchical dynamic adjustment method to adjust the CPU activity state, specifically: determine the required number of active CPUs based on the global load, and derive the required number of clusters; combine the local load optimization strategies between clusters and within the cluster to achieve hierarchical dynamic adjustment from core to cluster; The task allocation module is configured to: reallocate tasks and balance processor loads according to the adjusted CPU state.

5. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, a RISC-V platform dynamic CPU scheduling method as described in any one of claims 1 to 3 is implemented.

6. A non-transitory computer-readable storage medium, characterized in that: The non-transitory computer-readable storage medium is used to store computer instructions. When the computer instructions are executed by the processor, a RISC-V platform dynamic CPU scheduling method as described in any one of claims 1 to 3 is implemented.

7. An electronic device, characterized in that: include: A processor, a memory and a computer program; wherein the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device is running, the processor executes the computer program stored in the memory so that the electronic device executes a RISC-V platform dynamic CPU scheduling method as described in any one of claims 1 to 3.

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