Data transmission verification method, device and equipment based on I3C bus and medium

Abstract

The invention provides a data transmission verification method, device and equipment based on an I3C bus and a medium, and relates to the technical field of data verification, the method is applied to a host, the host is connected with a slave through the I3C bus, and the method comprises the steps that when the numerical value of a host verification enabling register corresponding to the host meets a first preset condition, the host verification enabling register is connected with the slave through the I3C bus; determining a first check code corresponding to the write transmission data based on the write transmission data; sending the first check code and the write transmission data to a slave, wherein the slave is used for determining a first check result corresponding to the write transmission data based on the first check code and the write transmission data; or sending the read transmission data to the slave; receiving a third check code sent by the slave, and determining a fourth check code corresponding to the read transmission data based on the read transmission data; the third check code is determined by the slave based on read transmission data; and determining a second check result corresponding to the read transmission data based on the third check code and the fourth check code. According to the invention, the data on the I3C bus can be detected more accurately.

Description

Technical Field

[0001] The present invention relates to the technical field of data verification, and in particular to a data transmission verification method, device, equipment and medium based on an I3C bus. Background Art

[0002] With the development of society and the improvement of science and technology, more and more sensor-related products are appearing in people's vision. Due to the lack of a unified physical sensor interface, chip designers need to choose from a variety of interface protocols such as I2C (Inter-Integrated Circuit, an interface protocol specification), SPI (an interface protocol specification) or UART (an interface protocol specification). However, with the increase in the number of sensors, the number of GPIO (General-purpose input / output) pins will increase and more packaging layers will be generated, which will increase the cost. Therefore, the limitations of the above interface protocols are becoming more and more serious. Based on the above reasons, the Mobile Industry Processor Interface (MIPI) Alliance proposed the I3C (Improved Inter Integrated Circuit) interface protocol. The I3C interface protocol is a new protocol standard. The advantages of the I3C interface protocol are lower energy consumption, faster data transmission rate, higher scalability, and the number of GPIO pins is reduced as much as possible. It is also backward compatible with the traditional I2C interface protocol. Due to the advantages of the above I3C interface protocol, more and more integrated circuit chips use the I3C interface protocol to implement circuit design.

[0003] According to the I3C interface protocol proposed by the MIPI Alliance, in the data transmission process corresponding to the I3C interface protocol, each byte will be followed by a transition bit (hereinafter referred to as the T bit), and the meaning of the T bit in write transmission and read transmission is different. For write transmission, the T bit is a parity bit; for read transmission, the T bit is a conversion bit, that is, when the data transmission is not completed, the T bit is 1, and when the data transmission is completed, the T bit is 0.

[0004] The current problem is that when data is transmitted on the I3C bus, environmental factors such as noise interference may cause bus data errors. Furthermore, for write transmission, if the data is wrong during the transmission process, the parity check method specified in the I3C interface protocol will not be able to detect it; and for read transmission, since there is no parity check, when the data transmitted on the bus is wrong, it is difficult to identify the erroneous data.

[0005] Based on the above situation, a data transmission verification method based on I3C bus is urgently needed. Summary of the invention

[0006] The present invention provides a data transmission verification method, device, equipment and medium based on an I3C bus, which are used to solve the defect in the prior art that when the data transmitted on the bus is erroneous, it is difficult to identify the erroneous data. The present invention can perform more accurate detection on the data on the I3C bus, and enhance the anti-interference ability and transmission stability of data transmission.

[0007] The present invention provides a data transmission verification method based on an I3C bus, which is applied to a host, wherein the host is connected to a slave via the I3C bus, and comprises the following steps.

[0008] In the case where the value of the host check enable register corresponding to the host satisfies the first preset condition, determining a first check code corresponding to the write transfer data based on the write transfer data; sending the first check code and the write transfer data to the slave, and the slave is used to determine a first check result corresponding to the write transfer data based on the first check code and the write transfer data; or,

[0009] When the value of the host check enable register corresponding to the host satisfies the first preset condition, the read transmission data is sent to the slave; the third check code sent by the slave is received, and the fourth check code corresponding to the read transmission data is determined based on the read transmission data; the third check code is determined by the slave based on the read transmission data; and the second check result corresponding to the read transmission data is determined based on the third check code and the fourth check code.

[0010] According to a data transmission verification method based on an I3C bus provided by the present invention, the first verification code corresponding to the write transmission data is determined based on the write transmission data, comprising: A CRC-8 algorithm is used to perform cyclic calculation on the write transmission data to obtain a first check code corresponding to the write transmission data.

[0011] According to a data transmission verification method based on an I3C bus provided by the present invention, the CRC-8 algorithm is used to perform cyclic calculation on the write transmission data to obtain a first verification code corresponding to the write transmission data, including: XOR the first byte in the write transmission data with the initial CRC value to obtain a first XOR value; Determine the sub-check code corresponding to the first byte according to the first value of the first XOR value; Traverse all bytes in the write transmission data, use the sub-check code corresponding to the previous byte in the write transmission data as a new initial CRC value, determine the sub-check code corresponding to the current byte; determine the sub-check code corresponding to the last byte in the write transmission data as the first check code.

[0012] According to a data transmission verification method based on an I3C bus provided by the present invention, the sub-verification code corresponding to the first byte is determined according to the first value of the first XOR value, including: S1. When the first digit of the first XOR value is 1, shift the first digit to the left by one bit to obtain a first shift value; XOR the first shift value with the preset binary number to obtain a second XOR value; when the first digit of the first XOR value is 0, shift the first digit to the left by one bit to obtain a second shift value; S2. Repeat steps S1 to S2 using the second XOR value or the second shift value as a new first XOR value until the number of executions of step S1 meets a preset number of times, and determine the second XOR value or the second shift value obtained when step S1 is executed for the last time as the sub-check code corresponding to the first byte.

[0013] According to a data transmission verification method based on an I3C bus provided by the present invention, the second verification result corresponding to the read transmission data is determined based on the third verification code and the fourth verification code, including: In a case where the third check code is the same as the fourth check code, determining that the second check result is that the read transmission data is correct; In a case where the third check code is different from the fourth check code, it is determined that the second check result is a read transmission data error.

[0014] The present invention provides a data transmission verification method based on an I3C bus, which is applied to a slave machine, wherein the slave machine is connected to a host machine via the I3C bus, and comprises the following steps.

[0015] Receive a first check code and write transfer data sent by the host; determine a second check code corresponding to the write transfer data based on the write transfer data when the value of the slave check enable register corresponding to the slave satisfies a first preset condition; determine a first check result corresponding to the write transfer data based on the first check code and the second check code; Receive the read transmission data sent by the host; when the value of the slave check enable register corresponding to the slave satisfies the first preset condition, determine the third check code corresponding to the read transmission data based on the read transmission data, and send the third check code to the host, and the host is used to determine the second check result corresponding to the read transmission data based on the third check code.

[0016] The present invention also provides a data transmission verification device based on an I3C bus, which is applied to a host, wherein the host is connected to a slave via the I3C bus, and comprises the following modules: A host write transfer module, configured to determine a first check code corresponding to the write transfer data based on the write transfer data when the value of the host check enable register corresponding to the host satisfies a first preset condition; send the first check code and the write transfer data to the slave, and the slave is configured to determine a first check result corresponding to the write transfer data based on the first check code and the write transfer data; or,

[0017] A host read transmission module, used for sending read transmission data to the slave when the value of the host check enable register corresponding to the host meets the first preset condition; receiving a third check code sent by the slave, and determining a fourth check code corresponding to the read transmission data based on the read transmission data; the third check code is determined by the slave based on the read transmission data; and determining a second check result corresponding to the read transmission data based on the third check code and the fourth check code.

[0018] The present invention also provides a data transmission verification device based on an I3C bus, which is applied to a slave, wherein the slave is connected to a host via an I3C bus, and comprises the following modules: A slave write transmission module, configured to receive a first check code and write transmission data sent by the host; determine a second check code corresponding to the write transmission data based on the write transmission data when a value of a slave check enable register corresponding to the slave satisfies a first preset condition; and determine a first check result corresponding to the write transmission data based on the first check code and the second check code; A slave read transmission module is used to receive the read transmission data sent by the host; when the value of the slave check enable register corresponding to the slave satisfies the first preset condition, a third check code corresponding to the read transmission data is determined based on the read transmission data, and the third check code is sent to the host, and the host is used to determine a second check result corresponding to the read transmission data based on the third check code.

[0019] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the data transmission verification method based on the I3C bus as described above is implemented.

[0020] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the data transmission verification method based on the I3C bus as described above is implemented.

[0021] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned data transmission verification methods based on the I3C bus.

[0022] The data transmission verification method, device, equipment and medium based on I3C bus provided by the present invention, the host connects the slave through I3C bus, and when the value of the host verification enable register corresponding to the host satisfies the first preset condition, the first verification code corresponding to the write transmission data is determined based on the write transmission data, and then the first verification code and the write transmission data are sent to the slave, and the slave is used to determine the first verification result corresponding to the write transmission data based on the first verification code and the write transmission data. Alternatively, the read transmission data is sent to the slave, and then the third verification code sent by the slave is received, and the fourth verification code corresponding to the read transmission data is determined based on the read transmission data, and the second verification result corresponding to the read transmission data is further determined based on the third verification code and the fourth verification code. In the technical solution of the present invention, the host sends the first verification code and the write transmission data to the slave, so that the slave can determine the first verification result corresponding to the write transmission data, and the host can also determine the second verification result corresponding to the read transmission data according to the third verification code and the fourth verification code. The present invention can detect the data on the I3C bus more accurately, enhance the anti-interference ability and transmission stability of data transmission, and can accurately identify the data on the I3C bus when it is wrong. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 This is one of the flow charts of the data transmission verification method based on I3C bus provided by the present invention.

[0025] Figure 2 It is a schematic diagram of a host provided by the present invention connecting to a slave via an I3C bus.

[0026] Figure 3 This is the second flow chart of the data transmission verification method based on I3C bus provided by the present invention.

[0027] Figure 4 This is one of the structural schematic diagrams of the data transmission verification device based on the I3C bus provided by the present invention.

[0028] Figure 5 This is the second structural schematic diagram of the data transmission verification device based on I3C bus provided by the present invention.

[0029] Figure 6 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] In view of the above problems in the prior art, the present invention provides a data transmission verification method based on I3C bus, which is applied to a host, wherein the host is connected to a slave via the I3C bus. Figure 1 FIG. 1 is one of the flow charts of the data transmission verification method based on I3C bus provided by the present invention, such as Figure 1 As shown, the method includes the following step 110 or step 120.

[0032] Step 110: When the value of the host check enable register corresponding to the host satisfies the first preset condition, determine a first check code corresponding to the write transfer data based on the write transfer data; send the first check code and the write transfer data to the slave, and the slave is used to determine a first check result corresponding to the write transfer data based on the first check code and the write transfer data.

[0033] Specifically, the host connects to the slave via the I3C bus. Figure 2 FIG. 1 is a schematic diagram of a host provided by the present invention connecting to a slave via an I3C bus. Figure 2 As shown, the I3C bus includes a clock line and a data line. The host and the slave transmit data via the data line in the I3C bus. Figure 2The APB (Advanced Peripheral Bus) in the I3C bus represents an advanced peripheral bus, which is a low-speed and low-power peripheral bus protocol. The present invention can determine whether to execute the method of the present invention to verify the data on the I3C bus by pre-configuring the value of the host check enable register corresponding to the host. When the value of the host check enable register corresponding to the host meets the first preset condition, the data on the I3C bus can be verified. The first preset condition can be set as needed, for example, when the value of the host check enable register is configured from 0 to 1, the subsequent verification steps are performed. Further, when the value of the host check enable register corresponding to the host meets the first preset condition, the host can determine the first verification code corresponding to the write transfer data based on the write transfer data. The first verification code can be written based on the write transfer data using a verification algorithm, and the verification algorithm is not specifically limited in this embodiment. Among them, the write transfer data can also be called single data rate (Signal Data Rate, SDR) write transfer data.

[0034] Furthermore, the host may send the first check code and the write transfer data to the slave, and after receiving the first check code and the write transfer data, the slave may determine a first check result corresponding to the write transfer data based on the first check code and the write transfer data. The first check result may indicate whether there is an error in the write transfer data.

[0035] In addition, in addition to sending the first check code and write transmission data to the slave, the host can also send a slave check enable register configuration instruction to the slave, and the slave check enable register configuration instruction is used to configure the value of the slave check enable register corresponding to the slave. Exemplarily, the slave check enable register configuration instruction can carry 1 byte of data. When the value of the host check enable register corresponding to the host meets the first preset condition, the 1 byte of data corresponding to the slave check enable register configuration instruction can be 00000001, so as to configure the value of the slave check enable register to be 1. When the value of the host check enable register corresponding to the host does not meet the first preset condition, the 1 byte of data corresponding to the slave check enable register configuration instruction can be 00000000, so as to configure the value of the slave check enable register to be 0. It should be noted that the sending order of various types of data is not specifically limited in the embodiment of the present invention. The host can also first send write transfer data to the slave, and then send the slave check enable register configuration instruction and the first check code to the slave at the same time. For example, after completing the sending of the write transfer data, 2 bytes of data can also be sent, the first byte of data is the slave check enable register configuration instruction, and the second byte of data is the first check code.

[0036] In one embodiment, determining a first check code corresponding to the write transfer data based on the write transfer data includes: A CRC-8 algorithm is used to perform cyclic calculation on the write transmission data to obtain a first check code corresponding to the write transmission data.

[0037] Specifically, the host uses a cyclic redundancy check code-8 (CRC-8) algorithm to perform cyclic calculations on the write transmission data to obtain a first check code corresponding to the write transmission data. The CRC-8 algorithm can verify the data by defining a specific generating polynomial to ensure the integrity and accuracy of the data.

[0038] In the above embodiment, the CRC-8 algorithm is used to perform cyclic calculations on the write transmission data to obtain a first check code corresponding to the write transmission data, and then the check code is subsequently used to meet specific verification requirements and improve verification accuracy.

[0039] In one embodiment, the cyclic calculation of the write transmission data using the CRC-8 algorithm to obtain a first check code corresponding to the write transmission data includes: XOR the first byte in the write transmission data with the initial CRC value to obtain a first XOR value; Determine the sub-check code corresponding to the first byte according to the first value of the first XOR value; Traverse all bytes in the write transmission data, use the sub-check code corresponding to the previous byte in the write transmission data as a new initial CRC value, determine the sub-check code corresponding to the current byte; determine the sub-check code corresponding to the last byte in the write transmission data as the first check code.

[0040] Specifically, the host can XOR the first byte in the write transmission data with the initial CRC value to obtain a first XOR value. The initial CRC value can be set in advance as needed. The embodiment of the present invention does not make specific limitations here. For example, for the convenience of calculation, the initial CRC value can be set to 00000000. Further, the sub-check code corresponding to the first byte can be determined according to the first numerical value of the first XOR value, and then all bytes in the write transmission data can be traversed, and the sub-check code corresponding to the previous byte in the write transmission data is used as a new initial CRC value to determine the sub-check code corresponding to the current byte, and the sub-check code corresponding to the last byte in the write transmission data is determined as the first check code.

[0041] Exemplarily, assuming that the write transfer data includes three bytes in total, the first byte is XORed with the initial CRC value to obtain a first XOR value corresponding to the first byte, and the sub-check code corresponding to the first byte is determined based on the first bit value of the first XOR value corresponding to the first byte. The second byte is then XORed with the sub-check code corresponding to the first byte to obtain the first XOR value corresponding to the second byte, and the sub-check code corresponding to the second byte is determined based on the first bit value of the first XOR value corresponding to the second byte. The third byte is further XORed with the sub-check code corresponding to the second byte to obtain the first XOR value corresponding to the third byte, and the sub-check code corresponding to the third byte is determined based on the first bit value of the first XOR value corresponding to the third byte, and the sub-check code corresponding to the third byte is determined as the first check code.

[0042] In the above embodiment, the first byte in the write transmission data is XORed with the initial CRC value to obtain a first XOR value, and the sub-check code corresponding to the first byte is determined according to the first value of the first XOR value, and all bytes in the write transmission data are traversed, and the sub-check code corresponding to the previous byte in the write transmission data is used as a new initial CRC value to determine the sub-check code corresponding to the current byte, and the sub-check code corresponding to the last byte in the write transmission data is determined as the first check code. This embodiment traverses all bytes in the write transmission data, and determines the first sub-check code by multiple XORs, which enhances the complexity of the sub-check code, thereby enhancing the accuracy of data verification.

[0043] In one embodiment, determining the sub-check code corresponding to the first byte according to the first value of the first XOR value includes: S1. When the first digit of the first XOR value is 1, shift the first digit to the left by one bit to obtain a first shift value; XOR the first shift value with the preset binary number to obtain a second XOR value; when the first digit of the first XOR value is 0, shift the first digit to the left by one bit to obtain a second shift value; S2. Repeat steps S1 to S2 using the second XOR value or the second shift value as a new first XOR value until the number of executions of step S1 meets a preset number of times, and determine the second XOR value or the second shift value obtained when step S1 is executed for the last time as the sub-check code corresponding to the first byte.

[0044] Specifically, in step S1, when the first digit of the first XOR value is 1, the first digit can be shifted left by one bit to obtain a first shift value. For example, when the first XOR value is 11000001, the first shift value is 10000011. Then, the first shift value can be XORed with a preset binary number to obtain a second XOR value. The preset binary number corresponds to a polynomial defined by the CRC-8 algorithm, such as the polynomial The corresponding preset binary number is 0x07, that is, 00000111. The present invention may also use preset binary numbers corresponding to other polynomials. When the first leading value of the first XOR value is 0, the first leading value may be shifted left by one position to obtain a second shift value.

[0045] Step S2, the second XOR value or the second shift value can be used as a new first XOR value to repeatedly perform steps S1 to S2 until the number of times step S1 is performed meets the preset number, and the second XOR value or the second shift value obtained when step S1 is last performed is determined as the sub-check code corresponding to the first byte. The preset number of times can be set as needed, and the embodiment of the present invention does not make a specific limitation here. Preferably, the preset number of times can be eight times.

[0046] In the above embodiment, the first XOR value is processed differently according to the first digit value of the first XOR value to obtain the second XOR value or the second shift value, and the second XOR value or the second shift value obtained when step S1 is executed for the last time is further determined as the sub-check code corresponding to the first byte, thereby increasing the complexity of the sub-check code and thus increasing the complexity of the first check code.

[0047] Step 120: When the value of the host check enable register corresponding to the host satisfies the first preset condition, the read transmission data is sent to the slave; a third check code sent by the slave is received, and a fourth check code corresponding to the read transmission data is determined based on the read transmission data; the third check code is determined by the slave based on the read transmission data; and a second check result corresponding to the read transmission data is determined based on the third check code and the fourth check code.

[0048] Specifically, when the value of the host check enable register corresponding to the host satisfies the first preset condition, the host can send the read transmission data to the slave. After receiving the read transmission data, the slave can determine the third check code based on the read transmission data, and send the third check code to the host. The transmission process of the slave transmitting the third check code to the host can be called a slave transmission request (Slave Interrupt Request, SIR). The SIR transmission can be sent by the slave to the host. 2 bytes of data, the first byte data can be agreed data, for example, when the first byte data is 00000000, it indicates that the second byte data is the third check code. The host can receive the third check code sent by the slave, and can determine the fourth check code corresponding to the read transmission data based on the read transmission data. It is easy to understand that the process of the host determining the fourth check code based on the read transmission data is the same as the process of the host determining the first check code based on the write transmission data. For details, refer to the embodiment corresponding to step 110, which will not be repeated in this embodiment. Further, the host can determine the second check result corresponding to the read transmission data based on the third check code and the fourth check code.

[0049] In one embodiment, determining a second verification result corresponding to the read transmission data based on the third verification code and the fourth verification code includes: In a case where the third check code is the same as the fourth check code, determining that the second check result is that the read transmission data is correct; In a case where the third check code is different from the fourth check code, it is determined that the second check result is a read transmission data error.

[0050] Specifically, the host can compare the third check code with the fourth check code. When the third check code is the same as the fourth check code, the host determines that the second check result is correct read transmission data. When the third check code is different from the fourth check code, the host determines that the second check result is incorrect read transmission data.

[0051] Optionally, when the second verification result is that the read transmission data is wrong, the host may also discard the read transmission data.

[0052] In the above embodiment, the host determines the second verification result as correct or incorrect read transmission data based on the comparison result of the third verification code and the fourth verification code, and can accurately judge whether the read transmission data transmitted on the I3C bus is affected by the environment and has errors.

[0053] The data transmission verification method based on I3C bus provided by the present invention, the host connects the slave through I3C bus, and when the value of the host verification enable register corresponding to the host satisfies the first preset condition, the first verification code corresponding to the write transmission data is determined based on the write transmission data, and then the first verification code and the write transmission data are sent to the slave, and the slave is used to determine the first verification result corresponding to the write transmission data based on the first verification code and the write transmission data. Alternatively, the read transmission data is sent to the slave, and then the third verification code sent by the slave is received, and the fourth verification code corresponding to the read transmission data is determined based on the read transmission data, and the second verification result corresponding to the read transmission data is further determined based on the third verification code and the fourth verification code. In the technical solution of the present invention, the host sends the first verification code and the write transmission data to the slave, so that the slave can determine the first verification result corresponding to the write transmission data, and the host can also determine the second verification result corresponding to the read transmission data according to the third verification code and the fourth verification code. The present invention can detect the data on the I3C bus more accurately, enhance the anti-interference ability and transmission stability of data transmission, and can accurately identify the data on the I3C bus when it is wrong.

[0054] The present invention also provides a data transmission verification method based on I3C bus, which is applied to a slave, and the slave is connected to a host via I3C bus. Figure 3 FIG. 2 is a flow chart of a data transmission verification method based on the I3C bus provided by the present invention. Figure 3 As shown, the method includes the following steps 310 and 320.

[0055] Step 310: Receive a first check code and write transfer data sent by the host; determine a second check code corresponding to the write transfer data based on the write transfer data when the value of the slave check enable register corresponding to the slave satisfies a first preset condition; determine a first check result corresponding to the write transfer data based on the first check code and the second check code.

[0056] Specifically, the slave can also receive a slave check enable register configuration instruction sent by the host, and the slave check enable register configuration instruction is used to configure the value of the slave check enable register corresponding to the slave. Exemplarily, the slave check enable register configuration instruction can carry 1 byte of data, and the 1 byte of data corresponding to the slave check enable register configuration instruction can be 00000001, and the slave can configure the value of the slave check enable register to be 1 based on the slave check enable register configuration instruction. The 1 byte of data corresponding to the slave check enable register configuration instruction can also be 00000000, and the slave can configure the value of the slave check enable register to be 0 based on the slave check enable register configuration instruction. The slave can also receive the first check code and write transmission data sent by the host. It should be noted that the order of sending various types of data is not specifically limited in the embodiment of the present invention. When the value of the slave check enable register corresponding to the slave meets the first preset condition, the data on the I3C bus can be checked. The first preset condition may be set as required, for example, when the value of the slave check enable register is configured from 0 to 1, the subsequent check step is performed. When the value of the slave check enable register corresponding to the slave satisfies the first preset condition, the slave may determine the second check code corresponding to the write transfer data based on the write transfer data. It is easy to understand that the process of the slave determining the second check code based on the write transfer data is the same as the process of the host determining the first check code based on the write transfer data. For details, reference may be made to the embodiment corresponding to step 110, which will not be described in detail in this embodiment.

[0057] Further, the slave machine can determine a first verification result corresponding to the write transmission data based on the first verification code and the second verification code, that is, the slave machine can compare the first verification code with the second verification code, and when the first verification code is the same as the second verification code, determine that the first verification result is that the write transmission data is correct; when the first verification code is different from the second verification code, determine that the first verification result is that the write transmission data is wrong.

[0058] Step 320: Receive the read transmission data sent by the host; when the value of the slave check enable register corresponding to the slave satisfies the first preset condition, determine a third check code corresponding to the read transmission data based on the read transmission data, and send the third check code to the host, and the host is used to determine a second check result corresponding to the read transmission data based on the third check code.

[0059] Specifically, the slave can also receive the read transmission data sent by the host. When the value of the slave check enable register corresponding to the slave satisfies the first preset condition, the slave can also determine the third check code corresponding to the read transmission data based on the read transmission data. It is easy to understand that the process of the slave determining the third check code based on the read transmission data is the same as the process of the host determining the first check code based on the write transmission data. For details, please refer to the embodiment corresponding to step 110, which will not be repeated in this embodiment. The slave can also send the third check code to the host, and in addition to sending the third check code to the host, the slave can also send a host check enable register configuration instruction to the host, and the host check enable register configuration instruction is used to configure the value of the slave check enable register corresponding to the host. It should be noted that the order of sending various types of data is not specifically limited in the embodiment of the present invention. After receiving the third check code, the host can determine the second check result corresponding to the read transmission data based on the third check code. The second check result can characterize whether there is an error in the read transmission data.

[0060] The data transmission verification method based on I3C bus provided by the present invention comprises: a slave is connected to a host through an I3C bus, receives a first verification code and write transmission data sent by the host, and determines a second verification code corresponding to the write transmission data based on the write transmission data when the value of the slave verification enable register corresponding to the slave meets the first preset condition, and then determines a first verification result corresponding to the write transmission data based on the first verification code and the second verification code. The read transmission data sent by the host can also be received, and when the value of the slave verification enable register corresponding to the slave meets the first preset condition, a third verification code corresponding to the read transmission data is determined based on the read transmission data, and the third verification code is sent to the host, and the host is used to determine a second verification result corresponding to the read transmission data based on the third verification code. In the technical solution of the present invention, the slave can determine the first verification result corresponding to the write transmission data based on the first verification code and the second verification code, and the slave can also send the third verification code to the host, so that the host determines the second verification result corresponding to the read transmission data based on the third verification code. The present invention can detect the data on the I3C bus more accurately, enhance the anti-interference ability and transmission stability of data transmission, and can accurately identify the data on the I3C bus when it is wrong.

[0061] The data transmission verification device based on the I3C bus provided by the present invention is described below. The data transmission verification device based on the I3C bus described below and the data transmission verification method based on the I3C bus described above can correspond to each other.

[0062] Figure 4 FIG. 1 is one of the structural diagrams of the data transmission verification device based on the I3C bus provided by the present invention, such as Figure 4As shown, the data transmission verification device 400 based on the I3C bus is applied to a host, and the host is connected to a slave via the I3C bus. The device includes: A host write transfer module 410 is used to determine a first check code corresponding to the write transfer data based on the write transfer data when the value of the host check enable register corresponding to the host satisfies a first preset condition; send the first check code and the write transfer data to the slave, and the slave is used to determine a first check result corresponding to the write transfer data based on the first check code and the write transfer data; or,

[0063] The host read transmission module 420 is used to send the read transmission data to the slave when the value of the host check enable register corresponding to the host meets the first preset condition; receive the third check code sent by the slave, and determine the fourth check code corresponding to the read transmission data based on the read transmission data; the third check code is determined by the slave based on the read transmission data; and determine the second check result corresponding to the read transmission data based on the third check code and the fourth check code.

[0064] In one embodiment, the host write transfer module 410 is specifically used for: A CRC-8 algorithm is used to perform cyclic calculation on the write transmission data to obtain a first check code corresponding to the write transmission data.

[0065] In one embodiment, the host write transmission module 410 is further configured to: XOR the first byte in the write transmission data with the initial CRC value to obtain a first XOR value; Determine the sub-check code corresponding to the first byte according to the first value of the first XOR value; Traverse all bytes in the write transmission data, use the sub-check code corresponding to the previous byte in the write transmission data as a new initial CRC value, determine the sub-check code corresponding to the current byte; determine the sub-check code corresponding to the last byte in the write transmission data as the first check code.

[0066] In one embodiment, the host write transmission module 410 is further configured to: S1. When the first digit of the first XOR value is 1, shift the first digit to the left by one bit to obtain a first shift value; XOR the first shift value with the preset binary number to obtain a second XOR value; when the first digit of the first XOR value is 0, shift the first digit to the left by one bit to obtain a second shift value; S2. Repeat steps S1 to S2 using the second XOR value or the second shift value as a new first XOR value until the number of executions of step S1 meets a preset number of times, and determine the second XOR value or the second shift value obtained when step S1 is executed for the last time as the sub-check code corresponding to the first byte.

[0067] In one embodiment, the host read transmission module 420 is specifically used for: In a case where the third check code is the same as the fourth check code, determining that the second check result is that the read transmission data is correct; In a case where the third check code is different from the fourth check code, it is determined that the second check result is a read transmission data error.

[0068] The data transmission verification device based on I3C bus provided by the present invention, the host connects the slave through I3C bus, and when the value of the host verification enable register corresponding to the host satisfies the first preset condition, the first verification code corresponding to the write transmission data is determined based on the write transmission data, and then the first verification code and the write transmission data are sent to the slave, and the slave is used to determine the first verification result corresponding to the write transmission data based on the first verification code and the write transmission data. Alternatively, the read transmission data is sent to the slave, and then the third verification code sent by the slave is received, and the fourth verification code corresponding to the read transmission data is determined based on the read transmission data, and the second verification result corresponding to the read transmission data is further determined based on the third verification code and the fourth verification code. In the technical solution of the present invention, the host sends the first verification code and the write transmission data to the slave, so that the slave can determine the first verification result corresponding to the write transmission data, and the host can also determine the second verification result corresponding to the read transmission data according to the third verification code and the fourth verification code. The present invention can detect the data on the I3C bus more accurately, enhance the anti-interference ability and transmission stability of data transmission, and can accurately identify the data on the I3C bus when it is wrong.

[0069] Figure 5 FIG. 2 is a second structural diagram of a data transmission verification device based on an I3C bus provided by the present invention. Figure 5 As shown, the data transmission verification device 500 based on the I3C bus is applied to a slave, and the slave is connected to the host through the I3C bus. The device includes: A slave write transmission module 510 is configured to receive a first check code and write transmission data sent by the host; determine a second check code corresponding to the write transmission data based on the write transmission data when the value of the slave check enable register corresponding to the slave satisfies a first preset condition; and determine a first check result corresponding to the write transmission data based on the first check code and the second check code; The slave read transmission module 520 is used to receive the read transmission data sent by the host; when the value of the slave check enable register corresponding to the slave satisfies the first preset condition, the third check code corresponding to the read transmission data is determined based on the read transmission data, and the third check code is sent to the host, and the host is used to determine the second check result corresponding to the read transmission data based on the third check code.

[0070] The data transmission verification device based on I3C bus provided by the present invention, the slave is connected to the host through the I3C bus, receives the first verification code and write transmission data sent by the host, and determines the second verification code corresponding to the write transmission data based on the write transmission data when the value of the slave verification enable register corresponding to the slave meets the first preset condition, and then determines the first verification result corresponding to the write transmission data based on the first verification code and the second verification code. It can also receive the read transmission data sent by the host, and determine the third verification code corresponding to the read transmission data based on the read transmission data when the value of the slave verification enable register corresponding to the slave meets the first preset condition, and send the third verification code to the host, and the host is used to determine the second verification result corresponding to the read transmission data based on the third verification code. In the technical solution of the present invention, the slave can determine the first verification result corresponding to the write transmission data based on the first verification code and the second verification code, and the slave can also send the third verification code to the host, so that the host determines the second verification result corresponding to the read transmission data based on the third verification code. The present invention can detect the data on the I3C bus more accurately, enhance the anti-interference ability and transmission stability of data transmission, and can accurately identify the data on the I3C bus when it is wrong.

[0071] Figure 6 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 6 As shown, the electronic device may include: a processor 610, a communication interface 620, a memory 630 and a communication bus 640, wherein the processor 610, the communication interface 620 and the memory 630 communicate with each other through the communication bus 640. The processor 610 may call the logic instructions in the memory 630 to execute the data transmission verification method based on the I3C bus, the method is applied to the host, the host is connected to the slave through the I3C bus, and the method includes: In the case where the value of the host check enable register corresponding to the host satisfies the first preset condition, determining a first check code corresponding to the write transfer data based on the write transfer data; sending the first check code and the write transfer data to the slave, and the slave is used to determine a first check result corresponding to the write transfer data based on the first check code and the write transfer data; or,

[0072] When the value of the host check enable register corresponding to the host satisfies the first preset condition, the read transmission data is sent to the slave; the third check code sent by the slave is received, and the fourth check code corresponding to the read transmission data is determined based on the read transmission data; the third check code is determined by the slave based on the read transmission data; and the second check result corresponding to the read transmission data is determined based on the third check code and the fourth check code.

[0073] The processor 610 may call the logic instructions in the memory 630 to execute a data transmission verification method based on the I3C bus. The method is applied to a slave device, and the slave device is connected to the host device through the I3C bus. The method includes: Receive a first check code and write transfer data sent by the host; determine a second check code corresponding to the write transfer data based on the write transfer data when the value of the slave check enable register corresponding to the slave satisfies a first preset condition; determine a first check result corresponding to the write transfer data based on the first check code and the second check code; Receive the read transmission data sent by the host; when the value of the slave check enable register corresponding to the slave satisfies the first preset condition, determine the third check code corresponding to the read transmission data based on the read transmission data, and send the third check code to the host, and the host is used to determine the second check result corresponding to the read transmission data based on the third check code.

[0074] In addition, the logic instructions in the above-mentioned memory 630 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0075] On the other hand, the present invention further provides a computer program product, the computer program product includes a computer program, the computer program can be stored in a non-transitory computer-readable storage medium, when the computer program is executed by a processor, the computer can execute the data transmission verification method based on the I3C bus provided by the above methods, the method is applied to a host, the host is connected to a slave through the I3C bus, the method includes: In the case where the value of the host check enable register corresponding to the host satisfies the first preset condition, determining a first check code corresponding to the write transfer data based on the write transfer data; sending the first check code and the write transfer data to the slave, and the slave is used to determine a first check result corresponding to the write transfer data based on the first check code and the write transfer data; or,

[0076] When the value of the host check enable register corresponding to the host satisfies the first preset condition, the read transmission data is sent to the slave; the third check code sent by the slave is received, and the fourth check code corresponding to the read transmission data is determined based on the read transmission data; the third check code is determined by the slave based on the read transmission data; and the second check result corresponding to the read transmission data is determined based on the third check code and the fourth check code.

[0077] Alternatively, the method is applied to a slave device, the slave device is connected to a host device via an I3C bus, and the method comprises: Receive a first check code and write transfer data sent by the host; determine a second check code corresponding to the write transfer data based on the write transfer data when the value of the slave check enable register corresponding to the slave satisfies a first preset condition; determine a first check result corresponding to the write transfer data based on the first check code and the second check code; Receive the read transmission data sent by the host; when the value of the slave check enable register corresponding to the slave satisfies the first preset condition, determine the third check code corresponding to the read transmission data based on the read transmission data, and send the third check code to the host, and the host is used to determine the second check result corresponding to the read transmission data based on the third check code.

[0078] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which is implemented when the computer program is executed by a processor to execute the data transmission verification method based on the I3C bus provided by the above methods, the method is applied to a host, the host is connected to a slave via the I3C bus, and the method comprises: In the case where the value of the host check enable register corresponding to the host satisfies the first preset condition, determining a first check code corresponding to the write transfer data based on the write transfer data; sending the first check code and the write transfer data to the slave, and the slave is used to determine a first check result corresponding to the write transfer data based on the first check code and the write transfer data; or,

[0079] When the value of the host check enable register corresponding to the host satisfies the first preset condition, the read transmission data is sent to the slave; the third check code sent by the slave is received, and the fourth check code corresponding to the read transmission data is determined based on the read transmission data; the third check code is determined by the slave based on the read transmission data; and the second check result corresponding to the read transmission data is determined based on the third check code and the fourth check code.

[0080] Alternatively, the method is applied to a slave device, the slave device is connected to a host device via an I3C bus, and the method comprises: Receive a first check code and write transfer data sent by the host; determine a second check code corresponding to the write transfer data based on the write transfer data when the value of the slave check enable register corresponding to the slave satisfies a first preset condition; determine a first check result corresponding to the write transfer data based on the first check code and the second check code; Receive the read transmission data sent by the host; when the value of the slave check enable register corresponding to the slave satisfies the first preset condition, determine the third check code corresponding to the read transmission data based on the read transmission data, and send the third check code to the host, and the host is used to determine the second check result corresponding to the read transmission data based on the third check code.

[0081] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0082] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data transmission verification method based on I3C bus, characterized in that: Applied to a host, the host is connected to a slave via an I3C bus, the method comprising: In the case where the value of the host check enable register corresponding to the host satisfies the first preset condition, determining a first check code corresponding to the write transfer data based on the write transfer data; sending the first check code and the write transfer data to the slave, and the slave is used to determine a first check result corresponding to the write transfer data based on the first check code and the write transfer data; or, When the value of the host check enable register corresponding to the host satisfies the first preset condition, the read transmission data is sent to the slave; the third check code sent by the slave is received, and the fourth check code corresponding to the read transmission data is determined based on the read transmission data; the third check code is determined by the slave based on the read transmission data; and the second check result corresponding to the read transmission data is determined based on the third check code and the fourth check code.

2. The data transmission verification method based on I3C bus according to claim 1, characterized in that: The determining, based on the write transmission data, a first check code corresponding to the write transmission data comprises: A CRC-8 algorithm is used to perform cyclic calculation on the write transmission data to obtain a first check code corresponding to the write transmission data.

3. The data transmission verification method based on I3C bus according to claim 2, characterized in that: The adopting the CRC-8 algorithm to perform cyclic calculation on the write transmission data to obtain a first check code corresponding to the write transmission data includes: XOR the first byte in the write transmission data with the initial CRC value to obtain a first XOR value; Determine the sub-check code corresponding to the first byte according to the first value of the first XOR value; Traverse all bytes in the write transmission data, use the sub-check code corresponding to the previous byte in the write transmission data as a new initial CRC value, determine the sub-check code corresponding to the current byte; determine the sub-check code corresponding to the last byte in the write transmission data as the first check code.

4. The data transmission verification method based on I3C bus according to claim 3 is characterized in that: The determining the sub-check code corresponding to the first byte according to the first value of the first XOR value includes: S1. When the first digit of the first XOR value is 1, shift the first digit to the left by one bit to obtain a first shift value; XOR the first shift value with the preset binary number to obtain a second XOR value; when the first digit of the first XOR value is 0, shift the first digit to the left by one bit to obtain a second shift value; S2. Repeat steps S1 to S2 using the second XOR value or the second shift value as a new first XOR value until the number of executions of step S1 meets a preset number of times, and determine the second XOR value or the second shift value obtained when step S1 is executed for the last time as the sub-check code corresponding to the first byte.

5. The data transmission verification method based on I3C bus according to any one of claims 1 to 4, characterized in that: The determining a second verification result corresponding to the read transmission data based on the third verification code and the fourth verification code includes: In a case where the third check code is the same as the fourth check code, determining that the second check result is that the read transmission data is correct; In a case where the third check code is different from the fourth check code, it is determined that the second check result is a read transmission data error.

6. A data transmission verification method based on I3C bus, characterized in that: Applied to a slave, the slave is connected to a host via an I3C bus, and the method comprises: Receive a first check code and write transfer data sent by the host; determine a second check code corresponding to the write transfer data based on the write transfer data when the value of the slave check enable register corresponding to the slave satisfies a first preset condition; determine a first check result corresponding to the write transfer data based on the first check code and the second check code; Receive the read transmission data sent by the host; when the value of the slave check enable register corresponding to the slave satisfies the first preset condition, determine the third check code corresponding to the read transmission data based on the read transmission data, and send the third check code to the host, and the host is used to determine the second check result corresponding to the read transmission data based on the third check code.

7. A data transmission verification device based on I3C bus, characterized in that: Applied to a host, the host is connected to a slave via an I3C bus, and the device comprises: A host write transfer module, configured to determine a first check code corresponding to the write transfer data based on the write transfer data when the value of the host check enable register corresponding to the host satisfies a first preset condition; send the first check code and the write transfer data to the slave, and the slave is configured to determine a first check result corresponding to the write transfer data based on the first check code and the write transfer data; or, A host read transmission module, used for sending read transmission data to the slave when the value of the host check enable register corresponding to the host meets the first preset condition; receiving a third check code sent by the slave, and determining a fourth check code corresponding to the read transmission data based on the read transmission data; the third check code is determined by the slave based on the read transmission data; and determining a second check result corresponding to the read transmission data based on the third check code and the fourth check code.

8. A data transmission verification device based on I3C bus, characterized in that: Applied to a slave, the slave is connected to a host via an I3C bus, and the device comprises: A slave write transmission module, configured to receive a first check code and write transmission data sent by the host; determine a second check code corresponding to the write transmission data based on the write transmission data when a value of a slave check enable register corresponding to the slave satisfies a first preset condition; and determine a first check result corresponding to the write transmission data based on the first check code and the second check code; A slave read transmission module is used to receive the read transmission data sent by the host; when the value of the slave check enable register corresponding to the slave satisfies the first preset condition, a third check code corresponding to the read transmission data is determined based on the read transmission data, and the third check code is sent to the host, and the host is used to determine a second check result corresponding to the read transmission data based on the third check code.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the data transmission verification method based on the I3C bus is implemented as described in any one of claims 1 to 5, or when the processor executes the computer program, the data transmission verification method based on the I3C bus is implemented as described in claim 6.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, the data transmission verification method based on the I3C bus is implemented as claimed in any one of claims 1 to 5, or when the computer program is executed by the processor, the data transmission verification method based on the I3C bus is implemented as claimed in claim 6.

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