Bus communication module, method and device, electronic equipment, chip and medium

Abstract

The invention provides a bus communication module and method, and relates to the field of bus flow control. Comprising a master device interface and a slave device interface, the master device interface is used for receiving a bus signal, and the slave device interface is used for outputting the bus signal; the bridging assembly is connected with the main equipment interface of the bus interconnection assembly, the bridging assembly comprises a command channel, the bus signal comprises a command signal and a pressure signal corresponding to the command signal, and the command channel is used for transmitting the command signal; the pressure path is connected with the bridging assembly, and the pressure path is used for transmitting the pressure signal and adjusting the pressure value of the pressure signal, so that the slave device interface of the bus interconnection assembly outputs the command signal with the highest priority in the command queue and the command signal with the low priority before the command signal with the highest priority. By adding a pressure channel, a command signal with a high priority is output earlier than a signal with a low priority, and the trailing problem and the falling problem of a back pressure mechanism are further avoided.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic communications, and in particular to a bus communication module, method and device, electronic equipment, chip and medium. Background Art

[0002] As the utilization rate of the chip's internal bus increases, the bus will remain busy, and the response to the transfer request initiated by the host will become slow. Transfer requests with high real-time requirements need to be completed as soon as possible. However, some bus architectures do not have pressure capabilities, resulting in high-priority requests not being responded to, thereby increasing the transmission delay of the system bus. Summary of the invention

[0003] The present disclosure provides a bus communication module, method and device, electronic device, chip and medium. By adding a pressure path in the bus architecture, the pressure path adjusts the pressure value of the pressure signal so that the high-priority command signal in the command queue is not blocked by the low-priority signal, so as to achieve the high-priority signal to complete the transmission as soon as possible and reduce the delay of high-real-time transmission requests.

[0004] The first aspect of the present disclosure proposes a bus communication module, including: a bus interconnection component, the bus interconnection component has a master device interface and a slave device interface, the master device interface is used to receive bus signals, and the slave device interface is used to output bus signals; a bridge component, the bridge component is connected to the master device interface of the bus interconnection component, the bridge component includes a command path, the bus signal includes a command signal and a pressure signal corresponding to the command signal, and the command path is used to transmit the command signal; a pressure path, the pressure path is connected to the bridge component, the pressure path is used to transmit the pressure signal and adjust the pressure value of the pressure signal so that the slave device interface of the bus interconnection component outputs the highest priority command signal in the command queue and the low priority command signal before the highest priority command signal.

[0005] In some embodiments of the present disclosure, the pressure path includes: a first cache space, the first cache space is used to cache a first pressure signal and a second pressure signal, the first pressure signal is a pressure signal when there is back pressure in the command path, and the second pressure signal is a pressure signal when there is no back pressure in the command path.

[0006] In the above embodiment, a pressure path connected by a bridge component is added to the original bus communication module, and the pressure value of the pressure signal is adjusted through the pressure path so that the high-priority signal in the corresponding command signal will not be blocked by the low-priority signal, thereby achieving the transmission of high-priority transmission requests as quickly as possible and reducing the delay of high-real-time transmission requests.

[0007] In some embodiments of the present disclosure, the pressure path includes: a second cache space, the second cache space is used to cache a first pressure signal, the first pressure signal is a pressure signal when there is no back pressure in the command path; a third cache space, the third cache space is used to cache a second pressure signal, the second pressure signal is a pressure signal when there is back pressure in the command path.

[0008] In some embodiments of the present disclosure, a first end of the bridge component is connected to a master device interface of a first bus interconnection component, and a second end of the bridge component is connected to a slave device interface of a second bus interconnection component.

[0009] In the above embodiment, by adding a pressure path with two buffer spaces in the bus communication module, a high-priority transmission request can be transmitted as quickly as possible, further avoiding the tailing problem and the drop problem.

[0010] A second aspect embodiment of the present disclosure provides a bus communication method, including: receiving a first bus signal, the first bus signal including a first command signal and a first pressure signal corresponding to the first command signal; in a pressure signal queue, when there is at least one second pressure signal before the first pressure signal, and the second pressure value of at least one second pressure signal is less than the first pressure value of the first pressure signal, adjusting the second pressure value to the first pressure value; outputting at least one second command signal and the first command signal in the command queue, the at least one second command signal corresponding to the at least one second pressure signal.

[0011] In some embodiments of the present disclosure, in a pressure signal queue, when there is at least one second pressure signal before a first pressure signal, and the second pressure value of at least one second pressure signal is less than the first pressure value of the first pressure signal, adjusting the second pressure value to the first pressure value includes: adjusting the second pressure value to the first pressure value through a pressure path in a bridging component of a bus communication module, the pressure path being connected to the bridging component of the bus communication module, the bridging component including a command path, and the command path being used to transmit command signals.

[0012] In some embodiments of the present disclosure, adjusting the second pressure value to the first pressure value through the pressure path in the bridge component of the bus communication module includes: storing the first pressure signal in a first cache space of the pressure path, wherein at least one second pressure signal is also stored in the first cache space; determining the first pressure value as the maximum value of all pressure signals in the first cache space; and adjusting the second pressure value to the first pressure value.

[0013] In some embodiments of the present disclosure, adjusting the second pressure value to the first pressure value through the pressure path in the bridge component of the bus communication module includes: storing the first pressure signal in the second cache space when there is no back pressure in the command path, and storing the first pressure signal in the third cache space when there is back pressure in the command path; determining the first maximum pressure value of all pressure signals in the second cache space, and determining the second maximum pressure value of all pressure signals in the third cache space; taking the larger of the first maximum pressure value and the second maximum pressure value as the first pressure value, and adjusting the second pressure value to the first pressure value.

[0014] In some embodiments of the present disclosure, when there is no back pressure in the command path, storing the first pressure signal in the second cache space, and when there is back pressure in the command path, storing the first pressure signal in the third cache space includes: when there is no back pressure in the command path, storing the first pressure signal in the second cache space; when there is back pressure in the command path and the third cache space is not full, storing the first pressure signal in the third cache space; when there is back pressure in the command path and the third cache space is full, discarding the first pressure signal.

[0015] In the above embodiment, by adjusting the larger pressure value in the pressure signal queue to the pressure value of the output pressure signal, the command channel outputs the corresponding command signal, so that high-priority transmission requests can be transmitted as quickly as possible, and by setting two cache spaces, the tailing problem and drop problem of a single cache space are further avoided.

[0016] The third aspect embodiment of the present disclosure proposes a bus communication device, including: a receiving module, used to receive a first bus signal, the first bus signal including a first command signal and a first pressure signal corresponding to the first command signal; a pressure module, used to adjust the second pressure value to the first pressure value in the pressure signal queue when there is at least one second pressure signal before the first pressure signal and the second pressure value of at least one second pressure signal is less than the first pressure value of the first pressure signal; a command module, used to output at least one second command signal and the first command signal in the command queue, at least one second command signal corresponding to at least one second pressure signal.

[0017] An embodiment of the fourth aspect of the present disclosure proposes an electronic device, comprising: a processor and a memory for storing a computer program that can be run on the processor, wherein the processor, when used to run the computer program, executes the method described in any one of the embodiments of the second aspect of the present disclosure.

[0018] The fifth aspect embodiment of the present disclosure proposes a non-transitory computer-readable storage medium storing computer instructions, and the computer instructions are used to enable a computer to execute the method described in any one of the embodiments of the second aspect of the present disclosure.

[0019] The sixth aspect embodiment of the present disclosure proposes a chip, comprising at least one processor and a communication interface, the communication interface being used to receive signals input into the chip or output signals from the chip, the processor communicating with the communication interface and implementing any method described in the second aspect through logic circuits or executing code instructions.

[0020] In summary, the bus communication module, method and device, electronic device, chip and medium proposed in the present disclosure include: a bus interconnection component, the bus interconnection component has a master device interface and a slave device interface, the master device interface is used to receive bus signals, and the slave device interface is used to output bus signals; a bridge component, the bridge component is connected to the master device interface of the bus interconnection component, the bridge component includes a command path, the bus signal includes a command signal and a pressure signal corresponding to the command signal, and the command path is used to transmit the command signal; a pressure path, the pressure path is connected to the bridge component, the pressure path is used to transmit the pressure signal and adjust the pressure value of the pressure signal, so that the slave device interface of the bus interconnection component outputs the highest priority command signal in the command queue and the low priority command signal before the highest priority command signal. The bus communication module proposed in the present disclosure, by adding a pressure path to connect with the bridge component, so as to adjust the pressure value of the pressure signal through the pressure path, so that the high priority signal in the command signal is not blocked by the low priority signal, so that the transmission request with a higher priority is completed as soon as possible, and by setting two cache spaces, on the basis of realizing the fastest transmission, the tailing problem and drop problem existing in the single cache space are avoided.

[0021] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description are used to explain the principles of the present disclosure, and do not constitute improper limitations on the present disclosure.

[0023] Figure 1 A schematic diagram of the architecture of a bus communication module proposed in an embodiment of the present disclosure;

[0024] Figure 2 A schematic diagram of the architecture of a bus communication module proposed in an embodiment of the present disclosure;

[0025] Figure 3 A flowchart of a bus communication method proposed in an embodiment of the present disclosure;

[0026] Figure 4 A schematic diagram of a process for adjusting a pressure value proposed in an embodiment of the present disclosure;

[0027] Figure 5 A schematic diagram of a process for adjusting a pressure value proposed in an embodiment of the present disclosure;

[0028] Figure 6 A schematic diagram of a process flow of a bus communication method proposed in an embodiment of the present disclosure;

[0029] Fig. 7A A schematic diagram of an AXI bus architecture with pressure capability provided by the present disclosure;

[0030] Figure 7B A schematic diagram of the push function provided by the present disclosure;

[0031] Fig. 8A A schematic diagram of a double-buffered AXI bus architecture with pressure capability provided by the present disclosure;

[0032] Figure 8B A schematic diagram of the push function provided by the present disclosure;

[0033] Fig. 9 A schematic diagram of the structure of a bus communication device proposed in an embodiment of the present disclosure;

[0034] Fig.10 A schematic diagram of the structure of an electronic device proposed in an embodiment of the present disclosure;

[0035] Fig.11 A schematic diagram of the structure of a chip proposed in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] Embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0037] Advanced eXtensible Interface (AXI) bus is used in large chips, such as Network Interface Controller (NIC) and Network-on-Chip (NoC). Multiple bus master interfaces and slave interfaces are linked through NIC and NOC, and bus transmission requests are distributed to different interfaces. Buses above AXI4 have Quality of Service (QOS) signals, which can be used to adjust the transmission response priority of the bus. However, QOS is generally a controller for storage devices such as Double Data Rate (DDR), and has no control over the transmission process of transmission requests within the bus. NOC bus generally has the ability to adjust the priority of the transmission request initiated by the master end (master node) in the NOC through pressure signals. The higher the priority, the easier it is to win the arbitration and thus be transmitted from the NOC. The pressure signal required by NOC is from the upstream of the bus. When the bus crosses the clock domain and power domain, an AXI asynchronous bridge is generally used.

[0038] Common asynchronous bridges do not have pressure capabilities. When the command with the head priority is blocked by other high-priority commands, the high-priority command behind the low-priority command cannot be transmitted, resulting in no response to the high-priority request. Some asynchronous bridges can implement pressure capabilities, but there are limitations on usage scenarios, such as the tailing problem. After the high-priority pressure is output, multiple high-priority pressure signals will continue to be output, thus affecting the transmission efficiency of the system bus.

[0039] In summary, in order to solve the technical problems in the related technology, the embodiments of the present disclosure provide a bus communication module and a bus communication method. The bus communication module increases the pressure mechanism in the process of signal transmission of the bridging component to advance the high-priority signal before the low-priority signal, thereby improving the priority of the high-priority commands blocked in the subsequent stage to participate in arbitration, so that the low-priority commands can quickly win the arbitration, thereby releasing the command path, and the high-priority commands can complete the transmission as soon as possible, reducing the delay of high-real-time transmission requests.

[0040] The bus communication module and bus communication method provided in the present application will be described in detail below with reference to the accompanying drawings.

[0041] First, the professional terms used in this disclosure are introduced.

[0042] 1. AXI (Advanced eXtensible Interface): is a bus protocol, an on-chip bus for high performance, high bandwidth, and low latency. Its address / control and data phases are separated, supporting unaligned data transmission. In burst transmission, only the first address is required, and the separate read and write data channels support outstanding transmission access and out-of-order access, making it easier to perform timing convergence.

[0043] 2. Network-on-Chip (NoC): It is a network-based communication subsystem on an integrated circuit, used between modules in a system on a chip (SoC), and is based on a packet switching network based on routers to connect the modules of the SoC. A single master and slave (slave node) are connected in series, and both NOC and NIC are used to implement this function.

[0044] 3. Clock domain: refers to the area controlled by the same clock signal. In the circuit, the clock domain is the area driven by the same clock signal. Signals crossing the clock domain need special processing to ensure correct transmission.

[0045] 4. Power domain: refers to an area within the chip that contains a group of related circuits and logic that can be independently powered. The concept of power domain is related to voltage domain, but it is different. Voltage domain refers to a collection of modules that use the same voltage source, while power domain refers to a collection of modules that share the same power switch logic within the same voltage domain. This means that modules in the same power domain are controlled by the same power switch logic and are powered on and off at the same time. Modules within a voltage domain can be split into different power domains according to design requirements, thereby achieving more refined power management.

[0046] Figure 1 A schematic diagram of the architecture of a bus communication module proposed in an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the bus communication module includes a bus interconnection component, a bridge component, and a pressure path.

[0047] In some embodiments, the bus interconnection component has a master device interface and a slave device interface, the master device interface is used to receive bus signals, and the slave device interface is used to output bus signals.

[0048] In some embodiments, the bus interconnection component may be a NOC bus, or a MATRIX bus, a NIC bus, an AXI bus, etc.

[0049] In some embodiments, the bridge component is connected to the main device interface of the bus interconnection component, the bridge component includes a command path, the bus signal includes a command signal and a pressure signal corresponding to the command signal, and the command path is used to transmit the command signal.

[0050] In some embodiments, the bridge component may be an AXI asynchronous bridge, a NOC asynchronous bridge, or the like.

[0051] In some embodiments, the bus signal may include a command signal, a pressure signal, and may also include a data signal, which is not limited in the present disclosure.

[0052] In some embodiments, the pressure path is connected to the bridge component, and the pressure path is used to transmit the pressure signal and adjust the pressure value of the pressure signal so that the bus interconnection component outputs the highest priority command signal in the command queue from the device interface and the low priority command signal before the highest priority command signal.

[0053] In some embodiments, the pressure path and the bridge component are connected to the upstream of the bus interconnection component, that is, connected to the master device interface of the bus interconnection component, so as to transmit the highest priority command signal and the low priority command signal before the highest priority command signal to the slave device interface of the bus interconnection component, and output to the interface of the downstream component. The bridge component and the pressure path can be connected to the master device interface directly or indirectly.

[0054] In some embodiments, the pressure passage and the bridge component may also be connected to the slave device interface of the bus interconnection component, that is, connected downstream of the bus interconnection component, and the connection method may be direct connection or indirect connection.

[0055] In some embodiments, the pressure path includes a first buffer space, the first buffer space is used to buffer a first pressure signal and a second pressure signal, the first pressure signal is a pressure signal when the command path has a back pressure, and the second pressure signal is a pressure signal when the command path does not have a back pressure. The first pressure signal corresponds to the first command signal, and the second pressure signal corresponds to the second command signal.

[0056] Among them, back pressure means that when the destination end does not have the receiving capability, it will feedback to the superior and stop transmitting the signal, and wait until it has the receiving capability before transmitting.

[0057] In some embodiments, the cache space of the pressure path shares a set of read and write logic with the command path.

[0058] In some embodiments, the pressure path stores a pressure signal queue in a first cache space, the pressure signal queue stores a first pressure signal and at least one second pressure signal, the pressure channel takes the maximum value of all pressure signals in the first cache space as the first pressure value, and adjusts the second pressure value of at least one second pressure signal to the first pressure value.

[0059] In some embodiments, the command path in the bridge assembly outputs a first command signal corresponding to the first pressure signal, and outputs at least one second command signal corresponding to at least one second pressure signal.

[0060] For example, Fig. 7A The bus communication module architecture diagram shown includes a Master end, a Slave end, a Press channel, and a command channel. The Press channel includes a Press buffer for caching the Pressure signal. The Press buffer in the Press channel shares a set of read and write logic with the command channel.

[0061] In some embodiments, a first end of the bridge component is connected to a master device interface of a first bus interconnect component, and a second end of the bridge component is connected to a slave device interface of a second bus interconnect component.

[0062] In some embodiments, the first bus interconnection component and the second bus interconnection component may be in different clock domains or power domains, or may be in the same clock domain or power domain, which is not limited by the present disclosure.

[0063] For example, Fig. 7A The Master and Slave ends can be in the same clock domain or power domain, or in different clock domains or power domains.

[0064] In the above embodiment, when the first bus interconnection component and the second bus interconnection component are in different clock domains or power domains, cross-domain signal transmission can be achieved.

[0065] In the above embodiment, by adding a pressure path in the bus communication module, the pressure path provides a push function, so that high-priority signals are not blocked by low-priority signals, and further the high-priority signals are transmitted to the next stage as quickly as possible, reducing the delay of high-real-time transmission requests.

[0066] Figure 2 A schematic diagram of the architecture of a bus communication module proposed in an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the bus communication module includes a bus interconnection component, a bridge component, and a pressure passage. Figure 2 based on Figure 1 The structure shown in the figure further improves the pressure path to solve the problem. Figure 1The architecture shown has smearing and dropout issues.

[0067] In some embodiments, the bus interconnection component has a master device interface and a slave device interface, the master device interface is used to receive bus signals, and the slave device interface is used to output bus signals.

[0068] In some embodiments, the bus interconnection component may be a NOC bus, or a MATRIX bus, a NIC bus, an AXI bus, etc.

[0069] In some embodiments, the bridge component is connected to the main device interface of the bus interconnection component, the bridge component includes a command path, the bus signal includes a command signal and a pressure signal corresponding to the command signal, and the command path is used to transmit the command signal.

[0070] In some embodiments, the bridge component may be an AXI asynchronous bridge, a NOC asynchronous bridge, an AXI synchronous bridge, a NOC synchronous bridge, or the like.

[0071] In some embodiments, the bus signal may include a command signal, a pressure signal, and a data signal, which is not limited in the present disclosure.

[0072] In some embodiments, the pressure path is connected to the bridge component, and the pressure path is used to transmit the pressure signal and adjust the pressure value of the pressure signal so that the bus interconnection component outputs the highest priority command signal in the command queue from the device interface and the low priority command signal before the highest priority command signal.

[0073] In some embodiments, the pressure path and the bridge component are connected to the upstream of the bus interconnection component, that is, connected to the master device interface of the bus interconnection component, so as to transmit the current highest priority command signal and the low priority command signal before the highest priority command signal to the slave device interface of the bus interconnection component, and output to the master device interface of the downstream component. The bridge component and the pressure path can be connected to the master device interface directly or indirectly.

[0074] In some embodiments, the pressure passage and the bridge component may also be connected to the slave device interface of the bus interconnection component, that is, connected downstream of the bus interconnection component, and the connection method may be direct connection or indirect connection.

[0075] In some embodiments, the pressure path includes a second buffer space and a third buffer space, the second buffer space is used to buffer a first pressure signal, the first pressure signal is a pressure signal when the command path does not have back pressure; the third buffer space is used to buffer a second pressure signal, the second pressure signal is a pressure signal when the command path has back pressure. Wherein, back pressure means that when the destination end does not have the receiving capability, it will feedback to the superior that it will no longer transmit the signal and wait until it has the receiving capability before transmitting.

[0076] In some embodiments, the second cache space of the pressure path shares a set of read and write logic with the command path.

[0077] For example, Fig. 8A As shown in the architecture diagram, there are two cache spaces in the Press channel. The two cache spaces are not the same standard asynchronous first-in-first-out data storage device (First In First Out, FIFO), but writing and reading data to the cache space follows the first-in-first-out principle. The cache space with back pressure needs to synchronize the write pointer to the read clock domain, and synchronize the read pointer to the write clock domain; the cache space without back pressure shares a set of read and write logic with the command channel.

[0078] In some embodiments, the pressure path stores a first pressure signal in a second cache space when there is no back pressure in the command path, and stores the first pressure signal in a third cache space when there is back pressure in the command path; determines a first maximum pressure value of all pressure signals in the second cache space, and determines a second maximum pressure value of all pressure signals in the third cache space; takes the larger of the first maximum pressure value and the second maximum pressure value as the first pressure value, and adjusts the second pressure value to the first pressure value.

[0079] In some embodiments, there are valid data and invalid data in the second cache space and the third cache space. For the second cache space without back pressure, the valid space is divided by the address pointer of the command path. The third cache space with back pressure judges the valid data by the flag signal generated during reading. The maximum value of the valid data in the second cache space and the third cache space is used as the first pressure value, that is, the pressure signal finally output.

[0080] For example, Figure 8B The push function diagram shown in the figure shows that the Press buffer with back pressure and the Press buffer without back pressure determine the maximum value respectively, and the larger of the two maximum values ​​is used as the output of the Press channel. Then the corresponding command signal is output in the command channel, achieving the purpose of outputting the high priority signal as soon as possible. Fig. 7A The architecture of a Press cache is shown, which avoids the tailing problem and the drop problem.

[0081] In some embodiments, the command path in the bridge assembly outputs a first command signal corresponding to the first pressure signal, and outputs at least one second command signal corresponding to at least one second pressure signal.

[0082] In some embodiments, when there is no back pressure in the command path, the pressure path stores the first pressure signal in the second cache space; when there is back pressure in the command path and the third cache space is not full, the first pressure signal is stored in the third cache space; when there is back pressure in the command path and the third cache space is full, the first pressure signal is discarded.

[0083] For example, in Fig. 8A In the architecture shown, when the command channel has no back pressure, the pressure signal is synchronized with the command signal to enter the cache space without back pressure. When the command channel is back pressured, if the cache space with back pressure is not full, the pressure signal is written to the cache space with back pressure. If the cache space is full at this time, the current pressure signal is discarded.

[0084] For example, Fig. 8A The bus communication module architecture diagram shown in the figure includes a Master end, a Slave end, a Press channel, and a command channel. Among them, the Press channel includes a Press cache with back pressure and a Press cache without back pressure, and the command channel includes a command cache. The two Press caches are processed across clock domains respectively, and the depth of the cache space is consistent with the command channel. The data of the two caches need to be directly introduced into the read clock domain, and the valid data is found through the read-write pointer in the read clock domain. The maximum value of the pressure signal is determined in the two cache spaces respectively, and the larger of the two maximum values ​​is used as the output of the Press channel, and the command channel outputs the corresponding command signal.

[0085] In some embodiments, a first end of the bridge component is connected to a master device interface of a first bus interconnect component, and a second end of the bridge component is connected to a slave device interface of a second bus interconnect component.

[0086] In some embodiments, the first bus interconnection component and the second bus interconnection component may be in different clock domains or power domains, or may be in the same clock domain or power domain, which is not limited by the present disclosure.

[0087] For example, Fig. 8A The Master and Slave ends can be in the same clock domain or power domain, or in different clock domains or power domains.

[0088] In the above embodiment, two buffer spaces are set in the pressure path to cache the pressure signal when the command path has back pressure and the pressure signal when the command path does not have back pressure, respectively, so as to judge the maximum value of the pressure values ​​of the pressure signals in the two buffer spaces, and after comparison, the larger value is used as the pressure value output by the pressure path, so that the command signal of the corresponding command path can be outputted preferentially, compared with the Figure 1 The bus communication module shown in can avoid the existing tailing problem and falling problem.

[0089] In the above embodiment, since the two cache spaces are divided into a cache space with back pressure and a cache space without back pressure, the deviation of the clock domain will cause the command path and the pressure path to not correspond one to one, while the current cache space without back pressure is consistent with the command path. For example, if the pressure value of the pressure signal of the cache space is the maximum pressure value, it is consistent with the command channel and will not drop. At the same time, the signal of the maximum pressure value can be cleared at the exact time, thereby solving the tailing problem.

[0090] Figure 3 FIG. 1 is a flow chart of a bus communication method proposed in an embodiment of the present disclosure. Figure 3 As shown, the method comprises the following steps:

[0091] Step 301: Receive a first bus signal.

[0092] In some embodiments, the first bus signal includes a first command signal and a first pressure signal corresponding to the first command signal.

[0093] In some embodiments, the first bus signal further includes a data signal.

[0094] In some embodiments, the first bus signal is currently input to the bus communication module through the bus and received by the main device interface of the bus interconnection component, including a first command signal and a first pressure signal. There is a one-to-one correspondence between the first command signal and the first pressure signal, and the first pressure signal includes a first pressure value.

[0095] In some embodiments, before the first bus signal, the bus communication module also receives at least one bus signal, the bus signal includes a command signal and a pressure signal, there is a one-to-one correspondence between the command signal and the pressure signal, and the pressure signal includes a pressure value.

[0096] In some embodiments, by Figure 1 The main device interface of the bus communication module shown receives a first bus signal and at least one second bus signal. The first bus signal and the second bus signal both include corresponding command signals and pressure signals, and the pressure signal includes a pressure value.

[0097] In some embodiments, by Figure 2 The main device interface of the bus communication module shown receives a first bus signal and at least one second bus signal. The first bus signal and the second bus signal both include corresponding command signals and pressure signals, and the pressure signal includes a pressure value.

[0098] Step 302: In the pressure signal queue, when there is at least one second pressure signal before the first pressure signal, and the second pressure value of the at least one second pressure signal is smaller than the first pressure value of the first pressure signal, the second pressure value is adjusted to the first pressure value.

[0099] In some embodiments, the pressure signal in the bus signal will enter the pressure signal queue in the cache space. When the first pressure signal enters the pressure signal queue, there is already at least one second pressure signal in the pressure signal queue, and the second pressure values ​​of the second pressure signals are all smaller than the first pressure value, then the second pressure value of at least one second pressure signal preceding the first pressure signal in the pressure signal queue is changed to the first pressure value.

[0100] In some embodiments, a larger pressure value indicates a higher priority, and by adjusting the second pressure value to the first pressure value, a high priority signal is pushed ahead of a low priority signal.

[0101] In some embodiments, the second pressure value is adjusted to the first pressure value through a pressure path in a bridge component of the bus communication module. The pressure path is connected to the bridge component of the bus communication module. The bridge component includes a command path for transmitting command signals.

[0102] In some embodiments, the specific architecture of the bus communication module can be as follows: Figure 1 The architecture diagram shown can also be Figure 2 The architecture diagram shown.

[0103] In some embodiments, the pressure signal queue follows the first-in-first-out principle. When a first pressure signal enters the pressure signal queue, there is already at least one second pressure signal in the pressure signal queue. When the second pressure value corresponding to each second pressure signal is lower than the first pressure value, it indicates that the priority of at least one second pressure signal is lower than the first pressure signal. The second pressure value is adjusted to the first pressure value, so that the high-priority pressure signal is promoted to the lower end of the queue, that is, it is changed from the position that enters the queue later to the position that enters the queue first, so that the pressure signal of the first pressure value can be output from the pressure queue.

[0104] Step 303: output at least one second command signal and the first command signal in the command queue.

[0105] In some embodiments, the at least one second command signal corresponds to the at least one second pressure signal.

[0106] In some embodiments, the command signal in the command queue corresponds to the pressure signal, and the second pressure value of the second pressure signal is adjusted to the first pressure value. Therefore, the pressure signal with the first pressure value is first output in the pressure signal queue, and the corresponding first command signal is first output in the command queue.

[0107] In some embodiments, the bridge component of the bus communication module is connected to the pressure path, the pressure path transmits a pressure signal and adjusts the pressure value of the pressure signal, that is, adjusts the second pressure value to the first pressure value, and the command path in the bridge component transmits the corresponding command signal. Therefore, when the pressure signal queue in the pressure path outputs the first pressure signal of the first pressure value, the command path outputs the corresponding first pressure signal, so that the bus interconnection component outputs the highest priority command signal in the command queue from the device interface, and outputs a command signal lower than the highest priority.

[0108] In the above embodiment, by increasing the adjustment of the pressure value in the pressure signal queue, the pressure signal with the maximum pressure value among the currently input pressure signal and the existing pressure signals in the pressure signal queue is adjusted to the position of being output first, so that the high-priority command signal in the corresponding command signal is output first, thereby achieving the purpose of transmitting the high-priority pressure signal to the next stage in advance, and then achieving the purpose of transmitting the high-priority signal as soon as possible.

[0109] Figure 4 This is a schematic diagram of the process of adjusting the pressure value proposed in the embodiment of the present disclosure. Figure 3 The embodiment shown, Figure 4 right Figure 3 The 302 in the code is further limited, such as Figure 4 As shown, including:

[0110] Step 401: store a first pressure signal into a first buffer space of a pressure path.

[0111] In some embodiments, there is also at least one second pressure signal in the first buffer space.

[0112] In some embodiments, the pressure path includes a first cache space, the first cache space is used to store the pressure signal in the bus signal, and the first cache space follows the first-in-first-out principle.

[0113] In some embodiments, when the first pressure signal enters the first cache space of the pressure path, there is already at least one second pressure signal in the first cache space, the first pressure signal includes a first pressure value, the second pressure signal includes a second pressure value, the first pressure signal corresponds to the first command signal, and the second pressure signal corresponds to the second command signal.

[0114] In some embodiments, the first buffer space of the pressure path is used to store the pressure signal when the command path has back pressure and the pressure signal when the command path does not have back pressure. In other words, regardless of whether the command path has back pressure, the pressure signal in the bus signal will enter the first buffer space of the pressure path, and when the pressure signal in the first buffer space is output, the corresponding command signal in the command path is output.

[0115] Among them, back pressure means that when the destination end does not have the receiving capability, it will feedback to the superior and stop transmitting the signal, and wait until it has the receiving capability before transmitting.

[0116] In some embodiments, Figure 1 The pressure path of the bus communication module shown includes a first cache space for caching a first pressure signal and a second pressure signal. The first pressure signal is a pressure signal when there is back pressure in the command path, and the second pressure signal is a pressure signal when there is no back pressure in the command path.

[0117] Step 402: determine that the first pressure value is the maximum value of all pressure signals in the first buffer space.

[0118] In some embodiments, the first pressure value is determined to be the maximum value of all pressure signals in the first cache space, that is, the first pressure value of the first pressure signal in the currently input first bus signal is the maximum pressure value among all pressure signals in the first cache space.

[0119] In some embodiments, determining the maximum value of the pressure signal in the first cache space is used to push the pressure signal of the maximum pressure value to the output position of the cache space, that is, to enable the high-priority pressure signal to be output to the next stage as quickly as possible.

[0120] In some embodiments, Figure 1 In the first cache space of the bus communication module shown, the maximum value of the pressure signal stored therein is determined.

[0121] For example, in Fig. 7A In the Press channel of the bus communication module shown in FIG. 1 , the pressure signal enters the Press buffer, and the maximum value of the pressure signal in the Press buffer is determined. Figure 7B The schematic diagram of the push function shown in FIG. 1 determines 15 as the maximum value of the pressure signal in the Press buffer.

[0122] Step 403: adjust the second pressure value to the first pressure value.

[0123] In some embodiments, the second pressure value is adjusted to the first pressure value, that is, the pressure value of the second pressure signal is adjusted to the pressure value of the first pressure signal. In other words, the current high-priority pressure signal is output to the next stage before the low-priority signal.

[0124] In some embodiments, Figure 1 The first buffer space of the bus communication module shown adjusts the pressure value of the pressure signal that is lower than the maximum value to the maximum value determined in step 402 .

[0125] For example, in Fig. 7A In the Press channel of the bus communication module shown, Figure 7B As shown, the pressure value below the maximum value of 15 is adjusted to 15.

[0126] In the above embodiment, a pressure function is added to the bus communication module, that is, the pressure signal in the currently input bus signal is stored in the pressure signal queue, and the maximum pressure value in the pressure signal is determined, and the pressure value in the pressure signal queue is adjusted so that the pressure signal with the maximum value is output first, thereby achieving the purpose of outputting high-priority signals as soon as possible and reducing the delay of high-real-time transmission requests.

[0127] Figure 5 A schematic diagram of a process for adjusting the pressure value proposed in an embodiment of the present disclosure, based on Figure 3 The embodiment shown, Figure 5 right Figure 3 302 in the code is further limited, as shown in the figure Figure 5 As shown, including:

[0128] Step 501, when there is no back pressure in the command path, the first pressure signal is stored in the second cache space, and when there is back pressure in the command path, the first pressure signal is stored in the third cache space.

[0129] In some embodiments, back pressure means that when the destination end does not have the receiving capability, it feeds back to the superior end to stop transmitting the signal and wait until it has the receiving capability before transmitting again.

[0130] In some embodiments, the bridge component of the bus communication module includes a pressure path, the pressure path is connected to the bridge component of the bus communication module, and the bridge component includes a command path, and the command path is used to transmit command signals.

[0131] In some embodiments, the architecture diagram of the bus communication module can be as follows: Figure 2 As shown, the Press channel includes two cache spaces, one for when there is no upstream back pressure and the other for when there is upstream back pressure. The two cache spaces can be in the same clock domain or power domain, or in different clock domains or power domains. The depth of the cache space without back pressure is consistent with that of the command channel. The two cache spaces are independent of each other and have independent read and write logic. The cache space without back pressure shares the read and write logic with the command channel.

[0132] In some embodiments, the pressure path includes a second cache space and a third cache space, the second cache space is used to store the pressure signal when there is no back pressure in the command path, and the third cache space is used to store the pressure signal when there is back pressure in the command path.

[0133] For example, Fig. 8A As shown in the architecture diagram of the bus communication module, when there is back pressure, the pressure signal enters the Press buffer of the Press channel when there is back pressure, and when there is no back pressure, the pressure signal enters the Press buffer of the Press channel when there is no back pressure.

[0134] In some embodiments, Figure 2 In the architecture diagram of the bus communication module shown, the second cache space is used to cache the first pressure signal, which is a pressure signal when there is no back pressure in the command path, and the third cache space is used to cache the second pressure signal, which is a pressure signal when there is back pressure in the command path.

[0135] Step 502: determine a first maximum pressure value of all pressure signals in the second buffer space, and determine a second maximum pressure value of all pressure signals in the third buffer space.

[0136] In some embodiments, the second buffer space and the third buffer space respectively determine the maximum pressure value of the pressure signal buffered therein.

[0137] In some embodiments, the read and write logic of the second cache space and the third cache space are inconsistent, and the read and write logic of the second cache space is consistent with the read and write logic of the command path.

[0138] In some embodiments, the second cache space is not a standard FIFO structure, and the second cache can be written when the command channel handshake succeeds. The data cached in the second cache space is directly transferred from the write clock domain to the read clock domain, and the selection of valid data is realized through the read-write pointer of the command channel read clock domain. The data in the second cache space does not need to be read out from the cache one by one, but the valid data is directly selected through the read-write pointer of the command channel.

[0139] In some embodiments, the third cache space is a standard asynchronous FIFO structure that follows the first-in, first-out principle. When the upstream is under back pressure, write to this cache, and when the downstream is not empty, start reading, and distribute the read data to different address spaces to complete the data selection. After the data is read from the third cache space, a flag signal will be generated. This flag signal is used to indicate whether the corresponding pressure data is valid, and the corresponding flag signal will be cleared after the pressure signal of the second cache space is transmitted to the downstream.

[0140] In some embodiments, the second cache space and the third cache space determine the maximum pressure value in different ways. The data in the second cache space and the third cache space include valid data and invalid data. For the second cache space, the valid data is divided by the address pointer of the command channel, and the third cache space determines the valid data through the flag signal generated after reading the data. The second cache space and the third cache space respectively determine the pressure signal of the maximum pressure value in the valid data.

[0141] In some embodiments, Figure 2 In the architecture diagram of the bus communication module shown, the second cache space and the third cache space respectively determine the maximum pressure value in the pressure signals cached therein.

[0142] For example, in Fig. 8A In the architecture of the bus communication module shown in FIG. Figure 8B As shown, the buffer with back pressure and the buffer without back pressure respectively determine the pressure signal of the maximum pressure value.

[0143] Step 503: The larger one of the first maximum pressure value and the second maximum pressure value is used as the first pressure value, and the second pressure value is adjusted to the first pressure value.

[0144] In some embodiments, the second pressure value is adjusted to the first pressure value through a pressure path in a bridge component of the bus communication module.

[0145] In some embodiments, the second cache space and the third cache space compare the respectively determined maximum pressure values, and determine the larger one as the pressure value of the current pressure signal, that is, the pressure value of the second pressure signal preceding the first pressure signal stored in the cache space is adjusted to the determined pressure value of the current pressure signal. That is, the first maximum pressure value and the second maximum pressure value are compared, the larger one is used as the first pressure value, and the second pressure value is adjusted to the first pressure value.

[0146] For example, Figure 8B The schematic diagram of the pressure function shown compares the maximum value 13 in the cache without back pressure with the maximum value 12 in the cache with back pressure, determines that the maximum value of the pressure signal is 13, and adjusts all pressure values ​​before 13 to 13.

[0147] In the above embodiment, two cache spaces are divided to store the pressure signal when the command path has back pressure and the pressure signal when the command path has no back pressure, and the maximum pressure values ​​in the two cache spaces are determined respectively. The larger of the two maximum pressure values ​​is used as the pressure value currently output by the pressure signal queue and pushed to the output end of the pressure signal queue, so that the high priority signal is output first, further avoiding Figure 3 , Figure 4 The tailing and falling problems that occur in the system.

[0148] Figure 6 The flowchart of the bus communication method proposed in the embodiment of the present disclosure is shown in FIG. Figure 5 The embodiment shown, Figure 6 right Figure 5 Step 501 in is further defined. Figure 6 As shown, including:

[0149] Step 601: When there is no back pressure in the command path, the first pressure signal is stored in the second cache space.

[0150] In some embodiments, when there is no back pressure in the command path, storing the first pressure signal in the second buffer space may be performed as follows: Figure 2 In the bus communication module shown, the first pressure signal is stored in the second buffer space of the pressure path.

[0151] For example, in Fig. 8A In the architecture, when there is no back pressure in the command channel, the pressure signal is stored in the Press buffer when there is no back pressure.

[0152] Step 602, when there is back pressure in the command path and the third cache space is not full, store the first pressure signal in the third cache space; when there is back pressure in the command path and the third cache space is full, discard the first pressure signal.

[0153] In some embodiments, when there is back pressure in the command path and the third cache space is not full, that is, there is back pressure in the command path, the pressure signal needs to be stored in the third cache space, and the current third cache space still has storage space.

[0154] In some embodiments, when there is back pressure in the command path and the third cache space is full, that is, there is back pressure in the command path, the pressure signal needs to be stored in the third cache space, but the current third cache space has no storage space.

[0155] In some embodiments, when there is storage space in the third cache space, the pressure signal can be stored in the third cache space. When there is no storage space in the third cache space, the pressure signal needs to be discarded. The command signal corresponding to the pressure signal is upstream of the command channel and waits for the next pressure signal to be output. When there is storage space in the third cache space, it enters the cache of the command channel.

[0156] In the above embodiment, the cache space without back pressure can be entered and exited at any time, while the cache space with back pressure needs to wait until there is a position in the cache space before entering the corresponding cache space. When the cache space with back pressure is full, the currently entering pressure signal can be discarded, and the command signal of the corresponding command channel has not yet entered. It can wait for the next pressure signal with back pressure to enter before entering the cache of the command channel.

[0157] Fig. 7A A schematic diagram of an AXI bus architecture with pressure capability provided by the present disclosure is shown as follows: Fig. 7A As shown in the figure, a pressure signal channel is added to the periphery of the AXI bus, and the blocked high-priority pressure signal is transmitted to the subsequent stage in advance, so as to improve the priority of the blocked low-priority command in the subsequent stage to participate in arbitration, so that the low-priority command can win the arbitration, thereby releasing the command path, so that the high-priority command can be transmitted smoothly. The core function of the AXI asynchronous bridge is: when the downstream back pressure of the bus causes the command channel to be unable to continue to be transmitted to the subsequent stage, the pressure channel provided by the flow control function will transmit the high pressure value of the back pressure to the downstream bus, improve the priority of the low-priority command that blocks the high-priority command, so that the front low-priority command can win the arbitration and complete the transmission as soon as possible, thereby achieving the purpose of fast transmission of high-priority commands.

[0158] like Fig. 7A As shown, the bus communication module includes a Master end, a Slave end, a Press channel, and a command channel. After the bus signal enters, the pressure signal enters the Press channel, and the command signal enters the command channel. In the AXI bus architecture with pressure capability, a push function is added. The pressure cache channel uses an asynchronous FIFO structure. After the upstream input press_in enters the cache, it is read out from the downstream in sequence, and a maximum value is selected from the read press_out as the pressure of the subsequent command. Since the output of the pressure cache channel does not perform back pressure, as long as the cache is not empty, the data will be taken out from the cache one by one. This solution determines whether to update the pressure max output value through the pressure_max_up signal, and the implementation logic of the pressure_max_up signal depends on the cnt value of the decrement counter. When the high-priority pressure signal pushed out in advance continues to maintain multiple high-priority transmission requests after the corresponding command is successfully transmitted, it may cause a tailing problem.

[0159] like Figure 7BAs shown in the push function diagram, when the transmission request with priority 15 is blocked by the transmission request with priority 1, the higher priority is pushed to the next stage in advance, and finally the transmission request with priority 15 is output from the bus earlier than the transmission request without the push function. After the transmission request with priority 15 has been passed normally, it will continue to participate in arbitration with priority 15 for a period of time, which will increase the delay of the high-priority command of input port 2, thereby causing the tailing problem and drop problem.

[0160] In order to solve the above-mentioned tailing problem and drop problem, the present disclosure proposes a double-buffered AXI bus architecture with pressure capability, such as Fig. 8A FIG. 1 is a schematic diagram of a dual-buffered AXI bus architecture with pressure capability, including a Press channel and a command channel, wherein the Press channel includes a Press buffer when there is back pressure and a Press buffer when there is no back pressure.

[0161] like Fig. 8A As shown, two cache spaces are provided for the Pressure signal, one for when there is no upstream back pressure and the other for when there is upstream back pressure. The two cache spaces perform cross-clock domain processing respectively, and the depth of the cache space without back pressure is consistent with the command channel. The two cache spaces are not a standard asynchronous FIFO (First input first put), but writing to the cache and reading data from the cache follow the first-in, first-out principle. The pressure cache with back pressure has independent read and write logic, with data written upstream and read downstream, and the downstream read pointer needs to participate in the logic of the upstream write pointer; the pressure cache without back pressure shares the read and write logic with the command channel.

[0162] The cache structure with back pressure is a standard asynchronous FIFO structure, following the first-in, first-out principle. When the upstream is under back pressure, write to this cache, and when the downstream is not empty, start reading, and distribute the read data to different address spaces to complete the data selection. After the data is read from the cache with back pressure, a flag signal will be generated. This flag signal is used to indicate whether the corresponding pressure data is valid, and the corresponding flag signal will be cleared after the pressure signal corresponding to the non-back pressure channel is transmitted to the downstream.

[0163] The cache without back pressure is not a standard FIFO structure. When the command channel handshake succeeds, it can be written to this cache. The data cached in the cache channel without back pressure is directly transferred from the write clock domain to the read clock domain, and the selection of valid data is realized through the read-write pointer of the command channel read clock domain. The data without back pressure does not need to be read out from the cache one by one, but the valid data is directly selected through the read-write pointer of the command channel. Finally, the maximum pressure signal is selected from the valid data in the two caches with back pressure and without back pressure and output to the downstream.

[0164] When there is no back pressure on the command main channel, the pressure signal is synchronized with the command to enter the cache space without back pressure; when the command main channel is back pressured, if the cache space with back pressure is not full, the pressure signal is written to the cache space. If the cache space is full, the current pressure signal is discarded.

[0165] like Figure 8B As shown in the schematic diagram of the push function, the depth of the cache space with back pressure and the cache space without back pressure are the same, both are 8. When the command channel has no back pressure, the pressure signals 0, 1, 1, 1, 1, 1, 2, and 3 enter the cache space without back pressure. When the command channel has back pressure, the pressure signals 4, 5, 6, 7, 8, 9, 10, 11, and 12 enter the cache space with back pressure. When the current pressure signal 13 enters, the command channel has no back pressure, then it enters the cache space without back pressure, and the maximum value of the two cache spaces is selected, which is 13. The pressure values ​​of the signals before the pressure signal 13 will be adjusted to 13, so that the pressure channel outputs 13, and the corresponding command channel will output the command signal corresponding to 13.

[0166] The above Figure 8B The architecture diagram shown in the figure can realize the transmission of high-priority transmission commands to the subsequent bus as quickly as possible, and solve the problem of Fig. 7A The tailing and falling problems exist in the display.

[0167] Fig. 9 FIG. 9 is a schematic diagram of the structure of a bus communication device 900 according to an embodiment of the present disclosure. Fig. 9 As shown, the device includes: a receiving module 910, a pressure module 920, and a command module 930.

[0168] A receiving module 910 is used to receive a first bus signal, where the first bus signal includes a first command signal and a first pressure signal corresponding to the first command signal;

[0169] A pressure module 920, configured to adjust the second pressure value to the first pressure value when there is at least one second pressure signal before the first pressure signal in the pressure signal queue and the second pressure value of the at least one second pressure signal is less than the first pressure value of the first pressure signal;

[0170] The command module 930 is used to output at least one second command signal in the command queue and the first command signal, and the at least one second command signal corresponds to at least one second pressure signal.

[0171] In some embodiments, the pressure module is also used to adjust the second pressure value to the first pressure value through a pressure path in a bridge component of the bus communication module. The pressure path is connected to the bridge component of the bus communication module. The bridge component includes a command path, which is used to transmit command signals.

[0172] In some embodiments, the pressure module is also used to store the first pressure signal in a first cache space of the pressure path, in which at least one second pressure signal is also stored; determine the first pressure value as the maximum value of all pressure signals in the first cache space; and adjust the second pressure value to the first pressure value.

[0173] In some embodiments, the pressure module is also used to store the first pressure signal in a second cache space when there is no back pressure in the command path, and to store the first pressure signal in a third cache space when there is back pressure in the command path; determine a first maximum pressure value of all pressure signals in the second cache space, and determine a second maximum pressure value of all pressure signals in the third cache space; take the larger of the first maximum pressure value and the second maximum pressure value as the first pressure value, and adjust the second pressure value to the first pressure value.

[0174] In some embodiments, the pressure module is also used to store the first pressure signal in the second cache space when there is no back pressure in the command path; store the first pressure signal in the third cache space when there is back pressure in the command path and the third cache space is not full; and discard the first pressure signal when there is back pressure in the command path and the third cache space is full.

[0175] In summary, the bus communication device proposed in the present disclosure, by adding a pressure module in the bus communication device, is used to adjust the second pressure value to the first pressure value in the pressure signal queue when the second pressure value of at least one second pressure signal existing before the first pressure signal is less than the first pressure value of the first pressure signal, thereby outputting the corresponding pressure signal and command signal, so as to transmit the high-priority command signal to the subsequent bus as soon as possible, and reduce the delay of high-real-time transmission requests. Furthermore, the bus communication transposition with two cache spaces added can avoid the tailing problem and drop problem existing in one cache space.

[0176] Fig.10 is a schematic structural diagram of an electronic device 1000 for implementing the above bus communication method according to an exemplary embodiment.

[0177] Reference Fig.10 , the electronic device 1000 may include one or more of the following components: a processing component 1002 , a memory 1004 , a power component 1006 , a multimedia component 1008 , an audio component 1010 , an input / output (I / O) interface 1012 , a sensor component 1014 , and a communication component 1016 .

[0178] The processing component 1002 generally controls the overall operation of the electronic device 1000, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 1002 may include one or more processors 1020 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 1002 may include one or more modules to facilitate the interaction between the processing component 1002 and other components. For example, the processing component 1002 may include a multimedia module to facilitate the interaction between the multimedia component 1008 and the processing component 1002.

[0179] The memory 1004 is configured to store various types of data to support operations on the electronic device 1000. Examples of such data include instructions for any application or method operating on the electronic device 1000, contact data, phone book data, messages, pictures, videos, etc. The memory 1004 may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0180] The power supply component 1006 provides power to various components of the electronic device 1000. The power supply component 1006 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 1000.

[0181] The multimedia component 1008 includes a screen that provides an output interface between the electronic device 1000 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 1008 includes a front camera and / or a rear camera. When the electronic device 1000 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0182] The audio component 1010 is configured to output and / or input audio signals. For example, the audio component 1010 includes a microphone (MIC), and when the electronic device 1000 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 1004 or sent via the communication component 1016. In some embodiments, the audio component 1010 also includes a speaker for outputting audio signals.

[0183] I / O interface 1012 provides an interface between processing component 1002 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: home button, volume button, start button, and lock button.

[0184] The sensor assembly 1014 includes one or more sensors for providing various aspects of status assessment for the electronic device 1000. For example, the sensor assembly 1014 can detect the open / closed state of the electronic device 1000, the relative positioning of components, such as the display and keypad of the electronic device 1000, and the sensor assembly 1014 can also detect the position change of the electronic device 1000 or a component of the electronic device 1000, the presence or absence of user contact with the electronic device 1000, the orientation or acceleration / deceleration of the electronic device 1000, and the temperature change of the electronic device 1000. The sensor assembly 1014 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 1014 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 1014 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0185] The communication component 1016 is configured to facilitate wired or wireless communication between the electronic device 1000 and other devices. The electronic device 1000 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio) or a combination thereof. In an exemplary embodiment, the communication component 1016 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 1016 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0186] In an exemplary embodiment, the electronic device 1000 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0187] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 1004 including instructions, and the instructions can be executed by the processor 1020 of the electronic device 1000 to complete the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0188] The embodiments of the present disclosure further provide a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute the bus communication method described in the above embodiments of the present disclosure.

[0189] An embodiment of the present disclosure further provides a computer program product, including a computer program, which executes the bus communication method described in the above embodiment of the present disclosure when a processor executes the computer program.

[0190] A chip is also proposed in an embodiment of the present disclosure, including at least one processor and a communication interface, the communication interface is used to receive signals input into the chip or output signals from the chip, the processor communicates with the communication interface and implements the bus communication method described in the above embodiment of the present disclosure through logic circuits or execution of code instructions.

[0191] Fig.11 FIG. 1 is a schematic diagram of a structure of a chip 1000 for implementing the above bus communication method according to an exemplary embodiment. Fig.11 The chip 1100 includes at least one communication interface 1101 and a processor 1102. The communication interface 1101 is used to receive signals input into the chip 1100 or signals output from the above chip 1100. The processor 1102 communicates with the communication interface 1101 and implements the bus communication method described in the above embodiments of the present disclosure through logic circuits or executing code instructions.

[0192] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0193] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0194] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present disclosure includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present disclosure belong.

[0195] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processing module, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (control method), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or otherwise processing in a suitable manner if necessary, and then stored in a computer memory.

[0196] It should be understood that the various parts of the embodiments of the present disclosure can be implemented by hardware, software, firmware or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0197] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0198] In addition, each functional unit in each embodiment of the present disclosure may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium. The above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0199] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present disclosure. A person skilled in the art may change, modify, substitute and vary the above embodiments within the scope of the present disclosure.

Claims

1. A bus communication module, characterized in that: include: A bus interconnection component, the bus interconnection component having a master device interface and a slave device interface, the master device interface is used to receive a bus signal, and the slave device interface is used to output the bus signal; a bridge component, the bridge component being connected to the master device interface of the bus interconnection component, the bridge component comprising a command path, the bus signal comprising a command signal and a pressure signal corresponding to the command signal, the command path being used to transmit the command signal; A pressure path, wherein the pressure path is connected to the bridge component, and the pressure path is used to transmit the pressure signal and adjust the pressure value of the pressure signal so that the slave device interface of the bus interconnection component outputs the highest priority command signal in the command queue and the low priority command signal before the highest priority command signal.

2. The bus communication module according to claim 1, characterized in that: The pressure path comprises: The first cache space is used to cache a first pressure signal and a second pressure signal, the first pressure signal is a pressure signal when there is back pressure in the command path, and the second pressure signal is a pressure signal when there is no back pressure in the command path.

3. The bus communication module according to claim 1, characterized in that: The pressure path comprises: a second buffer space, the second buffer space being used to buffer a first pressure signal, the first pressure signal being a pressure signal when the command path does not have a back pressure; The third cache space is used to cache a second pressure signal, where the second pressure signal is a pressure signal when there is back pressure in the command path.

4. The bus communication module according to any one of claims 1 to 3, characterized in that: The first end of the bridge component is connected to the master device interface of the first bus interconnection component, and the second end of the bridge component is connected to the slave device interface of the second bus interconnection component.

5. A bus communication method, characterized in that: include: receiving a first bus signal, wherein the first bus signal includes a first command signal and a first pressure signal corresponding to the first command signal; In the pressure signal queue, when there is at least one second pressure signal before the first pressure signal, and the second pressure value of the at least one second pressure signal is less than the first pressure value of the first pressure signal, adjusting the second pressure value to the first pressure value; At least one second command signal in the output command queue and the first command signal, the at least one second command signal corresponding to the at least one second pressure signal.

6. The method according to claim 5, characterized in that: In the pressure signal queue, when there is at least one second pressure signal before the first pressure signal, and a second pressure value of the at least one second pressure signal is less than a first pressure value of the first pressure signal, adjusting the second pressure value to the first pressure value includes: The second pressure value is adjusted to the first pressure value through a pressure path in a bridge component of a bus communication module, wherein the pressure path is connected to the bridge component of the bus communication module, and the bridge component includes a command path for transmitting command signals.

7. The method according to claim 6, characterized in that The adjusting the second pressure value to the first pressure value through the pressure passage in the bridge component of the bus communication module comprises: storing the first pressure signal in a first buffer space of the pressure passage, wherein the first buffer space also stores the at least one second pressure signal; Determining the first pressure value as the maximum value of all pressure signals in the first buffer space; The second pressure value is adjusted to the first pressure value.

8. The method according to claim 6, characterized in that The adjusting the second pressure value to the first pressure value through the pressure passage in the bridge component of the bus communication module comprises: When there is no back pressure in the command path, storing the first pressure signal in the second buffer space, and when there is back pressure in the command path, storing the first pressure signal in the third buffer space; Determining a first maximum pressure value of all pressure signals in the second buffer space, and determining a second maximum pressure value of all pressure signals in the third buffer space; The larger one of the first maximum pressure value and the second maximum pressure value is used as the first pressure value, and the second pressure value is adjusted to the first pressure value.

9. The method according to claim 8, characterized in that The step of storing the first pressure signal in the second buffer space when there is no back pressure in the command path, and storing the first pressure signal in the third buffer space when there is back pressure in the command path comprises: When there is no back pressure in the command path, storing the first pressure signal in the second buffer space; When there is back pressure in the command path and the third cache space is not full, the first pressure signal is stored in the third cache space; when there is back pressure in the command path and the third cache space is full, the first pressure signal is discarded.

10. A bus communication device, characterized in that: include: A receiving module, configured to receive a first bus signal, wherein the first bus signal includes a first command signal and a first pressure signal corresponding to the first command signal; a pressure module, configured to, in a pressure signal queue, adjust the second pressure value to the first pressure value when there is at least one second pressure signal before the first pressure signal and a second pressure value of the at least one second pressure signal is less than a first pressure value of the first pressure signal; The command module is used to output at least one second command signal in the command queue and the first command signal, wherein the at least one second command signal corresponds to the at least one second pressure signal.

11. An electronic device, characterized in that: include: A processor and a memory for storing a computer program that can be run on the processor, wherein the processor executes the method according to any one of claims 5 to 9 when running the computer program.

12. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 5-9.

13. A chip, characterized in that: It includes at least one processor and a communication interface; the communication interface is used to receive a signal input to the chip or a signal output from the chip, and the processor communicates with the communication interface and implements the method as described in any one of claims 5-9 through a logic circuit or executing code instructions.

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