Multi-core series-parallel power module parasitic parameter modeling method based on field-circuit combination

Abstract

The invention discloses a multi-core series-parallel power module parasitic parameter modeling method based on field-circuit combination. The method comprises the steps of S100, determining a current path, S200, establishing a parasitic parameter network, S300, extracting parasitic parameters of a power module, S400, obtaining equivalent parasitic parameters, and S500, establishing a parasitic parameter model. According to the scheme, the parasitic parameter size and symmetry of each parallel branch circuit under different structural designs can be judged more comprehensively and specifically, the method is more effective and simpler, can be completed without depending on very high computing power and time, and is almost zero in error, higher in efficiency and lower in cost compared with an experimental test. The design and production periods of the multi-chip series-parallel power module are shortened, and great assistance is provided for semiconductor enterprises to seize the market, innovatively research and develop and reduce the cost.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor power electronics technology, and in particular to a parasitic parameter modeling method of a multi-core series-parallel power module based on field-circuit combination. Background Art

[0002] The statements in this section merely provide background technical information related to the present application and do not necessarily constitute prior art.

[0003] Whether it is the parallel application of discrete devices or the parallel application of multiple chips, there are common technical requirements, that is, through the reasonable and reliable interconnection structure design, the symmetry of the parasitic parameters of each parallel branch is achieved to achieve the effect of current balanced distribution. However, the parallel application of devices will cause complex current paths in the interconnection structure, which will lead to a large-scale coupled parasitic parameter network, and this network will become more complex as the number of parallel devices increases, and it cannot be used to judge the size and symmetry of the parasitic parameters of each parallel branch under different structural designs. Simple matrix algebra and form cannot obtain the equivalent parasitic parameters of each parallel branch, and experimental testing will inevitably bring errors and low efficiency. Therefore, for the parallel application of devices, a multi-parallel branch parasitic parameter modeling method is needed to quickly extract the equivalent parasitic parameters of each parallel branch from the large-scale coupled parasitic parameter network, thereby forming a forward iterative design process and accelerating the design cycle to determine the optimal interconnection structure.

[0004] In the existing literature "Yuan L, Yu H, Wang X, Zhao Z. Design, simulation and analysis of the low stray inductance bus bar for voltage source inverters[C]. (2011 International Conference on Electrical Machines and Systems. 2011:1-5.)", the method adopted is to calculate the algebraic sum of all elements in each row of the parasitic inductance matrix to obtain the equivalent parasitic inductance of each branch. Although this method effectively establishes the PEEC model (Partial Element Equivalent Circuit Model), this method is only suitable for the case where each conductor segment has the same current. In power modules with multiple chips connected in parallel, there are often different distances between each device and each terminal, different position arrangements, and other situations such as current unequal flow. Therefore, it has limitations and cannot be applied to situations with more complex current paths.

[0005] In the existing literature "Yuan L, Li G, Yu H, Wang X, Lu T, Zhao Z. Improvement for planar bus bars of high power inverters based on segmented evaluation of stray parameters[C]. (2013 International Conference on Electrical Machines and Systems (ICEMS). 2013:1782-1787.)", the method adopted is to divide the busbar into a limited number of partial conductors along the current direction for the large-size laminated busbar structure under the application of multiple capacitors in parallel. Although this method can effectively simulate the parasitic parameters of each partial conductor, the parasitic parameter network brought about by this modeling method is relatively complex, and the accuracy of the model is related to the number of divided conductors, which is difficult to control.

[0006] In view of this, how to solve the problem that the large-scale parasitic parameter network in the multi-chip series-parallel power module is difficult to obtain through simple matrix algebra and form, and experimental testing will inevitably bring errors and low efficiency, has become the subject to be studied by the present invention. Summary of the invention

[0007] The purpose of the present invention is to provide a parasitic parameter modeling method for a multi-core series-parallel power module based on field-circuit combination, so as to solve the problem that a large-scale parasitic parameter network in a multi-chip series-parallel power module is difficult to obtain through simple matrix algebra and form, and experimental testing will inevitably bring errors and low efficiency.

[0008] To achieve the above object, the technical solution adopted by the present invention is: to propose a parasitic parameter modeling method of a multi-core series-parallel power module based on field-circuit combination, the method comprising:

[0009] S100, determining a current path, determining a current loop according to a circuit topology of a power module, wherein the circuit topology of a multi-chip series-parallel power module includes a half-bridge circuit composed of a plurality of upper bridge arm devices and a plurality of lower bridge arm devices, and determining a current path of the current on the power module according to the current loop;

[0010] S200, establishing a parasitic parameter network, according to the electromagnetic induction between the conductor segments between any paths of the multi-chip series-parallel power module, the resistance characteristics of the conductor segments corresponding to each current path, and the proximity effect between the conductor segments of each current path, establishing a parasitic parameter network including self-inductance, mutual inductance, self-resistance and mutual resistance;

[0011] S300, extracting parasitic parameters of the power module, performing electromagnetic field simulation including a simulation path according to a parasitic parameter network and a current path, obtaining a parasitic parameter matrix, and extracting parasitic parameters in the parasitic parameter matrix;

[0012] S400, obtaining equivalent parasitic parameters, importing the extracted parasitic parameters into a simulation circuit, and obtaining equivalent parasitic parameters of the parallel branches of the power module;

[0013] S500: Establish a parasitic parameter model according to the obtained equivalent parasitic parameters.

[0014] The relevant contents of the present invention are explained as follows:

[0015] 1. The implementation of the above technical solution of the present invention aims at the problem that the large-scale parasitic parameter network in the existing multi-chip series-parallel power module is difficult to obtain through simple matrix algebra and form, and experimental testing will inevitably bring errors and low efficiency. In this way, an innovative parasitic parameter modeling method of a multi-core series-parallel power module based on field-circuit combination is designed. The equivalent parasitic parameters of each parallel branch are quickly extracted from the large-scale coupled parasitic parameter network by the finite element physical field and circuit combination, so as to establish a parasitic parameter model; in the parasitic parameter modeling method of the multi-core series-parallel power module, a set of processes including determining the current path, establishing the parasitic parameter network, extracting the parasitic parameters of the power module, obtaining the equivalent parasitic parameters, and establishing the parasitic parameter model are adopted to complete the parasitic parameter modeling of the multi-chip series-parallel power module, and the inductance / resistance coupling between the branches is fully considered. The effect can quickly extract the equivalent parasitic parameters of each parallel branch from a large-scale coupled parasitic parameter network. It is suitable for the design of more complex multi-chip series-parallel power modules with complex current paths, and can quickly and effectively control the extraction of the equivalent parasitic parameters of each parallel branch, thereby forming a forward iterative design process and accelerating the design cycle to determine the optimal interconnection structure. Compared with the traditional method of calculating the parasitic parameters of series-parallel branches in the form of matrix sum, it can more comprehensively and specifically judge the size and symmetry of the parasitic parameters of each parallel branch under different structural designs. This method is more effective and simple, and can be completed without relying on very high computing power and time. Compared with experimental tests, it has almost zero error and higher efficiency, shortens the design and production cycle of multi-chip series-parallel power modules, and provides great help for semiconductor companies to seize the market, innovate research and development, and reduce costs.

[0016] 2. In the above technical solution, the process of implementing step S100 to determine the current path includes the following steps:

[0017] S110, determining a current loop according to a circuit topology of the power module, wherein the circuit topology of the multi-chip series-parallel power module includes a half-bridge circuit composed of a plurality of upper bridge arm devices and a plurality of lower bridge arm devices;

[0018] S120, determining the current path of the current on the power module according to the current loop, and obtaining the current path of the current on the multi-chip series-parallel power module according to the current loop determined in step S110.

[0019] The implementation of the above specific steps provides an accurate current path for the subsequent establishment of a parasitic parameter network, thereby helping to quickly obtain parasitic parameters and providing a correct data basis for the subsequent acquisition of parameters and establishment of models.

[0020] 3. In the above technical solution, the process of implementing step S100 to determine the current path includes the following steps:

[0021] S110, determining a current loop according to a circuit topology of the power module, wherein the circuit topology of the multi-chip series-parallel power module includes a half-bridge circuit composed of a plurality of upper bridge arm devices and a plurality of lower bridge arm devices, wherein the devices of the upper and lower half-bridges are turned on alternately, and the current loop is determined by taking the upper bridge arm device being fully turned on and the lower bridge arm device being fully turned off as an example, at which time the current flows from the DC+ terminal of the half-bridge circuit into the power module, and flows out from the AC terminal after passing through the upper bridge arm device to energize the load, thereby forming a current loop;

[0022] S120. Determine the current path of the current on the power module according to the current loop. According to the current loop determined in step S110, the current path of the current on the multi-chip series-parallel power module is obtained as follows: the current flows into the power module from the DC+ terminal, then flows in through the drain of the upper bridge arm device located in the front position, and flows out from the source of the upper bridge arm device located in the front position, and then flows in through the drain of the upper bridge arm device located in the rear position and flows out from the source, until it flows out through the source of the last upper bridge arm device, and finally flows out of the power module through the AC terminal.

[0023] By implementing the above more specific steps and applying them to more specific multi-chip series-parallel power modules, the accuracy of the parasitic parameter modeling process of the symmetrical multi-chip series-parallel power modules can be better controlled, thereby further shortening the structural design cycle of the multi-chip series-parallel power modules.

[0024] 4. In the above technical solution, in the process of implementing step S200 to determine the parasitic parameter network, according to the situation that the parallel devices in the multi-chip series-parallel power module have uneven current due to the different distances between the drain of the parallel upper bridge arm device and the DC+ terminal, the current path between the drain of the parallel upper bridge arm device in the multi-chip series-parallel power module and the DC+ terminal is represented as self-inductance; according to the situation that electromagnetic induction exists between the conductor segments between any paths in the multi-chip series-parallel power module, the coupled electromagnetic induction between the conductor segments between any paths is represented as mutual inductance; according to the situation that the conductor segments corresponding to each current path in the multi-chip series-parallel power module have resistance characteristics, the resistance of the conductor segments corresponding to each current path is represented as self-resistance; according to the situation that there is a proximity effect between the conductor segments of each current path, the proximity effect between the conductor segments of each current path is represented as mutual resistance; the established parasitic parameter network includes the inductance elements including self-inductance and mutual inductance as described above, and the resistance elements including self-resistance and mutual resistance. By implementing this specific step, for various situations existing in the complex parasitic parameter network of the multi-chip series-parallel power module, the designed and established parasitic parameter network includes the inductance elements including self-inductance and mutual inductance mentioned above, and the resistance elements including self-resistance and mutual resistance. It can more comprehensively and specifically judge the parasitic parameter size and symmetry of each parallel branch under different structural designs, which is suitable for the design of various more complex multi-chip series-parallel power modules.

[0025] 5. In the above technical solution, in the process of implementing step S200 to determine the parasitic parameter network, the multi-chip series-parallel power module has a linear circuit, the time domain circuit model of the linear circuit includes parasitic inductance parameters and parasitic resistance parameters, and the bridge arm terminal voltage u1 in the linear circuit is related to the branch parasitic inductance induced voltage u Lai (i=1,2,3…6), voltage at the parasitic resistance terminal u Raj (j=1,2,3…6) and device on-state voltage u dsk (k=1,2,3…6) satisfies the following formula 1:

[0026] Formula 1;

[0027] Where L matrix and R matrix is the parasitic parameter matrix of the external circuit, i=1,2,3…6, j=1,2,3…6, k=1,2,3…6, L matrix and R matrix They are: , ;

[0028] L Ematrix and R EmatrixThe equivalent parasitic parameters used to evaluate the symmetry design of the parallel branches and analyze the relevant electrical characteristics after decoupling are:

[0029] , ;

[0030] In formula 1, L matrix and R matrix Replace with L Ematrix and R Ematrix , the phasor method is used to equivalently solve the parasitic inductance and parasitic resistance in the linear circuit;

[0031] When a sinusoidal voltage excitation is applied to a linear circuit, the ratio of the sinusoidal voltage excitation to the current response is the impedance corresponding to each parallel branch, which is expressed by Formula 2:

[0032] Formula 2:

[0033] In the formula is the impedance corresponding to the parallel branch, is the voltage across the branch, is the current flowing through a branch, the real part R Hj The imaginary part ωL is the sum of the equivalent parasitic resistance of the branch and the on-state resistance of the IGBT. Hj is the inductive reactance, ω is the angular velocity, and the ratio of the inductive reactance to the angular velocity is the equivalent parasitic inductance of the branch.

[0034] The implementation of more specific steps further fully considers the inductance / resistance coupling effect between each branch, making the obtained parasitic parameter network including self-inductance mutual inductance and self-resistance mutual resistance more accurate, while expanding the scale and reducing the extraction accuracy and extraction speed of related parameters. The use of the mentioned matrices and formulas is more reasonable and accurate, and less computing power is required, without the need for complex calculations.

[0035] 6. In the above technical solution, the process of extracting the parasitic parameters of the power module in step S300 includes the following steps:

[0036] S310, performing electromagnetic field simulation including the simulation path according to the parasitic parameter network and the current path, and obtaining a parasitic parameter matrix by running the electromagnetic field simulation;

[0037] S320, exporting the parasitic parameter matrix and extracting the parasitic parameter L in the parasitic parameter matrix matrix and R matrix .

[0038] By implementing the above specific steps, a reasonable and correct method is adopted to perform the corresponding electromagnetic field simulation according to the parasitic parameter network and the current path, and after running the simulation, the parasitic parameter matrix is ​​obtained, and the parasitic parameters in the parasitic parameter matrix are extracted, so that the obtained parasitic parameters L matrix and R matrix Reasonable and accurate.

[0039] 7. In the technical solution of the second aspect, the process of extracting the parasitic parameters of the power module in step S300 includes the following steps:

[0040] S310, according to the parasitic parameter network and the current path, an electromagnetic field simulation including a simulation path is performed, wherein the drain Source of the upper bridge arm device is set, the DC+ terminal Sink1 is set, the contact surface Sink2 between the bonding wire and the copper clad board is set, and the contact surface Sink3 between the bonding wire and the copper clad board is set; the AC terminal Sink4 is set, the simulation frequency is set, and the electromagnetic field simulation is run to obtain the parasitic parameter matrix;

[0041] S320, exporting the parasitic parameter matrix and extracting the parasitic parameter L in the parasitic parameter matrix matrix and R matrix .

[0042] By implementing the above more specific steps, a more reasonable and correct method is adopted to perform the corresponding electromagnetic field simulation according to the parasitic parameter network and the current path, and after running the simulation, the parasitic parameter matrix is ​​obtained, and the parasitic parameters in the parasitic parameter matrix are extracted, so that the obtained parasitic parameters L matrix and R matrix More reasonable and accurate.

[0043] 8. In the technical solution of the second aspect, the process of implementing step S400 to obtain equivalent parasitic parameters includes the following steps:

[0044] S410, importing the parasitic parameter matrix into the simulation software, and constructing a simulation extraction circuit for the double pulse circuit;

[0045] S420, setting an AC simulation environment in the simulation software;

[0046] S430 , obtaining the impedance of each branch through the ratio of each bridge arm voltage to each branch current, thereby obtaining the equivalent parasitic parameters of the parallel branches of the power module.

[0047] By implementing these specific steps, equivalent parasitic parameters are obtained in a fast and efficient manner, so that the obtained equivalent parasitic parameters are reasonable and accurate.

[0048] 9. In the above technical solution, in the process of implementing step S400 to obtain equivalent parasitic parameters, the equivalent parasitic parameters are obtained using Simplorer software, the parasitic parameter matrix is ​​imported into the Simplorer software, and a simulation extraction circuit is built in the Simplorer software. The double pulse circuit built in the Simplorer software sets up an AC simulation environment in the Simplorer. The application of this solution to the Simplorer software can make the implementation of this step convenient, fast and accurate, but the present invention is not limited thereto, and other similar simulation software can also be used.

[0049] 10. In the above technical solution, in the process of extracting the parasitic parameters of the power module in step S300, the parasitic parameters of the power module are extracted using Ansys Q3D software, and the simulation path of Ansys Q3D software is set according to the parasitic parameter network and the current path, and the drain Source of the upper bridge arm device is set in Ansys Q3D software, the DC+ terminal Sink1 is set, the contact surface Sink2 of the bonding wire and the copper clad board is set, and the contact surface Sink3 of the bonding wire and the copper clad board is set, and the simulation frequency set in Ansys Q3D software is 10MHZ. The application of this solution to Ansys Q3D software can make the implementation of this step convenient, fast and accurate, but the present invention is not limited thereto, and other similar simulation software can also be used.

[0050] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art:

[0051] 1. The present invention aims to solve the problem that the large-scale parasitic parameter network in the existing multi-chip series-parallel power module is difficult to obtain through simple matrix algebra and form, and experimental testing will inevitably bring errors and low efficiency. The present invention innovatively designs a parasitic parameter modeling method for multi-core series-parallel power modules based on field-circuit combination, and adopts a finite element physical field and circuit combination method to quickly extract the equivalent parasitic parameters of each parallel branch from the large-scale coupled parasitic parameter network, so as to establish a parasitic parameter model.

[0052] 2. In the parasitic parameter modeling method of the multi-core series-parallel power module of the present invention, a set of processes including determining the current path, establishing the parasitic parameter network, extracting the parasitic parameters of the power module, obtaining the equivalent parasitic parameters, and establishing the parasitic parameter model are adopted to complete the parasitic parameter modeling of the multi-chip series-parallel power module. The inductance / resistance coupling effect between the branches is fully considered, and the equivalent parasitic parameters of each parallel branch can be quickly extracted from the large-scale coupled parasitic parameter network. It is suitable for the design of more complex multi-chip series-parallel power modules with complex current path situations, and can quickly and effectively controllably extract the equivalent parasitic parameters of each parallel branch, thereby forming a forward iterative design process and accelerating the design cycle to determine a better interconnection structure.

[0053] 3. Compared with the traditional method of calculating the parasitic parameters of series-parallel branches in the form of matrix sum, the present invention can more comprehensively and specifically judge the size and symmetry of the parasitic parameters of each parallel branch under different structural designs. This method is more effective and simple, and can be completed without relying on very high computing power and time. Compared with experimental testing, it has almost zero error and higher efficiency, shortening the design and production cycle of multi-chip series-parallel power modules, and providing great help for semiconductor companies to seize the market, innovate research and development, and reduce costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A circuit topology diagram of a multi-chip series-parallel power module in an embodiment of the present invention;

[0055] Figure 2 It is a current flow path when the upper bridge arm of the multi-chip series-parallel power module in the embodiment of the present invention is turned on and the lower bridge arm is turned off;

[0056] Figure 3 3D schematic diagram of a multi-chip series-parallel power module according to an embodiment of the present invention;

[0057] Figure 4A , Figure 4B is a parasitic parameter model of a multi-chip series-parallel power module in an embodiment of the present invention, wherein Figure 4A is the parasitic inductance parameter model, Figure 4B is the parasitic resistance parameter model;

[0058] Figure 5A , Figure 5B The time domain circuit and frequency domain circuit models of the multi-chip series-parallel power module in the embodiment of the present invention are shown in FIG. Figure 5A For the time domain circuit, Figure 5B is the frequency domain circuit model;

[0059] Figure 6 3D schematic diagram of the upper bridge arm of a multi-chip series-parallel power module in an embodiment of the present invention;

[0060] Figure 7 is a parasitic parameter matrix of a multi-chip series-parallel power module in an embodiment of the present invention;

[0061] Figure 8 A parasitic parameter model of a multi-chip series-parallel power module in an embodiment of the present invention;

[0062] Fig. 9 It is an equivalent parasitic parameter extraction circuit of a multi-chip series-parallel power module in an embodiment of the present invention;

[0063] Fig.10 is the equivalent parasitic parameter of the multi-chip series-parallel power module in the embodiment of the present invention;

[0064] Fig.11 The figure is a schematic diagram of the method flow of an embodiment of the present invention. DETAILED DESCRIPTION

[0065] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0066] The present invention aims to solve the problems that the large-scale parasitic parameter network in the existing multi-chip series-parallel power module is difficult to obtain through simple matrix algebra and form, and experimental testing will inevitably bring errors and low efficiency. An innovative parasitic parameter modeling method for multi-core series-parallel power modules based on field-circuit combination is designed. The finite element physical field and circuit combination method is used to quickly extract the equivalent parasitic parameters of each parallel branch from the large-scale coupled parasitic parameter network, so as to establish a parasitic parameter model.

[0067] The embodiment of the present invention proposes a parasitic parameter modeling method of a multi-core series-parallel power module based on field-circuit combination, and the method comprises:

[0068] S100, determining a current path, and determining the current path according to a circuit structure of a power module;

[0069] S200, establishing a parasitic parameter network, and establishing a parasitic parameter network including self-inductance, mutual inductance, self-resistance and mutual resistance according to the current path;

[0070] S300, extracting parasitic parameters of the power module, extracting the parasitic parameters of the power module according to the parasitic parameter network and the current path;

[0071] S400, obtaining equivalent parasitic parameters, importing the extracted parasitic parameters into a simulation circuit, and obtaining equivalent parasitic parameters of the parallel branches of the power module;

[0072] S500: Establish a parasitic parameter model according to the obtained equivalent parasitic parameters.

[0073] Through the implementation of the embodiment of the present invention, in the parasitic parameter modeling method of the multi-core series-parallel power module, a set of processes including determining the current path, establishing the parasitic parameter network, extracting the parasitic parameters of the power module, obtaining the equivalent parasitic parameters, and establishing the parasitic parameter model are adopted to complete the parasitic parameter modeling of the multi-chip series-parallel power module, which fully considers the inductance / resistance coupling effect between the branches, and can quickly extract the equivalent parasitic parameters of each parallel branch from the large-scale coupled parasitic parameter network. It is suitable for more complex multi-chip series-parallel power module designs with complex current path situations, and can quickly and effectively controllably obtain the parasitic parameters of the multi-chip series-parallel power module. Take the equivalent parasitic parameters of each parallel branch to form a forward iterative design process, accelerate the design cycle to determine the optimal interconnection structure. Compared with the traditional method of calculating the parasitic parameters of series and parallel branches in the form of matrix sum, it can more comprehensively and specifically judge the size and symmetry of the parasitic parameters of each parallel branch under different structural designs. This method is more effective and simple, and can be completed without relying on very high computing power and time. Compared with experimental testing, it has almost zero error and higher efficiency, shortens the design and production cycle of multi-chip series-parallel power modules, and provides great help for semiconductor companies to seize the market, innovate research and development, and reduce costs.

[0074] In one embodiment of the present invention, the process of implementing step S100 to determine the current path includes the following steps:

[0075] S110, determining a current loop according to a circuit topology of the power module;

[0076] S120 . Determine a current path of the current on the power module according to the current loop.

[0077] The implementation of the above specific steps provides an accurate current path for the subsequent establishment of a parasitic parameter network, thereby helping to quickly obtain parasitic parameters and providing a correct data basis for the subsequent acquisition of parameters and establishment of models.

[0078] More specifically, the process of implementing step S100 to determine the current path includes the following steps:

[0079] S110, determining a current loop according to a circuit topology of the power module, wherein the circuit topology of the multi-chip series-parallel power module includes a half-bridge circuit composed of a plurality of upper bridge arm devices and a plurality of lower bridge arm devices, wherein the devices of the upper and lower half-bridges are turned on alternately, and the current loop is determined by taking the upper bridge arm device being fully turned on and the lower bridge arm device being fully turned off as an example, at which time the current flows from the DC+ terminal of the half-bridge circuit into the power module, and flows out from the AC terminal after passing through the upper bridge arm device to energize the load, thereby forming a current loop;

[0080] S120. Determine the current path of the current on the power module according to the current loop. According to the current loop determined in step S110, the current path of the current on the multi-chip series-parallel power module is obtained as follows: the current flows into the power module from the DC+ terminal, then flows in through the drain of the upper bridge arm device located in the front position, and flows out from the source of the upper bridge arm device located in the front position, and then flows in through the drain of the upper bridge arm device located in the rear position and flows out from the source, until it flows out through the source of the last upper bridge arm device, and finally flows out of the power module through the AC terminal.

[0081] By implementing the above more specific steps and applying them to more specific multi-chip series-parallel power modules, the accuracy of the parasitic parameter modeling process of the symmetrical multi-chip series-parallel power modules can be better controlled, thereby further shortening the structural design cycle of the multi-chip series-parallel power modules.

[0082] In another embodiment of the present invention, in the process of implementing step S200 to determine the parasitic parameter network, according to the situation that the parallel devices in the multi-chip series-parallel power module have uneven current due to the different distances between the drain of the parallel upper bridge arm device and the DC+ terminal, the current path between the drain of the parallel upper bridge arm device in the multi-chip series-parallel power module is represented as self-inductance; according to the situation that electromagnetic induction exists between the conductor segments between any paths in the multi-chip series-parallel power module, the coupled electromagnetic induction between the conductor segments between any paths is represented as mutual inductance; according to the situation that the conductor segments corresponding to each current path in the multi-chip series-parallel power module have resistance characteristics, the resistance of the conductor segments corresponding to each current path is represented as self-resistance; according to the situation that there is a proximity effect between the conductor segments of each current path, the proximity effect between the conductor segments of each current path is represented as mutual resistance; the established parasitic parameter network includes the inductance elements including self-inductance and mutual inductance as described above, and the resistance elements including self-resistance and mutual resistance. By implementing this specific step, for various situations existing in the complex parasitic parameter network of the multi-chip series-parallel power module, the designed and established parasitic parameter network includes the inductance elements including self-inductance and mutual inductance mentioned above, and the resistance elements including self-resistance and mutual resistance. It can more comprehensively and specifically judge the parasitic parameter size and symmetry of each parallel branch under different structural designs, which is suitable for the design of various more complex multi-chip series-parallel power modules.

[0083] More specifically, in the process of implementing step S200 to determine the parasitic parameter network, the multi-chip series-parallel power module has a linear circuit, and the time domain circuit model of the linear circuit includes parasitic inductance parameters and parasitic resistance parameters. The bridge arm terminal voltage u1 in the linear circuit is related to the branch parasitic inductance induced voltage u Lai (i=1,2,3…6), voltage at the parasitic resistance terminal u Raj (j=1,2,3…6) and device on-state voltage u dsk (k=1,2,3…6) satisfies the following formula 1:

[0084] (Formula 1);

[0085] Where L matrix and R matrix is the parasitic parameter matrix of the external circuit, i=1,2,3…6, j=1,2,3…6, k=1,2,3…6, L matrix and R matrix They are: , ;

[0086] L Ematrix and R Ematrix The equivalent parasitic parameters used to evaluate the symmetry design of the parallel branches and analyze the relevant electrical characteristics after decoupling are:

[0087] , ;

[0088] In formula 1, L matrix and R matrix Replace with L Ematrix and R Ematrix , the phasor method is used to equivalently solve the parasitic inductance and parasitic resistance in the linear circuit;

[0089] When a sinusoidal voltage excitation is applied to a linear circuit, the ratio of the sinusoidal voltage excitation to the current response is the impedance corresponding to each parallel branch, which is expressed by Formula 2:

[0090] Formula 2:

[0091] In the formula is the impedance corresponding to the parallel branch, is the voltage across the branch, is the current flowing through a branch, the real part R Hj The imaginary part ωL is the sum of the equivalent parasitic resistance of the branch and the on-state resistance of the IGBT. Hjis the inductive reactance, ω is the angular velocity, and the ratio of the inductive reactance to the angular velocity is the equivalent parasitic inductance of the branch.

[0092] The implementation of more specific steps further fully considers the inductance / resistance coupling effect between each branch, making the obtained parasitic parameter network including self-inductance mutual inductance and self-resistance mutual resistance more accurate, while expanding the scale and reducing the extraction accuracy and extraction speed of related parameters. The use of the mentioned matrices and formulas is more reasonable and accurate, and less computing power is required, without the need for complex calculations.

[0093] In another embodiment of the present invention, the process of extracting the parasitic parameters of the power module in step S300 includes the following steps:

[0094] S310, performing electromagnetic field simulation including the simulation path according to the parasitic parameter network and the current path, and obtaining a parasitic parameter matrix;

[0095] S320, extracting parasitic parameters L in the parasitic parameter matrix matrix and R matrix .

[0096] By implementing the above specific steps, a reasonable and correct method is adopted to perform the corresponding electromagnetic field simulation according to the parasitic parameter network and the current path, and after running the simulation, the parasitic parameter matrix is ​​obtained, and the parasitic parameters in the parasitic parameter matrix are extracted, so that the obtained parasitic parameters L matrix and R matrix Reasonable and accurate.

[0097] More specifically, the process of extracting the parasitic parameters of the power module in step S300 includes the following steps:

[0098] S310, according to the parasitic parameter network and the current path, an electromagnetic field simulation including a simulation path is performed, wherein the drain Source of the upper bridge arm device is set, the DC+ terminal Sink1 is set, the contact surface Sink2 between the bonding wire and the copper clad board is set, and the contact surface Sink3 between the bonding wire and the copper clad board is set; the AC terminal Sink4 is set, the simulation frequency is set, and the electromagnetic field simulation is run to obtain the parasitic parameter matrix;

[0099] S320, exporting the parasitic parameter matrix and extracting the parasitic parameter L in the parasitic parameter matrix matrix and R matrix .

[0100] By implementing the above more specific steps, a more reasonable and correct method is adopted to perform the corresponding electromagnetic field simulation according to the parasitic parameter network and the current path, and after running the simulation, the parasitic parameter matrix is ​​obtained, and the parasitic parameters in the parasitic parameter matrix are extracted, so that the obtained parasitic parameters L matrix and Rmatrix More reasonable and accurate.

[0101] In the process of extracting the parasitic parameters of the power module in step S300, the parasitic parameters of the power module are extracted using Ansys Q3D software, and the simulation path of the Ansys Q3D software is set according to the parasitic parameter network and the current path, and the drain Source of the upper bridge arm device is set in the Ansys Q3D software, the DC+ terminal Sink1 is set, the contact surface Sink2 between the bonding wire and the copper clad board is set, and the contact surface Sink3 between the bonding wire and the copper clad board is set, and the simulation frequency set in the Ansys Q3D software is 10MHZ. The application of this solution to the Ansys Q3D software can make the implementation of this step convenient, fast and accurate, but the present invention is not limited thereto, and other similar simulation software can also be used.

[0102] In one embodiment of the present invention, the process of obtaining equivalent parasitic parameters in step S400 includes the following steps:

[0103] S410, importing the parasitic parameter matrix into the simulation software, and constructing a simulation extraction circuit for the double pulse circuit;

[0104] S420, setting an AC simulation environment in the simulation software;

[0105] S430 , obtaining the impedance of each branch through the ratio of each bridge arm voltage to each branch current, thereby obtaining the equivalent parasitic parameters of the parallel branches of the power module.

[0106] By implementing these specific steps, equivalent parasitic parameters are obtained in a fast and efficient manner, so that the obtained equivalent parasitic parameters are reasonable and accurate.

[0107] More specifically, in the process of implementing step S400 to obtain equivalent parasitic parameters, the equivalent parasitic parameters are obtained using Simplorer software, the parasitic parameter matrix is ​​imported into the Simplorer software, and a simulation extraction circuit is built in the Simplorer software. The double pulse circuit built in the Simplorer software sets up an AC simulation environment in Simplorer. The application of this solution to the Simplorer software can make the implementation of this step convenient, fast and accurate, but the present invention is not limited thereto, and other similar simulation software can also be used.

[0108] In addition, the technical solution of the parasitic parameter modeling method of a multi-core series-parallel power module based on field-circuit combination of the present invention is introduced by using one of the detailed method embodiments.

[0109] In this detailed method embodiment, a method for modeling parasitic parameters of a multi-core series-parallel power module based on field-circuit combination is used to model the parasitic parameters of a multi-chip series-parallel power module using a field-circuit combination method. The method comprises the following steps:

[0110] S100, determining a current path, determining the current path according to the circuit structure of the power module; specifically comprising the following steps:

[0111] S110. Determine the current loop according to the circuit topology of the power module. The circuit topology of the multi-chip series-parallel power module includes a half-bridge circuit composed of multiple upper bridge arm devices and multiple lower bridge arm devices, wherein the devices of the upper and lower half bridges are turned on alternately. The current loop is determined by taking the upper bridge arm device being fully turned on and the lower bridge arm device being fully turned off as an example. At this time, the current flows into the power module from the DC+ terminal of the half-bridge circuit, flows out from the AC terminal after passing through the upper bridge arm device to energize the load, thereby forming a current loop.

[0112] S120. Determine the current path of the current on the power module according to the current loop. According to the current loop determined in step S110, the current path of the current on the multi-chip series-parallel power module is obtained as follows: the current flows into the power module from the DC+ terminal, then flows in through the drain of the upper bridge arm device located in the front position, and flows out from the source of the upper bridge arm device located in the front position, and then flows in through the drain of the upper bridge arm device located in the rear position and flows out from the source, until it flows out through the source of the last upper bridge arm device, and finally flows out of the power module through the AC terminal.

[0113] S200, establishing a parasitic parameter network, and establishing a parasitic parameter network including self-inductance, mutual inductance, and self-resistance and mutual resistance according to the current path; specifically comprising the following steps:

[0114] In the process of implementing step S200 to determine the parasitic parameter network, according to the situation that the parallel devices in the multi-chip series-parallel power module have uneven current due to the different distances between the drain of the parallel upper bridge arm device and the DC+ terminal, the current path between the drain of the parallel upper bridge arm device in the multi-chip series-parallel power module is represented as self-inductance; according to the situation that electromagnetic induction exists between the conductor segments between any paths in the multi-chip series-parallel power module, the coupled electromagnetic induction between the conductor segments between any paths is represented as mutual inductance; according to the situation that the conductor segments corresponding to each current path in the multi-chip series-parallel power module have resistance characteristics, the resistance of the conductor segments corresponding to each current path is represented as self-resistance; according to the situation that there is a proximity effect between the conductor segments of each current path, the proximity effect between the conductor segments of each current path is represented as mutual resistance; the established parasitic parameter network includes the inductance elements including self-inductance and mutual inductance as described above, and the resistance elements including self-resistance and mutual resistance.

[0115] In the process of implementing step S200 to determine the parasitic parameter network, the multi-chip series-parallel power module has a linear circuit, and the time domain circuit model of the linear circuit includes parasitic inductance parameters and parasitic resistance parameters. The bridge arm terminal voltage u1 in the linear circuit is related to the branch parasitic inductance induced voltage u Lai , voltage at the parasitic resistance u Raj And the device on-state voltage u dsk Satisfies the following formula 1:

[0116] Formula 1;

[0117] Where L matrix and R matrix is the parasitic parameter matrix of the external circuit, i=1,2,3…6, j=1,2,3…6, k=1,2,3…6, L matrix and R matrix They are: , ;

[0118] L Ematrix and R Ematrix The equivalent parasitic parameters used to evaluate the symmetry design of the parallel branches and analyze the relevant electrical characteristics after decoupling are:

[0119] , ;

[0120] In formula 1, L matrix and R matrix Replace with L Ematrix and R Ematrix , the phasor method is used to equivalently solve the parasitic inductance and parasitic resistance in the linear circuit;

[0121] When a sinusoidal voltage excitation is applied to a linear circuit, the ratio of the sinusoidal voltage excitation to the current response is the impedance corresponding to each parallel branch, which is expressed by Formula 2:

[0122] ;

[0123] In the formula is the impedance corresponding to the parallel branch, is the voltage across the branch, is the current flowing through a branch, the real part R Hj The imaginary part ωL is the sum of the equivalent parasitic resistance of the branch and the on-state resistance of the IGBT. Hj is the inductive reactance, and its ratio to the angular velocity is the equivalent parasitic inductance of the branch.

[0124] S300, extracting parasitic parameters of the power module, extracting the parasitic parameters of the power module according to the parasitic parameter network and the current path; specifically comprising the following steps:

[0125] S310, according to the parasitic parameter network and the current path, an electromagnetic field simulation including a simulation path is performed, wherein the drain Source of the upper bridge arm device is set, the DC+ terminal Sink1 is set, the contact surface Sink2 between the bonding wire and the copper clad board is set, and the contact surface Sink3 between the bonding wire and the copper clad board is set; the AC terminal Sink4 is set, the simulation frequency is set, and the electromagnetic field simulation is run to obtain the parasitic parameter matrix;

[0126] S320, exporting the parasitic parameter matrix and extracting the parasitic parameter L in the parasitic parameter matrix matrix and R matrix .

[0127] S400, obtaining equivalent parasitic parameters, importing the extracted parasitic parameters into a simulation circuit, and obtaining equivalent parasitic parameters of the parallel branches of the power module; specifically comprising the following steps:

[0128] S410, importing the parasitic parameter matrix into the simulation software, and constructing a simulation extraction circuit for the double pulse circuit;

[0129] S420, setting an AC simulation environment in the simulation software;

[0130] S430 , obtaining the impedance of each branch through the ratio of each bridge arm voltage to each branch current, thereby obtaining the equivalent parasitic parameters of the parallel branches of the power module.

[0131] S500: Establish a parasitic parameter model according to the obtained equivalent parasitic parameters.

[0132] Next, a multi-chip series-parallel power module with a specific structure is used as an example to illustrate the circuit topology of the multi-chip series-parallel power module in the embodiment of the present invention, including 18 chips of the upper bridge arm, which are chips h of the first branch to the sixth branch. 1i 、h 2i 、h 3i (i=1, 2, 3, 4, 5, 6); the 18 chips of the lower bridge arm are chips l from the first branch to the sixth branch 1i , l 2i , l 3i (i=1, 2, 3, 4, 5, 6).

[0133] Step S100: determining a current path according to a circuit structure of a power module.

[0134] Step S110, determine the current path according to the circuit topology of the power module. For a half-bridge circuit, the devices of the upper and lower half bridges are turned on alternately. For example, when the upper bridge arm devices are fully turned on and the lower bridge arm devices are fully turned off, the current flows in from the DC+ terminal, passes through the upper bridge arm MOSFETs, and flows out from the AC terminal to supply power to the load. The current path of this process is as follows: Figure 2 shown.

[0135] Step S120: determining a current path of the current on the power module according to the current loop. Figure 3 The multi-chip series-parallel power module in this embodiment is shown, which includes a DC+ terminal, chips from the first branch to the sixth branch of the upper bridge arm, and a 1i 2.h 2i 3.h 3i 4. AC terminal 5. Chip l from the first branch to the sixth branch of the lower bridge arm 1i 6. l 2i 7. l 3i 8, DC-terminal 9 and DBC substrate 10. According to the current loop obtained in step S110, the current path of the current on the power module should be: first flow from the DC+ terminal 1 into the power module, then pass through the upper bridge arm device h 1i 2 flows into the drain and out of its source; then it flows through the upper bridge arm device h 2i 3's drain and flows out from its source; then it flows through the upper bridge arm device h 3i 4 flows into the drain and out of its source; finally, it flows out of the power module through the AC terminal 5.

[0136] Step S200, determining the parasitic parameter network including self-inductance, mutual inductance, self-resistance and mutual resistance according to the current path obtained in step S100. Figure 3 , the six MOSFETs in the upper bridge arm h 11 、h 12 …h 16 For example, since their drains are at different distances from the DC+ terminal 1, the parasitic parameters between the parallel devices will be inconsistent, resulting in uneven current in the parallel devices. Due to the difference in the size of the parasitic parameters, the current imbalance can be reflected to a certain extent. Therefore, the path from the drain of the parallel MOSFETs to the DC+ terminal 1 can be represented as self-inductance. Due to electromagnetic induction, there is a coupled mutual inductance between the conductor segments between any paths. In fact, the conductor segments corresponding to each current path also have resistance characteristics, and due to the influence of the proximity effect, there are also mutual resistance parameters between the paths, so the parasitic parameter model needs to include both inductance and resistance elements. Finally, the established parasitic parameter model that considers self-inductance, mutual inductance, self-resistance, and mutual resistance is as follows. Figure 4A , Figure 4BAs shown, for a clearer display, the parasitic inductance and parasitic resistance are drawn separately, where Figure 4A is the parasitic inductance parameter model, Figure 4B This is a parasitic resistance parameter model. To make the diagram clear, only part of the mutual inductance and mutual resistance are drawn in the figure.

[0137] Taking T1 fully turned on as an example, Figure 5 shows the time domain circuit model of the six parallel branches, which includes parasitic resistance and parasitic inductance parameters. For the sake of clarity, the mutual inductance and mutual resistance are omitted in the figure. Since the upper bridge arm device is fully turned on, it can be equivalent to a resistor R on .exist Figure 5A In the figure, the bridge arm voltage u1 and the branch parasitic inductance induced voltage u Lai (i=1,2,3…6), voltage at the parasitic resistance terminal u Raj (j=1,2,3…6) and device on-state voltage u dsk (k=1,2,3…6) satisfies the following formula 1:

[0138] Formula 1

[0139] Where L matrix and R matrix are the parasitic parameter matrices of the external circuit extracted from Q3D, which are:

[0140] , ;

[0141] L Ematrix and R Ematrix The equivalent parasitic parameters used to evaluate the symmetry design of the parallel branches and analyze the relevant electrical characteristics after decoupling are:

[0142] , .

[0143] The relationship between the bridge arm terminal voltages u2 and u3 and the branch parasitic inductance induced voltage, the parasitic resistance terminal voltage and the device on-voltage is similar to that of u1 and will not be repeated here.

[0144] However, in formula (1), there are both inductance and resistance elements, so it is difficult to directly obtain L by mathematical derivation. Ematrix and R Ematrix Since the decoupled equivalent parasitic parameters have the same VI characteristics as the original parasitic parameters, L is replaced by matrix and R matrix Replace with L Ematrix and R EmatrixThe same is true. Based on this, the phasor method can be used to equivalently solve the parasitic inductance and parasitic resistance in the linear circuit. The corresponding circuit is as follows Figure 5B As shown. When a sinusoidal voltage excitation is applied to the circuit, the ratio of the voltage excitation to the current response is the impedance corresponding to each parallel branch, which can be expressed by Formula 2. The real part R Hj It is the sum of the equivalent parasitic resistance of the branch and the on-state resistance of the IGBT. Hj is the inductive reactance, and its ratio to the angular velocity is the equivalent parasitic inductance of the branch. j is the branch number, (1, 2, 3…6).

[0145] ; Formula 2

[0146] With the help of Q3D and Simplorer's field-circuit joint simulation, the equivalent parasitic parameters of each parallel branch can be extracted through the above-mentioned phasor method.

[0147] Step S300: extracting parasitic parameters of the power module using Q3D.

[0148] Step S310: Set the simulation path of Q3D according to the current path of the current on the power module obtained in step 2. Since the lower bridge arm device is turned off, no current flows through the lower bridge arm. Therefore, only the parasitic parameters of the upper bridge arm need to be extracted at this time. Figure 6 The 3D model of the upper bridge arm of the multi-chip series-parallel power module is shown. The Sink and Source for parasitic parameter extraction can be set according to the parasitic parameter model shown in Figure 4. Figure 6 As shown, set the upper bridge arm device h 1i The drain of 2 is Source1-1 to Source1-6, and the DC+ terminal 1 is set to Sink1; set the upper bridge arm device h 2i The drain of 3 is Source2-1 to Source2-6, and the contact surface between the bonding wire 11 and the DBC substrate is set as Sink2; the upper bridge arm device h is set 3i The drain of 3 is Source3-1 to Source3-6, and the contact surface between the bonding wire 12 and the DBC substrate is set as Sink3; the upper bridge arm device h 3i The source of 4 is Source4-1 to Source4-6, and the AC terminal 5 is set to Sink4. After setting the Source and Sink for parasitic parameter extraction, the simulation frequency needs to be set in Q3D. In this embodiment, the simulation frequency is set to 10 MHz. Then run the simulation to get the parasitic parameter matrix, as shown in Figure 7 shown.

[0149] Step S320, export the parasitic parameter matrix. After using Q3D to extract the parasitic parameters of the upper bridge arm of the multi-chip series-parallel power module, use the function of Q3D software to import the parasitic parameter matrix into Simplorer, such as Figure 8 shown.

[0150] Step S400, using Simplorer to obtain equivalent parasitic parameters of the parallel branches of the power module.

[0151] Step S410: Build a simulation extraction circuit in Simplorer. Fig. 9 The double pulse circuit shown.

[0152] Step S420: Setting up an AC simulation environment in Simplorer.

[0153] Step S430, obtaining the impedance of each branch through the ratio of each bridge arm voltage to each branch current.

[0154] Step S500: According to the obtained equivalent parasitic parameters, the following can be obtained: Fig.10 The parasitic parameter model shown.

[0155] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A parasitic parameter modeling method for multi-chip series-parallel power modules based on field-circuit combination, characterized in that: The method comprises: S100, determining a current path, determining a current loop according to a circuit topology of a power module, wherein the circuit topology of a multi-chip series-parallel power module includes a half-bridge circuit composed of a plurality of upper bridge arm devices and a plurality of lower bridge arm devices, and determining a current path of the current on the power module according to the current loop; S200, establishing a parasitic parameter network, according to the electromagnetic induction between the conductor segments between any paths of the multi-chip series-parallel power module, the resistance characteristics of the conductor segments corresponding to each current path, and the proximity effect between the conductor segments of each current path, establishing a parasitic parameter network including self-inductance, mutual inductance, self-resistance and mutual resistance; S300, extracting parasitic parameters of the power module, performing electromagnetic field simulation including a simulation path according to a parasitic parameter network and a current path, obtaining a parasitic parameter matrix, and extracting parasitic parameters in the parasitic parameter matrix; S400, obtaining equivalent parasitic parameters, importing the extracted parasitic parameters into a simulation circuit, and obtaining equivalent parasitic parameters of the parallel branches of the power module; S500: Establish a parasitic parameter model according to the obtained equivalent parasitic parameters.

2. The parasitic parameter modeling method of a multi-chip series-parallel power module based on field-circuit combination according to claim 1 is characterized in that: The process of implementing step S100 to determine the current path includes the following steps: S110, determining a current loop according to a circuit topology of the power module, wherein the circuit topology of the multi-chip series-parallel power module includes a half-bridge circuit composed of a plurality of upper bridge arm devices and a plurality of lower bridge arm devices; S120, determining the current path of the current on the power module according to the current loop, and obtaining the current path of the current on the multi-chip series-parallel power module according to the current loop determined in step S110.

3. The parasitic parameter modeling method of a multi-chip series-parallel power module based on field-circuit combination according to claim 1, characterized in that: The process of implementing step S100 to determine the current path includes the following steps: S110, determining a current loop according to a circuit topology of the power module, wherein the circuit topology of the multi-chip series-parallel power module includes a half-bridge circuit composed of a plurality of upper bridge arm devices and a plurality of lower bridge arm devices, wherein the devices of the upper and lower half-bridges are turned on alternately, and the current loop is determined by taking the upper bridge arm device being fully turned on and the lower bridge arm device being fully turned off as an example, at which time the current flows from the DC+ terminal of the half-bridge circuit into the power module, and flows out from the AC terminal after passing through the upper bridge arm device to energize the load, thereby forming a current loop; S120. Determine the current path of the current on the power module according to the current loop. According to the current loop determined in step S110, the current path of the current on the multi-chip series-parallel power module is obtained as follows: the current flows into the power module from the DC+ terminal, then flows in through the drain of the upper bridge arm device located in the front position, and flows out from the source of the upper bridge arm device located in the front position, and then flows in through the drain of the upper bridge arm device located in the rear position and flows out from the source, until it flows out through the source of the last upper bridge arm device, and finally flows out of the power module through the AC terminal.

4. The parasitic parameter modeling method of a multi-chip series-parallel power module based on field-circuit combination according to claim 1 is characterized in that: In the process of implementing step S200 to determine the parasitic parameter network, according to the situation that the parallel devices have uneven current due to the different distances between the drain of the parallel upper bridge arm device and the DC+ terminal in the multi-chip series-parallel power module, the current path between the drain of the parallel upper bridge arm device and the DC+ terminal in the multi-chip series-parallel power module is represented as self-inductance; according to the situation that electromagnetic induction exists between the conductor segments between any paths in the multi-chip series-parallel power module, the coupled electromagnetic induction between the conductor segments between any paths is represented as mutual inductance; according to the situation that the conductor segments corresponding to each current path in the multi-chip series-parallel power module have resistance characteristics, the resistance of the conductor segments corresponding to each current path is represented as self-resistance; According to the situation that there is a proximity effect between the conductor segments of each current path, the proximity effect between the conductor segments of each current path is expressed as mutual resistance; the established parasitic parameter network includes the inductance element including self-inductance and mutual inductance mentioned above, and the resistance element including self-resistance and mutual resistance.

5. The parasitic parameter modeling method of a multi-chip series-parallel power module based on field-circuit combination according to claim 4, characterized in that: In the process of implementing step S200 to determine the parasitic parameter network, the multi-chip series-parallel power module has a linear circuit, and the time domain circuit model of the linear circuit includes parasitic inductance parameters and parasitic resistance parameters. The bridge arm terminal voltage in the linear circuit u 1 and branch parasitic inductance induced voltage u Lai , parasitic resistance terminal voltage u Raj And the device on-state voltage u dsk Satisfies the following formula 1: ; Formula 1 In the formula L matrix and R matrix is the parasitic parameter matrix of the external circuit, i=1,2,3…6, j=1,2,3…6, k=1,2,3…6, L matrix and R matrix They are: 、 ； L Ematrix and R Ematrix The equivalent parasitic parameters used to evaluate the symmetry design of the parallel branches and analyze the relevant electrical characteristics after decoupling are: 、 ； In formula 1, L matrix and R matrix Replace with L Ematrix and R Ematrix , the phasor method is used to equivalently solve the parasitic inductance and parasitic resistance in the linear circuit; When a sinusoidal voltage excitation is applied to a linear circuit, the ratio of the sinusoidal voltage excitation to the current response is the impedance corresponding to each parallel branch, which is expressed by Formula 2: ; Formula 2 In the formula is the impedance corresponding to the parallel branch, is the voltage across the branch, is the current flowing through a branch, real part R Hj The imaginary part is the sum of the equivalent parasitic resistance of the branch and the on-state resistance of the IGBT. ωL Hj is the inductive reactance, ω is the angular velocity, and the ratio of the inductive reactance to the angular velocity is the equivalent parasitic inductance of the branch.

6. The parasitic parameter modeling method of a multi-chip series-parallel power module based on field-circuit combination according to claim 1 is characterized in that: The process of extracting the parasitic parameters of the power module in step S300 includes the following steps: S310, performing electromagnetic field simulation including the simulation path according to the parasitic parameter network and the current path, and obtaining a parasitic parameter matrix by running the electromagnetic field simulation; S320, exporting the parasitic parameter matrix and extracting the parasitic parameters in the parasitic parameter matrix L matrix and R matrix .

7. The parasitic parameter modeling method of a multi-chip series-parallel power module based on field-circuit combination according to claim 6, characterized in that: The process of extracting the parasitic parameters of the power module in step S300 includes the following steps: S310, according to the parasitic parameter network and the current path, an electromagnetic field simulation including a simulation path is performed, wherein the drain Source of the upper bridge arm device is set, the DC+ terminal Sink1 is set, the contact surface Sink2 between the bonding wire and the copper clad board is set, and the contact surface Sink3 between the bonding wire and the copper clad board is set; the AC terminal Sink4 is set, the simulation frequency is set, and the electromagnetic field simulation is run to obtain the parasitic parameter matrix; S320, exporting the parasitic parameter matrix and extracting the parasitic parameters in the parasitic parameter matrix L matrix and R matrix .

8. The parasitic parameter modeling method of a multi-chip series-parallel power module based on field-circuit combination according to claim 7 is characterized in that: The process of implementing step S400 to obtain equivalent parasitic parameters includes the following steps: S410, importing the parasitic parameter matrix into the simulation software, and constructing a simulation extraction circuit for the double pulse circuit; S420, setting an AC simulation environment in the simulation software; S430 , obtaining the impedance of each branch through the ratio of each bridge arm voltage to each branch current, thereby obtaining the equivalent parasitic parameters of the parallel branches of the power module.

9. The parasitic parameter modeling method of a multi-chip series-parallel power module based on field-circuit combination according to claim 8, characterized in that: In the process of implementing step S400 to obtain equivalent parasitic parameters, the Simplorer software is used to obtain equivalent parasitic parameters, the parasitic parameter matrix is ​​imported into the Simplorer software, a simulation extraction circuit is built in the Simplorer software, a dual pulse circuit is built in the Simplorer software, and an AC simulation environment is set in Simplorer.

10. The parasitic parameter modeling method of a multi-chip series-parallel power module based on field-circuit combination according to claim 9, characterized in that: In the process of implementing step S300 to extract the parasitic parameters of the power module, the parasitic parameters of the power module are extracted using Ansys Q3D software, and the simulation path of the Ansys Q3D software is set according to the parasitic parameter network and the current path. The drain Source of the upper bridge arm device is set in the Ansys Q3D software, the DC+ terminal Sink1 is set, the contact surface Sink2 between the bonding wire and the copper clad board is set, and the contact surface Sink3 between the bonding wire and the copper clad board is set. The simulation frequency set in the Ansys Q3D software is 10MHZ.

Images