A method for outputting RTL netlist files at a specified level and related equipment

Abstract

The present application discloses a method for outputting an RTL netlist file at a specified level and related equipment, including: reading a high-level design file based on a Python file reading script; inputting the high-level design file into a syntax parsing module for syntax analysis, and dividing the hierarchical structure information of each module based on the number of resources of each module; performing integration operations through a Python integration script based on the target modules selected by the target user in the hierarchical structure information of each module to generate multiple synthesizable files; generating multiple parallel synthesis tasks based on all synthesizable files; calling an external synthesis tool to perform synthesis operations on all synthesis tasks and obtain multiple synthesis data; sending all synthesis data to a netlist collection module for connection operations to generate a complete RTL netlist; performing format conversion operations on the complete RTL netlist based on the specified format selected by the target user to generate a target RTL netlist file.

Description

Technical Field

[0001] The present invention relates to the field of electronic design automation, and more specifically, to a method for outputting an RTL netlist file at a specified level and related equipment. Background Art

[0002] As the complexity and scale of IC designs increase rapidly, the number of logic gates and modules included in the design has increased significantly, making the synthesis process more complex and time-consuming. Modern chip designs may contain millions to billions of logic gates and multiple functional modules, and the functions and performance requirements of these modules vary. Existing synthesis tools face at least the following challenges when dealing with such large designs:

[0003] 1. Computational complexity: Synthesis tools need to optimize the logic of the entire design, including logic synthesis, timing constraint checking, power optimization, and area control. These optimization processes become more time-consuming as the design scale increases.

[0004] 2. Resource limitation: Although modern synthesis tools have parallel processing capabilities, they can usually only perform simple parallelization at the task level, and it is difficult to perform customized parallel synthesis at the module level or level according to the designer's needs. This results in the synthesis process not being able to fully utilize the system's computing resources.

[0005] Therefore, it is necessary to propose a method for outputting an RTL netlist file at a specified level and a related device to solve at least some of the above problems. Summary of the invention

[0006] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0007] In a first aspect, the present application proposes a method for outputting an RTL netlist file at a specified level, comprising:

[0008] Read high-level design files based on Python file reading scripts;

[0009] Input the high-level design file into the syntax parsing module for syntax analysis, and divide the hierarchical structure information of each module based on the number of resources of each module, wherein the syntax parsing module is constructed based on the combination of regular expressions and a specific Python parsing library;

[0010] Based on the target module selected by the target user in the hierarchical structure information of each module, an integration operation is performed through a Python integration script to generate multiple synthesizable files;

[0011] Generate multiple parallel synthesis tasks based on all synthesizable files by calling a specific Python concurrent execution library, wherein each of the above synthesis tasks is used to perform synthesis operations on one or more specified hierarchical modules;

[0012] Calling external synthesis tools to perform synthesis operations on all synthesis tasks and obtain multiple synthesis data;

[0013] Send all the above comprehensive data to the netlist collection module for connection operation to generate a complete RTL netlist;

[0014] The complete RTL netlist is converted into a target RTL netlist file based on the specified format selected by the target user.

[0015] In a feasible implementation manner, the high-level design file is input into the syntax analysis module for syntax analysis, and the hierarchical structure information of each module is divided based on the number of resources of each module, including:

[0016] Parsing the high-level design file based on the syntax parsing module to generate an abstract syntax tree;

[0017] Extracting definition information of each module from the abstract syntax tree, wherein the definition information includes module name, port information, information of other instantiated modules, and dependency relationship with other modules;

[0018] Based on the definition information of each module, count the number of resources in each module;

[0019] Based on the above resource quantity information and the instantiation relationship of the modules, the hierarchical structure information of each module is constructed.

[0020] In a feasible implementation manner, the above-mentioned syntax parsing module performs a parsing operation on the above-mentioned high-level design file to generate an abstract syntax tree, including:

[0021] Performing a preliminary parsing operation on the high-level design file based on the regular expression to obtain a preliminary parsed file, wherein the regular expression includes a module definition expression, a port declaration expression, a signal declaration expression, a module instantiation expression, and an assignment statement expression;

[0022] Perform deep parsing on the unparsed file based on the above-mentioned specific Python parsing library to obtain a deep parsed file;

[0023] Based on the preliminary parsing file and the deep parsing file, the abstract syntax tree is generated.

[0024] In a feasible implementation, the target modules selected by the target user based on the hierarchical information of the modules are integrated through a Python integration script to generate multiple synthesizable files, including:

[0025] Recursively extract all target modules and the dependent modules corresponding to the target modules according to the target modules selected above;

[0026] All target modules and dependent modules corresponding to the target modules are divided into files based on preset division rules to generate multiple synthesizable files, wherein the above division rules are determined based on the objective function, and the above objective function is based on resource consumption items, synthesis time items, module size items and dependency items.

[0027] In a feasible implementation, the above objective function is determined based on the following formula:

[0028]

[0029] in, For the above resource consumption items, is the above-mentioned comprehensive time term, is the module size item above, For the above dependency items, , , and are the weight coefficients of each item, is the resource consumption of the ith module, is the total resource consumption, is the comprehensive time of the ith module, is the total integrated time, is the size of the i-th module, is the size of the largest module, represents the dependency weight between module i and module j, N is the number of files generated, is the module set of the kth file.

[0030] In a feasible implementation, the above-mentioned specific Python parsing library includes the pyvhdlparser library and the pyverilog library, the above-mentioned specific Python concurrent execution library includes the multiprocessing library and the concurrent.futures library, and the above-mentioned external synthesis tool includes Vivado and QuartusPrime.

[0031] The above method further includes:

[0032] Obtain the above high-level design file format suffix information, current system resource information and target FPGA information;

[0033] Determine the above-mentioned specific Python parsing library based on the above-mentioned file format suffix information;

[0034] Determine the Python concurrent execution library based on the current system resource information;

[0035] The external synthesis tool is determined based on the target FPGA information.

[0036] In a feasible implementation manner, all the above-mentioned integrated data are sent to the netlist collection module for connection operation to generate a complete RTL netlist, including:

[0037] Based on the netlist collection module, traverse the synthesis output directory to obtain all the post-synthesis netlist files;

[0038] Performing module name uniqueness processing operations and module instance check and correction operations on all the above-mentioned synthesized netlist files to obtain processed netlist files;

[0039] Based on the above processed netlist file and the designed module hierarchy, a top-level module is created, and all sub-modules are instantiated and port-connected to generate the above complete RTL netlist.

[0040] In a second aspect, the present application proposes a device for outputting an RTL netlist file at a specified level, comprising:

[0041] A reading unit, used to read high-level design files based on Python file reading scripts;

[0042] A syntax analysis unit, used for inputting the high-level design file into a syntax analysis module for syntax analysis, and dividing the hierarchical structure information of each module based on the number of resources of each module, wherein the syntax analysis module is constructed based on a combination of regular expressions and a specific Python parsing library;

[0043] An integration unit, for performing integration operations based on the target modules selected by the target user in the hierarchical structure information of the above modules through a Python integration script to generate a plurality of synthesizable files;

[0044] A parallel task generation unit, used to generate multiple parallel synthesis tasks based on all synthesizable files by calling a specific Python concurrent execution library, wherein each of the above synthesis tasks is used to perform synthesis operations on one or more specified hierarchical modules;

[0045] A comprehensive operation unit, used for calling an external comprehensive tool to perform comprehensive operations on all comprehensive tasks and obtain multiple comprehensive data;

[0046] A connection operation unit, used for sending all the above-mentioned comprehensive data to the netlist collection module for connection operation to generate a complete RTL netlist;

[0047] The format conversion unit is used to perform a format conversion operation on the above complete RTL netlist based on a specified format selected by a target user to generate a target RTL netlist file.

[0048] In a third aspect, an electronic device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is used to implement the steps of the method for outputting an RTL netlist file at a specified level as described in any one of the first aspects above when executing the computer program stored in the memory.

[0049] In a fourth aspect, the present application further proposes a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method for outputting an RTL netlist file at a specified level according to any one of the first aspects is implemented.

[0050] In summary, traditional synthesis tools are often based on proprietary languages ​​or graphical interfaces, and it is difficult to provide users with flexible customized processing. The present disclosure uses Python scripts to realize the reading, parsing, generation and concurrent processing of synthesis tasks of design files, which greatly enhances the designer's control ability in the synthesis process. Target users can flexibly select and configure modules according to actual needs, and can customize the parallel synthesis strategy at the module level. This flexibility enables designers to flexibly adjust for different design scenarios, improving the overall design efficiency. Most existing synthesis tools only support task-level parallelization. The present disclosure allows designers to customize parallel synthesis operations at the module level or level by introducing Python's concurrent execution library (such as multiprocessing and concurrent.futures). Each module or level can be synthesized separately, and the system can automatically assign the synthesis tasks of each module to the parallel processing unit, which can not only make full use of multi-core computing resources, but also optimize the synthesis process at a finer level, greatly improving the synthesis efficiency and reducing the time consumption in the design process. With the increase in the complexity and scale of IC design, existing tools are difficult to effectively handle designs containing millions to billions of logic gates. The present disclosure divides the design into multiple modules, and performs hierarchical division and optimization according to the resource consumption and dependency of the modules. This modular design method enables the system to better manage and process complex large-scale designs, reducing the computational complexity caused by the design scale. At the same time, the present disclosure introduces a module hierarchy division method based on resource consumption (such as logic units, number of registers, etc.). Through the syntax parsing module, the system can automatically analyze the resource occupancy of each module, and then automatically generate reasonable module division according to the complexity, resource consumption and timing constraints of the module. This resource-based optimization synthesis strategy effectively reduces the risks of power consumption, area and timing violations, making the synthesis results more in line with design requirements. After the synthesis is completed, the present disclosure integrates the synthesis data of each module through the netlist collection module to generate a complete RTL netlist, and supports multiple output formats (such as Verilog, VHDL, EDIF, etc.). This format conversion function allows different design teams to choose the appropriate format according to their respective needs, and provide consistent and standardized RTL netlist files for the subsequent physical implementation stage, reducing format compatibility issues in design conversion. This solution discloses the automation of the design process through Python scripts, from reading design files, module division, synthesis task generation, parallel processing to netlist generation and format conversion, all of which can be completed in an automated way. Designers only need to provide input files and target formats to automatically complete complex large-scale design synthesis processes. This highly automated design process not only reduces human intervention and the probability of errors, but also improves the efficiency of the design process.The present disclosure overcomes the problems of high computational complexity, insufficient resource utilization, and poor flexibility of existing synthesis tools when processing large-scale designs through parallel synthesis at a specified level, flexible modular processing, intelligent resource allocation, and highly automated processes. The method provides designers with a more efficient and flexible synthesis solution, which can effectively improve the efficiency and synthesis quality in the IC design process while reducing complexity and time costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present specification. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0052] Figure 1 A schematic diagram of the process of outputting an RTL netlist file at a specified level provided in an embodiment of the present application;

[0053] Figure 2 A schematic diagram of the structure of a device for outputting an RTL netlist file at a specified level provided in an embodiment of the present application;

[0054] Figure 3 A schematic diagram of the structure of an electronic device for outputting an RTL netlist file at a specified level provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0056] See also Figure 1 , is a flow chart of a method for outputting an RTL netlist file at a specified level provided in an embodiment of the present application, which may specifically include:

[0057] S110, read high-level design files based on Python file reading script;

[0058] Exemplarily, a high-level design file is read through a Python file reading script. The design file can be in a common hardware description language (HDL) format such as Verilog or VHDL, and contains a functional description and module information of the design. The file reading script uses file operation functions (such as open()) in the Python standard library to read the design file, ensuring that the design file is correctly loaded for subsequent processing.

[0059] S120, inputting the high-level design file into a syntax analysis module for syntax analysis, and dividing the hierarchical structure information of each module based on the number of resources of each module, wherein the syntax analysis module is constructed based on a combination of regular expressions and a specific Python parsing library;

[0060] Exemplarily, the read high-level design file is input into the syntax parsing module. The syntax parsing module uses a combination of regular expressions and specific Python parsing libraries (such as pyverilog or pyvhdlparser) to perform syntax analysis on the design file. Regular expressions are used to preliminarily parse basic structural information such as module names, port declarations, signal declarations, instantiation statements, and assignment statements. Subsequently, the Python parsing library is used for in-depth parsing to obtain detailed resource information of each module, such as logic units, register numbers, etc., and the hierarchical structure information of each module is divided according to these resource numbers.

[0061] S130, based on the target module selected by the target user in the hierarchical structure information of each module, performing an integration operation through a Python integration script to generate a plurality of synthesizable files;

[0062] Exemplarily, according to the target module selected by the target user in the module hierarchy information, the integration operation is performed through the Python integration script. The integration operation includes recursively extracting the target module and its dependent modules to ensure that all modules required in the synthesis process are complete. After the integration is completed, the system generates multiple synthesizable files, each of which may contain the definition of one or more modules for subsequent synthesis operations.

[0063] S140, generating multiple parallel synthesis tasks based on all synthesizable files by calling a specific Python concurrent execution library, wherein each of the above synthesis tasks is used for one or more specified hierarchical modules to perform synthesis operations;

[0064] For example, to improve the synthesis efficiency, a specific Python concurrent execution library (such as multiprocessing or concurrent.futures) is called to create parallel synthesis tasks based on all generated synthesizable files. Each synthesis task processes one or more modules at a specified level, performs synthesis operations in parallel, maximizes the use of system resources, and speeds up synthesis.

[0065] S150, calling an external synthesis tool to perform synthesis operations on all synthesis tasks and obtain a plurality of synthesis data;

[0066] Exemplarily, after the parallel tasks are generated, the system calls an external synthesis tool (such as Vivado or Quartus Prime) to perform the actual synthesis operation on all synthesis tasks. The synthesis tool converts the high-level design file into a gate-level netlist and generates related synthesis data. Each synthesis task generates a set of gate-level netlists and resource usage reports, representing the synthesis results of one or more modules processed by the task.

[0067] S160, sending all the above-mentioned comprehensive data to the netlist collection module for connection operation to generate a complete RTL netlist;

[0068] Exemplarily, all synthesis data are sent to the netlist collection module for connection operation. The netlist collection module is responsible for integrating and connecting the gate-level netlist files generated by each independent synthesis task to ensure that the signals and interfaces between modules are correctly connected. Finally, a complete RTL netlist is generated, which contains the gate-level implementation of the entire design.

[0069] S170 , performing a format conversion operation on the complete RTL netlist based on the specified format selected by the target user to generate a target RTL netlist file.

[0070] Exemplarily, finally, the system performs a format conversion operation on the complete RTL netlist based on the specified format selected by the target user (such as Verilog, VHDL, EDIF, etc.). This operation converts the netlist file into the target format required by the user and generates the final RTL netlist file for use in the subsequent physical implementation stage.

[0071] In summary, traditional synthesis tools are often based on proprietary languages ​​or graphical interfaces, and it is difficult to provide users with flexible customized processing. The present disclosure uses Python scripts to realize the reading, parsing, generation and concurrent processing of synthesis tasks of design files, which greatly enhances the designer's control ability in the synthesis process. Target users can flexibly select and configure modules according to actual needs, and can customize the parallel synthesis strategy at the module level. This flexibility enables designers to flexibly adjust for different design scenarios, improving the overall design efficiency. Most existing synthesis tools only support task-level parallelization. The present disclosure allows designers to customize parallel synthesis operations at the module level or level by introducing Python's concurrent execution library (such as multiprocessing and concurrent.futures). Each module or level can be synthesized separately, and the system can automatically assign the synthesis tasks of each module to the parallel processing unit, which can not only make full use of multi-core computing resources, but also optimize the synthesis process at a finer level, greatly improving the synthesis efficiency and reducing the time consumption in the design process. With the increase in the complexity and scale of IC design, existing tools are difficult to effectively handle designs containing millions to billions of logic gates. The present disclosure divides the design into multiple modules, and performs hierarchical division and optimization according to the resource consumption and dependency of the modules. This modular design method enables the system to better manage and process complex large-scale designs, reducing the computational complexity caused by the design scale. At the same time, the present disclosure introduces a module hierarchy division method based on resource consumption (such as logic units, number of registers, etc.). Through the syntax parsing module, the system can automatically analyze the resource occupancy of each module, and then automatically generate reasonable module division according to the complexity, resource consumption and timing constraints of the module. This resource-based optimization synthesis strategy effectively reduces the risks of power consumption, area and timing violations, making the synthesis results more in line with design requirements. After the synthesis is completed, the present disclosure integrates the synthesis data of each module through the netlist collection module to generate a complete RTL netlist, and supports multiple output formats (such as Verilog, VHDL, EDIF, etc.). This format conversion function allows different design teams to choose the appropriate format according to their respective needs, and provide consistent and standardized RTL netlist files for the subsequent physical implementation stage, reducing format compatibility issues in design conversion. This solution discloses the automation of the design process through Python scripts, from reading design files, module division, synthesis task generation, parallel processing to netlist generation and format conversion, all of which can be completed in an automated way. Designers only need to provide input files and target formats to automatically complete complex large-scale design synthesis processes. This highly automated design process not only reduces human intervention and the probability of errors, but also improves the efficiency of the design process.The present disclosure overcomes the problems of high computational complexity, insufficient resource utilization, and poor flexibility of existing synthesis tools when processing large-scale designs through parallel synthesis at a specified level, flexible modular processing, intelligent resource allocation, and highly automated processes. The method provides designers with a more efficient and flexible synthesis solution, which can effectively improve the efficiency and synthesis quality in the IC design process while reducing complexity and time costs.

[0072] In some examples, the high-level design file is input into a syntax parsing module for syntax analysis, and hierarchical structure information of each module is divided based on the number of resources of each module, including:

[0073] Parsing the high-level design file based on the syntax parsing module to generate an abstract syntax tree;

[0074] Extracting definition information of each module from the abstract syntax tree, wherein the definition information includes module name, port information, information of other instantiated modules, and dependency relationship with other modules;

[0075] Based on the definition information of each module, count the number of resources in each module;

[0076] Based on the above resource quantity information and the instantiation relationship of the modules, the hierarchical structure information of each module is constructed.

[0077] Exemplarily, first, the high-level design file is input into the syntax parsing module, which generates an AST (Abstract Syntax Tree) through parsing operations. The abstract syntax tree is a complete representation of the structure of the design file, capturing the syntax elements in the file, including module definitions, signal declarations, port declarations, instantiation statements, etc. The syntax parsing module can be implemented by combining regular expressions and specific Python parsing libraries (such as pyverilog or pyvhdlparser). Regular expressions are responsible for the preliminary parsing of the basic structure in the design file, while the Python parsing library further performs in-depth parsing of the design file to generate a detailed abstract syntax tree.

[0078] After generating the abstract syntax tree, the system will extract the definition information of each module from the abstract syntax tree. This definition information includes but is not limited to:

[0079] Module name: represents the unique identifier of each module.

[0080] Port information: includes the definition of module input, output, and bidirectional ports, usually used for data transmission between modules.

[0081] Information about other instantiated modules: indicates which other modules are instantiated in this module, indicating the hierarchical dependencies between modules.

[0082] Dependencies with other modules: By parsing instantiation statements, the system can extract the dependencies between the current module and other modules. Module dependencies are an important basis for the module hierarchy.

[0083] Through this definition information, the system can understand the basic structure of each module and its role in the entire design.

[0084] After obtaining the module definition information, the system will count the number of resources for each module based on this information. The resource quantity information mainly includes but is not limited to:

[0085] Logic unit (Gates): used to describe the number of basic units for implementing logical functions in a module.

[0086] Registers: The basic unit number used to store data.

[0087] Number of signals: The number of signals used to transfer data between modules or within a module.

[0088] Number of ports: The number of input, output, and bidirectional ports included in the module interface.

[0089] This resource quantity information provides a basis for subsequent comprehensive operations and can help designers identify which modules occupy more hardware resources, thereby providing a reference for optimizing the design.

[0090] After counting the number of resources, the system combines the instantiation relationship of the modules to build the hierarchical structure information of each module. The module hierarchy is built based on the dependency relationship, resource usage and instantiation relationship between each module.

[0091] The specific process includes:

[0092] Recursively traverse the module dependencies: The system checks whether each module instantiates other modules. If a module instantiates other modules, it indicates that it is a higher-level module that depends on the instantiated module. Through recursive traversal, the module hierarchy tree of the entire design can be constructed.

[0093] Hierarchical division: Based on the dependencies and resource consumption between modules, the system will divide the modules into different levels to ensure that the modules at higher levels give priority to calling the modules at lower levels. This division can not only optimize the design structure, but also provide a basis for subsequent parallel synthesis operations.

[0094] In this way, the system can clearly identify the dependencies between modules and ensure that all modules are processed in the correct hierarchy during the synthesis process.

[0095] This embodiment provides an effective method for parsing high-level design files through a syntax parsing module, generating an abstract syntax tree, extracting module definition information, counting the number of resources, and constructing hierarchical information based on the instantiation relationship of the modules. This method not only improves the parsing efficiency of the design file, but also provides an accurate basis for module division and hierarchical structure for the subsequent synthesis process, which helps to optimize the design, improve resource utilization, and accelerate the synthesis process.

[0096] In some examples, the above-mentioned syntax parsing module performs a parsing operation on the above-mentioned high-level design file to generate an abstract syntax tree, including:

[0097] Performing a preliminary parsing operation on the high-level design file based on the regular expression to obtain a preliminary parsed file, wherein the regular expression includes a module definition expression, a port declaration expression, a signal declaration expression, a module instantiation expression, and an assignment statement expression;

[0098] Perform deep parsing on the unparsed file based on the above-mentioned specific Python parsing library to obtain a deep parsed file;

[0099] Based on the preliminary parsing file and the deep parsing file, the abstract syntax tree is generated.

[0100] For example, a preliminary parsing operation is first performed on the high-level design file, and the basic structure of the file is extracted using regular expressions to generate a preliminary parsed file. Specifically, the regular expression is responsible for matching and parsing including but not limited to the following key elements:

[0101] Module definition expression: used to match the module declaration part in the design file, including the module name and port list. For example, module module_name (input clk, output rst); indicates the definition of a module.

[0102] Port declaration expression: used to identify the port type (input, output, bidirectional port) and its signal in the module. For example, input clk; indicates an input port declaration.

[0103] Signal declaration expression: used to match the definition part of a signal, such as declarations of internal signals and registers. For example, reg [3:0] count; indicates a signal declaration.

[0104] Module instantiation expression: used to match module instantiation statements and identify module calls in other modules. For example, module_name u1 ( .clk(clk), .rst(rst) ); represents an instantiation statement.

[0105] Assignment statement expression: used to match the internal logical assignment statement of the module, such as assign out = in1&in2;.

[0106] Through the analysis of the above regular expressions, the system can quickly obtain the basic structural information of the module and generate a preliminary analysis file. The role of this step is to extract efficient and structured information from the design file, laying the foundation for subsequent in-depth analysis.

[0107] After the initial parsing is completed, some complex grammatical structures are still not fully parsed. To this end, the system inputs these unparsed files into a specific Python parsing library for deep parsing. Specific Python parsing libraries, such as pyverilog or pyvhdlparser, can parse more complex hardware description language structures, such as conditional statements, loop statements, and complex logical expressions.

[0108] The deep parsing operation parses the detailed syntax and semantics of the file through the API call of the parsing library to obtain more accurate design logic and dependencies between modules. The deep parsing file contains not only the structural information of the module, but also the complete logic and process information inside the module. This provides a basis for subsequent design synthesis and optimization.

[0109] After completing the preliminary analysis and deep analysis, the system integrates the results of these two parts to generate an abstract syntax tree (AST). The process of generating the abstract syntax tree combines the structured information in the preliminary analysis file and the detailed logical information in the deep analysis file to ensure that the module definition, port, signal declaration, module instantiation and assignment statements can be fully reflected in the AST.

[0110] This embodiment uses regular expressions for preliminary parsing to quickly extract the basic structural information of the design file, and further parses the complex syntax and logical structure through the deep parsing operation of a specific Python parsing library. Finally, a complete abstract syntax tree is generated based on the preliminary parsing file and the deep parsing file. The abstract syntax tree provides a complete representation of the design file and can effectively support the subsequent design synthesis and optimization process.

[0111] In some examples, the target modules selected by the target user based on the hierarchical information of the modules are integrated by a Python integration script to generate multiple synthesizable files, including:

[0112] Recursively extract all target modules and the dependent modules corresponding to the target modules according to the target modules selected above;

[0113] All target modules and dependent modules corresponding to the target modules are divided into files based on preset division rules to generate multiple synthesizable files, wherein the above division rules are determined based on the objective function, and the above objective function is based on resource consumption items, synthesis time items, module size items and dependency items.

[0114] Exemplarily, after the user specifies the target module, the system first recursively extracts the target module and all its related dependent modules from the hierarchical information of the design file. The dependency relationship of each module has been obtained through the syntax parsing module, including the instantiation of other modules within the module, the signal and logical association between modules, etc.

[0115] Recursive traversal of dependencies: Starting from the target module selected by the user, the system will check other modules instantiated by the module layer by layer. If the target module depends on other modules, these dependent modules will also be recursively extracted to ensure that all necessary modules are included in the synthesis process.

[0116] Module hierarchy analysis: With the module hierarchy information, the system can determine the level at which each module is located and how it is related to other modules. This analysis ensures that no necessary modules are missed during the synthesis process, especially when there are complex dependencies between modules.

[0117] After recursively extracting the target module and its dependent modules, the system needs to divide the module files according to the preset division rules. The purpose of this step is to split the complex design into multiple smaller module files that can be independently synthesized. The division rules are determined by multiple influencing factors, and the system optimizes the division of each module through the objective function.

[0118] In some examples, the objective function is determined based on the following formula:

[0119]

[0120] in, For the above resource consumption items, is the above-mentioned comprehensive time term, is the module size item above, For the above dependency items, , , and are the weight coefficients of each item, is the resource consumption of the ith module, is the total resource consumption, is the comprehensive time of the ith module, is the total integrated time, is the size of the i-th module, is the size of the largest module, represents the dependency weight between module i and module j, N is the number of files generated, is the module set of the kth file.

[0121] Exemplarily, the objective function is a core criterion for guiding file partitioning. In this embodiment, the objective function is composed of the following main items:

[0122] Resource consumption item: This item indicates the resource usage of each module, such as logic units (gates), registers (registers), number of signals, etc. The system will give priority to modules with large resource consumption to ensure that these modules can be reasonably divided into independent files so that the synthesis tool can better handle resource-intensive modules.

[0123] Synthesis time item: This item indicates the synthesis time of the module. The synthesis time is closely related to the logic complexity, resource usage and design structure of the module. By analyzing historical data or experience, the system can predict the synthesis time of each module and optimize the division based on this time, trying to avoid dividing modules with too long synthesis time into the same file, thereby balancing the task load.

[0124] Module size: This item is used to measure factors such as the number of lines of code, number of ports, and signal complexity of the module. Larger modules may require more resources and time to synthesize, so when dividing, the system will try to divide larger modules into separate files to avoid merging with other large modules to prevent synthesis bottlenecks.

[0125] Dependency item: This item is used to describe the dependencies between modules. If there are strong dependencies between some modules (such as instantiation relationships, signal connections), the system will try to divide them into the same synthesis file to reduce the interaction overhead between modules and optimize the synthesis effect.

[0126] In some examples, the specific Python parsing libraries include the pyvhdlparser library and the pyverilog library, the specific Python concurrent execution libraries include the multiprocessing library and the concurrent.futures library, and the external synthesis tools include Vivado and QuartusPrime.

[0127] The above method further includes:

[0128] Obtain the above high-level design file format suffix information, current system resource information and target FPGA information;

[0129] Determine the above-mentioned specific Python parsing library based on the above-mentioned file format suffix information;

[0130] Determine the Python concurrent execution library based on the current system resource information;

[0131] The external synthesis tool is determined based on the target FPGA information.

[0132] Exemplarily, the method first obtains necessary basic information from the input design file, including:

[0133] High-level design file format suffix information: Design files may use different hardware description languages, such as Verilog (file suffix .v) or VHDL (file suffix .vhd). The suffix information is the key to determine the design file format and is used to determine the subsequent parsing library.

[0134] Current system resource information: including the number of CPU cores and memory size of the system, determines the selection of concurrent execution libraries, ensures that system resources are used reasonably, and improves the efficiency of concurrent execution.

[0135] Target FPGA information: The design will eventually be deployed on different FPGA devices. Different FPGA vendors (such as Xilinx or Intel) use different synthesis tools, so obtaining information about the target FPGA helps choose the right synthesis tool, such as Vivado or Quartus Prime.

[0136] According to the format of the design file, the system will select a suitable Python parsing library. If the design file suffix is ​​.v, it means that the file uses the Verilog language, and the system will automatically select the pyverilog parsing library. If the design file suffix is ​​.vhd, it means that the file uses the VHDL language, and the system will select the pyvhdlparser parsing library.

[0137] If the system has a large number of CPU cores, such as 8 or more cores, the system will choose the multiprocessing library, which can use multiple processes to execute different comprehensive tasks simultaneously, giving full play to the advantages of multi-core processors. If the system has a small number of CPU cores or wants to perform concurrent processing with a smaller resource footprint, the system will choose the concurrent.futures library, which provides a more lightweight concurrent execution method through thread pools and process pools, suitable for resource-constrained environments.

[0138] In this way, the system can flexibly select the concurrent execution library according to the current resource conditions to maximize the utilization of system resources and improve the efficiency of concurrent integration.

[0139] If the target FPGA is a Xilinx FPGA (for example, Virtex, Zynq, etc.), the system will select the Vivado synthesis tool. Vivado is a design, synthesis, timing analysis, and placement and routing tool provided by Xilinx that can convert high-level design files into gate-level netlists suitable for Xilinx FPGA deployment. If the target FPGA is an Intel FPGA (for example, Stratix, Cyclone, etc.), the system will select the Quartus Prime synthesis tool. Quartus Prime is an FPGA design synthesis tool provided by Intel (formerly Altera) and is specifically designed to handle Intel FPGA designs.

[0140] In some examples, all of the above-mentioned integrated data are sent to the netlist collection module for connection operation to generate a complete RTL netlist, including:

[0141] Based on the netlist collection module, traverse the synthesis output directory to obtain all the post-synthesis netlist files;

[0142] Performing module name uniqueness processing operations and module instance check and correction operations on all the above-mentioned synthesized netlist files to obtain processed netlist files;

[0143] Based on the above processed netlist file and the designed module hierarchy, a top-level module is created, and all sub-modules are instantiated and port-connected to generate the above complete RTL netlist.

[0144] Exemplarily, the system traverses the synthesis output directory through the netlist collection module to obtain all netlist files generated by the synthesis tool. These files may be generated in parallel by multiple synthesis tasks and distributed in different folders or subdirectories. The system needs to find all the netlist files that meet the requirements (such as .v, .vhd or .edf format files) by traversing the directory for subsequent processing.

[0145] After collecting all the netlist files, the system needs to preprocess these netlist files. The main operations include module name uniqueness processing and module instance checking and correction operations.

[0146] Since multiple synthesis tasks may independently generate netlist files for different modules, there may be module name conflicts (that is, different modules use the same name). To avoid module name conflicts, the system needs to uniquely process the name of each module. You can add a prefix or suffix to each module name to ensure that its name is unique in the entire design.

[0147] The instantiation relationship between modules needs to be checked to ensure that all instantiated modules exist in the design file. If it is found that some modules instantiate non-existent modules, the system will issue a warning and ask the designer to make corrections. At the same time, it is also necessary to ensure that the module's port connections, port numbers and types match.

[0148] After completing the module name uniqueness and instance check and correction, the system creates a top-level module based on the designed module hierarchy. The role of the top-level module is to instantiate all sub-modules and connect their ports to form a complete design. This step requires layer-by-layer instantiation and signal connection based on the module hierarchy (that is, which module depends on which module).

[0149] The specific operations of creating a top-level module include: traversing the processed netlist file, generating corresponding instantiation codes for each module, and calling them in the top-level module. According to the signal interaction between modules, connect the ports of each module to ensure that data can be correctly transmitted between modules. The top-level module usually also needs to define global signals, such as clk (clock) and rst (reset). After completing the creation of the top-level module and the instantiation and port connection of all sub-modules, the system integrates the processed netlist file and the top-level module to generate the final complete RTL netlist. The netlist file will include the definitions of all modules and the connections between them to ensure the synthesizability and correctness of the design.

[0150] like Figure 2 As shown, the present application proposes a device for outputting an RTL netlist file at a specified level, comprising:

[0151] A reading unit 21, used for reading a high-level design file based on a Python file reading script;

[0152] The syntax analysis unit 22 is used to input the high-level design file into the syntax analysis module for syntax analysis, and divide the hierarchical structure information of each module based on the number of resources of each module, wherein the syntax analysis module is constructed based on the combination of regular expressions and a specific Python parsing library;

[0153] An integration unit 23, configured to perform an integration operation based on the target module selected by the target user in the hierarchical structure information of the above modules through a Python integration script to generate a plurality of synthesizable files;

[0154] A parallel task generation unit 24 is used to generate a plurality of parallel synthesis tasks based on all synthesizable files by calling a specific Python concurrent execution library, wherein each of the above synthesis tasks is used to perform synthesis operations on one or more specified hierarchical modules;

[0155] The integrated operation unit 25 is used to call the external integrated tool to perform integrated operations on all integrated tasks and obtain multiple integrated data;

[0156] A connection operation unit 26, used for sending all the above-mentioned integrated data to the netlist collection module for connection operation to generate a complete RTL netlist;

[0157] The format conversion unit 27 is used to perform a format conversion operation on the above complete RTL netlist based on the specified format selected by the target user to generate a target RTL netlist file.

[0158] The above-mentioned netlist file device may further perform the following steps:

[0159] In some examples, the high-level design file is input into a syntax parsing module for syntax analysis, and hierarchical structure information of each module is divided based on the number of resources of each module, including:

[0160] Parsing the high-level design file based on the syntax parsing module to generate an abstract syntax tree;

[0161] Extracting definition information of each module from the abstract syntax tree, wherein the definition information includes module name, port information, information of other instantiated modules, and dependency relationship with other modules;

[0162] Based on the definition information of each module, count the number of resources in each module;

[0163] Based on the above resource quantity information and the instantiation relationship of the modules, the hierarchical structure information of each module is constructed.

[0164] In some examples, the above-mentioned syntax parsing module performs a parsing operation on the above-mentioned high-level design file to generate an abstract syntax tree, including:

[0165] Performing a preliminary parsing operation on the high-level design file based on the regular expression to obtain a preliminary parsed file, wherein the regular expression includes a module definition expression, a port declaration expression, a signal declaration expression, a module instantiation expression, and an assignment statement expression;

[0166] Perform deep parsing on the unparsed file based on the above-mentioned specific Python parsing library to obtain a deep parsed file;

[0167] Based on the preliminary parsing file and the deep parsing file, the abstract syntax tree is generated.

[0168] In some examples, the target modules selected by the target user based on the hierarchical information of the modules are integrated by a Python integration script to generate multiple synthesizable files, including:

[0169] Recursively extract all target modules and the dependent modules corresponding to the target modules according to the target modules selected above;

[0170] All target modules and dependent modules corresponding to the target modules are divided into files based on preset division rules to generate multiple synthesizable files, wherein the above division rules are determined based on the objective function, and the above objective function is based on resource consumption items, synthesis time items, module size items and dependency items.

[0171] In some examples, the objective function is determined based on the following formula:

[0172]

[0173] in, For the above resource consumption items, is the above-mentioned comprehensive time term, is the module size item above, For the above dependency items, , , and are the weight coefficients of each item, is the resource consumption of the ith module, is the total resource consumption, is the comprehensive time of the ith module, is the total integrated time, is the size of the i-th module, is the size of the largest module, represents the dependency weight between module i and module j, N is the number of files generated, is the module set of the kth file.

[0174] In some examples, the specific Python parsing libraries include the pyvhdlparser library and the pyverilog library, the specific Python concurrent execution libraries include the multiprocessing library and the concurrent.futures library, and the external synthesis tools include Vivado and QuartusPrime.

[0175] The above method further includes:

[0176] Obtain the above high-level design file format suffix information, current system resource information and target FPGA information;

[0177] Determine the above-mentioned specific Python parsing library based on the above-mentioned file format suffix information;

[0178] Determine the Python concurrent execution library based on the current system resource information;

[0179] The external synthesis tool is determined based on the target FPGA information.

[0180] In some examples, all of the above-mentioned integrated data are sent to the netlist collection module for connection operation to generate a complete RTL netlist, including:

[0181] Based on the netlist collection module, traverse the synthesis output directory to obtain all the post-synthesis netlist files;

[0182] Performing module name uniqueness processing operations and module instance check and correction operations on all the above-mentioned synthesized netlist files to obtain processed netlist files;

[0183] Based on the above processed netlist file and the designed module hierarchy, a top-level module is created, and all sub-modules are instantiated and port-connected to generate the above complete RTL netlist.

[0184] like Figure 3 As shown, an embodiment of the present application also provides an electronic device 300, including a memory 310, a processor 320, and a computer program 311 stored in the memory 310 and executable on the processor. When the processor 320 executes the computer program 311, the steps of any method of outputting an RTL netlist file at a specified level are implemented.

[0185] Since the electronic device introduced in this embodiment is a device used to implement a device for outputting an RTL netlist file at a specified level in the embodiment of the present application, based on the method introduced in the embodiment of the present application, technical personnel in this field can understand the specific implementation mode of the electronic device of this embodiment and its various variations. Therefore, how the electronic device implements the method in the embodiment of the present application is not introduced in detail here. As long as the equipment used by technical personnel in this field to implement the method in the embodiment of the present application is within the scope of protection of this application.

[0186] In the specific implementation process, when the computer program 311 is executed by the processor, it can achieve Figure 1 Any implementation manner in the corresponding embodiments.

[0187] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0188] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0189] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0190] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0191] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0192] An embodiment of the present application also provides a computer program product, which includes computer software instructions. When the computer software instructions are executed on a processing device, the processing device executes the process of outputting an RTL netlist file at a specified level in the corresponding embodiment.

[0193] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc.

[0194] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0195] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0196] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0197] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0198] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program codes.

[0199] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for outputting an RTL netlist file at a specified level, characterized in that: include: Read high-level design files based on Python file reading scripts; Input the high-level design file into a syntax analysis module for syntax analysis, and divide the hierarchical structure information of each module based on the number of resources of each module, wherein the syntax analysis module is constructed based on a combination of regular expressions and a specific Python parsing library; Based on the target modules selected by the target user in the hierarchical structure information of each module, an integration operation is performed through a Python integration script to generate a plurality of synthesizable files; Generate multiple parallel synthesis tasks based on all synthesizable files by calling a specific Python concurrent execution library, wherein each of the synthesis tasks is used to perform synthesis operations on one or more specified hierarchical modules, the specific Python parsing library includes a pyvhdlparser library and a pyverilog library, and the specific Python concurrent execution library includes a multiprocessing library and a concurrent.futures library; Calling external synthesis tools to perform synthesis operations on all synthesis tasks and obtain multiple synthesis data; Sending all the synthesis data to a netlist collection module for connection operation to generate a complete RTL netlist; The complete RTL netlist is format converted based on a specified format selected by a target user to generate a target RTL netlist file.

2. The method for outputting RTL netlist files at a specified level according to claim 1, characterized in that: The step of inputting the high-level design file into a syntax analysis module for syntax analysis, and dividing the hierarchical structure information of each module based on the number of resources of each module, includes: Parsing the high-level design file based on the syntax parsing module to generate an abstract syntax tree; Extracting definition information of each module from the abstract syntax tree, wherein the definition information includes module name, port information, information of other instantiated modules, and dependency relationship with other modules; Counting the quantity of resources in each module based on the definition information of each module; Based on the resource quantity information and the instantiation relationship of the modules, the hierarchical structure information of each module is constructed.

3. The method for outputting RTL netlist files at a specified level according to claim 1, characterized in that: The parsing operation on the high-level design file based on the syntax parsing module to generate an abstract syntax tree includes: Performing a preliminary parsing operation on the high-level design file based on the regular expression to obtain a preliminary parsed file, wherein the regular expression includes a module definition expression, a port declaration expression, a signal declaration expression, a module instantiation expression, and an assignment statement expression; Performing a deep parsing operation on the unparsed file based on the specific Python parsing library to obtain a deep parsed file; The abstract syntax tree is generated based on the preliminary parsing file and the deep parsing file.

4. The method for outputting RTL netlist files at a specified level according to claim 1, characterized in that: The target modules selected by the target user based on the hierarchical structure information of each module are integrated by a Python integration script to generate a plurality of synthesizable files, including: Recursively extract all target modules and dependent modules corresponding to the target modules according to the selected target module; All target modules and dependent modules corresponding to the target modules are divided into files based on preset division rules to generate multiple synthesizable files, wherein the division rules are determined based on an objective function, and the objective function is based on resource consumption items, synthesis time items, module size items and dependency items.

5. The method for outputting RTL netlist files at a specified level according to claim 4, characterized in that: The objective function is determined based on the following formula: in, is the resource consumption item, is the comprehensive time term, is the module size item, is the dependency item, , , and are the weight coefficients of each item, is the resource consumption of the ith module, is the total resource consumption, is the comprehensive time of the ith module, is the total integrated time, is the size of the i-th module, is the size of the largest module, represents the dependency weight between module i and module j, N is the number of generated files, is the module set of the kth file.

6. The method for outputting RTL netlist files at a specified level according to claim 1, characterized in that: The external synthesis tools include Vivado and Quartus Prime, The method further comprises: Obtaining the high-level design file format suffix information, current system resource information, and target FPGA information; Determine the specific Python parsing library based on the file format suffix information; Determine the Python concurrent execution library based on the current system resource information; The external synthesis tool is determined based on the target FPGA information.

7. The method for outputting RTL netlist files at a specified level according to claim 1, characterized in that: The step of sending all the synthesis data to the netlist collection module for connection operation to generate a complete RTL netlist includes: Based on the netlist collection module, traverse the synthesis output directory to obtain all the post-synthesis netlist files; Performing module name uniqueness processing operations and module instance checking and correction operations on all the synthesized netlist files to obtain processed netlist files; Based on the processed netlist file and the designed module hierarchy, a top-level module is created, and all submodules are instantiated and port connected to generate the complete RTL netlist.

8. A device for outputting RTL netlist files at a specified level, characterized in that: include: A reading unit, used to read high-level design files based on Python file reading scripts; A syntax analysis unit, used for inputting the high-level design file into a syntax analysis module for syntax analysis, and dividing the hierarchical structure information of each module based on the number of resources of each module, wherein the syntax analysis module is constructed based on a combination of regular expressions and a specific Python parsing library; An integration unit, for performing an integration operation through a Python integration script based on the target module selected by the target user in the hierarchical structure information of each module, so as to generate a plurality of synthesizable files; A parallel task generation unit, used to generate a plurality of parallel synthesis tasks based on all synthesizable files by calling a specific Python concurrent execution library, wherein each of the synthesis tasks is used to perform synthesis operations on one or more specified hierarchical modules, the specific Python parsing library includes a pyvhdlparser library and a pyverilog library, and the specific Python concurrent execution library includes a multiprocessing library and a concurrent.futures library; A comprehensive operation unit, used for calling an external comprehensive tool to perform comprehensive operations on all comprehensive tasks and obtain multiple comprehensive data; A connection operation unit, used for sending all the integrated data to the netlist collection module for connection operation to generate a complete RTL netlist; The format conversion unit is used to perform a format conversion operation on the complete RTL netlist based on a specified format selected by a target user to generate a target RTL netlist file.

9. An electronic device, comprising: A memory and a processor, wherein the processor is used to implement the steps of the method for outputting an RTL netlist file at a specified level as described in any one of claims 1 to 7 when executing a computer program stored in the memory.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for outputting an RTL netlist file at a specified level according to any one of claims 1 to 7 are implemented.

Images