Prototype verification method and related equipment

Abstract

The invention discloses a prototype verification method and related equipment, and the prototype verification method comprises the steps that an RISC-V processor core is designed through a target hardware description language, and the RISC-V processor core comprises an instruction decoding unit, a register file unit, an arithmetic logic and data path unit and a peripheral module integration unit; performing testing and verification based on the RISC-V processor core to obtain a preliminary testing result and a simulation verification result; under the condition that both the preliminary test result and the simulation verification result meet preset requirements, making a target system mirror image file corresponding to the target hardware description language; and performing on-board verification and performance test operation on the FPGA based on the target system mirror image file, and verifying the RISC-V processor core to obtain a prototype verification report.

Description

Technical Field

[0001] The present invention relates to the field of electronic design automation, and more specifically, to a prototype verification method and related equipment. Background Art

[0002] As the complexity of processor design increases, especially in processors with RISC-V architecture (Reduced Instruction Set Computer-V), it is crucial to verify the functionality, performance, and feasibility of the processor. As an open instruction set architecture (ISA), RISC-V provides high flexibility in processor design, but it also increases the difficulty of verification. The prototype verification process of the processor includes interactive testing of hardware and software, which involves a comprehensive evaluation from instruction set architecture verification to hardware implementation and software ecosystem. Most existing technical solutions focus on a single verification level and lack a systematic and universal verification process.

[0003] Therefore, it is necessary to propose a prototype verification method and related equipment to at least solve some of the above problems. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In a first aspect, the present application proposes a prototype verification method, comprising: Designing a RISC-V processor core by using a target hardware description language, wherein the RISC-V processor core includes an instruction decoding unit, a register file unit, an arithmetic logic and data path unit, and a peripheral module integration unit; Conduct testing and verification based on the above RISC-V processor core to obtain preliminary test results and simulation verification results; When the preliminary test results and the simulation verification results meet the preset requirements, a target system image file corresponding to the target hardware description language is prepared; Based on the above target system image file, perform board verification and performance test operations on the FPGA and verify the above RISC-V processor core to obtain a prototype verification report.

[0006] In a feasible implementation, the above-mentioned RISC-V processor core is tested and verified to obtain preliminary test results and simulation verification results, including: Based on the stimulus program, the RISC-V processor core is called to perform preliminary testing to obtain preliminary test results, wherein the stimulus program is used to verify the correctness of the RISC-V processor core when loading, decoding, and executing basic instructions; Functional verification and timing verification operations are performed on the above-mentioned RISC-V processor core based on an integrated simulation tool to obtain simulation verification results, wherein the above-mentioned simulation tool is used to verify the correctness of the processor core and evaluate the performance of the design through timing simulation.

[0007] In a feasible implementation manner, the preliminary test result score includes a preliminary test score. Based on the following calculation: in, is the correctness of instruction execution, is the register consistency rate, is the average execution delay and is the weight coefficient corresponding to the above instruction execution accuracy, the above register consistency rate and the above average execution delay, ; The correctness of the execution of the above instructions Determined based on the following formula: in, is the total number of test instructions, For instructions The weight of For instructions The correctness of the execution result, if the instruction If executed correctly, it is 1, otherwise it is 0; The consistency rate of the above register values Determined based on the following formula: in, is the total number of test instructions, Q=P, is the total number of registers, For instructions Post register The expected value of is the weight factor for register consistency check, is a small constant used to avoid division by zero errors; Average execution delay Determined based on the following formula: in, is the total number of the above test instructions, For instructions The time to start execution, For instructions The timestamp of the completed execution, For instructions The delay weight of .

[0008] In a feasible implementation manner, the above-mentioned simulation verification result includes a simulation image and a simulation verification score, and the above-mentioned simulation verification score F2 is calculated based on the following formula: in, is the functional correctness error, is the timing error, is the energy consumption deviation, For cache utilization efficiency, The above are the weight coefficients corresponding to the functional correctness error, the timing error, the energy consumption deviation and the cache utilization efficiency. ; The above functional correctness error Determined based on the following formula: in, is the total number of instructions tested, For instructions The weight of For instructions The actual execution result, For instructions The expected results of the execution; The above timing error score Determined based on the following formula: in, is the total number of instructions for the above test, For instructions The actual completion time, For instructions The expected completion time, is the standard deviation of the timing deviation; Energy expenditure deviation score Determined based on the following formula: in, is the total number of instructions for the above test, For instructions The actual energy consumption, For instructions The expected energy consumption, For instructions The weight of The cache utilization efficiency score above Determined based on the following formula: in, is the total number of cache accesses, For the Whether the cache access is a hit, a hit is 1, a miss is 0, For the The weight of the cache access, is the weight of the cache layer.

[0009] In a feasible implementation manner, the instruction decoding unit is used to fetch instructions from the instruction memory and decode them into control signals and operand information; and / or, The register file unit contains all general registers and special registers in the RISC-V processor; and / or, The arithmetic logic and data path unit comprises an arithmetic logic unit and a data path, the arithmetic logic unit is used to process arithmetic and logic operations, and the data path is used to transmit data; and / or, The above peripheral module integrated unit includes a memory controller, a cache layer, a bus interface and an external device interface; and / or, The above target system image file includes a Linux kernel, a file system and a proxy kernel.

[0010] In a feasible implementation, it also includes: Get the verification goals for prototype verification; The target hardware description language is determined based on the verification target.

[0011] In a feasible implementation, it also includes: Obtain the verification objectives of prototype verification; Determine the chip type of the RISC-V processor based on the above verification purpose.

[0012] In a second aspect, the present application proposes a prototype verification device, comprising: A design unit, used for designing a RISC-V processor core by using a target hardware description language, wherein the RISC-V processor core includes an instruction decoding unit, a register file unit, an arithmetic logic and data path unit, and a peripheral module integration unit; A test unit, used to perform testing and verification based on the RISC-V processor core to obtain preliminary test results and simulation verification results; An image making unit, used for making a target system image file corresponding to the target hardware description language when both the preliminary test result and the simulation verification result meet the preset requirements; A verification unit is used to perform board verification and performance test operations on the FPGA based on the target system image file and verify the RISC-V processor core to obtain a prototype verification report.

[0013] In a third aspect, an electronic device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is configured to implement the steps of the prototype verification method of any one of the first aspects described above when executing the computer program stored in the memory.

[0014] In a fourth aspect, the present application further proposes a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the prototype verification method of any one of the first aspects is implemented.

[0015] In summary, this application supports various FPGA hardware platforms (such as Xilinx, Altera, etc.), and through modular design and standardized interface protocols (such as AXI, Wishbone), various parts of the processor design (such as instruction decoders, register groups, arithmetic logic units, etc.) can be independently configured and ported. Engineers can flexibly reorganize these modules according to the resources and performance characteristics of the selected FPGA platform, thereby efficiently completing cross-platform verification tasks. This method greatly improves the portability and compatibility of processor designs on different FPGA platforms. This application supports a variety of extensions of the RISC-V instruction set architecture, from basic RV32I (32-bit integer instruction set), RV64I (64-bit integer instruction set) to more advanced extensions (such as floating-point operations RV32F / RV64F, vector processing RVV, compressed instructions RVC, etc.). This support enables engineers to flexibly select and configure instruction sets during the verification process according to the needs of different application scenarios, which helps to adapt to a wide range of application scenarios from general computing to high-performance computing, and improves the applicability and extensibility of the verification method. This application provides a comprehensive processor core function verification framework. By writing multiple test programs and covering different instructions and functions, engineers can ensure the correctness of the processor core under various operating conditions. This method not only focuses on the execution correctness of a single instruction, but also covers complex instruction combinations, register operations, and data paths, ensuring the reliable operation of the processor in complex scenarios, significantly improving the comprehensiveness and accuracy of verification. This method allows performance evaluation and optimization on the FPGA hardware platform. Engineers can design performance test programs and collect data on key performance indicators such as clock frequency, throughput, and latency to improve the processor design. This method enables performance testing and design optimization to be completed in the hardware prototype stage, which helps to discover and solve performance bottlenecks in advance and improve the efficiency and performance of processor design. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present specification. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings: Figure 1 A schematic diagram of a prototype verification method provided in an embodiment of the present application; Figure 2 A schematic diagram of a prototype verification method provided in an embodiment of the present application; Figure 3 A schematic diagram of another prototype verification method provided in an embodiment of the present application; Figure 4A schematic diagram of the structure of a prototype verification device provided in an embodiment of the present application; Figure 5 A schematic diagram of the structure of a prototype verification electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0018] See also Figure 1 , is a schematic diagram of a prototype verification method provided in an embodiment of the present application, Figure 2 A schematic diagram of a prototype verification method provided in an embodiment of the present application, the method may specifically include: S110, designing a RISC-V processor core by using a target hardware description language, wherein the RISC-V processor core includes an instruction decoding unit, a register file unit, an arithmetic logic and data path unit, and a peripheral module integration unit; Exemplarily, a RISC-V processor core is designed by a target hardware description language (such as Verilog or VHDL). The core includes an instruction decoding unit, a register file unit, an arithmetic logic and data path unit, and a peripheral module integration unit.

[0019] The instruction decoding unit is responsible for decoding the instruction into control signals and operands for execution by the processing unit.

[0020] The register file unit is used to store general registers and special registers, supporting data storage and transmission of the processor.

[0021] The arithmetic logic unit (ALU) and datapath units are used to perform arithmetic and logic operations and pass data in the datapath.

[0022] The peripheral module integration unit is used to connect external devices and interface modules, such as memory controllers, bus interfaces, etc., to ensure compatibility with peripherals.

[0023] S120, testing and verifying based on the RISC-V processor core to obtain preliminary test results and simulation verification results; Exemplarily, after the design is completed, the RISC-V processor core is tested and verified to obtain preliminary test results and simulation verification results.

[0024] The preliminary test verifies the correctness of the processor core in executing basic instructions by writing stimulus programs to test basic functions such as instruction decoding, data path and register operations.

[0025] Simulation verification is based on integrated simulation tools (such as VivadoSimulator) to perform functional and timing simulation on the processor core to further verify the correctness and performance of the design. Timing simulation can be used to evaluate the performance of the design at different operating frequencies to ensure that performance requirements are met.

[0026] S130, when both the preliminary test results and the simulation verification results meet the preset requirements, preparing a target system image file corresponding to the target hardware description language; Exemplarily, when both the preliminary test results and the simulation verification results meet the preset requirements, the target hardware description language is compiled into a system image file. The image file is a binary form of the processor core running on the FPGA (Field-Programmable Gate Array) and is used to load into the FPGA development board to ensure that the design can be verified on real hardware.

[0027] S140. Perform board verification and performance test operations based on the target system image file and verify the RISC-V processor core to obtain a prototype verification report.

[0028] Exemplarily, based on the generated target system image file, the processor core is verified on the FPGA. The system image file is loaded into the FPGA for operation to verify the stability and correctness of the processor in the actual hardware environment. Through actual load testing and performance benchmark tests (such as MIPS, DMIPS, power consumption, etc.), the processor's operating efficiency, power consumption performance, bandwidth utilization, cache hit rate and other performance indicators are fully evaluated. The operating system (such as Linux) and other software applications are run on the processor core to ensure the compatibility of hardware and software and verify the overall feasibility and reliability of the processor system.

[0029] Specifically, you can use JTAG to burn a self-made operating system image on the XCVU19P-2FSVA3824E development board and verify the RISC-V processor. Run test programs on the hardware platform, such as CPU performance test tools such as dhrystone and coremark, and perform performance evaluation. Based on the evaluation results, you can make optimizations, such as increasing instruction-level parallelism, optimizing data paths, or adjusting cache strategies. Generate a detailed report of prototype verification, including verification methods, test programs, simulation results, and performance evaluation. At the same time, analyze and compare the results to verify the effectiveness and practicality of the design.

[0030] In summary, this application supports various FPGA hardware platforms (such as Xilinx, Altera, etc.), and through modular design and standardized interface protocols (such as AXI, Wishbone), various parts of the processor design (such as instruction decoders, register groups, arithmetic logic units, etc.) can be independently configured and ported. Engineers can flexibly reorganize these modules according to the resources and performance characteristics of the selected FPGA platform, thereby efficiently completing cross-platform verification tasks. This method greatly improves the portability and compatibility of processor designs on different FPGA platforms. This application supports a variety of extensions of the RISC-V instruction set architecture, from basic RV32I (32-bit integer instruction set), RV64I (64-bit integer instruction set) to more advanced extensions (such as floating-point operations RV32F / RV64F, vector processing RVV, compressed instructions RVC, etc.). This support enables engineers to flexibly select and configure instruction sets during the verification process according to the needs of different application scenarios, which helps to adapt to a wide range of application scenarios from general computing to high-performance computing, and improves the applicability and extensibility of the verification method. This application provides a comprehensive processor core function verification framework. By writing multiple test programs and covering different instructions and functions, engineers can ensure the correctness of the processor core under various operating conditions. This method not only focuses on the execution correctness of a single instruction, but also covers complex instruction combinations, register operations, and data paths, ensuring the reliable operation of the processor in complex scenarios, significantly improving the comprehensiveness and accuracy of verification. This method allows performance evaluation and optimization on the FPGA hardware platform. Engineers can design performance test programs and collect data on key performance indicators such as clock frequency, throughput, and latency to improve the processor design. This method enables performance testing and design optimization to be completed in the hardware prototype stage, which helps to discover and solve performance bottlenecks in advance and improve the efficiency and performance of processor design.

[0031] In some examples, the above-mentioned RISC-V processor core is tested and verified to obtain preliminary test results and simulation verification results, including: Based on the stimulus program, the RISC-V processor core is called to perform preliminary testing to obtain preliminary test results, wherein the stimulus program is used to verify the correctness of the RISC-V processor core when loading, decoding, and executing basic instructions; Functional verification and timing verification operations are performed on the above-mentioned RISC-V processor core based on an integrated simulation tool to obtain simulation verification results, wherein the above-mentioned simulation tool is used to verify the correctness of the processor core and evaluate the performance of the design through timing simulation.

[0032] Exemplarily, in the preliminary testing phase of the scheme, a stimulus program is used to drive the RISC-V processor core to run a series of basic instructions to verify its correctness in loading, decoding, and execution.

[0033] A stimulus program is a program containing typical instruction sequences, which is specially designed to test the basic functions of a processor. A stimulus program usually contains various instructions, such as load instructions, arithmetic instructions, jump instructions, etc., which are used to trigger different modules of the processor (such as instruction decoding unit, register file, arithmetic logic unit, etc.) to work.

[0034] The purpose of the preliminary test is to ensure that the basic functions of the RISC-V processor core are operating normally, including the correct decoding of instructions, the correctness of the execution process, the transmission of data flow, etc. By comparing the input of the stimulus program and the execution results, it is determined whether the processor can correctly execute these basic instructions.

[0035] By comparing the processor output with the expected results, preliminary test results are generated. If the execution results of the stimulus program are consistent with expectations, it can be confirmed that the basic functions of the processor core are normal; otherwise, potential problems in the design need to be investigated.

[0036] In the simulation verification phase, integrated simulation tools are used to further verify the processor core, especially in terms of functional correctness and timing performance. Simulation tools are usually integrated into the design software (such as VivadoSimulator), which can perform functional and timing simulation on the processor. Functional simulation is used to verify the correctness of the processor when executing more complex instruction sets or operations, while timing simulation is used to evaluate the timing performance of the processor design at different operating frequencies.

[0037] During functional simulation, the simulation tool simulates the behavior of the processor core under different instructions and verifies the correctness of its internal logic. For example, it ensures that the output of modules such as registers, data paths, and arithmetic logic are consistent with expectations during the execution of a specific instruction sequence.

[0038] Through timing simulation, the performance of the processor at different frequencies and loads is evaluated to ensure that the design can run stably under the target clock. Timing simulation will detect potential timing violations, such as whether the setup and hold time of the signal meets the design requirements.

[0039] The result report generated by the simulation tool can help engineers confirm the functional and timing performance of the processor core design. If the result is as expected, it means that the processor design has passed the simulation verification; otherwise, further optimization or repair of design problems is required.

[0040] In some examples, this verification process can be carried out as follows: The stimulus program can contain multiple basic operations of the instruction set. Through the stimulus file, the basic functions of the CPU are tested, such as shift instructions, memory access instructions, instruction jumps, etc. When testing shift instructions, for example, luix1,1, luix2255 are defined. When running, the x1 value should be 0x00001000 and the x2 value should be 0x000ff000; similarly, the memory access instruction and instruction jump can be implemented through the LB instruction and the JAL instruction respectively. For example, data loading (LOAD), arithmetic operations (ADD, SUB), conditional jumps, etc. By executing these operations, it is ensured that the processor can work normally in the decoding, execution, write-back and other stages.

[0041] In simulation verification, integrated simulation tools are used to check the processor's responsiveness in complex instruction operations and continuous instruction streams, and to evaluate whether timing requirements are met, such as ensuring the response speed of registers and data consistency in instruction execution.

[0042] In summary, this embodiment proposes a two-layer verification method based on stimulus program and simulation tool, covering the basic functional test of RISC-V processor core and comprehensive timing and performance simulation verification. This method not only ensures the functional correctness of the processor core, but also ensures its compliance in timing and performance, providing sufficient verification support for the actual application of the processor.

[0043] In some examples, the preliminary test result score includes a preliminary test score. Based on the following calculation: in, is the correctness of instruction execution, is the register consistency rate, is the average execution delay and is the weight coefficient corresponding to the above instruction execution accuracy, the above register consistency rate and the above average execution delay, ; The correctness of the execution of the above instructions Determined based on the following formula: in, is the total number of test instructions, For instructions The weight of For instructions The correctness of the execution result, if the instruction If executed correctly, it is 1, otherwise it is 0; The consistency rate of the above register values Determined based on the following formula: in, is the total number of test instructions, Q=P, is the total number of registers, For instructions Post register The expected value of is the weight factor for register consistency check, is a small constant used to avoid division by zero errors; Average execution delay Determined based on the following formula: in, is the total number of the above test instructions, For instructions The time to start execution, For instructions The timestamp of the completed execution, For instructions The delay weight of .

[0044] For example, by calculating the three core indicators of instruction execution correctness, register consistency rate and average execution delay, the preliminary test score of the RISC-V processor core is obtained. This scoring system not only focuses on the functional correctness of the processor (instruction execution and register consistency), but also covers the performance of the processor (execution delay). By setting reasonable weight coefficients, different indicators can be adjusted according to application requirements to ensure that the verification results meet expectations.

[0045] In some examples, the simulation verification result includes a simulation image and a simulation verification score, and the simulation verification score F2 is calculated based on the following formula: in, is the functional correctness error, is the timing error, is the energy consumption deviation, For cache utilization efficiency, The above are the weight coefficients corresponding to the functional correctness error, the timing error, the energy consumption deviation and the cache utilization efficiency. ; The above functional correctness error Determined based on the following formula: in, is the total number of instructions tested, For instructions The weight of For instructions The actual execution result, For instructions The expected results of the execution; The above timing error score Determined based on the following formula: in, is the total number of instructions for the above test, For instructions The actual completion time, For instructions The expected completion time, is the standard deviation of the timing deviation; Energy expenditure deviation score Determined based on the following formula: in, is the total number of instructions for the above test, For instructions The actual energy consumption, For instructions The expected energy consumption, For instructions The weight of The above cache utilization efficiency score Determined based on the following formula: in, is the total number of cache accesses, For the Whether the cache access is a hit, a hit is 1, a miss is 0, For the The weight of the cache access, is the weight of the cache layer.

[0046] For example, four key indicators are used: functional correctness error, timing error, energy consumption deviation, and cache utilization efficiency to comprehensively calculate the simulation verification score F2 to evaluate the performance of the RISC-V processor core in the simulation environment, such as function, timing, energy efficiency, and cache utilization. By setting reasonable weight coefficients, the impact of various indicators can be flexibly adjusted according to different verification requirements to comprehensively measure the performance and reliability of the processor.

[0047] In some examples, the instruction decoding unit is used to fetch instructions from the instruction memory and decode them into control signals and operand information; and / or, The register file unit contains all general registers and special registers in the RISC-V processor; and / or, The arithmetic logic and data path unit comprises an arithmetic logic unit and a data path, the arithmetic logic unit is used to process arithmetic and logic operations, and the data path is used to transmit data; and / or, The above peripheral module integrated unit includes a memory controller, a cache layer, a bus interface and an external device interface; and / or, The above target system image file includes a Linux kernel, a file system and a proxy kernel.

[0048] Exemplarily, the instruction decoding unit is responsible for taking instructions from the instruction memory and decoding them into control signals and operand information for execution by subsequent processing units. The method uses Verilog to write decoding logic, parses the instruction's opcode, function code, register address and other information according to the format of the RISC-V instruction set, designs a state machine or combinational logic to control the instruction fetching and decoding process, and outputs control signals to each execution unit to indicate the next operation.

[0049] The register file unit stores all general registers and special registers in the RISC-V processor and is a key part of data storage and transmission in the processor. A sufficient number of registers are designed according to the RISC-V specification, and the width of each register matches the processor architecture (such as 32 bits or 64 bits). The register group is designed using Verilog to implement the register file and provide a read and write interface for the instruction execution unit to access.

[0050] The arithmetic logic and data path unit includes an arithmetic logic unit and a data path. The arithmetic logic unit is used to process arithmetic and logic operations, and the data path is used to transmit data.

[0051] The peripheral module integrated unit includes a memory controller, a cache layer, a bus interface, and an external device interface.

[0052] System image production requires three parts: Linux kernel, file system and proxy kernel. Before making the image, install and compile the RISC-V cross-compilation tool chain. You can use the 5.10.167 version of the Linux kernel and tailor the kernel functions according to the peripherals of the development board, retaining the relevant peripherals of the development board. The tailoring is performed by executing the command makemenuconfig. The file system is made using the compiled busybox tool to generate basic system libraries such as / bin, / root and / sys, system dynamic link library / lib, and copy related files from the cross-compilation tool, as well as the rcS file and inittab file for kernel startup initialization. The general proxy kernel is a lightweight application execution environment that can host statically linked RISC-VELF binary files. It mainly hosts the Linux port of RISC-V through BerkeleyBootLoader. In addition, the system's device tree file is defined, and the memory address allocation and detailed information design of the processor, clock and peripherals are defined.

[0053] In some examples, such as Figure 3 As shown in the figure, first verify the functions of the processor, including the instruction set and memory access functions, then configure the peripherals according to your own needs, then design the operating system, and verify the RISC-V processor and the operating system together on the development board, and finally further verify the performance of the processor by compiling the application (dhrystone, coremark) in the operating system In some examples, this also includes: Get the verification goals for prototype verification; The target hardware description language is determined based on the verification target.

[0054] For example, to clarify the goal of prototype verification, first of all, we need to focus on the basic functional verification of the RISC-V processor core, such as the complete execution of the instruction set, register operations, interrupt handling, etc., and verify specific instruction set extensions (such as RVV vector extensions, RVB bit operation extensions, etc.) according to requirements. If the verification goal is to evaluate the performance of the processor in a specific system or application, it is necessary to define system-level characteristics such as system architecture, peripheral interfaces, interrupt sources, power management, and determine the benchmark for performance testing. Determine performance indicators such as execution speed (MIPS, DMIPS), power consumption, power efficiency (MIPS / Watt), memory bandwidth utilization, cache hit rate, etc. Design representative test scenarios and test cases to ensure that the evaluation of target performance points can be fully covered.

[0055] After the verification goal is clear, an appropriate hardware description language (HDL) is selected to implement the design of the RISC-V processor. The hardware description language is used to describe the behavior and structure of the processor design so that the functional and performance characteristics of the processor can be precisely controlled during the verification process.

[0056] In some examples, this also includes: Obtain the verification objectives of prototype verification; Determine the chip type of the RISC-V processor based on the above verification purpose.

[0057] For example, before selecting a hardware platform, you first need to clarify the specific purpose of the verification so that you can choose the most suitable chip type and hardware platform according to your needs. The verification purposes can usually be divided into the following categories: If the purpose of verification is to quickly develop and test the basic functions of the RISC-V processor, the prototype development phase will give priority to design flexibility and rapid iteration capabilities. For example, testing the integrity of the instruction set, verifying the correctness of register operations, and interrupt handling functions.

[0058] When the verification targets include system-level verification, such as compatibility with peripheral interfaces, external interrupt sources, and power management functions, a verification platform that can integrate system modules is required to ensure the stability of the processor in the target application scenario.

[0059] If the purpose of verification is to evaluate the performance of the processor (such as execution speed, power consumption, power efficiency, memory bandwidth utilization, etc.), it is usually necessary to accurately measure the performance and power consumption data of the processor in specific scenarios in order to optimize the processor design and ultimately provide support for commercial products.

[0060] Depending on the purpose of verification, different types of hardware platforms can be selected to implement the prototype of the RISC-V processor, mainly including the following two types: 1. FPGA development board is suitable for prototype development and preliminary verification.

[0061] If the purpose of verification is mainly to quickly develop and test the functions of the RISC-V processor, then FPGA is an ideal choice. FPGA provides a high degree of flexibility, allowing rapid iteration and modification of the design on hardware, which is suitable for the initial verification stage of the processor design. You can choose a development board with Xilinx's xcvu19p chip as the core. This chip has sufficient resources and is suitable for complex design and high-performance verification. At the same time, Xilinx provides a wealth of development tools and libraries, which have good support for RISC-V processor design, including ready-made IP cores and reference designs, which help speed up the development process. On FPGA, engineers can repeatedly modify, debug and verify various modules of the processor (such as instruction decoding, register files, arithmetic logic units, etc.) to quickly detect and solve problems and obtain preliminary performance and functional verification results.

[0062] 2. ASIC design process is suitable for performance and cost optimization of the final product.

[0063] When the verification goal is to develop a RISC-V processor core for commercial products and there are strict requirements for performance, power consumption and cost, choosing ASIC is a better choice. ASIC design is more suitable for the mass production needs of processors. Through fine layout and process, power consumption and performance can be optimized. For ASIC design, detailed design documents such as specifications, circuit diagrams, layout and wiring need to be prepared. In addition, it is necessary to select a suitable foundry for tape-out and optimize the design according to the actual application requirements of the processor to ensure efficient performance in a mass production environment. The ASIC design process supports the release of the final product. Through detailed layout and process optimization, higher efficiency can be achieved in performance and power consumption, making the processor core more suitable for a commercial environment.

[0064] like Figure 4 As shown, a prototype verification device is proposed for this application, including: A design unit 21, used to design a RISC-V processor core by using a target hardware description language, wherein the RISC-V processor core includes an instruction decoding unit, a register file unit, an arithmetic logic and data path unit, and a peripheral module integration unit; A testing unit 22, used to perform testing and verification based on the RISC-V processor core to obtain preliminary test results and simulation verification results; An image making unit 23 is used to make a target system image file corresponding to the target hardware description language when both the preliminary test result and the simulation verification result meet the preset requirements; The verification unit 24 is used to perform board verification and performance test operations on the FPGA based on the target system image file and verify the RISC-V processor core to obtain a prototype verification report.

[0065] The above prototype verification device can also perform the following steps: In some examples, the above-mentioned RISC-V processor core is tested and verified to obtain preliminary test results and simulation verification results, including: Based on the stimulus program, the RISC-V processor core is called to perform preliminary testing to obtain preliminary test results, wherein the stimulus program is used to verify the correctness of the RISC-V processor core when loading, decoding, and executing basic instructions; Functional verification and timing verification operations are performed on the above-mentioned RISC-V processor core based on an integrated simulation tool to obtain simulation verification results, wherein the above-mentioned simulation tool is used to verify the correctness of the processor core and evaluate the performance of the design through timing simulation.

[0066] In some examples, the preliminary test result score includes a preliminary test score. Based on the following calculation: in, is the correctness of instruction execution, is the register consistency rate, is the average execution delay and is the weight coefficient corresponding to the above instruction execution accuracy, the above register consistency rate and the above average execution delay, The correctness of the execution of the above instructions Determined based on the following formula: in, is the total number of test instructions, For instructions The weight of For instructions The correctness of the execution result, if the instruction If executed correctly, it is 1, otherwise it is 0; The consistency rate of the above register values Determined based on the following formula: in, is the total number of test instructions, Q=P, is the total number of registers, For instructions Post register The expected value of is the weight factor for register consistency check, is a small constant used to avoid division by zero errors; Average execution delay Determined based on the following formula: in, is the total number of the above test instructions, For instructions The time to start execution, For instructions The timestamp of the completed execution, For instructions The delay weight of .

[0067] In some examples, the simulation verification result includes a simulation image and a simulation verification score, and the simulation verification score F2 is calculated based on the following formula: in, is the functional correctness error, is the timing error, is the energy consumption deviation, For cache utilization efficiency, The above are the weight coefficients corresponding to the functional correctness error, the timing error, the energy consumption deviation and the cache utilization efficiency. ; The above functional correctness error Determined based on the following formula: in, is the total number of instructions tested, For instructions The weight of For instructions The actual execution result, For instructions The expected results of the execution; The above timing error score Determined based on the following formula: in, is the total number of instructions for the above test, For instructions The actual completion time, For instructions The expected completion time, is the standard deviation of the timing deviation Energy expenditure deviation score Determined based on the following formula: in, is the total number of instructions for the above test, For instructions The actual energy consumption, For instructions The expected energy consumption, For instructions Weight The above cache utilization efficiency score Determined based on the following formula: in, is the total number of cache accesses, For the Whether the cache access is a hit, a hit is 1, a miss is 0, For the The weight of the cache access, is the weight of the cache layer.

[0068] In some examples, the instruction decoding unit is used to fetch instructions from the instruction memory and decode them into control signals and operand information; and / or, The register file unit contains all general registers and special registers in the RISC-V processor; and / or, The arithmetic logic and data path unit comprises an arithmetic logic unit and a data path, the arithmetic logic unit is used to process arithmetic and logic operations, and the data path is used to transmit data; and / or, The above peripheral module integrated unit includes a memory controller, a cache layer, a bus interface and an external device interface; and / or, The above target system image file includes a Linux kernel, a file system and a proxy kernel.

[0069] In some examples, this also includes: Get the verification goals for prototype verification; The target hardware description language is determined based on the verification target.

[0070] In some examples, this also includes: Obtain the verification objectives of prototype verification; Determine the chip type of the RISC-V processor based on the above verification purpose.

[0071] like Figure 5 As shown, an embodiment of the present application also provides an electronic device 300, including a memory 310, a processor 320, and a computer program 311 stored in the memory 310 and executable on the processor, and when the processor 320 executes the computer program 311, the steps of any of the above-mentioned prototype verification methods are implemented.

[0072] Since the electronic device introduced in this embodiment is a device used to implement a prototype verification device in the embodiment of the present application, based on the method introduced in the embodiment of the present application, the technical personnel in this field can understand the specific implementation mode of the electronic device of this embodiment and its various variations. Therefore, how the electronic device implements the method in the embodiment of the present application is not introduced in detail here. As long as the equipment adopted by the technical personnel in this field to implement the method in the embodiment of the present application falls within the scope of protection of this application.

[0073] In the specific implementation process, when the computer program 311 is executed by the processor, it can achieve Figure 1 Any implementation manner in the corresponding embodiments.

[0074] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0075] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0076] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0077] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0078] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0079] An embodiment of the present application further provides a computer program product, which includes computer software instructions. When the computer software instructions are executed on a processing device, the processing device executes the prototype verification process in the corresponding embodiment.

[0080] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server, or data center. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or a data center that includes one or more available media integrations. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state drive (SSD)), etc.

[0081] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0082] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0083] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0084] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0085] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0086] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A prototype verification method, characterized in that: include: Designing a RISC-V processor core by using a target hardware description language, wherein the RISC-V processor core includes an instruction decoding unit, a register file unit, an arithmetic logic and data path unit, and a peripheral module integration unit; Performing testing and verification based on the RISC-V processor core to obtain preliminary test results and simulation verification results; When both the preliminary test result and the simulation verification result meet the preset requirements, a target system image file corresponding to the target hardware description language is prepared; Based on the target system image file, board verification and performance test operations are performed on the FPGA and the RISC-V processor core is verified to obtain a prototype verification report.

2. The prototype verification method according to claim 1, characterized in that: The testing and verification based on the RISC-V processor core to obtain preliminary test results and simulation verification results include: Calling the RISC-V processor core to perform preliminary testing based on the stimulus program to obtain preliminary test results, wherein the stimulus program is used to verify the correctness of the RISC-V processor core when loading, decoding, and executing basic instructions; Functional verification and timing verification operations are performed on the RISC-V processor core based on an integrated simulation tool to obtain simulation verification results, wherein the simulation tool is used to verify the correctness of the processor core and evaluate the performance of the design through timing simulation.

3. The prototype verification method according to claim 2, characterized in that: The preliminary test result score includes a preliminary test score. Based on the following calculation: in, is the correctness of instruction execution, is the register consistency rate, is the average execution delay, , and is the weight coefficient corresponding to the instruction execution accuracy, the register consistency rate and the average execution delay, ; The correctness of instruction execution Determined based on the following formula: in, is the total number of test instructions, For instructions The weight of For instructions The correctness of the execution result, if the instruction If executed correctly, it is 1, otherwise it is 0; The register value consistency rate Determined based on the following formula: in, is the total number of test instructions, is the total number of registers, For instructions Post register The expected value of is the weight factor for register consistency check, is a small constant used to avoid division by zero errors; The average execution delay Determined based on the following formula: in, is the total number of the test instructions, For instructions The time to start execution, For instructions The timestamp of the completed execution, For instructions The delay weight of .

4. The prototype verification method according to claim 2, characterized in that: The simulation verification result includes a simulation image and a simulation verification score, and the simulation verification score F2 is calculated based on the following formula: in, is the functional correctness error, is the timing error, is the energy consumption deviation, For cache utilization efficiency, The weight coefficients corresponding to the functional correctness error, the timing error, the energy consumption deviation and the cache utilization efficiency are respectively ; The functional correctness error Determined based on the following formula: in, is the total number of instructions tested, For instructions The weight of For instructions The actual execution result, For instructions The expected results of the execution; The timing error Determined based on the following formula: in, is the total number of instructions tested, For instructions The actual completion time, For instructions The expected completion time, is the standard deviation of the timing deviation; The energy consumption deviation Determined based on the following formula: in, is the total number of instructions tested, For instructions The actual energy consumption, For instructions The expected energy consumption, For instructions The weight of The cache utilization efficiency score Determined based on the following formula: in, is the total number of cache accesses, For the Whether the cache access is a hit, a hit is 1, a miss is 0, For the The weight of the cache access, is the weight of the cache layer.

5. The prototype verification method according to claim 1, characterized in that: The instruction decoding unit is used to fetch instructions from the instruction memory and decode them into control signals and operand information; and / or, The register file unit contains all general registers and special registers in the RISC-V processor; and / or, The arithmetic logic and data path unit comprises an arithmetic logic unit and a data path, wherein the arithmetic logic unit is used to process arithmetic and logic operations, and the data path is used to transmit data; and / or, The peripheral module integrated unit includes a memory controller, a cache layer, a bus interface and an external device interface; and / or, The target system image file includes a Linux kernel, a file system and a proxy kernel.

6. The prototype verification method according to claim 1, characterized in that: Also includes: Get the verification goals for prototype verification; The target hardware description language is determined based on the verification target.

7. The prototype verification method according to claim 1, characterized in that: Also includes: Obtain the verification objectives of prototype verification; The chip type of the RISC-V processor is determined based on the verification purpose.

8. A prototype verification device, characterized in that: include: A design unit, used for designing a RISC-V processor core by using a target hardware description language, wherein the RISC-V processor core includes an instruction decoding unit, a register file unit, an arithmetic logic and data path unit, and a peripheral module integration unit; A test unit, used to perform testing and verification based on the RISC-V processor core to obtain preliminary test results and simulation verification results; An image making unit, used for making a target system image file corresponding to the target hardware description language when both the preliminary test result and the simulation verification result meet the preset requirements; A verification unit is used to perform board verification and performance test operations on the FPGA based on the target system image file and verify the RISC-V processor core to obtain a prototype verification report.

9. An electronic device, comprising: A memory and a processor, wherein the processor is used to implement the steps of the prototype verification method according to any one of claims 1 to 7 when executing the computer program stored in the memory.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the prototype verification method according to any one of claims 1 to 7 are implemented.

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