A sub-threshold circuit timing optimization method and related apparatus
By performing timing analysis and classification optimization on subthreshold circuits, and adopting methods such as feedback equalization, clock delay, and input data delay, the timing convergence problem of subthreshold circuits was solved, and rapid convergence and stability improvement of the circuit were achieved.
Patent Information
- Application Number
- CN202411493413.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-24
- Publication Date
- 2025-10-10
- Estimated Expiration
- 2044-10-24
AI Technical Summary
Subthreshold circuits suffer from circuit timing closure issues due to their low power consumption characteristics, and existing technologies make it difficult to effectively optimize their timing convergence.
By performing timing analysis on the data input and output paths of each trigger in the subthreshold circuit, paths that do not meet the setup time or hold time requirements are identified. Timing optimization is then performed using methods such as feedback equalization, clock delay, or increasing input data delay, and appropriate optimization strategies are selected for different types of timing problems.
It accelerates the timing convergence of subthreshold circuits, generates a more matched unit circuit layout, and improves the timing convergence and stability of the circuit.
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Figure CN119358487B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of power electronics technology, and in particular to a subthreshold circuit timing optimization method and related devices. Background Art
[0002] Subthreshold circuits utilize transistors operating in the subthreshold region (i.e., the region where the transistor's gate voltage is lower than the threshold voltage). These circuits offer low power consumption, but this comes at the expense of circuit speed, potentially leading to timing closure issues (timing closure refers to the design of a circuit to ensure that all signals reach their destination within the specified timeframe to meet the circuit's functional and performance requirements). Therefore, more effective timing optimization techniques are required to ensure the proper operation of subthreshold circuits. Summary of the Invention
[0003] In view of the above problems, this application provides a subthreshold circuit timing optimization method and related devices to optimize the timing convergence problem of subthreshold circuits. The specific solution is as follows:
[0004] A first aspect of the present application provides a subthreshold circuit timing optimization method, comprising:
[0005] Perform timing analysis on the data input and output paths of each flip-flop in the subthreshold circuit to identify paths that do not meet setup or hold time requirements.
[0006] For paths that do not meet setup time requirements but meet hold time requirements: between the output of a combinational circuit and the data input of a flip-flop, the path is optimized for timing using feedback equalization; or, at the clock input of the flip-flop, the path is optimized for timing using clock delay. The combinational circuit is a digital circuit connected to the data input of the flip-flop and composed of multiple logic units connected according to a specific logic function.
[0007] For a path that does not meet the hold time requirement but meets the setup time requirement: between the output terminal of the combinational circuit and the data input terminal of the trigger, the path is optimized by increasing the input data delay;
[0008] For paths that do not meet the hold time requirement and do not meet the setup time requirement: the paths are divided into four categories of sub-paths, the first category of sub-paths are sub-paths that do not meet the setup time requirement but meet the hold time requirement, the second category of sub-paths are sub-paths that do not meet the hold time requirement but meet the setup time requirement, the third category of sub-paths are sub-paths that do not meet the hold time requirement and do not meet the setup time requirement, and the fourth category of sub-paths are sub-paths that meet both the hold time requirement and the setup time requirement; between all logic units that belong only to the first category of sub-paths, the first category of sub-paths are optimized for timing by using feedback equalization; between all logic units that belong only to the second category of sub-paths, the second category of sub-paths are optimized for timing by using an increased input data delay; between all logic units that belong only to the third category of sub-paths, the third category of sub-paths are optimized for timing by using feedback equalization and an increased input data delay.
[0009] In a possible implementation, optimizing the timing of the path between the output terminal of the combinational circuit and the data input terminal of the trigger by using feedback equalization includes:
[0010] disconnecting the output of the combinational circuit from the data input of the flip-flop;
[0011] A feedback equalizer is inserted between the output terminal of the combinational circuit and the data input terminal of the trigger, so that the output terminal of the combinational circuit is connected to the data input terminal of the feedback equalizer, the data output terminal of the feedback equalizer is connected to the data input terminal of the trigger, and the data output terminal of the trigger is connected to the feedback input terminal of the feedback equalizer.
[0012] In a possible implementation, the method of optimizing the timing of the path between the output terminal of the combinational circuit and the data input terminal of the trigger by using feedback equalization further includes:
[0013] A Schmitt trigger is inserted between the data output of the feedback equalizer and the data input of the trigger, so that the input of the Schmitt trigger is connected to the data output of the feedback equalizer, and the output of the Schmitt trigger is connected to the data input of the trigger.
[0014] In a possible implementation, the timing optimization of the path by using clock delay at the clock input end of the trigger includes: adding a delay circuit at the clock input end of the trigger;
[0015] The delay circuit includes: a PMOS capacitor or an NMOS capacitor; when the MOS capacitor is an NMOS capacitor, the gate of the NMOS capacitor is connected to the clock input terminal of the trigger, and the semiconductor substrate of the NMOS capacitor is grounded; when the MOS capacitor is a PMOS capacitor, the gate of the PMOS capacitor is connected to the clock input terminal of the trigger, and the semiconductor substrate of the PMOS capacitor is connected to the power supply;
[0016] Alternatively, the delay circuit comprises: a logic unit having an input signal and an output signal that are the same, an input terminal of the logic unit being connected to a clock input terminal of a trigger, and an output terminal of the logic unit being left floating;
[0017] Alternatively, the output end of the delay circuit is connected to the clock input end of the trigger, and the input end of the delay circuit is used to receive a clock signal.
[0018] In one possible implementation, the timing optimization of the path between the output terminal of the combinational circuit and the data input terminal of the trigger by increasing the input data delay includes: disconnecting the output terminal of the combinational circuit and the data input terminal of the trigger; inserting a delay circuit between the output terminal of the combinational circuit and the data input terminal of the trigger;
[0019] Alternatively, the timing of the path is optimized by increasing an input data delay between the output terminal of the combinational circuit and the data input terminal of the trigger, including: adding a delay circuit to the data input terminal of the trigger; the delay circuit includes a PMOS capacitor or an NMOS capacitor; when the MOS capacitor is an NMOS capacitor, the gate of the NMOS capacitor is connected to the data input terminal of the trigger, and the semiconductor substrate of the NMOS capacitor is grounded; when the MOS capacitor is a PMOS capacitor, the gate of the PMOS capacitor is connected to the data input terminal of the trigger, and the semiconductor substrate of the PMOS capacitor is connected to a power supply;
[0020] Alternatively, the timing of the path is optimized by increasing the input data delay between the output terminal of the combinational circuit and the data input terminal of the trigger, including: adding a delay circuit to the data input terminal of the trigger; the delay circuit includes a logic unit whose input signal and output signal are the same, the input terminal of the logic unit is connected to the data input terminal of the trigger, and the output terminal of the logic unit is left floating.
[0021] In one possible implementation, before performing timing analysis on the data input and output paths of each trigger in the subthreshold circuit, the method further includes: performing isomorphic analysis on each path of the subthreshold circuit, performing timing analysis and timing optimization on only one of all isomorphic paths, and then reusing the timing optimization result of the current path in other isomorphic paths.
[0022] A second aspect of the present application provides a subthreshold circuit timing optimization device, comprising:
[0023] A timing analysis unit is used to perform timing analysis on the data input and output paths of each trigger in the sub-threshold circuit and identify the paths that do not meet the setup time requirement or the hold time requirement;
[0024] A first timing optimization unit is configured to optimize the timing of a path that does not meet the setup time requirement but meets the hold time requirement by: optimizing the timing of the path between the output of the combinational circuit and the data input of the flip-flop using feedback equalization; or optimizing the timing of the path at the clock input of the flip-flop using clock delay; the combinational circuit is a digital circuit connected to the data input of the flip-flop and composed of multiple logic units connected according to a specific logic function;
[0025] A second timing optimization unit is configured to optimize the timing of a path that does not meet the hold time requirement but meets the setup time requirement by increasing an input data delay between the output terminal of the combinational circuit and the data input terminal of the trigger;
[0026] The third timing optimization unit is used to divide the paths that do not meet the hold time requirement and the setup time requirement into four categories of sub-paths, the first category of sub-paths being sub-paths that do not meet the setup time requirement but meet the hold time requirement, the second category of sub-paths being sub-paths that do not meet the hold time requirement but meet the setup time requirement, the third category of sub-paths being sub-paths that do not meet the hold time requirement and do not meet the setup time requirement, and the fourth category of sub-paths being sub-paths that meet both the hold time requirement and the setup time requirement; among all logic units that belong only to the first category of sub-paths, the first category of sub-paths are timing optimized by feedback equalization; among all logic units that belong only to the second category of sub-paths, the second category of sub-paths are timing optimized by increasing input data delay; and among all logic units that belong only to the third category of sub-paths, the third category of sub-paths are timing optimized by both feedback equalization and increasing input data delay.
[0027] A third aspect of the present application provides a computer program product comprising computer-readable instructions. When the computer-readable instructions are executed on an electronic device, the electronic device implements the sub-threshold circuit timing optimization method of the first aspect or any implementation of the first aspect.
[0028] A fourth aspect of the present application provides an electronic device, comprising at least one processor and a memory connected to the processor, wherein:
[0029] The memory is used to store computer programs;
[0030] The processor is used to execute the computer program so that the electronic device can implement the subthreshold circuit timing optimization method of the above-mentioned first aspect or any implementation manner of the first aspect.
[0031] In a fifth aspect, the present application provides a computer storage medium, which carries one or more computer programs. When the one or more computer programs are executed by an electronic device, the electronic device can implement the sub-threshold circuit timing optimization method of the above-mentioned first aspect or any implementation of the first aspect.
[0032] With the help of the above technical solution, the subthreshold circuit timing optimization method provided by this application first classifies the situations that do not meet the timing requirements, and then selects a more suitable timing optimization method for each specific situation where the timing is not met, and implements corresponding timing optimization measures accordingly, so as to generate a more matching unit circuit layout and accelerate the timing convergence speed of the subthreshold circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] The above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that the originals and elements are not necessarily drawn to scale.
[0034] Figure 1 A flow chart of a subthreshold circuit timing optimization method provided by this application;
[0035] Figure 2 A schematic diagram of a subthreshold circuit structure before timing optimization provided by this application;
[0036] Figure 3 A schematic diagram of a subthreshold circuit structure provided by this application that has been optimized for timing to meet setup time requirements;
[0037] Figure 4 A schematic diagram of another subthreshold circuit structure provided by the present application that has been optimized for timing to meet setup time requirements;
[0038] Figure 5 A schematic diagram of another subthreshold circuit structure provided by the present application that has been optimized for timing to meet setup time requirements;
[0039] Figure 6 A schematic diagram of another subthreshold circuit structure provided by the present application that has been optimized for timing to meet setup time requirements;
[0040] Figure 7 A schematic diagram of another subthreshold circuit structure provided by the present application that has been optimized for timing to meet setup time requirements;
[0041] Figure 8 A schematic diagram of another subthreshold circuit structure provided by the present application that has been optimized for timing to meet setup time requirements;
[0042] Figure 9 A schematic diagram of a subthreshold circuit structure provided by the present application that has been optimized for timing to meet hold time requirements;
[0043] Figure 10 A schematic diagram of another subthreshold circuit structure provided by the present application that has been optimized for timing to meet hold time requirements;
[0044] Figure 11 A schematic diagram of another subthreshold circuit structure provided by the present application that has been optimized for timing to meet hold time requirements;
[0045] Figure 12 A schematic diagram of another subthreshold circuit structure provided by the present application that has been optimized for timing to meet hold time requirements;
[0046] Figure 13 This is another schematic diagram of a sub-threshold circuit structure before timing optimization provided by the present application. DETAILED DESCRIPTION
[0047] The threshold voltage is the minimum gate voltage required for a transistor to enter the saturation or linear region from the cutoff region. Based on the magnitude of the transistor's gate voltage relative to its threshold voltage, the transistor's operating region can be divided into the superthreshold region, the near-threshold region, and the subthreshold region. These three regions are described in detail below:
[0048] 1. Superthreshold region
[0049] The superthreshold region is the region where the gate voltage of a transistor is significantly higher than its threshold voltage. A circuit that utilizes a transistor operating in the superthreshold region is called a superthreshold circuit.
[0050] 2. Near-threshold area
[0051] The near-threshold region lies between the subthreshold and superthreshold regions and specifically refers to the region where the transistor's gate voltage is slightly above or close to its threshold voltage. Circuits that utilize transistors operating in this region are called near-threshold circuits.
[0052] 3. Subthreshold region
[0053] The subthreshold region is the region where the gate voltage of a transistor is lower than its threshold voltage. A circuit that utilizes a transistor operating in the subthreshold region is called a subthreshold circuit.
[0054] In the subthreshold region, the conductive path (channel) between the source and drain of a transistor is not fully formed, so the transistor is not fully conductive, resulting in a relatively low operating voltage. Due to the low operating voltage, the transistor's leakage current (the small current flowing from the source to the drain; leakage current in the subthreshold region is also called subthreshold current, which decays exponentially with gate voltage) is significantly reduced. Therefore, the static power consumption of subthreshold circuits is much lower than that of superthreshold and near-threshold circuits. The low power consumption of subthreshold circuits makes them very promising for use in flip-flop design and other digital circuit designs.
[0055] However, the low power consumption of subthreshold circuits comes at the expense of circuit speed. In subthreshold circuits, the reduced operating voltage slows transistor speed (increases switching time), leading to increased signal propagation delay within the circuit. The cumulative effect of this delay is particularly pronounced in complex circuits, potentially leading to timing closure issues (timing closure refers to the design process of ensuring that all signals reach their destination within a predetermined timeframe to meet functional and performance requirements). Therefore, more effective timing optimization techniques are needed to ensure the proper operation of subthreshold circuits.
[0056] To address this issue, embodiments of the present application provide a subthreshold circuit timing optimization method. This method first categorizes situations where timing requirements are not met, then selects a more appropriate timing optimization method for each specific situation where timing requirements are not met, and implements corresponding timing optimization measures accordingly, thereby generating a more suitable unit circuit layout and accelerating the timing closure of the subthreshold circuit.
[0057] The following is a detailed description of a subthreshold circuit timing optimization method provided by an embodiment of the present application in conjunction with the accompanying drawings. Those skilled in the art will appreciate that, with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.
[0058] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, and this is merely a way of distinguishing the objects of the same attributes when describing them in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.
[0059] See also Figure 1, an embodiment of the present application provides a subthreshold circuit timing optimization method, comprising:
[0060] Step S01: performing timing analysis on the data input and output paths of each trigger in the sub-threshold circuit to identify paths that do not meet the setup time requirement or the hold time requirement.
[0061] Specifically, in digital circuit design, a flip-flop is a bistable circuit element with memory functionality. It can store one bit of binary information (i.e., 0 or 1) and update its state under the control of a specific clock signal. In subthreshold circuit design, ensuring the correct operation of the flip-flop is crucial, which requires precise control of timing parameters, particularly setup and hold times.
[0062] The trigger edge refers to the edge of the clock signal (rising or falling) that causes the flip-flop to change state. For example, a D flip-flop is triggered by the rising edge of the clock signal.
[0063] Setup time is the minimum amount of time that a data input signal must remain stable before the trigger edge of the flip-flop clock signal arrives. In other words, the data input signal must arrive and remain stable well before the trigger edge of the clock signal to ensure the flip-flop has sufficient time to recognize and stably capture the data input signal. If the data input signal changes too quickly before the trigger edge of the clock signal, the flip-flop may not correctly capture the data input signal, resulting in erroneous or unstable data.
[0064] Hold time is the minimum amount of time that the data input signal must remain stable after the trigger edge of the flip-flop's clock signal. This is because even after the clock signal's trigger edge occurs, the flip-flop's internal circuitry needs time to process and stabilize the new state. If the data input signal changes immediately after the clock signal's trigger edge, this change may be misinterpreted by the flip-flop's internal circuitry, resulting in data errors or instability.
[0065] In subthreshold circuit design, static timing analysis software or Monte Carlo circuit simulation software can be used to perform timing analysis on the data input and output paths of each trigger in the subthreshold circuit to identify all paths in the subthreshold circuit that do not meet timing requirements, including paths that do not meet setup time requirements but meet hold time requirements, paths that do not meet hold time requirements but meet setup time requirements, and paths that meet neither setup time nor hold time requirements. The embodiments of the present application employ different optimization strategies for different types of timing issues.
[0066] Step S02: For paths that do not meet the setup time requirement but meet the hold time requirement: between the output of the combinational circuit and the data input of the trigger, the path is optimized for timing using feedback equalization; or, at the clock input of the trigger, the path is optimized for timing using clock delay so that the path meets both the setup time and hold time requirements, and the control ends here.
[0067] Specifically, for paths that do not meet the setup time requirements but meet the hold time requirements, the embodiments of the present application propose two optimization strategies: using feedback equalization to perform timing optimization, or using clock delay to perform timing optimization, so that the path also meets the setup time requirements (that is, ensuring that the data stably arrives at the trigger data input before the clock edge arrives, meeting the setup time requirements).
[0068] Feedback equalization, one of the timing optimization strategies, specifically involves inserting a feedback equalizer at an appropriate location in the path. By adjusting the phase and amplitude of the feedback signal, this compensates for path delays and stabilizes the data before the clock edge. Feedback equalization is used between the output of the combinational circuit and the data input of the trigger to optimize the path timing. The specific implementation method includes the following steps Sa1 to Sa2:
[0069] Step Sa1: Disconnect the connection between the output terminal of the combinational circuit and the data input terminal of the trigger, such as Figure 2 As shown, then enter step Sa2; Figure 2 As shown ( Figure 2 DFF in the figure represents a flip-flop, and the pins D, Clk, Q, and Q_bar of the flip-flop represent the data input terminal, clock input terminal, data output terminal, and inverted phase output terminal, respectively. The output state of pin Q_bar is opposite to that of pin Q). The combinational circuit is a digital circuit connected to the data input terminal of the flip-flop and composed of multiple logic units connected according to specific logic functions.
[0070] Specifically, a combinational circuit, also known as a combinational logic circuit, is a digital circuit composed of multiple logic units connected according to specific logical functions. These logic units typically refer to various logic gates, such as AND gates, OR gates, NOT gates, NAND gates, NOR gates, and XOR gates. The output of a combinational circuit depends solely on the current input signal and is independent of the circuit's previous state or historical inputs. In other words, the output of a combinational circuit is a function of the input signal, and this function does not involve time delay (other than propagation delay, which is the time it takes for the signal to pass through the circuit).
[0071] Step Sa2: insert a feedback equalizer between the output of the combinational circuit and the data input of the trigger, that is, connect the output of the combinational circuit to the data input of the feedback equalizer, connect the data output of the feedback equalizer to the data input of the trigger, and feed back the data output of the trigger to the feedback input of the feedback equalizer, as shown in FIG. Figure 3 See also Figure 3 The feedback equalizer includes, for example, an inverter INV1 and four MOS transistors M1 to M4 , and the data output end of the trigger is connected to the gates of the MOS transistors M2 to M3 in the feedback equalizer.
[0072] Specifically, the output signal of the combinational circuit is first processed by a feedback equalizer before being used as the input of a trigger. The feedback equalizer adjusts the switching threshold of the logic gate preceding the trigger based on the pre-sampled output, enabling rapid charging / discharging of the load capacitance of the critical path. This can reduce the propagation delay of the critical path in the combinational circuit, creating opportunities for increasing the operating frequency and / or voltage expansion of the combinational circuit, making the subthreshold circuit more robust to timing errors, and significantly reducing the main leakage power consumption of the entire design. The design parameters of the feedback equalizer depend on the specific timing problem and the required adjustment amount.
[0073] It should be noted that changes to the circuit connection relationships (disconnection, insertion, etc.) in the embodiments of the present application can be adjusted using EDA (Electronic Design Automation) software. In traditional circuit design, circuit disconnection and insertion typically require engineers to perform manual operations, which is time-consuming and error-prone. However, using EDA software, circuit disconnection and insertion can be automated. EDA software automatically adjusts the circuit connection relationships based on design rules and user requirements to ensure circuit accuracy and stability.
[0074] In one possible implementation, see Figure 4 , a Schmitt trigger can also be inserted between the data output of the feedback equalizer and the data input of the trigger, that is, the input of the Schmitt trigger is connected to the data output of the feedback equalizer, and the output of the Schmitt trigger is connected to the data input of the trigger.
[0075] As a dual-threshold buffer, the Schmitt trigger cleverly connects the output of the feedback circuit (i.e., the feedback equalizer) to its own input. This connection offers two major benefits: first, the feedback circuit stage effectively reduces inter-symbol interference (ISI) caused by voltage scaling, improving circuit stability; second, the Schmitt trigger can smoothly process any abnormal signals that may be generated by the feedback circuit, thereby preventing timing errors during high-speed operation and ensuring high-speed and reliable operation.
[0076] Another timing optimization strategy is to use clock delay at the clock input of the flip-flop (i.e., add a delay circuit at the clock input of the flip-flop) to optimize the path timing. This is to delay the arrival of the clock signal, thereby giving the data signal more time to meet the setup time requirement. The design of this delay circuit can adopt the following three schemes:
[0077] Solution 1: The delay circuit added to the clock input end of the trigger may include a MOS capacitor. Specifically, in the MOS tube, the gate is isolated from the source and the drain by an insulating layer (usually silicon dioxide). This insulating layer, the gate, and the semiconductor substrate constitute a MOS capacitor. When the MOS tube is used as a capacitor, a capacitor can be formed between its gate and the source (or drain). Since the capacitor has the characteristics of charging and discharging, when the input signal changes, the capacitor needs a certain amount of time to charge or discharge, thereby reaching a stable state. This process generates a delay. By adjusting the size or structure of the MOS tube, the size of the capacitor can be changed, thereby controlling the delay time. The MOS capacitor used in the embodiment of the present application can be an NMOS capacitor or a PMOS capacitor, such as Figure 5 or Figure 6 shown. Figure 5 It shows that when the MOS capacitor is an NMOS capacitor, the gate of the NMOS capacitor is connected to the clock input terminal of the trigger, and the semiconductor substrate of the NMOS capacitor is grounded; Figure 6 It shows that when the MOS capacitor is a PMOS capacitor, the gate of the PMOS capacitor is connected to the clock input terminal of the trigger, and the semiconductor substrate of the PMOS capacitor is connected to the power supply).
[0078] Solution 2: The delay circuit added to the clock input of the trigger can also include a logic unit with the same input signal and output signal. The input of the logic unit is connected to the clock input of the trigger, and the output of the logic unit is left floating. Figure 7 shown.
[0079] A logic cell whose input and output signals are identical—that is, a logic cell that does not perform any logical function—may include buffer circuits, drivers, and even-numbered inverters in series. While these cells do not themselves change the logic state, they introduce a certain amount of delay due to the presence of internal circuitry. The magnitude of this delay depends on the logic cell's internal circuit structure and component parameters. Leaving the output of a logic cell floating means it is not connected to a subsequent load circuit. In this case, signal propagation within the logic cell is not disturbed by the subsequent load, resulting in a more stable delay.
[0080] In one possible implementation, Figure 7 The logic units in the chip can adopt low-power design to reduce energy waste.
[0081] In a possible implementation, Figure 7 The logic unit in the combination circuit can be a logic unit using wide-gate-length MOS devices. The specific analysis is as follows: the wide-gate-length MOS devices have a longer gate length compared with the MOS devices used in conventional logic units. The increase in the gate length causes the switching speed of the MOS devices to slow down, because the carriers need a longer time to cross the channel under the gate. When the output signal of the combination circuit reaches the input end of the delay logic unit, the signal will experience an additional delay when passing through the delay logic unit due to the slower switching speed of the wide-gate-length MOS devices. The time of this delay depends on the specific parameters (such as the gate length, channel width, etc.) of the wide-gate-length MOS devices and the characteristics (such as the amplitude, frequency, etc.) of the input signal. Finally, the delayed signal will reach the data input end of the flip-flop, thereby achieving the delay processing of the signal.
[0082] Scheme three: the specific structure of the delay circuit added at the clock input end of the flip-flop is not limited, but the output end of the delay circuit is connected to the clock input end of the flip-flop, and the input end of the delay circuit is used to receive the clock signal, as shown in Figure 8 .
[0083] Of course, the two timing optimization strategies given in step S02 can also be combined and applied, and any two or three delay circuit design schemes under the second timing optimization strategy can also be combined and applied.
[0084] Step S03: for the path that does not meet the hold time requirement but meets the setup time requirement: between the output end of the combination circuit and the data input end of the flip-flop, the timing optimization of the path is performed in the manner of increasing the input data delay (i.e., increasing the cell delay time), so that the path meets both the hold time requirement and the setup time requirement, and the control ends.
[0085] Specifically, the input data delay is increased between the output end of the combination circuit and the data input end of the flip-flop, that is, the input data of the flip-flop is delayed, thereby prolonging the hold time of the data signal and ensuring that the data is kept long enough after the clock edge to meet the hold time requirement of the flip-flop. The specific implementation manner can include the following steps Sb1-Sb2:
[0086] Step Sb1: disconnect the connection between the output end of the combination circuit and the data input end of the flip-flop, and then enter step Sb2;
[0087] Step Sb2: insert a delay circuit (such as Figure 9), specifically including: connecting the input of the delay circuit to the input of the combinational circuit, and connecting the output of the delay circuit to the data input of the trigger. The delay circuit can be composed of multiple small delay circuit units connected in series.
[0088] Alternatively, the specific implementation method of delaying the input data of the trigger may also include: adding a delay circuit to the data input end of the trigger; the delay circuit includes a MOS capacitor. The MOS capacitor may be an NMOS capacitor or a PMOS capacitor, such as Figure 10 or Figure 11 shown. Figure 10 It shows that when the MOS capacitor is an NMOS capacitor, the gate of the NMOS capacitor is connected to the data input terminal of the trigger, and the semiconductor substrate of the NMOS capacitor is grounded; Figure 11 It shows that when the MOS capacitor is a PMOS capacitor, the gate of the PMOS capacitor is connected to the data input terminal of the trigger, and the semiconductor substrate of the PMOS capacitor is connected to the power supply.
[0089] Alternatively, the specific implementation method of delaying the input data of the trigger may also include: adding a delay circuit to the data input terminal of the trigger; the delay circuit includes a logic unit whose input signal and output signal are the same, the input terminal of the logic unit is connected to the data input terminal of the trigger, and the output terminal of the logic unit is left floating, such as Figure 12 In addition, the logic unit can adopt a low-power design to reduce energy waste. Figure 12 The logic unit device in the embodiment may be a logic unit using a wide gate length MOS device.
[0090] Of course, the above three design schemes for delaying the input data of the trigger can also be applied in combination.
[0091] Step S04: For paths that do not meet the hold time requirement and do not meet the setup time requirement: divide the path into four categories of sub-paths, the first category of sub-paths are sub-paths that do not meet the setup time requirement but meet the hold time requirement, the second category of sub-paths are sub-paths that do not meet the hold time requirement but meet the setup time requirement, the third category of sub-paths are sub-paths that do not meet the hold time requirement and do not meet the setup time requirement, and the fourth category of sub-paths are sub-paths that meet both the hold time requirement and the setup time requirement; then proceed to step S05.
[0092] Specifically, path partitioning refers to dividing the paths in the circuit into different groups or categories according to certain rules or algorithms in the circuit netlist (which can be regarded as a graph structure).
[0093] Step S05: Among all logic units belonging only to the first type of sub-path, feedback equalization is used to perform timing optimization on the first type of sub-path; among all logic units belonging only to the second type of sub-path, input data delay is increased to perform timing optimization on the second type of sub-path; among all logic units belonging only to the third type of sub-path, feedback equalization and input data delay are used to perform timing optimization on the third type of sub-path, so that the third type of sub-path meets both setup time requirements and hold time requirements. Control is terminated at this point.
[0094] Specifically, in order to simplify the optimization process, avoid optimization conflicts, and improve optimization efficiency and effect, this embodiment excludes corresponding common logic units from timing optimization, as detailed below:
[0095] Finding common logic cells between the first-type subpath and the second-type subpath, then, in the first-type subpath, excluding the logic cells shared with the second-type subpath, performing timing optimization on the first-type subpath among all remaining non-common logic cells (i.e., logic cells belonging only to the first-type subpath) by using feedback equalization, so that the first-type subpath meets both setup and hold time requirements; and, in the second-type subpath, excluding the logic cells shared with the first-type subpath, performing timing optimization on the second-type subpath among the remaining non-common logic cells (i.e., logic cells belonging only to the second-type subpath) by increasing input data delay, so that the second-type subpath meets both hold and setup time requirements.
[0096] In the third type of sub-path, after excluding the logic cells shared with the first and second types of sub-paths, the timing of the third type of sub-path is optimized by feedback equalization and increasing the input data delay between all remaining non-common logic cells (that is, logic cells belonging only to the third type of sub-path), so that the third type of sub-path meets both the setup time and hold time requirements.
[0097] For example, Figure 13As shown, the first subpath P1 consists of: U1-U4-U7-U9, the second subpath P2 consists of: U2-U5-U7-U9, and the third subpath P3 consists of: U3-U6-U8-U9. Find common logic cells (U7, U9) that do not meet the requirements of subpaths P1 and P2. Then, perform timing optimization between all logic cells (U1, U4) before U7 on subpath P1 to ensure that subpath P1 meets the setup time requirement. Perform timing optimization between all logic cells (U2, U5) before U7 on subpath P2 to ensure that subpath P2 meets the hold time requirement. Find the common logic cell (U9) between the first subpath P1, the second subpath P2, and the third subpath P3. Perform timing optimization between all logic cells (U3, U6, U8) before U9 on subpath P3 to ensure that subpath P3 meets the setup and hold time requirements.
[0098] In summary, the embodiments of the present application select and implement a matching timing optimization method (including accurately determining the device parameter values of circuits such as the feedback equalizer and the delay circuit) for each specific path that does not meet the timing requirements, so that the path meets both the timing requirements and the hold time requirements, thereby generating a more matching unit circuit layout and accelerating the timing convergence speed of the subthreshold circuit.
[0099] It should be noted that all of the above timing optimization processes include optimizing the device size within that path to determine transistor size parameter values that are more suitable for the path's timing requirements. Based on these new device size parameter values, the system automatically fine-tunes the unit circuit layout to generate a unit circuit layout corresponding to the new parameter values. Compared to the existing practice of simply selecting appropriate units from a predefined unit library, this method can generate unit circuits that better meet specific requirements, thereby more effectively achieving timing optimization and significantly accelerating the convergence process.
[0100] In one possible implementation, before performing timing analysis on the data input and output paths of each flip-flop in a subthreshold circuit, isomorphism analysis can be performed on each path within the subthreshold circuit. For all isomorphic paths, timing analysis and timing optimization are performed on only one path. The timing optimization results of this path are then reused in other isomorphic paths. This strategy not only significantly reduces redundant calculations during the optimization process but also greatly improves optimization efficiency.
[0101] Corresponding to the above method embodiment, the embodiment of the present application further provides a subthreshold circuit timing optimization device, including:
[0102] A timing analysis unit is used to perform timing analysis on the data input and output paths of each trigger in the sub-threshold circuit and identify the paths that do not meet the setup time requirement or the hold time requirement;
[0103] A first timing optimization unit is configured to optimize the timing of a path that does not meet the setup time requirement but meets the hold time requirement by: optimizing the timing of the path between the output of the combinational circuit and the data input of the flip-flop using feedback equalization; or optimizing the timing of the path at the clock input of the flip-flop using clock delay; the combinational circuit is a digital circuit connected to the data input of the flip-flop and composed of multiple logic units connected according to a specific logic function;
[0104] A second timing optimization unit is configured to optimize the timing of a path that does not meet the hold time requirement but meets the setup time requirement by increasing an input data delay between the output terminal of the combinational circuit and the data input terminal of the trigger;
[0105] The third timing optimization unit is used to divide the paths that do not meet the hold time requirement and the setup time requirement into four categories of sub-paths, the first category of sub-paths being sub-paths that do not meet the setup time requirement but meet the hold time requirement, the second category of sub-paths being sub-paths that do not meet the hold time requirement but meet the setup time requirement, the third category of sub-paths being sub-paths that do not meet the hold time requirement and do not meet the setup time requirement, and the fourth category of sub-paths being sub-paths that meet both the hold time requirement and the setup time requirement; among all logic units that belong only to the first category of sub-paths, the first category of sub-paths are timing optimized by feedback equalization; among all logic units that belong only to the second category of sub-paths, the second category of sub-paths are timing optimized by increasing input data delay; and among all logic units that belong only to the third category of sub-paths, the third category of sub-paths are timing optimized by both feedback equalization and increasing input data delay.
[0106] In addition, an embodiment of the present application also provides a computer program product, including computer-readable instructions. When the computer-readable instructions are executed on an electronic device, the electronic device implements any of the above-mentioned subthreshold circuit timing optimization methods.
[0107] An embodiment of the present application further provides an electronic device, including at least one processor and a memory connected to the processor, wherein:
[0108] The memory is used to store computer programs;
[0109] The processor is configured to execute the computer program so as to enable the electronic device to implement any of the above-mentioned sub-threshold circuit timing optimization methods.
[0110] An embodiment of the present application also provides a computer storage medium, which carries one or more computer programs. When the one or more computer programs are executed by an electronic device, the electronic device can implement any of the above-mentioned subthreshold circuit timing optimization methods.
[0111] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the embodiments of the present application. Therefore, the embodiments of the present application are not limited to the embodiments shown herein, but are intended to conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A subthreshold circuit timing optimization method, characterized in that: include: Perform timing analysis on the data input and output paths of each flip-flop in the subthreshold circuit to identify paths that do not meet setup or hold time requirements. For paths that do not meet setup time requirements but meet hold time requirements: between the output of a combinational circuit and the data input of a flip-flop, the path is optimized for timing using feedback equalization; or, at the clock input of the flip-flop, the path is optimized for timing using clock delay. The combinational circuit is a digital circuit connected to the data input of the flip-flop and composed of multiple logic units connected according to a specific logic function. For a path that does not meet the hold time requirement but meets the setup time requirement: between the output terminal of the combinational circuit and the data input terminal of the trigger, the path is optimized by increasing the input data delay; For paths that do not meet the hold time requirement and do not meet the setup time requirement: the paths are divided into four categories of sub-paths, the first category of sub-paths are sub-paths that do not meet the setup time requirement but meet the hold time requirement, the second category of sub-paths are sub-paths that do not meet the hold time requirement but meet the setup time requirement, the third category of sub-paths are sub-paths that do not meet the hold time requirement and do not meet the setup time requirement, and the fourth category of sub-paths are sub-paths that meet both the hold time requirement and the setup time requirement; between all logic units that belong only to the first category of sub-paths, the first category of sub-paths are optimized for timing by using feedback equalization; between all logic units that belong only to the second category of sub-paths, the second category of sub-paths are optimized for timing by using an increased input data delay; between all logic units that belong only to the third category of sub-paths, the third category of sub-paths are optimized for timing by using feedback equalization and an increased input data delay.
2. The subthreshold circuit timing optimization method according to claim 1, characterized in that: The timing optimization of the path between the output terminal of the combinational circuit and the data input terminal of the trigger is performed by using feedback equalization, including: disconnecting the output of the combinational circuit from the data input of the flip-flop; A feedback equalizer is inserted between the output terminal of the combinational circuit and the data input terminal of the trigger, so that the output terminal of the combinational circuit is connected to the data input terminal of the feedback equalizer, the data output terminal of the feedback equalizer is connected to the data input terminal of the trigger, and the data output terminal of the trigger is connected to the feedback input terminal of the feedback equalizer.
3. The subthreshold circuit timing optimization method according to claim 2, characterized in that: The method of optimizing the timing of the path between the output terminal of the combinational circuit and the data input terminal of the trigger by using feedback equalization also includes: A Schmitt trigger is inserted between the data output of the feedback equalizer and the data input of the trigger, so that the input of the Schmitt trigger is connected to the data output of the feedback equalizer, and the output of the Schmitt trigger is connected to the data input of the trigger.
4. The subthreshold circuit timing optimization method according to claim 1, characterized in that: The method of optimizing the timing of the path by using clock delay at the clock input end of the trigger comprises: adding a delay circuit at the clock input end of the trigger; The delay circuit includes: a PMOS capacitor or an NMOS capacitor; when the MOS capacitor is an NMOS capacitor, the gate of the NMOS capacitor is connected to the clock input terminal of the trigger, and the semiconductor substrate of the NMOS capacitor is grounded; when the MOS capacitor is a PMOS capacitor, the gate of the PMOS capacitor is connected to the clock input terminal of the trigger, and the semiconductor substrate of the PMOS capacitor is connected to the power supply; Alternatively, the delay circuit comprises: a logic unit having an input signal and an output signal that are the same, an input terminal of the logic unit being connected to a clock input terminal of a trigger, and an output terminal of the logic unit being left floating; Alternatively, the output end of the delay circuit is connected to the clock input end of the trigger, and the input end of the delay circuit is used to receive a clock signal.
5. The subthreshold circuit timing optimization method according to claim 1, characterized in that: The timing optimization of the path between the output terminal of the combinational circuit and the data input terminal of the trigger is performed by increasing the input data delay, including: disconnecting the output terminal of the combinational circuit and the data input terminal of the trigger; inserting a delay circuit between the output terminal of the combinational circuit and the data input terminal of the trigger; Alternatively, the timing of the path is optimized by increasing an input data delay between the output terminal of the combinational circuit and the data input terminal of the trigger, including: adding a delay circuit to the data input terminal of the trigger; the delay circuit includes a PMOS capacitor or an NMOS capacitor; when the MOS capacitor is an NMOS capacitor, the gate of the NMOS capacitor is connected to the data input terminal of the trigger, and the semiconductor substrate of the NMOS capacitor is grounded; when the MOS capacitor is a PMOS capacitor, the gate of the PMOS capacitor is connected to the data input terminal of the trigger, and the semiconductor substrate of the PMOS capacitor is connected to a power supply; Alternatively, the timing of the path is optimized by increasing the input data delay between the output terminal of the combinational circuit and the data input terminal of the trigger, including: adding a delay circuit to the data input terminal of the trigger; the delay circuit includes a logic unit whose input signal and output signal are the same, the input terminal of the logic unit is connected to the data input terminal of the trigger, and the output terminal of the logic unit is left floating.
6. The subthreshold circuit timing optimization method according to any one of claims 1 to 5, characterized in that: Before performing timing analysis on the data input and output paths of each trigger in the subthreshold circuit, the method also includes: performing isomorphic analysis on each path of the subthreshold circuit, performing timing analysis and timing optimization on only one of all isomorphic paths, and then reusing the timing optimization result of the current path in other isomorphic paths.
7. A subthreshold circuit timing optimization device, characterized in that: include: A timing analysis unit is used to perform timing analysis on the data input and output paths of each trigger in the sub-threshold circuit and identify the paths that do not meet the setup time requirement or the hold time requirement; A first timing optimization unit is configured to optimize the timing of a path that does not meet the setup time requirement but meets the hold time requirement by: optimizing the timing of the path between the output of the combinational circuit and the data input of the flip-flop using feedback equalization; or optimizing the timing of the path at the clock input of the flip-flop using clock delay; the combinational circuit is a digital circuit connected to the data input of the flip-flop and composed of multiple logic units connected according to a specific logic function; A second timing optimization unit is configured to optimize the timing of a path that does not meet the hold time requirement but meets the setup time requirement by increasing an input data delay between the output terminal of the combinational circuit and the data input terminal of the trigger; The third timing optimization unit is used to divide the paths that do not meet the hold time requirement and the setup time requirement into four categories of sub-paths, the first category of sub-paths being sub-paths that do not meet the setup time requirement but meet the hold time requirement, the second category of sub-paths being sub-paths that do not meet the hold time requirement but meet the setup time requirement, the third category of sub-paths being sub-paths that do not meet the hold time requirement and do not meet the setup time requirement, and the fourth category of sub-paths being sub-paths that meet both the hold time requirement and the setup time requirement; among all logic units that belong only to the first category of sub-paths, the first category of sub-paths are timing optimized by feedback equalization; among all logic units that belong only to the second category of sub-paths, the second category of sub-paths are timing optimized by increasing input data delay; and among all logic units that belong only to the third category of sub-paths, the third category of sub-paths are timing optimized by both feedback equalization and increasing input data delay.
8. A computer program product, characterized in that The method comprises computer-readable instructions, which, when executed on an electronic device, enable the electronic device to implement the sub-threshold circuit timing optimization method according to any one of claims 1 to 6.
9. An electronic device, characterized in that: comprising at least one processor and a memory connected to the processor, wherein: The memory is used to store computer programs; The processor is configured to execute the computer program so as to enable the electronic device to implement the subthreshold circuit timing optimization method according to any one of claims 1 to 6.
10. A computer storage medium, characterized in that The storage medium carries one or more computer programs, and when the one or more computer programs are executed by an electronic device, the electronic device can implement the subthreshold circuit timing optimization method according to any one of claims 1 to 6.