Display panel and display device including the same

Abstract

Disclosed are a display panel having a large area, high resolution, a narrow bezel, low power consumption, and reduced RC (Resistance-Capacitance) delay, and a display device including the same. The display panel comprises an AAGIP (in-panel active area grid) unit which is arranged between adjacent pixel blocks, the AAGIP unit is configured to connect an n-scan line provided in an n-th row of sub-pixels in a pixel block along one side of the AAGIP unit and an n-scan line provided in an (n + 1)-th row of sub-pixels in a pixel block along the other side of the AAGIP unit to each other; and connecting an (n + 1)-th scan line provided in the (n + 1)-th row of sub-pixels in the pixel block along one side of the AAGIP unit and an (n + 1)-th scan line provided in the (n + 1)-th row of sub-pixels in the pixel block along the other side of the AAGIP unit to each other. Accordingly, defects such as crosstalk or smear caused by data line transitions are reduced.

Description

[0001] This application is a divisional application, and its parent application is an application with a filing date of July 21, 2022, an application number of 202210873648.4, and an invention name of “Display panel and display device comprising the display panel”. Technical Field

[0002] The present disclosure relates to a display panel having a large area, high resolution, narrow frame, low power consumption and reduced RC (resistance-capacitance) delay, and a display device including the display panel. Background Art

[0003] Flat panel display devices (FPDs) include organic light emitting diode (OLED) display devices having high brightness and low operating voltage.

[0004] The OLED display device is a self-luminous device that emits light by itself. Therefore, the contrast of the OLED display device is high, and the device can realize an ultra-thin display. The response time of the OLED display device is several microseconds, making it easy to realize moving images. There is no restriction on the viewing angle. The device is stable even at low temperatures. The device operates at a relatively low DC voltage of 5V to 15V. Therefore, it is easy to manufacture and design its operating circuit.

[0005] Each pixel region of the OLED display device includes a plurality of thin film transistors, such as a switching thin film transistor, a driving thin film transistor, and a sensing thin film transistor. Summary of the invention

[0006] As the size of display panels of OLED display devices becomes larger and larger, the design of the device becomes an increasingly important factor. The device adopts an AAGIP (active area gate in panel) scheme that sets a gate driving circuit in the display area (active area) AA for each predetermined pixel block.

[0007] The OLED display device of the AAGIP scheme applies the same GIP scan signal to the same horizontal line of the pixel block for each predetermined pixel block. In addition, a control share pixel that controls application of a voltage signal is used in the OLED display device of the AAGIP scheme.

[0008] The AAGIP disposed in the panel applies scan signals to the same horizontal scan lines. Since the scan lines are greatly affected by the data lines to which the data voltage signals are applied, crosstalk may occur.

[0009] For example, ripples occur due to fluctuations in the data voltage signal of the data line (data line transition), and horizontal crosstalk occurs due to the influence of non-black screen data (non-black box data) caused by the ripples. Thus, the degree of crosstalk or smear varies based on the size of the black box causing the ripples and the grayscale of the data voltage pattern.

[0010] Therefore, in order to solve the above problems, the inventors of the present disclosure invented an AAGIP scheme display panel in which a gate driving circuit is set in each predetermined pixel block in the display area of ​​an OLED display device to reduce defects such as crosstalk or smear caused by data signal fluctuations of data lines.

[0011] Furthermore, the inventors of the present disclosure have invented a display device in which individual operations of horizontal scan lines for each pixel block in a display area can minimize the influence of the same data signal (eg, a crosstalk pattern).

[0012] The purpose according to the present disclosure is not limited to the above-mentioned purpose. Other purposes and advantages according to the present disclosure that are not mentioned can be understood based on the following description, and these purposes and advantages can be more clearly understood according to the embodiments of the present disclosure. In addition, it is easy to understand that the methods shown in the claims and their combinations can be used to achieve the purposes and advantages according to the present disclosure.

[0013] A display panel according to a first embodiment of the present disclosure may be provided. The display panel includes: a plurality of pixel blocks, each pixel block including a plurality of sub-pixels arranged in rows and columns; and a plurality of AAGIP (active area gate within panel) units, each AAGIP unit being arranged between adjacent pixel blocks in the plurality of pixel blocks, wherein the n-th row of sub-pixels in the pixel blocks along one side of an AAGIP unit is provided with n scan lines in the n-th row of sub-pixels, and the n+1-th row of sub-pixels in the pixel blocks along one side of the AAGIP unit is provided with n+1 scan lines in the n+1-th row of sub-pixels, wherein the n-th row of sub-pixels in the pixel blocks along the other side of the AAGIP unit is provided with n+1 scan lines in the n-th row of sub-pixels, and the n+1-th row of sub-pixels in the pixel blocks along the other side of the AAGIP unit is provided with n+1 scan lines in the n-th row of sub-pixels. The n+1th row of sub-pixels in the pixel block is provided with n scan lines in the n+1th row of sub-pixels, wherein the one AAGIP unit is configured to: connect the n scan lines in the n+1th row of sub-pixels in the pixel block along one side of the one AAGIP unit to the n scan lines in the n+1th row of sub-pixels in the pixel block along the other side of the one AAGIP unit; and connect the n+1 scan lines in the n+1th row of sub-pixels in the pixel block along one side of the one AAGIP unit to the n+1 scan lines in the n+1th row of sub-pixels in the pixel block along the other side of the one AAGIP unit.

[0014] In addition, a display panel according to the second embodiment of the present disclosure may be provided. The display panel includes: a plurality of pixel blocks, each pixel block including a plurality of sub-pixels arranged in rows and columns; and a plurality of AAGIP (active area gate within panel) units, each AAGIP unit being arranged between adjacent pixel blocks in the plurality of pixel blocks, wherein the n-th row of sub-pixels in the pixel blocks along one side of an AAGIP unit is provided with n scan lines in the n-th row of sub-pixels, and the n+1-th row of sub-pixels in the pixel blocks along one side of the AAGIP unit is provided with n+1 scan lines in the n+1-th row of sub-pixels, wherein the n-th row of sub-pixels in the pixel blocks along the other side of the AAGIP unit is provided with n scan lines in the n-th row of sub-pixels, and the n+1-th row of sub-pixels in the pixel blocks along the other side of the AAGIP unit is provided with n scan lines in the n-th row of sub-pixels. The row sub-pixels are provided with n+1 scan lines in the n+1th row of sub-pixels, wherein the one AAGIP unit is configured to: apply N scan signals to the n scan lines in the n+1th row of sub-pixels in the pixel blocks along one side of the one AAGIP unit and to the n+1 scan lines in the n+1th row of sub-pixels in the pixel blocks along the other side of the one AAGIP unit; and apply N+1 scan signals to the n+1 scan lines in the n+1th row of sub-pixels in the pixel blocks along one side of the one AAGIP unit and to the n scan lines in the n+1th row of sub-pixels in the pixel blocks along the other side of the one AAGIP unit.

[0015] In addition, a display device according to one embodiment of the present disclosure may be provided. The display device includes the display panel according to the first embodiment as described above, a data driver for applying a data signal to the display panel, a power supply for providing various types of power to the display panel, and a timing controller for controlling a plurality of AAGIP units and the data driver.

[0016] In addition, a display device according to another embodiment of the present disclosure may be provided. The display device includes the display panel according to the second embodiment as described above, a data driver for applying a data signal to the display panel, a power supply for providing various types of power to the display panel, and a timing controller for controlling a plurality of AAGIP units and the data driver.

[0017] According to the embodiments of the present disclosure, the display device can reduce defect phenomena such as crosstalk or smear caused by a data signal change (data line transition) of a data line.

[0018] Furthermore, according to the embodiments of the present disclosure, the display device can significantly reduce the RC delay caused by the large-area screen.

[0019] Furthermore, according to an embodiment of the present disclosure, changing the operation timing used in the 2Scan 1EM scheme can compensate for the operating power reduction (VDDIR reduction).

[0020] In addition, according to the embodiments of the present disclosure, the display device can ensure a sampling time of more than 8H without increasing the signal lines in the 2Scan 1EM scheme.

[0021] Furthermore, according to an embodiment of the present disclosure, separate operations for the horizontal scan line of each pixel block can minimize the influence of the same data signal (eg, a crosstalk pattern).

[0022] Furthermore, according to the embodiments of the present disclosure, a display panel having a large area, high resolution, narrow frame, and low power consumption and a display device including the display panel may be realized.

[0023] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art through the following description.

[0024] In addition to the above-described effects, specific effects of the present disclosure will be described together with specific details for carrying out the present disclosure described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a configuration diagram schematically showing a configuration of a display panel according to an embodiment of the present disclosure.

[0026] Figure 2 is a view showing an example of the configuration of each block in a display panel according to an embodiment of the present disclosure.

[0027] Figure 3 It shows Figure 2 A view of an example of a pixel block configuration in each block in FIG.

[0028] Figure 4 is a view showing an example of a connection configuration of respective AAGIP units in a display panel according to an embodiment of the present disclosure.

[0029] Figure 5 is a view showing an example of applying AAGIP control signals having different timings to different blocks in a display panel according to an embodiment of the present disclosure.

[0030] Figure 6 is a view showing an example in which, when data voltage fluctuation occurs in a display panel, ripples are reduced as scan lines are switched by an AAGIP unit according to an embodiment of the present disclosure.

[0031] Figure 7is a view showing an example in which the AAGIP unit actually connects scan lines of adjacent pixel blocks to each other according to an embodiment of the present disclosure.

[0032] Figure 8 is an exemplary view showing the width of an AAGIP unit when one sub-pixel in a display panel has an 8T1C structure according to an embodiment of the present disclosure.

[0033] Fig. 9 2 is a view showing an example of respectively applying scan signals to 2 scan lines in a display panel according to an embodiment of the present disclosure.

[0034] Fig.10 and Fig.11 is a view illustrating an example of securing a bezel area due to an AAGIP unit in a display panel according to an embodiment of the present disclosure.

[0035] Fig.12 is a configuration diagram showing an example of providing an AAGIP unit for each data driver according to an embodiment of the present disclosure.

[0036] Fig.13 is a view showing a circuit configuration of one sub-pixel provided in a display area of ​​a display panel according to an embodiment of the present disclosure.

[0037] Fig.14 It is shown that Fig.13 A view showing an example of the arrangement of transistors and wirings of a sub-pixel circuit configuration. DETAILED DESCRIPTION

[0038] For the sake of simple and clear explanation, the elements in the drawings are not necessarily drawn to scale. The same reference numerals in different drawings represent the same or similar elements, and therefore perform similar functions. In addition, the description and details of known steps and elements are omitted to simplify the description. In addition, in the following detailed description of the present disclosure, many specific details are set forth to provide a comprehensive understanding of the present disclosure. However, it should be understood that the present disclosure can be implemented without these specific details. In other cases, known methods, procedures, components and circuits are not described in detail so as not to unnecessarily obscure various aspects of the present disclosure. The examples of various embodiments are further described and described below. It should be understood that the description herein is not intended to limit the claims to the specific embodiments described. On the contrary, it is intended to cover alternatives, modifications and equivalents that may be included in the spirit and scope of the present disclosure defined by the appended claims.

[0039] The shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings for describing the embodiments of the present disclosure are merely exemplary, and the present disclosure is not limited thereto. In this article, the same reference numerals refer to the same elements. In addition, the description and details of known steps and elements are omitted to simplify the description. In addition, in the following detailed description of the present disclosure, many specific details are set forth to provide a comprehensive understanding of the present disclosure. However, it should be understood that the present disclosure can be implemented without these specific details. In other cases, known methods, procedures, components and circuits are not described in detail so as not to unnecessarily obscure various aspects of the present disclosure.

[0040] The terms used herein are only used to describe the purpose of specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one" and "a" are intended to also include plural forms, unless the context clearly indicates otherwise. It should be further understood that when the terms "including" and "comprising" are used in this specification, it is explained that there are the features, integers, operations, elements and / or components described, but it is not excluded that there are or add one or more other features, integers, operations, elements, components and / or parts thereof. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. When, for example, the expression of "at least one" is before a series of elements, the series of elements can be modified as a whole, and the individual elements in the series of elements cannot be modified. When "C to D" is mentioned, it refers to C (including) to D (including), unless otherwise stated.

[0041] It should be understood that although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below can be referred to as the second element, component, region, layer or part.

[0042] It should be understood that when an element or layer is referred to as being “connected to” or “engaged to” another element or layer, it can be directly on, directly connected to or engaged to the other element or layer, or one or more intervening elements or layers may be present. Additionally, it should be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0043] In addition, as used herein, when a layer, film, region, plate, etc. can be arranged "on" or "on top" of another layer, film, region, plate, etc., the former can directly contact the latter, or another layer, film, region, plate, etc. can be arranged between the former and the latter. As used herein, when a layer, film, region, plate, etc. is directly arranged "on" or "on top" of another layer, film, region, plate, etc., the former directly contacts the latter, and another layer, film, region, plate, etc. is not arranged between the former and the latter. In addition, as used herein, when a layer, film, region, plate, etc. can be arranged "under" or "below" of another layer, film, region, plate, etc., the former can directly contact the latter, or another layer, film, region, plate, etc. can be arranged between the former and the latter. As used herein, when a layer, film, region, plate, etc. is directly arranged "under" or "below" of another layer, film, region, plate, etc., the former directly contacts the latter, and another layer, film, region, plate, etc. is not arranged between the former and the latter.

[0044] For ease of explanation, spatially relative terms such as "under," "beneath," "lower," "below," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the accompanying drawings. For example, when the device in the accompanying drawings is turned over, elements described as being "under," "below," or "below" other elements or features will be oriented "above" the other elements or features. Thus, the example terms "under" and "below" may encompass both above and below orientations. The device may be oriented in other ways, for example, rotated 90 degrees or in other orientations, and the spatially relative descriptions used herein should be interpreted accordingly.

[0045] Unless otherwise defined, all terms (including technical or scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the inventive concept belongs. It should be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted as an idealized or overly formalized meaning unless explicitly defined herein.

[0046] The features of various embodiments of the present disclosure may be combined with each other in part or in whole, and may be technically associated with each other or interoperate with each other. These embodiments may be implemented independently of each other, and may be implemented together in an associated relationship.

[0047] In interpreting numerical values ​​in the present disclosure, a range of error may be inherent even if not expressly stated individually.

[0048] In the description of a signal flow relationship, for example, when a signal is transmitted from node A to node B, the signal may be transmitted from node A to node B via node C unless an indication that the signal is transmitted directly from node A to node B is described.

[0049] Hereinafter, a display panel and a display device including the same according to an embodiment of the present disclosure will be described.

[0050] Figure 1 is a schematic view showing a configuration of a display panel according to an embodiment of the present disclosure. Figure 2 is a diagram showing a configuration example of each block in a display panel according to an embodiment of the present disclosure. Figure 3 It shows Figure 2 A view of an example of a pixel block configuration in each block. Figure 4 is a view showing an example of a connection configuration of respective AAGIP units in a display panel according to an embodiment of the present disclosure.

[0051] refer to Figures 1 to 4 , the display panel 100 according to an embodiment of the present disclosure may include a plurality of pixel blocks 110 and 120 and a plurality of AAGIP units 210 and 220 .

[0052] The plurality of pixel blocks 110 and 120 may be arranged so that the same pixel blocks may be arranged in the same row. For example, the same first pixel block 110 may be arranged in the first row, and the same second pixel block 120 may be arranged in the second row.

[0053] The plurality of AAGIP units 210 and 220 may be provided such that one AAGIP unit 210 may be provided between the plurality of pixel blocks 110 and 120 .

[0054] A pixel block group may include at least one pixel block. Figure 1 As shown, one pixel block group may include a first pixel block 110 in the first row and first column and a second pixel block 120 in the second row and first column. However, the present disclosure is not limited thereto, and one pixel block group may include pixel blocks arranged in two rows and two columns.

[0055] An AAGIP unit may be provided for each of at least one pixel block. Figure 1 As shown, an AAGIP unit can be set for a group of pixel blocks arranged in two rows and one column. That is, a first AAGIP unit 210 can be set for the first pixel block 110 and the second pixel block 120 of the first pixel block group, and a second AAGIP unit 220 can be set for the first pixel block 110 and the second pixel block 120 of the second pixel block group.

[0056] In an embodiment of the present disclosure, at least one AAGIP unit is disposed in a display area (active area) of a display panel, and thus may be referred to as an “AAGIP” or an “AAGIP unit”.

[0057] Each pixel block may include a plurality of sub-pixels arranged in rows and columns, wherein each sub-pixel includes a light-emitting element OLED. For example, the plurality of sub-pixels may include at least one of red, green, blue and white sub-pixels. Each pixel block may include a unit pixel area composed of at least one sub-pixel. A driving element may be provided in each of the at least one sub-pixel. The AAGIP elements constituting the level may be dispersedly arranged in the unit pixel area. The AAGIP element may include an AAGIP TFT and a capacitor.

[0058] In the pixel block on one side of the AAGIP unit, the n scan line can be arranged in the nth row of sub-pixels along the nth row of sub-pixels, and the n+1 scan line can be arranged in the n+1th row of sub-pixels along the n+1th row of sub-pixels. Figure 1 As shown, N+1 scanning line SL N+1 The first pixel block 110 may be arranged along the left side of the first AAGIP unit 210. In the first pixel block 110, the N scan lines SL N The sub-pixels may be arranged in the second pixel block 120 along the left side of the first AAGIP unit 210. Thus, the n+1th row of sub-pixels is arranged in the first pixel block 110 on the left side of the first AAGIP unit 210, and the nth row of sub-pixels is arranged in the second pixel block 120 on the left side of the first AAGIP unit 210. In the embodiment of the present disclosure, N or n is a natural number or a non-negative integer.

[0059] In addition, in the pixel block on the other side of the AAGIP unit, the n+1 scan line can be arranged in the nth row of sub-pixels along the nth row of sub-pixels, and the n scan line can be arranged in the n+1th row of sub-pixels along the n+1th row of sub-pixels. Figure 1 As shown, N scanning lines SL N It can be set in the first pixel block 110 on the right side of the first AAGIP unit 210, and the N+1 scan line SL N+1 The nth row of subpixels may be arranged in the second pixel block 120 on the right side of the first AAGIP unit 210. Thus, the nth row of subpixels is arranged in the first pixel block 110 on the right side of the first AAGIP unit 210, and the n+1th row of subpixels is arranged in the second pixel block 120 on the right side of the first AAGIP unit 210.

[0060] The AAGIP unit can electrically connect the N scan lines of the pixel block on one side with the N scan lines of the pixel block on the other side. That is, the AAGIP unit can electrically connect the N scan lines arranged in the nth row of sub-pixels along the nth row of sub-pixels in the pixel block on one side with the N scan lines arranged in the nth row of sub-pixels along the n+1th row of sub-pixels in the pixel block on the other side. For example, Figure 1 In the example, the first AAGIP unit 210 can make the N scan lines SL of the second pixel block 120 on the left side N and the N scanning lines SL of the first pixel block 110 on the right side N Thus, the second pixel block 120 on the left side of the first AAGIP unit 210 and the first pixel block 110 on the right side of the first AAGIP unit 210 are located in different rows.

[0061] The AAGIP unit can electrically connect the N+1 scan line of the pixel block on one side with the N+1 scan line of the pixel block on the other side. That is, the AAGIP unit can electrically connect the N+1 scan line set in the n+1 row of sub-pixels along the n+1 row of sub-pixels in the pixel block on one side with the N+1 scan line set in the n row of sub-pixels along the n row of sub-pixels in the pixel block on the other side. For example, Figure 1 In the example, the first AAGIP unit 210 can make the N+1 scan line SL of the first pixel block 110 on the left side N+1 and the N+1 scanning line SL of the second pixel block 120 on the right side N+1 Thus, the first pixel block 110 on the left side of the first AAGIP unit 210 and the second pixel block 120 on the right side of the first AAGIP unit 210 are located in different rows.

[0062] As described above, an AAGIP unit disposed between multiple pixel blocks can electrically connect N scan lines of one pixel block on one side and N scan lines of another pixel block located in different rows. Thus, a pixel block group can be composed of the nth row of pixel blocks and the n+1th row of pixel blocks.

[0063] In addition, one AAGIP unit disposed between a plurality of pixel blocks may electrically connect an N+1 scan line of a pixel block on one side and an N+1 scan line of a pixel block on the other side located in different rows.

[0064] The AAGIP unit with the above configuration can apply N scan signals to n scan lines of pixel blocks on one side and n scan lines of pixel blocks on the other side, and can apply N+1 scan signals to n+1 scan lines of pixel blocks on one side and n+1 scan lines of pixel blocks on the other side.

[0065] For example, in Figure 1In the embodiment, the first AAGIP unit 210 may apply the N scan signal GIP N to the N scan line SL in the second pixel block 120 disposed in the second row and the first column on the left side thereof. N , and the N scanning lines SL in the first pixel block 110 in the first row and second column arranged on the right side thereof N .

[0066] In addition, Figure 1 In the embodiment, the first AAGIP unit 210 may apply the N+1 scan signal GIP N+1 to the n+1 scan line SL in the first pixel block 110 in the first row and the first column disposed on the left side thereof. N+1 , and the n+1 scanning line SL in the second pixel block 120 in the second row and the second column arranged on the right side thereof N+1 .

[0067] In one example, if Figure 2 As shown, one block may include a plurality of pixels PXL and a plurality of AAGIP units 210 , 212 , and 214 .

[0068] refer to Figure 2 , the first block BL1 may include an n-th row of pixels PXL and an (n+1)-th row of pixels PXL. That is, the first block BL1 may include pixels arranged in 2 rows and 3 columns and 3 AAGIP units 210 , 212 , and 214 .

[0069] Thus, in the first block BL1 , a first-second AAGIP unit 214 is provided for the first column of pixels, a first-first AAGIP unit 212 is provided for the second column of pixels, and a first AAGIP unit 210 is provided for the third column of pixels.

[0070] In addition, in the first block BL1, the N scanning lines SL N The pixels from the first to the third columns of the Nth row can be arranged therein, and the N+1 scanning line SL N-1 Pixels in the first to third columns along the N+1th row may be arranged therein.

[0071] exist Figure 2 , similar to the first block BL1 , each of the second block BL2 and the third block BL3 may include pixels arranged in 2 rows and 3 columns, and 3 AAGIP units 210 , 212 , and 214 , wherein the 2 rows include the Nth row and the N+1th row.

[0072] In the second block BL2, N scan lines SL N The pixels from the first to the third columns of the Nth row can be arranged therein, and the N+1 scanning line SL N-1 Pixels in the first to third columns along the N+1th row may be arranged therein.

[0073] In the third block BL3, N scan lines SL N The pixels from the first to the third columns of the Nth row can be arranged therein, and the N+1 scanning line SL N-1 Pixels in the first to third columns along the N+1th row may be arranged therein.

[0074] In each of the first block BL1, the second block BL2, and the third block BL3, one pixel PXL may include at least one of red, green, blue, and white sub-pixels. Hereinafter, a pixel may have a reference numeral "PXL" and a sub-pixel may have a reference numeral "PX". In addition, a sub-pixel may have a reference numeral "R", "G", "B", or "W" based on a color.

[0075] exist Figure 2 , it is shown that a block includes a plurality of pixels PXL and a plurality of AAGIP units 210, 212, and 214. However, the present disclosure is not limited thereto. A block may be configured in various ways. For example, although not shown in the drawings, a block may include a plurality of pixel blocks and a plurality of AAGIP units, or a block may include a pixel block and an AAGIP unit. Thus, a pixel block may include at least one sub-pixel.

[0076] In the pixel block on one side of the AAGIP unit, n scan lines may be arranged in the n-row sub-pixels along the n-row sub-pixels, and n+1 scan lines may be arranged in the n+1-row sub-pixels along the n+1-row sub-pixels. For example, the first to third columns of sub-pixels in the n-row along the left side of the first AAGIP unit 210 have n scan lines arranged therein, while the first to third columns of sub-pixels in the n+1-row along the left side of the first AAGIP unit 210 have n+1 scan lines arranged therein.

[0077] In the pixel block on the other side of the AAGIP unit, n scan lines may be arranged in the nth row of sub-pixels along the nth row, and n+1 scan lines may be arranged in the nth+1th row of sub-pixels along the nth+1th row of sub-pixels. The first to third columns of sub-pixels in the nth row on the right side of the first AAGIP unit 210 have n scan lines arranged therein, while the first to third columns of sub-pixels in the nth+1th row on the right side of the first AAGIP unit 210 have n+1 scan lines arranged therein.

[0078] The AAGIP unit can apply an N scan signal to the n scan line of the pixel block on one side and the n+1 scan line of the pixel block on the other side, and can apply an N+1 scan signal to the n+1 scan line of the pixel block on one side and the n scan line of the pixel block on the other side. For example, the first AAGIP unit 210 can apply the same N scan signal to the N scan line SL of the first block BL1. N and the N+1 scanning line SL of the second block BL2N+1 In addition, the first AAGIP unit 210 may apply the same N+1 scan signal to the N+1 scan line SL of the first block BL1. N+1 and the N scanning lines SL of the second block BL2 N Each of the .

[0079] That is, the AAGIP units set on a predetermined block basis may apply different scan signals to the same scan lines of different blocks, respectively, for their individual operations.

[0080] For example, the first AAGIP unit 210 may apply an N scan signal to the N scan line SL of the first block BL1. N , and applies the N+1 scan signal to the N scan line SL of the second block BL2 N , to operate independently on adjacent pixel blocks.

[0081] In addition, the first AAGIP unit 210 may apply an N+1 scan signal to the N+1 scan line SL of the first block BL1. N+1 , and the N scan signal may be applied to the N+1 scan line SL of the second block BL2 N+1 , to perform separate operations on adjacent pixel blocks.

[0082] As described above, the AAGIP based on the predetermined block setting can respectively apply different scan signals to two adjacent pixel blocks in a software manner to perform separate operations of the adjacent pixel blocks.

[0083] refer to Figure 3 According to an embodiment of the present disclosure, the display panel 100 may include a plurality of pixel blocks and a plurality of AAGIP units, wherein one pixel block may include at least one of the sub-pixels R, G, and B.

[0084] For example, the plurality of pixel blocks may include a first row and first column pixel block, a second row and first column pixel block, a first row and second column pixel block, and a second row and second column pixel block.

[0085] For example, the plurality of AAGIP units may include a first-first AAGIP unit 212 provided for first row and first column pixel blocks and a first AAGIP unit 210 provided for first row and second column pixel blocks.

[0086] For example, in the first row and first column pixel block, at least one of the sub-pixels R, G, and B may include a red sub-pixel 112R representing red (R), a green sub-pixel 112G representing green (G), and a blue sub-pixel 112B representing blue (B).

[0087] Thus, the N+1 scan line GIP N+1 can be arranged along the first row and first column pixel blocks and the first row and second column pixel blocks, and the N scan line GIP N can be arranged along the second row and first column pixel blocks and the second row and second column pixel blocks.

[0088] That is, one scan line can be set in two pixel blocks, and different scan lines can be set in two pixel blocks of different pairs.

[0089] exist Figure 3 In the embodiment, the Nth scan line GIP N can be arranged in the first row and third column pixel blocks and the first row and fourth column pixel blocks, and the N+1th scan line GIP N+1 can be arranged in the second row and third column pixel blocks and the second row and fourth column pixel blocks.

[0090] As described above, in the display panel according to the embodiment of the present disclosure, one scan line is arranged in each row, so that different scan lines can be arranged in two pixel blocks of different pairs, respectively.

[0091] refer to Figure 4 , a display panel according to an embodiment of the present disclosure may include a plurality of pixel blocks and a plurality of AAGIP units, wherein a scan line may be arranged in one pixel block.

[0092] like Figure 4 As shown, for example, the plurality of pixel blocks may include a first column and a first row pixel block, a first column and a second row pixel block, a second column and a first row pixel block, a second column and a second row pixel block, a third column and a first row pixel block, a third column and a second row pixel block, a fourth column and a first row pixel block, and a fourth column and a second row pixel block.

[0093] The multiple AAGIP units may include a first AAGIP unit 210 set for the first column and first row pixel blocks and the first column and second row pixel blocks, a second AAGIP unit 220 set for the second column and first row pixel blocks and the second column and second row pixel blocks, and a third AAGIP unit 230 set for the third column and first row pixel blocks and the third column and second row pixel blocks.

[0094] One pixel block may include at least one of the sub-pixels R, G, and B.

[0095] The N scan line GIP N may be disposed in the first column and the first row of the pixel block, and the N+1 scan line GIP N+1 may be disposed in the first column and the second row of the pixel block.

[0096] The N+1 scan line GIP N+1 may be disposed in the second column and first row of the pixel block, and the N scan line GIP N may be disposed in the second column and second row.

[0097] The N scan line GIP N may be disposed in the third column and first row of the pixel block, and the N+1 scan line GIP N+1 may be disposed in the third column and second row of the pixel block.

[0098] The N+1 scan line GIP N+1 may be disposed in the fourth column and first row pixel block, and the N scan line GIP N may be disposed in the fourth column and second row pixel block.

[0099] The first GIP unit 210 can electrically connect the N scan line GIP N of the first column and the first row pixel block and the N scan line GIP N of the second column and the second row pixel block to each other, and can electrically connect the N+1 scan line GIP N+1 of the first column and the second row pixel block and the N+1 scan line GIP N+1 of the second column and the first row pixel block to each other. Hereinafter, the first column and the first row pixel block to the fourth column and the second row pixel block may be referred to as the first column and the first row to the fourth column and the second row.

[0100] The second AAGIP unit 220 can electrically connect the N+1 scan line GIP N+1 of the first row and second column pixel block and the N+1 scan line GIP N+1 of the second row and third column pixel block to each other, and can electrically connect the N scan line GIP N of the second row and second column and the N scan line GIP N of the first row and third column pixel block to each other.

[0101] The third AAGIP unit 230 can electrically connect the N scan line GIP N of the first row and third column pixel block and the N scan line GIP N of the second row and fourth column pixel block to each other, and can electrically connect the N+1 scan line GIP N+1 of the second row and third column pixel block and the N+1 scan line GIP N+1 of the first row and fourth column pixel block to each other.

[0102] As described above, in the display panel according to the embodiment of the present disclosure, different scan lines are respectively arranged in the two pixel blocks of each row. The AAGIP unit connects the scan lines of the upper pixel block on one side of the AAGIP unit and the scan lines of the lower pixel block on the other side of the AAGIP unit to each other, and connects the scan lines of the lower pixel block on one side of the AAGIP unit and the scan lines of the upper pixel block on the other side of the AAGIP unit to each other.

[0103] Figure 5 is a view showing an example of applying different AAGIP control signals having different timings to different blocks in a display panel according to an embodiment of the present disclosure.

[0104] refer to Figure 5 , the AAGIP unit according to an embodiment of the present disclosure may include a scanning AAGIP unit AAGIP SCAN and a light emitting AAGIP unit AAGIP EM.

[0105] In the display area, the scanning AAGIP units AAGIP SCAN (①, ②, ③) are disposed to be spaced apart from each other at predetermined intervals, and the emitting AAGIP units AAGIP EM (①, ②, ③) are disposed to be spaced apart from each other at predetermined intervals.

[0106] For example, when three pixels constitute a unit pixel, one scanning AAGIP unit AAGIP SCAN and one emitting AAGIP unit AAGIP EM may be provided for each pixel.

[0107] In this case, three scanning AAGIP units AAGIP SCAN (①, ②, ③) may be provided for three pixels, respectively. Three emitting AAGIP units AAGIP EM (①, ②, ③) may be provided for three pixels, respectively. The present disclosure is not limited to this arrangement.

[0108] like Figure 5 As shown, in the display area of ​​the display panel according to an embodiment of the present disclosure, a plurality of groups of scanning AAGIP units AAGIP SCAN and a plurality of groups of emitting AAGIP units AAGIP EM may be alternately arranged with each other.

[0109] The AAGIP unit according to an embodiment of the present disclosure may apply the AAGIP control signal ControlSignal having different timings to one side pixel block and the other side pixel block, respectively.

[0110] When the N scan signal is a high level pulse signal, the N+1 scan signal may be a low level pulse signal. When the N scan signal is a low level pulse signal, the N+1 scan signal may be a high level pulse signal.

[0111] exist Figure 5 In the embodiment, the first scanning AAGIP unit Scan1 N (①, ②, ③) can apply the low-level first scanning control signal Scan Control Signal 1 to the N scanning line N Line. Thus, the scanning TFT of each pixel can be turned on based on the low-level scanning control signal and can be turned off based on the high-level scanning control signal.

[0112] In addition, the first scan AAGIP unit (①, ②, ③) can apply the first scan control signal ScanControlSignal 1 of a high level to the N+1 scan line N+1Line.

[0113] Therefore, the scanning TFT of the pixel connected to the N scanning line N Line may be turned on, and the scanning TFT of the pixel connected to the N+1 scanning line N+1 Line may be turned off.

[0114] exist Figure 5In the embodiment, the second scanning AAGIP unit Scan2 N (①, ②, ③) can apply the low-level second scanning control signal Scan Control Signal 2 to the N+1 scanning line N+1Line, and can apply the high-level second scanning control signal Scan Control Signal 2 to the N scanning line NLine.

[0115] Therefore, the scanning TFT of the pixel connected to the N+1 scanning line N+1Line may be turned on, and the scanning TFT of the pixel connected to the N scanning line NLine may be turned off.

[0116] Figure 6 is a view showing an example in which, when data voltage fluctuation occurs in a display panel, ripples are reduced as scan lines are switched by an AAGIP unit according to an embodiment of the present disclosure.

[0117] refer to Figure 6 In the display panel according to the embodiment of the present disclosure, a first AAGIP unit 210 can be set for the first pixel block 110 in the first column and the first row and the second pixel block 120 in the first column and the second row, and a second AAGIP unit 220 can be set for the first pixel block 110 in the first row and the second column and the second pixel block 120 in the second row and the second column.

[0118] The N+1 scan line GIP N+1 may be disposed in the first pixel block 110 of the first row and the first column, and the N scan line GIP N may be disposed in the second pixel block 120 of the second row and the first column.

[0119] The N scan line GIP N may be disposed in the first pixel block 110 of the first row and second column, and the N+1 scan line GIP N+1 may be disposed in the second pixel block 120 of the second row and second column.

[0120] When a data voltage transition occurs in the display area, a GIP N ripple signal GIP N Ripple may occur in the N scan line GIP N, and a GIP N+1 ripple signal GIP N+1 Ripple may occur in the N+1 scan line GIP N+1.

[0121] However, in the display panel according to the embodiment of the present disclosure, the scan lines are switched in the first AAGIP unit 210 and the second AAGIP unit 220 during the period of generating the ripple signal according to the data voltage transition. Therefore, for example, the ripple signal N line ripple associated with the N scan lines is significantly reduced.

[0122] Figure 7 is a view showing an example in which the AAGIP unit actually connects scan lines of adjacent pixel blocks to each other according to an embodiment of the present disclosure.

[0123] refer to Figure 7 , the display panel according to an embodiment of the present disclosure may include a plurality of pixel blocks and a plurality of AAGIP units 210 , 212 , and 220 .

[0124] Multiple AAGIP units 210, 212 and 220 can be set so that a first-first AAGIP unit 212 is set for the first column and first row pixel blocks and the first column and second row pixel blocks, a first AAGIP unit 210 is set for the second column and first row pixel blocks, the third column and first row pixel blocks, the second column and second row pixel blocks, and a second-first AAGIP unit 222 is set for the fourth column and first row pixel blocks and the fourth column and second row pixel blocks.

[0125] Thus, the N+1 scanning line SL N+1 The N scanning line SL is set in the first column and first row pixel block, the second column and first row pixel block, and the third column and first row pixel block, which are the pixel blocks on the left side of the first AAGIP unit 210. N The pixel blocks may be disposed in the first column and second row pixel blocks, the second column and second row pixel blocks, and the third column and second row pixel blocks which are pixel blocks on the left side of the first AAGIP unit 210 .

[0126] In addition, N scanning lines SL N The N+1 scan line SL may be disposed in the fourth column first row pixel block, the fifth column first row pixel block, and the sixth column first row pixel block, which are pixel blocks on the right side of the first AAGIP unit 210. N+1 The pixel blocks may be disposed in the fourth column and the first row, the fifth column and the second row, and the sixth column and the second row, which are pixel blocks on the right side of the first AAGIP unit 210 .

[0127] Therefore, the first AAGIP unit 210 can connect the N+1 scan line SL in the first row of the left pixel block through the source / drain connection line S / D. N+1 and the N+1 scan line SL in the second row of the right pixel block N+1 Connect with each other.

[0128] In addition, the first AAGIP unit 210 can enable the N scan lines SL in the second row of the left pixel block to be N and N scan lines SL in the first row of the right pixel block N Connect with each other.

[0129] For example, when manufacturing the TFT of the pixel, a BSM connection line may be formed on the base substrate in the first AAGIP unit 210 using a mask so that the N scan lines SL of the two pixel blocks NThe two are connected to each other through the bottom shield metal BSM.

[0130] In addition, when the source and drain are manufactured, a mask may be used to form an SD connection line in the first AAGIP unit 210 so that the N+1 scan line SL of the two pixel blocks N+1 The electrodes are connected to each other through source / drain connection lines S / D.

[0131] Thus, the source / drain connection line S / D may not use a mask, and the two opposite ends of the source / drain connection line S / D and the N+1 scanning line SL of the two pixel blocks are connected. N+1 The two opposite ends of the electrode may be connected to each other through contact holes, respectively.

[0132] Figure 8 is a view showing a width of an AAGIP unit when one sub-pixel in a display panel has an 8T1C structure according to an embodiment of the present disclosure.

[0133] refer to Figure 8 , in the display panel according to the embodiment of the present disclosure, the AAGIP unit may be set based on a predetermined number of pixel blocks, and one pixel block may include at least one sub-pixel.

[0134] Thus, when one sub-pixel has an 8T1C structure, the AAGIP unit may have a width of, for example, 27 μm in the row direction in which the scan line extends.

[0135] That is, the AAGIP unit includes the scanning AAGIP unit AAGIP SCAN and the emitting AAGIP unit AAGIP EM. Each of the scanning AAGIP unit AAGIP SCAN and the emitting AAGIP unit AAGIP EM may have a width of 27 μm.

[0136] Fig. 9 2 is a view showing an example of respectively applying scan signals to 2 scan lines in a display panel according to an embodiment of the present disclosure.

[0137] refer to Fig. 9 According to the display panel of an embodiment of the present disclosure, the AAGIP unit can apply a low-level first scan N signal SCAN(n)1 to the first scan line Scan 1 on the left side of the AAGIP unit, and can apply a low-level second scan N signal SCAN(n)2 with the next timing to the second scan line Scan 2 on the right side of the AAGIP unit.

[0138] In addition, the AAGIP unit can apply the first scan N+1 signal SCAN(n+1)1 to the first scan line Scan 1 on the left side of the AAGIP unit, and can apply the second scan N+1 signal SCAN(n+1)2 with a low level of the next timing to the second scan line Scan 2 on the right side of the AAGIP unit.

[0139] As described above, the display panel according to an embodiment of the present disclosure may apply different scan signals to the same scan line (eg, the same first scan line Scan 1 or the same second scan line Scan 2 ) of adjacent pixel blocks in a zigzag manner.

[0140] Therefore, the AAGIP scan signal applied to each pixel block can be varied so that the influence of data voltage fluctuation (data line transition) can be minimized.

[0141] Fig.10 and Fig.11 is a view illustrating an example of securing a bezel area by an AAGIP unit in a display panel according to an embodiment of the present disclosure.

[0142] refer to Fig.10 and Fig.11 In the display panel according to the embodiment of the present disclosure, one or more AAGIP units are provided in the display area AA, so that the gate driving circuit existing in the non-display area NA in the prior art can be removed. Therefore, the frame area of ​​the non-display area on each of the two opposite sides of the display panel can be wider.

[0143] In the display area AA, an AAGIP unit may be provided for pixels arranged in two rows and one column. Thus, one pixel may include at least one of the sub-pixels R, G, and B.

[0144] Thus, the AAGIP unit may include scanning AAGIP units AAGIP SCAN respectively provided for three columns of pixels, and emitting AAGIP units AAGIP EM respectively provided for the next three columns of pixels.

[0145] For example, one sub-pixel region Sub-PXL may include a first red (R) sub-pixel 112R, a first green (G) sub-pixel 112G, a first blue (B) sub-pixel 112B, and the like.

[0146] Therefore, in the display panel, the first-first AAGIP unit 212 can be set in a manner to be located after the first red (R) sub-pixel 112R, the first green (G) sub-pixel 112G and the first blue (B) sub-pixel 112B, and the first AAGIP unit 210 can be set in a manner to be located after the second red (R) sub-pixel 114R, the second green (G) sub-pixel 114G and the second blue (B) sub-pixel 114B.

[0147] In this way, the AAGIP elements constituting the stage of the gate driving circuit can be dispersedly arranged in the display area AA, so that the widths of the left and right frame areas of the display panel can be ensured.

[0148] Therefore, the display panel according to the embodiment of the present disclosure can further ensure the widths of the left and right frame areas respectively located on the left and right sides of the display area AA.

[0149] Fig.12 is a configuration diagram showing an example of providing an AAGIP unit for each data driver according to an embodiment of the present disclosure.

[0150] refer to Fig.12 , when the AAGIP unit according to an embodiment of the present disclosure is applied to a display device, the AAGIP unit according to an embodiment of the present disclosure may be configured such that a single data driver D-IC region may correspond to three scanning blocks S1, S2, and S3.

[0151] In the display panel according to an embodiment of the present disclosure, a signal line (Line on Glass) LOG may be formed in the non-display area NA. Various control signals VSS, VDD, CLK, VST, and RESET from a timing controller T-conl (not shown) may be applied to the AAGIP unit through a COF (Chip on Film) of a data driver D-IC and the signal line LOG.

[0152] Thus, the signal lines LOG may include a left signal line LEFT LOG and a right signal line RIGHT LOG surrounding the center of the display panel.

[0153] In the display panel, a horizontal scan line H-LINE may be set, and one scan AAGIP block SCAN AAGIP 1Block may be set for a single data driver D-IC region.

[0154] Alternatively, in the display panel, 20 scanning AAGIP blocks may correspond to a single data driver D-IC region. Thus, each scanning AAGIP block may include three scanning blocks S1, S2, and S3.

[0155] In one example, an embodiment of the present disclosure may implement a display device including the display panel 100 configured as described above.

[0156] The display device according to an embodiment of the present disclosure may include the display panel 100 as described above, and a brightness controller, a data driver, a light emission controller, a power supply, and a timing controller which are not shown in the drawings.

[0157] The brightness controller may provide one gamma set selected from among a plurality of gamma sets each including a plurality of gamma data to the data driver, and provide dimming data corresponding to the selected gamma set to the light emitting controller.

[0158] The display panel 100 may include a display area AA and a non-display area NA.

[0159] In the display area AA, a plurality of scan lines SL respectively arranged in a plurality of rows and a plurality of data lines DL respectively arranged in a plurality of columns may intersect with each other, and each pixel may be arranged at each intersection therebetween. Each pixel may include at least one of sub-pixels R, G, B, etc. Therefore, at least one sub-pixel may be arranged at each intersection.

[0160] For example, the display panel 100 may include an organic substrate or a plastic substrate, a plurality of scan lines SL and a plurality of data lines DL, and red, green, and blue sub-pixels R, G, and B located at intersections between the scan lines SL and the data lines DL on the organic substrate or the plastic substrate. One pixel including one or more sub-pixels R, G, B, W, etc. may be referred to as a "unit pixel".

[0161] Thus, each sub-pixel may include an organic light emitting diode OLED. Each of the plurality of scan lines SL may be disposed in each row of the plurality of sub-pixels, and each of the plurality of data lines DL may be disposed in each column of the plurality of sub-pixels. Therefore, the plurality of sub-pixels may include a plurality of light emitting diodes OLED arranged in rows and columns.

[0162] The scan lines SL and the data lines DL of the display panel 100 may be respectively connected to an AAGIP unit disposed in the display area AA and a data driver formed outside the display panel 100. In addition, voltage supply lines VDD, Vini, and VSS extending in a direction parallel to the data lines DL may be further formed in the display panel 100 and may be connected to each pixel.

[0163] In addition, each pixel may include at least one organic light emitting diode OLED, a storage capacitor Cst, switching thin film transistors T1 to T9, and a driving thin film transistor DT. Thus, the organic light emitting diode OLED may include a first electrode (hole injection electrode), an organic compound layer, and a second electrode (electron injection electrode).

[0164] The organic compound layer may include a light-emitting layer that actually emits light, and may further include various organic layers for effectively transporting carriers including holes or electrons to the light-emitting layer. These organic layers may include a hole injection layer and a hole transport layer between the first electrode and the light-emitting layer, and an electron injection layer and an electron transport layer between the second electrode and the light-emitting layer.

[0165] In addition, the switching thin film transistors T1 to T9 and the driving thin film transistor TD may be connected to the scan line SL and the control signal supply line EL and the data line DL. The switching thin film transistors T1 to T9 may be turned on based on the gate voltage input to the scan line SL, and thus may transmit the data voltage input to the data line DL to the driving thin film transistor TD. The storage capacitor Cst may be connected to and disposed between the thin film transistor and the power line, may be charged with the data voltage transmitted from the thin film transistor, and its charged state may be maintained for 1 frame.

[0166] In addition, the driving thin film transistor TD can be connected to the power line and the storage capacitor Cst, and can supply a drain current corresponding to the voltage difference between its gate voltage and source voltage to the organic electroluminescent diode OLED. Therefore, the organic electroluminescent diode OLED emits light based on the drain current. Thus, the driving thin film transistor TD includes a gate, a source, and a drain, and the anode of the organic electroluminescent diode OLED can be connected to one electrode of the driving thin film transistor TD.

[0167] The AAGIP unit may apply scan signals to a plurality of scan lines SL. For example, the AAGIP unit may sequentially apply gate voltages to pixels based on one horizontal line in response to a gate control signal GCS. The AAGIP unit may be implemented as a shift register having a plurality of stages that sequentially output high-level gate voltages every 1 horizontal (1H) period.

[0168] The data driver may apply data signals to a plurality of data lines DL. For example, the data driver receives an image signal of a digital waveform applied from a timing controller, converts the image signal into a data voltage having a grayscale value that each sub-pixel can process as an analog voltage, and then supplies the data voltage to each sub-pixel through the data line DL in response to an input data control signal DCS. Thus, the data driver may convert the image signal into a data voltage based on a plurality of reference voltages supplied by a reference voltage supplier (not shown).

[0169] In addition, when the data driver receives the selected one gamma set from the brightness controller, the data driver may provide the display panel 100 with the low potential voltage VSS and the initialization voltage Vini corresponding to the selected one gamma set based on the lookup table.

[0170] The light emission controller may apply a light emission control signal EM to a plurality of pixels.

[0171] The power supply may provide a high potential voltage VDD, a low potential voltage VSS, a reference voltage Vref, and an initialization voltage Vini to each pixel.

[0172] The timing controller may control the AAGIP unit and the data driver. For example, the timing controller receives an image signal, a clock signal, and timing signals such as vertical and horizontal synchronization signals from an external system, generates a gate control signal GCS and a data control signal DCS based on the received signals, and provides the gate control signal GCS and the data control signal DCS to the AAGIP unit and the data driver, respectively.

[0173] Thus, the horizontal synchronization signal indicates the time required to display one line of the screen, and the vertical synchronization signal indicates the time required to display one frame of an image. In addition, the clock signal refers to a signal used to generate a control signal for a gate and each driver.

[0174] In one example, the timing controller can be connected to an external system through a predetermined interface, and can receive image-related signals and timing signals output from the external system at high speed without noise. The interface may include an LVDS (Low Voltage Differential Signal) scheme interface or a TTL (Transistor-Transistor Logic) scheme interface.

[0175] In addition, the timing controller according to an embodiment of the present disclosure may have an embedded microchip (not shown) therein, the embedded microchip containing a compensation model, the compensation model generating a compensation value of the data voltage based on the current deviation of each pixel. Therefore, the timing controller can apply the voltage compensation value to the image signal to be supplied to the data driver. Therefore, the voltage compensation value has been reflected in the data voltage supplied from the data driver.

[0176] The present disclosure may be applied to an organic light-emitting display device operating in a bottom emission scheme. However, the present disclosure is not limited thereto. If necessary, the present disclosure may be applied to an organic light-emitting display device operating in a top emission scheme or a double-sided emission scheme.

[0177] Fig.13 is a view showing a circuit configuration of one sub-pixel PX provided in a display area of ​​a display panel according to an embodiment of the present disclosure.

[0178] refer to Fig.13 , one sub-pixel PX according to an embodiment of the present disclosure may include a light emitting element OLED, a driving element DT, a storage capacitor Cst, and a compensation circuit.

[0179] The light emitting element OLED may be implemented as, for example, an organic light emitting diode OLED, and may include an anode as a first electrode and a cathode as a second electrode.

[0180] The driving element DT may be implemented as, for example, a driving thin film transistor DT, and may be electrically connected to the light emitting element, and may control a current flowing through the light emitting element.

[0181] One electrode of the storage capacitor Cst may be electrically connected to the driving element DT.

[0182] The compensation circuit may compensate for the variation of the threshold voltage of the driving element DT. To this end, the compensation circuit may include first to fourth switching elements T1 to T4 and fifth to ninth switching elements T5 to T9.

[0183] Each of the first switching element T1 to the ninth switching element T9 and the driving element DT can be implemented as a TFT having an N-type or P-type MOSFET (metal oxide semiconductor field effect transistor) structure. An example in which each of the first switching element T1 to the ninth switching element T9 and the driving element DT is implemented as a TFT having a P-type MOSFET (metal oxide semiconductor field effect transistor) structure is described in the following embodiments. However, the present disclosure is not limited thereto. A TFT is a three-electrode element including a gate, a source, and a drain. The source supplies carriers to the TFT. In a transistor, carriers can flow out from the source. The drain refers to the electrode through which carriers leave the TFT. That is, in a MOSFET, carriers flow from the source to the drain. In an N-type MOSFET (NMOS), carriers are electrons, so the voltage of the source is lower than the voltage of the drain, so that electrons can flow from the source to the drain. In an N-type MOSFET, electrons flow from the source to the drain, so that current flows from the drain to the source. In a P-type MOSFET (PMOS), the carriers are holes, so the voltage of the source is higher than the voltage of the drain, so that holes can flow from the source to the drain. In a P-type MOSFET, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET can be swapped based on the voltage applied thereto. Although in the following embodiments, each transistor constituting the AAGIP unit and the pixel circuit is implemented as a P-type TFT, the present disclosure is not limited thereto. Therefore, the present disclosure should not be limited by the source and drain of the TFT in the following description.

[0184] The compensation circuit may be configured such that the first switching element T1 may be connected to the gate and the second electrode of the driving element DT and disposed therebetween, and the data voltage Vdata may be applied to the first electrode of the driving element DT through the second switching element T2. The compensation circuit may be configured such that the driving voltage VDD may be applied to the driving element DT through the third switching element T3, and the driving voltage VDD may be applied to the storage capacitor Cst through the seventh switching element T7. The compensation circuit may be configured such that the reference voltage Vref may be applied to the storage capacitor Cst through the eighth switching element T8 and the ninth switching element T9, and the initialization voltage Vini may be applied to the light emitting element OLED through the sixth switching element T6.

[0185] Thus, each of the first to ninth switching elements T1 to T9 and the driving element DT may be implemented as a thin film transistor.

[0186] The first switch element T1 may be configured such that one of its first electrode and second electrode is connected to the gate (N2) of the driving element DT, the other is connected to the second electrode (N3) of the driving element DT, and its gate is connected to the n scan line Scan n. Thus, the first electrode may be a source electrode, and the second electrode may be a drain electrode. However, the present disclosure is not limited thereto. The first electrode may be a drain electrode, and the second electrode may be a source electrode.

[0187] The second switching element T2 may be configured such that one of the first electrode and the second electrode is connected to the data voltage Vdata(N1'), the other is connected to the first electrode (N1) of the driving element DT, and its gate is connected to the n scan line Scann. Thus, the first electrode may be a source electrode, and the second electrode may be a drain electrode. However, the present disclosure is not limited thereto. The first electrode may be a drain electrode, and the second electrode may be a source electrode.

[0188] The third switch element T3 may be configured such that one of the first electrode and the second electrode is connected to the first electrode (N1) of the driving element DT, the other is connected to the driving voltage line VDD (N7), and its gate is connected to the nth light emitting control line EM (n). Thus, the first electrode may be a source electrode, and the second electrode may be a drain electrode. However, the present disclosure is not limited thereto. The first electrode may be a drain electrode, and the second electrode may be a source electrode.

[0189] The fourth switch element T4 may be configured such that one of the first electrode and the second electrode is connected to the first electrode (N4) of the light emitting element OLED, the other is connected to the second electrode (N3) of the driving element DT, and its gate is connected to the nth light emitting control line EM (n). Thus, the first electrode may be a source electrode, and the second electrode may be a drain electrode. However, the present disclosure is not limited thereto. The first electrode may be a drain electrode, and the second electrode may be a source electrode.

[0190] The sixth switch element T6 may be configured such that one of the first electrode and the second electrode is connected to the initialization voltage line Vini (N6'), the other is connected to the first electrode (N4) of the light emitting element OLED, and its gate is connected to the n scan line Scan n. Thus, the first electrode may be a source electrode, and the second electrode may be a drain electrode. However, the present disclosure is not limited thereto. The first electrode may be a drain electrode, and the second electrode may be a source electrode.

[0191] The fifth switching element T5 may be configured such that one of the first electrode and the second electrode is connected to the connection point (N5) between the driving element DT and the storage capacitor Cst, the other is connected to the connection point (N6) between the sixth switching element T6 and the initialization voltage line Vini, and its gate is connected to the n-1th scan line Scan n-1. Thus, the first electrode may be a source electrode, and the second electrode may be a drain electrode. However, the present disclosure is not limited thereto. The first electrode may be a drain electrode, and the second electrode may be a source electrode.

[0192] The seventh switching element T7 may be configured such that one of the first electrode and the second electrode is connected to the driving voltage line VDD (N7), the other is connected to the first electrode (STR) of the storage capacitor Cst, and its gate is connected to the nth light emitting control line EM (n). Thus, the first electrode may be a source electrode, and the second electrode may be a drain electrode. However, the present disclosure is not limited thereto. The first electrode may be a drain electrode, and the second electrode may be a source electrode.

[0193] The eighth switching element T8 may be configured such that one of the first electrode and the second electrode is connected to the reference voltage line Vref (N8'), the other is connected to the first electrode (N8) of the storage capacitor Cst, and its gate is connected to the n-1th scan line Scan n-1. Thus, the first electrode may be a source electrode, and the second electrode may be a drain electrode. However, the present disclosure is not limited thereto. The first electrode may be a drain electrode, and the second electrode may be a source electrode.

[0194] The ninth switching element T9 may be configured such that one of the first electrode and the second electrode is connected to the reference voltage line Vref (N9), the other is connected to the first electrode (N8) of the storage capacitor Cst, and its gate is connected to the nth scan line Scan n. Thus, the first electrode may be a source electrode, and the second electrode may be a drain electrode. However, the present disclosure is not limited thereto. The first electrode may be a drain electrode, and the second electrode may be a source electrode.

[0195] In one example, the compensation circuit can be configured such that for the first switching element T1 to the fourth switching element T4, the first switching element T1 can be connected to the gate and the second electrode of the driving element and arranged therebetween, the second switching element T2 can be connected to the first electrode of the driving element and the data voltage line Vdata and arranged therebetween, the third switching element T3 can be connected to the first electrode of the driving element and the driving voltage line VDD and arranged therebetween, and the fourth switching element T4 can be connected to the first electrode of the light emitting element and the second electrode of the driving element and arranged therebetween.

[0196] In addition, the compensation circuit can be configured so that for the sixth switching element T6 to the eighth switching element T8, the sixth switching element T6 can be connected to the first electrode of the light emitting element and the initialization voltage line Vini and arranged therebetween, the seventh switching element T7 can be connected to the storage capacitor Cst and the driving voltage line VDD and arranged therebetween, and the eighth switching element T8 and the ninth switching element T9 can be connected to the storage capacitor Cst and the reference voltage line Vref and arranged therebetween.

[0197] The first switching element T1 , the second switching element T2 , the sixth switching element T6 , and the ninth switching element T9 may be switched based on the n th scan signal Scan n.

[0198] The third switching element T3 , the fourth switching element T4 , and the seventh switching element T7 may be switched based on the nth light emitting control signal EM(n).

[0199] The fifth switching element T5 and the eighth switching element T8 may be switched based on the n-1th scan signal Scan n-1.

[0200] The operation period of the display panel 100 according to the embodiment of the present disclosure may be divided into an initialization period Initial, a sampling period Sampling, and a light emitting period Emission.

[0201] Therefore, the sampling period Sampling can be called the sensing and initialization period Sensing & Initial, and in some cases, it can be called a "programming period".

[0202] In addition, the operation period of the display panel 100 may include a holding period between the sampling period Sampling and the light emitting period Emission.

[0203] The initialization period Initial may be set to be equal to or less than 1 horizontal period (1H).

[0204] The (n-1)th scan signal Scan n-1 may be a high signal for an initialization period, may be a low signal for a sampling period of 1H, and may be a high signal for a light emitting period.

[0205] The nth scan signal Scan n may be a low signal for an initialization period, may be a low signal for a sampling period of 2H, and may be a high signal for a light emitting period.

[0206] The n-1th light emitting control signal EM(n-1) may be a high signal for the initialization period and the sampling period, and may be a high signal for the light emitting period and the remaining periods.

[0207] The nth light emitting control signal EM(n) may be a high signal for a portion of each of the sampling period and the light emitting period, and may be a low signal for the rest thereof.

[0208] The data voltage signal Vdata applied to the source electrode of the driving element DT may be a low signal for a sampling period of 1H, and may be a high signal for the remaining periods.

[0209] The data voltage signal applied to the gate of the driving element DT may be a low signal for the initialization period 1H, and may increase from the low signal to a Vdata-Vth signal in the sampling period, and may be a high signal for the light emitting period.

[0210] The reference voltage signal Vref applied to the contact node STR of the storage capacitor Cst may be a low signal for the initialization period and the sampling period, and may be a high signal for the light emitting period.

[0211] For the light emission period Emission, the potential of the gate of the driving element DT may be set to (VDD-Vref)+(Vdata+Vref).

[0212] Therefore, a voltage difference Vgs between the gate voltage and the source voltage of the driving element DT capable of compensating for variations in the threshold voltage Vth of the driving element DT can be set. A driving current Ioled corresponding to the gate-source voltage Vgs shown in the following formula 1 can flow through the driving element DT.

[0213] Due to the driving current Ioled, the potential of each of the nodes N3 and N4 can rise to the operating point voltage Voled of the light emitting diode OLED, so the light emitting diode OLED can be turned on. Therefore, the light emitting diode OLED can emit light based on the driving current Ioled.

[0214] Formula 1

[0215] Ioled=K(Vgs-|Vth|

[0216] =K(EVDD-{EVDD-|Vth|-·Vdata+Vref}-|Vth|)

[0217] =K(Vdata-Vref)

[0218] Here, K represents a constant value determined based on the mobility, channel ratio, parasitic capacitance, etc. of the driving element DT, and Vth represents the threshold voltage of the driving element DT.

[0219] It can be seen from Formula 1 that the driving current Ioled of the light emitting diode OLED is not affected by the high potential voltage VDD as the driving voltage and the threshold voltage Vth of the driving element DT.

[0220] According to the present disclosure, when scan signals for pixel initialization and threshold voltage sensing operations are supplied to adjacent display lines so that the scan signals applied to the adjacent display lines overlap with each other within a predetermined period, the AAGIP unit for generating scan signals that overlap with each other can have a small number of clocks and a simple circuit configuration.

[0221] Fig.14 It is shown that Fig.13 A view showing an example of the arrangement of transistors and wirings of a sub-pixel circuit configuration.

[0222] refer to Fig.14 It can be seen that, in the sub-pixel PX according to an embodiment of the present disclosure, each of one electrode of the third switching element T3 and one electrode of the seventh switching element T7 is connected to the driving voltage line VDD through a contact hole.

[0223] Furthermore, it can be seen that in the subpixel PX according to an embodiment of the present disclosure, each of one electrode of the third switching element T3 , one electrode of the fourth switching element T4 , and one electrode of the seventh switching element T7 is connected to the emission line EM through a contact hole.

[0224] Furthermore, it can be seen that in the subpixel PX according to the embodiment of the present disclosure, each of one electrode of the fifth switching element T5 and one electrode of the eighth switching element T8 is connected to the first scan line Scan 1 through a contact hole.

[0225] Furthermore, it can be seen that in the subpixel PX according to the embodiment of the present disclosure, each of one electrode of the second switching element T2 , one electrode of the sixth switching element T6 , and one electrode of the ninth switching element T9 is connected to the second scan line Scan 2 through a contact hole.

[0226] Furthermore, it can be seen that in the sub-pixel PX according to an embodiment of the present disclosure, each of one electrode of the fifth switching element T5 and one electrode of the sixth switching element T6 is connected to the initialization voltage line Vini through a contact hole.

[0227] Furthermore, it can be seen that in the subpixel PX according to the embodiment of the present disclosure, each of one electrode of the eighth switching element T8 and one electrode of the ninth switching element T9 is connected to the reference voltage line Vref through a contact hole.

[0228] Furthermore, it can be seen that in the subpixel PX according to an embodiment of the present disclosure, the driving transistor DT is connected to the storage capacitor Cst and the first, second, fourth, and fifth switching elements T1, T2, T4, and T5.

[0229] As described above, according to the present disclosure, an AAGIP scheme display panel can be implemented in which an AAGIP unit is disposed in a display area of ​​an OLED display device, so that defects such as crosstalk or smear caused by transition or fluctuation of data signals of data lines can be reduced.

[0230] Furthermore, according to the present disclosure, an OLED display device in which individual operations of horizontal scan lines for each pixel block in a display area can minimize the influence of the same data signal (eg, a crosstalk pattern) can be implemented.

[0231] The scope of protection of the present disclosure shall be interpreted by the scope of the claims, and all technical concepts within the scope of the equivalents of the claims shall be interpreted as being included within the scope of the present disclosure. Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these embodiments. The present disclosure can be implemented in various modified ways without departing from the scope of the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical concept of the present disclosure, but are used to describe the present disclosure. The scope of the technical concept of the present disclosure is not limited by the embodiments. Therefore, it should be understood that the embodiments described above are illustrative and non-restrictive in all aspects. The scope of protection of the present disclosure shall be interpreted by the claims, and all technical concepts within the scope of the present disclosure shall be interpreted as being included within the scope of the present disclosure.

Claims

1. A display panel, comprising: a plurality of pixel blocks, each of the plurality of pixel blocks comprising a plurality of sub-pixels arranged in a row, the plurality of pixel blocks; as well as A plurality of intra-panel active area gate units, i.e., a plurality of AAGIP units, are arranged in rows, each of the plurality of AAGIP units being disposed between adjacent pixel blocks among the plurality of pixel blocks, Among the plurality of AAGIP units, an AAGIP unit in the nth row is arranged between the plurality of pixel blocks in the nth row, Among the plurality of AAGIP units, an AAGIP unit in the n+1th row is arranged between the plurality of pixel blocks in the nth row, wherein the one AAGIP unit in the nth row is configured to apply an N scanning signal to one pixel block in the plurality of pixel blocks in the nth row, The one AAGIP unit in the n+1th row is configured to apply an N+1 scan signal to another pixel block among the plurality of pixel blocks in the nth row.

2. The display panel according to claim 1, wherein: An nth scan line is disposed in sub-pixels of an nth row in a pixel block on one side of the one AAGIP unit in the nth row among the plurality of AAGIP units along the sub-pixels of the nth row in the pixel block.

3. The display panel according to claim 1, wherein: An (n+1)th scan line is disposed in sub-pixels in an n-th row in a pixel block on the other side of the one AAGIP unit in the n-th row among the plurality of AAGIP units along the sub-pixels in the n-th row in the pixel block.

4. The display panel according to claim 2, wherein: The nth scan line is disposed in sub-pixels in an n+1th row in a pixel block on one side of the one AAGIP unit in the n+1th row among the plurality of AAGIP units along sub-pixels in the n+1th row in the pixel block.

5. The display panel according to claim 3, wherein: The n+1th scan line is arranged in sub-pixels in the n+1th row in a pixel block on the other side of the one AAGIP unit in the n+1th row among the plurality of AAGIP units along sub-pixels in the n+1th row in the pixel block.

6. The display panel according to claim 2, wherein: The nth scan line in the nth row is connected to the n+1th scan line in the n+1th row in the one AAGIP cell in the nth row among the plurality of AAGIP cells.

7. The display panel according to claim 3, wherein: The n+1th scan line in the n+1th row is connected to the nth scan line in the nth row in the one AAGIP cell in the n+1th row among the plurality of AAGIP cells.

8. The display panel according to claim 1, wherein: The AAGIP unit in the nth row among the multiple AAGIP units applies different timing scanning signals to the pixel blocks on one side of the AAGIP unit in the nth row among the multiple AAGIP units and the pixel blocks on the other side of the AAGIP unit in the nth row among the multiple AAGIP units in the same row.

9. The display panel according to claim 1, wherein: When the N scanning signal is a high level pulse signal, the N+1 scanning signal is a low level pulse signal.

10. The display panel according to claim 1, wherein: When the N scanning signal is a low level pulse signal, the N+1 scanning signal is a high level pulse signal.

11. The display panel according to claim 1, wherein: Each of the plurality of pixel blocks includes a unit pixel region composed of at least one sub-pixel selected from a red (R) sub-pixel, a green (G) sub-pixel, a blue (B) sub-pixel, and a white (W) sub-pixel.

Images