Display panel and display device

Abstract

The present application belongs to the field of display, and specifically relates to a display panel and a display device, wherein the display panel includes a plurality of columns of data lines and a plurality of sub-pixels arranged in an array, wherein each column of sub-pixels is arranged between two adjacent data lines, and the sub-pixels of odd-numbered rows and even-numbered rows are connected to data lines on different sides of the adjacent data lines, and a double-controlled sub-pixel is arranged in a pixel column at the junction of a display area controlled by a source driver chip of an odd-numbered column and an even-numbered column, wherein the double-controlled sub-pixel is a sub-pixel of an odd-numbered row or an even-numbered row, and the double-controlled sub-pixel is also connected to another data line other than an adjacent data line, and each double-controlled sub-pixel is connected to a corresponding data line through a selection unit. In a polarity symmetric mode, the selection unit switches the polarity of the double-controlled sub-pixel, so that the polarity of the double-controlled sub-pixel is different from the polarity of other sub-pixels in the same column, so that the polarity of the sub-pixel in the pixel column at the junction is alternately positive and negative, so as to avoid the formation of bright and dark lines at the boundary, and improve the display effect of the display panel.

Description

Technical Field

[0001] The present application belongs to the field of display, and specifically relates to a display panel and a display device. Background Art

[0002] A thin film transistor liquid crystal display (TFT-LCD) includes an array substrate, an opposing substrate, and a liquid crystal layer disposed between the array substrate and the opposing substrate. When the liquid crystal display is displayed, the pixel electrode on one side of the array substrate and the common electrode on one side of the opposing substrate form a liquid crystal capacitor (Clc) to drive the liquid crystal molecules to deflect and control the brightness of each sub-pixel to achieve image display. The pixel electrode and the common electrode on one side of the array substrate form a storage capacitor (Cst) to maintain the voltage of the liquid crystal capacitor.

[0003] If a single-direction electric field is applied to the liquid crystal molecules for a long time, the liquid crystal molecules may be polarized, resulting in a decrease in display quality or even damage to the liquid crystal material. By reversing the polarity and alternating the direction of the electric field, the polarization of the liquid crystal molecules can be effectively avoided. Polarity reversal methods include frame reversal, row reversal, column reversal, and dot reversal.

[0004] When the liquid crystal display is displaying, the data line provides pixel voltage to the pixel electrode. The polarity reversal makes the pixel voltage greater than or less than the voltage of the common electrode. The coupling capacitance (Cdc) formed between the data line and the pixel electrode will cause the pixel voltage to shift, resulting in crosstalk, which affects the display effect of the liquid crystal display. Summary of the invention

[0005] The purpose of the present application is to provide a display panel and a display device to improve or eliminate crosstalk and improve the display effect of a liquid crystal display.

[0006] In order to achieve the above-mentioned purpose, the present application provides a display panel, comprising a plurality of columns of data lines and a plurality of sub-pixels arranged in an array, each column of the sub-pixels being arranged between two adjacent data lines, the sub-pixels in odd-numbered rows being connected to the data lines on a first side of the adjacent data lines, and the sub-pixels in even-numbered rows being connected to the data lines on a second side of the adjacent data lines, the data lines being used to connect a plurality of source driver chips, the source driver chips in odd-numbered columns controlling a first display area, and the source driver chips in even-numbered columns controlling a second display area, dual-controlled sub-pixels being arranged in the pixel columns at the junction of the first display area and the second display area, the dual-controlled sub-pixels being the sub-pixels in odd-numbered rows or even-numbered rows, and the dual-controlled sub-pixels being further connected to another data line other than the adjacent data lines, the display panel further comprising a plurality of selection units, each of the dual-controlled sub-pixels being connected to the corresponding data line through the selection unit, the selection unit being capable of controlling the data signal of one of the two data lines to be output to the dual-controlled sub-pixel, so that the polarity of the dual-controlled sub-pixel can be switched.

[0007] Optionally, when the dual-control sub-pixel is the sub-pixel in an odd row, the adjacent data line connected to the dual-control sub-pixel is the N+1th data line, and the other data line connected to the dual-control sub-pixel is the N+1+ath data line;

[0008] When the dual-control sub-pixel is the sub-pixel in an even row, the adjacent data line connected to the dual-control sub-pixel is the Nth data line, and the other data line connected to the dual-control sub-pixel is the N-ath data line, where a is an odd number and N is an integer greater than or equal to 2.

[0009] Optionally, when the dual-controlled sub-pixels are the sub-pixels in odd rows or the sub-pixels in even rows, a is 1.

[0010] Optionally, the display panel further includes a first transistor, a first end of the first transistor is connected to the control ends of the plurality of selection units, a second end of the first transistor is connected to the control power supply, and the control end of the first transistor is used to connect to a driving module.

[0011] Optionally, the display panel also includes a first transistor, a first end of the first transistor is connected to the control end of the plurality of selection units, a second end of the first transistor is connected to the control power supply, and the display panel also includes a comparison unit, two input ends of the comparison unit are connected to the adjacent data lines corresponding to the pixel columns, and an output end of the comparison unit is connected to the control end of the first transistor.

[0012] Optionally, the comparison unit includes a comparator, an XOR gate circuit or an XOR gate circuit. When the comparison unit is the comparator or the XOR gate circuit, the first transistor is a P-type transistor; when the comparison unit is the XOR gate circuit, the first transistor is an N-type transistor.

[0013] Optionally, the selection unit includes a second transistor and a third transistor, the second transistor is a P-type transistor, the third transistor is an N-type transistor, the control end of the second transistor and the control end of the third transistor are the control ends of the selection unit, the two connection ends of the second transistor are connected to the dual-control sub-pixel and one of the adjacent data lines, and the two connection ends of the third transistor are connected to the dual-control sub-pixel and another data line other than the adjacent data line.

[0014] The present application also provides a display device, comprising:

[0015] the display panel;

[0016] A driving module, the driving module includes a plurality of source driving chips, a picture detection module and a polarity partition control module, all the data lines of the display panel are connected to the plurality of source driving chips, the source driving chips in odd columns control the first display area, and the source driving chips in even columns control the second display area, the polarity partition control module is used to control the polarity of the second display area to be the same as or symmetrical with the polarity of the first display area, forming a conventional polarity mode and a polarity symmetry mode, the picture detection module is connected to the display panel and the polarity partition control module, and is used to control the operation of the polarity partition control module according to the detected crosstalk degree of the display picture.

[0017] Optionally, the polarity partition control module includes a resistor and a fourth transistor, the source driver chip of the odd column is connected to the ground end, the source driver chip of the even column is connected to the first end of the fourth transistor, the second end of the fourth transistor is connected to the control power supply, the control end of the fourth transistor is connected to the screen detection module, and the resistor is connected to the ground end and the first end of the fourth transistor.

[0018] Optionally, the display panel further includes a first transistor, a first end of the first transistor is connected to the control ends of the plurality of selection units, a second end of the first transistor is connected to the control power supply, and a control end of the first transistor is connected to the picture detection module.

[0019] The display panel and display device disclosed in this application have the following beneficial effects:

[0020] In the present application, the display panel includes a plurality of columns of data lines and a plurality of sub-pixels arranged in an array, each column of sub-pixels is arranged between two adjacent data lines, the sub-pixels in odd-numbered rows are connected to the data lines on the first side of the adjacent data lines, and the sub-pixels in even-numbered rows are connected to the data lines on the second side of the adjacent data lines, the data lines are used to connect a plurality of source driver chips, and dual-controlled sub-pixels are arranged in the pixel columns at the junction of the display areas controlled by the source driver chips in odd-numbered columns and even-numbered columns, the dual-controlled sub-pixels are sub-pixels in odd-numbered rows or even-numbered rows, and the dual-controlled sub-pixels are also connected to another data line other than the adjacent data lines, and the display panel also includes a plurality of selection units, each dual-controlled sub-pixel is connected to the corresponding data line through the selection unit, and the selection unit can control the data signal of one of the two data lines to be output to the dual-controlled sub-pixel, so that the polarity of the dual-controlled sub-pixel can be switched. In the polarity symmetry mode, the selection unit switches the polarity of the dual-controlled sub-pixel so that the polarity of the dual-controlled sub-pixel is different from the polarity of other sub-pixels in the same column, thereby achieving alternating positive and negative polarity of the sub-pixels in the pixel column at the junction, thereby avoiding the formation of bright and dark lines at the boundary and improving the display effect of the display panel.

[0021] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0022] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 It is a schematic diagram of a conventional polarity mode of the display panel in the first embodiment of the present application.

[0025] Figure 2 This is a schematic diagram of the polarity symmetry between the first display area and the second display area in the first embodiment of the present application.

[0026] Figure 3 It is a schematic diagram of the polarity symmetry mode of the display panel in the first embodiment of the present application.

[0027] Figure 4 This is a schematic diagram of the selection unit connecting the data line and the dual-control sub-pixel in the first embodiment of the present application.

[0028] Figure 5 This is a schematic diagram of the comparison unit controlling the selection unit in the first embodiment of the present application.

[0029] Figure 6 It is a schematic diagram of the structure of the XOR gate circuit in the first embodiment of the present application.

[0030] Figure 7 It is the truth table of the XOR gate circuit in the first embodiment of the present application.

[0031] Figure 8 It is a schematic diagram of the structure of the display device in the second embodiment of the present application.

[0032] Fig. 9 It is a schematic diagram of the common electrode voltage waveform in the second embodiment of the present application.

[0033] Description of reference numerals:

[0034] 100, display panel; 101, first display area; 102, second display area;

[0035] 110, data line; 120, sub-pixel; 121, dual-control sub-pixel; 130, selection unit; 131, second transistor; 132, third transistor; 140, first transistor; 150, comparison unit;

[0036] 200, drive module;

[0037] 210, source driver chip; 221, control power supply; 222, ground terminal; 230, image detection module; 231, waveform recognition unit; 240, polarity partition control module; 241, resistor; 242, fourth transistor. DETAILED DESCRIPTION

[0038] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of example embodiments to those skilled in the art.

[0039] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the present application.

[0040] The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0041] Embodiment 1

[0042] See also Figures 1 to 4 As shown, in this embodiment, the display panel 100 includes a plurality of columns of data lines 110 and a plurality of sub-pixels 120 arranged in an array, and each column of sub-pixels 120 is arranged between two adjacent data lines 110. That is, the data lines 110 have one more column than the sub-pixels 120. For example, the display panel 100 includes the N-4th column of data lines, the N-3rd column of data lines, ..., the Nth column of data lines, ..., the N+4th column of data lines, the N+5th column of data lines, and 9 columns of sub-pixels 120.

[0043] The sub-pixels 120 of the odd-numbered rows are connected to the data lines 110 on the first side of the adjacent data lines 110 of the columns in which they are located, and the sub-pixels 120 of the even-numbered rows are connected to the data lines 110 on the second side of the adjacent data lines 110 of the columns in which they are located. The data lines 110 are used to connect a plurality of source driver chips 210, and the plurality of source driver chips 210 form a plurality of columns of source driver chips 210. The source driver chips 210 of the odd-numbered columns control the first display area 101, and the source driver chips 210 of the even-numbered columns control the second display area 102. The first display area 101 and the second display area 102 are alternated in the row direction of the display panel 100, and the number of the first display area 101 and the second display area 102 may be the same or different.

[0044] When displaying a picture, the positive and negative polarities of the data signals output by the plurality of data lines 110 are alternated in sequence, and when scanning row by row, the polarity reversal interval is 1 frame, that is, the polarity reversal mode of the display panel 100 is dot reversal, such as Figure 1 shown.

[0045] It should be understood that if the polarity of the adjacent first display area 101 and the second display area 102 is symmetrical, the coupling directions of the pixel voltage and the common voltage of the first display area 101 and the second display area 102 are opposite, the coupling can be offset, and the crosstalk can be improved or eliminated. However, in the pixel column at the junction of the adjacent first display area 101 and the second display area 102, the sub-pixels 120 of the entire column are positive or negative, and the polarity of the sub-pixels 120 in other pixel columns is alternating between positive and negative, such as Figure 2 As shown, the pixel columns at the junction become brighter or darker than other pixel columns, that is, bright lines or dark lines are formed, which affects the display effect of the display panel 100 .

[0046] In order to improve or eliminate the display unevenness caused by the bright and dark lines, in this embodiment, a dual-control sub-pixel 121 is provided in the pixel column at the junction, and the dual-control sub-pixel 121 is a sub-pixel 120 in an odd row or an even row. The dual-control sub-pixel 121 is also connected to another data line 110 other than the adjacent data line 110 in the column where it is located. The display panel 100 also includes a plurality of selection units 130, and each dual-control sub-pixel 121 is connected to the corresponding two data lines 110 through the selection unit 130. The selection unit 130 can control the data signal of one of the two data lines 110 to be output to the dual-control sub-pixel 121, so that the polarity of the dual-control sub-pixel 121 can be switched.

[0047] In the normal polarity mode, the polarity of the first display area 101 and the second display area 102 is the same, and in the entire display panel 100: the polarity of the data signal output by the data line 110 along the row direction alternates between positive and negative. For example, when scanning the first row, the output data signal of the data line in the N-1 column is positive, the output data signal of the data line in the N column is negative, the output data signal of the data line in the N+1 column is positive, and the output data signal of the data line in the N+2 column is negative. The selection unit 130 turns on the dual-control sub-pixel 121 and one of the adjacent data lines 110, and when scanning row by row, the polarity reversal interval is 1 frame. The polarity reversal mode of the display panel 100 is dot reversal, such as Figure 1 shown.

[0048] In the polarity symmetry mode, the polarity of the first display area 101 is "+-+-", and the polarity of the second display area 102 is "-+-+", and the polarity of the first display area 101 and the second display area 102 are symmetrical. In each display area: the polarity of the data signal output by the data line 110 along the row direction alternates between positive and negative, and the polarity of the data signal output by the data lines 110 on both sides is the same, with the pixel column at the junction as the center. For example, when scanning the first row, the output data signal of the data line in the N-1 column is positive, the output data signal of the data line in the N column is negative, the output data signal of the data line in the N+1 column is negative, and the output data signal of the data line in the N+2 column is positive. The selection unit 130 turns on another data line 110 other than the dual-controlled sub-pixel 121 and the adjacent data line 110. The polarity of the dual-controlled sub-pixel 121 is different from the polarity of other sub-pixels 120 in the same column, and the positive and negative polarities of the sub-pixels 120 in the column direction alternate row by row. For example, the dual-controlled sub-pixel 121 is a sub-pixel 120 in an even row, the selection unit 130 turns on the N-1 column data line and the dual-controlled sub-pixel 121, the polarity of the dual-controlled sub-pixel 121 is positive, and the polarity of other sub-pixels 120 in the same column is negative. Figure 3 shown.

[0049] In this embodiment, the display panel 100 includes a plurality of columns of data lines 110 and a plurality of sub-pixels 120 arranged in an array. Each column of sub-pixels 120 is arranged between two adjacent data lines 110. The sub-pixels 120 in odd-numbered rows are connected to the data lines 110 on the first side of the adjacent data lines 110, and the sub-pixels 120 in even-numbered rows are connected to the data lines 110 on the second side of the adjacent data lines 110. The data lines 110 are used to connect to a plurality of source driver chips 210. The image electrodes at the junction of the display area controlled by the source driver chips 210 in the odd-numbered columns and the even-numbered columns are connected to the sub-pixels 120 in the even-numbered columns. A dual-control sub-pixel 121 is arranged in the pixel column. The dual-control sub-pixel 121 is a sub-pixel 120 in an odd row or an even row. The dual-control sub-pixel 121 is also connected to another data line 110 other than the adjacent data line 110. The display panel 100 also includes a plurality of selection units 130. Each dual-control sub-pixel 121 is connected to the corresponding data line 110 through the selection unit 130. The selection unit 130 can control the data signal of one of the two data lines 110 to be output to the dual-control sub-pixel 121, so that the polarity of the dual-control sub-pixel 121 can be switched. In the polarity symmetry mode, the selection unit 130 switches the polarity of the dual-control sub-pixel 121, so that the polarity of the dual-control sub-pixel 121 is different from the polarity of other sub-pixels 120 in the same column, so that the polarity of the sub-pixel 120 in the pixel column at the junction is alternately positive and negative, so as to avoid the formation of bright and dark lines at the boundary, thereby improving the display effect of the display panel 100.

[0050] In some embodiments, the dual-control sub-pixel 121 is a sub-pixel 120 in an even row, the adjacent data line 110 in the column to which the dual-control sub-pixel 121 is connected is the Nth data line, and the other data line 110 to which the dual-control sub-pixel 121 is connected is the N-ath data line, where a is an odd number and N is an integer greater than or equal to 2. For example, the other data line 110 to which the dual-control sub-pixel 121 is connected is the N-1th data line, the N-3th data line, and the like.

[0051] In the polarity symmetry mode, the polarity of the data signal output by the Nth data line is different from the polarity of the data signal output by the N-ath data line. The dual-control sub-pixel 121 is connected to the Nth data line and the N-ath data line through the selection unit 130, and the polarity of the dual-control sub-pixel 121 is switchable.

[0052] It should be noted that when the dual-controlled sub-pixel 121 is a sub-pixel 120 in an even row, the other data line 110 connected to the dual-controlled sub-pixel 121 may be the N-ath data line, but is not limited to this. The other data line 110 connected to the dual-controlled sub-pixel 121 may also be the N+bth data line, where b is an even number.

[0053] In some embodiments, the dual-control sub-pixel 121 is a sub-pixel 120 in an odd row, the adjacent data line 110 connected to the dual-control sub-pixel 121 is the N+1th data line, and the other data line 110 connected to the dual-control sub-pixel 121 is the N+1+ath data line, where a is an odd number and N is an integer greater than or equal to 2.

[0054] In the polarity symmetry mode, the polarity of the data signal output by the Nth data line is different from the polarity of the data signal output by the N+1+ath data line. The dual-control sub-pixel 121 is connected to the N+1th data line and the N+1+ath data line through the selection unit 130, and the polarity of the dual-control sub-pixel 121 is switchable.

[0055] It should be noted that when the dual-control sub-pixel 121 is a sub-pixel 120 in an odd row, the other data line 110 connected to the dual-control sub-pixel 121 may be the N+1+ath data line, but is not limited to this. The other data line 110 connected to the dual-control sub-pixel 121 may also be the Nath data line, where a is an odd number.

[0056] In some embodiments, when the dual-controlled sub-pixel 121 is a sub-pixel 120 in an odd row or a sub-pixel 120 in an even row, a is always 1. For example, when the dual-controlled sub-pixel 121 is a sub-pixel 120 in an even row, the dual-controlled sub-pixel 121 is connected to the Nth data line and the N-1th data line through the selection unit 130; when the dual-controlled sub-pixel 121 is a sub-pixel 120 in an odd row, the dual-controlled sub-pixel 121 is connected to the N+1th data line and the N+2th data line through the selection unit 130.

[0057] It should be noted that the data signal voltages of the N-1th data line and the Nth data line may be different, but the polarity symmetry mode is only used in special screens with severe crosstalk, and the data signal voltage difference of adjacent data lines 110 is small and does not affect the screen display.

[0058] Another data line 110 connected to the dual-control sub-pixel 121 is the nearest data line 110 with a different polarity, which can reduce the number of wirings and avoid the voltage difference of the data signal affecting the display effect.

[0059] See also Figure 4 As shown, the display panel 100 further includes a first transistor 140, a first end of the first transistor 140 is connected to the control end of the plurality of selection units 130, a second end of the first transistor 140 is connected to the control power supply 221, and the control end of the first transistor 140 is used to connect to the driving module 200. The first transistor 140 may be an N-type transistor.

[0060] In the normal polarity mode, the driving module 200 outputs a low-level control signal, the first transistor 140 is turned off, and the selection unit 130 turns on one of the dual-controlled sub-pixel 121 and the adjacent data line 110 in the column where the dual-controlled sub-pixel 121 is located by default; in the polarity symmetry mode, the driving module 200 outputs a high-level control signal, the first transistor 140 is turned on, the control power supply 221 voltage is written to the control end of the selection unit 130, and the selection unit 130 turns on the dual-controlled sub-pixel 121 and the other data line 110 other than the adjacent data line 110 in the column where the dual-controlled sub-pixel 121 is located.

[0061] The driving module 200 controls the first transistor 140 to turn on or off, and the first transistor 140 controls the voltage writing of the control power supply 221. Compared with directly using the driving module 200 to control the selection unit 130, the control signal attenuation of the driving module 200 can be avoided to affect the operation of the selection unit 130.

[0062] It should be noted that the first transistor 140 may be an N-type transistor, but is not limited thereto. The first transistor 140 may also be a P-type transistor, depending on the specific situation.

[0063] See also Figure 4 As shown, the selection unit 130 includes a second transistor 131 and a third transistor 132, the second transistor 131 is a P-type transistor, and the third transistor 132 is an N-type transistor. The control end of the second transistor 131 and the control end of the third transistor 132 are the control ends of the selection unit 130, the two connection ends of the second transistor 131 are connected to the dual-control sub-pixel 121 and one of the adjacent data lines 110 in the column where the dual-control sub-pixel 121 is located, and the two connection ends of the third transistor 132 are connected to the dual-control sub-pixel 121 and another data line 110 other than the adjacent data line 110 in the column where the dual-control sub-pixel 121 is located.

[0064] In the normal polarity mode, the first transistor 140 is turned off, the control power supply 221 voltage stops writing, the second transistor 131 is turned on and the third transistor 132 is turned off, and the second transistor 131 turns on one of the dual-control sub-pixel 121 and the adjacent data line 110; in the polarity symmetric mode, the first transistor 140 is turned on, the control power supply 221 voltage is written to the control ends of the second transistor 131 and the third transistor 132, the second transistor 131 is turned off and the third transistor 132 is turned on, and the third transistor 132 turns on the dual-control sub-pixel 121 and the other data line 110 other than the adjacent data line 110.

[0065] In some embodiments, the display panel 100 further includes a comparison unit 150, two input terminals of the comparison unit 150 are connected to the adjacent data lines 110 corresponding to the pixel columns at the junction, and an output terminal of the comparison unit 150 is connected to the control terminal of the first transistor 140. Figure 5 shown.

[0066] The comparison unit 150 compares the data signals of the adjacent data lines 110 corresponding to the pixel columns at the junction. In the conventional polarity mode, the data signals of the adjacent data lines 110 corresponding to the pixel columns at the junction are different. In the polarity symmetric mode, the data signals of the adjacent data lines 110 corresponding to the pixel columns at the junction are the same. The comparison unit 150 outputs a control signal to control the first transistor 140 to turn on or off, thereby reducing the control signal output by the driving module 200.

[0067] See also Figure 6 and Figure 7 As shown, the comparison unit 150 may be an XNOR gate circuit. The two input terminals (A and B) of the XNOR gate circuit are respectively connected to the two data lines 110 connected to the dual-control sub-pixel 121, and the output terminal (Y) of the XNOR gate circuit is connected to the control terminal of the first transistor 140. The first transistor 140 may be an N-type transistor.

[0068] In the normal polarity mode, the data signals of the adjacent data lines 110 corresponding to the pixel columns at the junction are different, the same OR gate circuit outputs a low-level control signal, and the first transistor 140 is turned off; in the polarity symmetric mode, the data signals of the adjacent data lines 110 corresponding to the pixel columns at the junction are the same, the same OR gate circuit outputs a high-level control signal, and the first transistor 140 is turned on.

[0069] It should be noted that the comparison unit 150 can be an XOR gate circuit, but is not limited thereto. The comparison unit 150 can also be a comparator, an operational amplifier or an XOR gate circuit, depending on the specific situation. When the comparison unit 150 is a comparator, an operational amplifier or an XOR gate circuit, the first transistor 140 is a P-type transistor.

[0070] Embodiment 2

[0071] The present application also provides a display device, see Figure 8 As shown, the display device includes the display panel 100 and the driving module 200 disclosed in the first embodiment. The driving module 200 includes a plurality of source driving chips 210, a picture detection module 230 and a polarity partition control module 240. All data lines 110 of the display panel 100 are connected to the plurality of source driving chips 210. The source driving chips 210 of the odd columns control the first display area 101, and the source driving chips 210 of the even columns control the second display area 102.

[0072] The polarity partition control module 240 is used to control the polarity of the second display area 102 to be the same as or symmetrical to the polarity of the first display area 101, forming a conventional polarity mode and a polarity symmetric mode. The image detection module 230 is connected to the display panel 100 and the polarity partition control module 240, and is used to control the polarity partition control module 240 to work according to the detected crosstalk degree of the display image.

[0073] In the present embodiment, a dual-controlled sub-pixel 121 is arranged in the pixel column at the junction of the display area controlled by the source driver chip 210 of the odd columns and the even columns. The dual-controlled sub-pixel 121 is a sub-pixel 120 of the odd rows or the even rows. The dual-controlled sub-pixel 121 is also connected to another data line 110 other than the adjacent data line 110. The display panel 100 also includes a plurality of selection units 130. Each dual-controlled sub-pixel 121 is connected to the corresponding data line 110 through the selection unit 130. The selection unit 130 can control the data signal of one of the two data lines 110 to be output to the dual-controlled sub-pixel 121, so that the polarity of the dual-controlled sub-pixel 121 can be switched. When the image detection module 230 detects that the crosstalk of the display image is serious, the polarity partition control module 240 is controlled to work, and the conventional polarity mode is switched to the polarity symmetry mode, so that the polarity of the dual-controlled sub-pixel 121 is different from the polarity of other sub-pixels 120 in the same column, so that the polarity of the sub-pixels 120 in the pixel column at the junction is alternately positive and negative, which can avoid the formation of bright and dark lines at the boundary, thereby improving the display effect of the display panel 100.

[0074] In some embodiments, the polarity partition control module 240 includes a resistor 241 and a fourth transistor 242. The source driver chip 210 of the odd columns is connected to the ground terminal 222, the source driver chip 210 of the even columns is connected to the first end of the fourth transistor 242, the second end of the fourth transistor 242 is connected to the control power supply 221, the control end of the fourth transistor 242 is connected to the picture detection module 230, and the resistor 241 is connected to the ground terminal 222 and the first end of the fourth transistor 242.

[0075] In the normal polarity mode, the ground terminal 222 outputs a low-level signal to the source driver chip 210 of the odd-numbered columns, and the polarity of the first display area 101 controlled by the source driver chip 210 of the odd-numbered columns in the row direction is "+-+-"; the resistor 241 connects the ground terminal 222 to the source driver chip 210 of the even-numbered columns, and the ground terminal 222 outputs a low-level signal to the source driver chip 210 of the even-numbered columns, and the polarity of the second display area 102 controlled by the source driver chip 210 of the even-numbered columns in the row direction is "+-+-", such as Figure 1 shown.

[0076] In the polarity symmetry mode, the ground terminal 222 outputs a low-level signal to the source driver chip 210 of the odd-numbered columns, and the polarity of the first display area 101 controlled by the source driver chip 210 of the odd-numbered columns in the row direction is "+-+-"; the fourth transistor 242 turns on the control power supply 221 and the source driver chip 210 of the even-numbered columns, and the control power supply 221 outputs a high-level signal to the source driver chip 210 of the even-numbered columns, so that the second display area 102 controlled by the source driver chip 210 of the even-numbered columns is polarity symmetrical with the first display area 101, that is, the polarity of the second display area 102 controlled by the source driver chip 210 of the even-numbered columns in the row direction is "-+-+", such as Figure 3 shown.

[0077] In some embodiments, the display panel 100 includes a first transistor 140 , a first end of the first transistor 140 is connected to the control end of the plurality of selection units 130 , a second end of the first transistor 140 is connected to the control power supply 221 , and a control end of the first transistor 140 is connected to the picture detection module 230 .

[0078] The first transistor 140 can be an N-type transistor. In the normal polarity mode, the picture detection module 230 outputs a low-level control signal, the first transistor 140 is turned off, and the selection unit 130 turns on one of the dual-controlled sub-pixel 121 and the adjacent data line 110 by default; in the polarity symmetric mode, the picture detection module 230 outputs a high-level control signal, the first transistor 140 is turned on, the control power supply 221 voltage is written to the control end of the selection unit 130, and the selection unit 130 turns on the dual-controlled sub-pixel 121 and another data line 110 other than the adjacent data line 110, so that the positive and negative polarities of the sub-pixels 120 in the pixel column at the junction are alternated.

[0079] In some embodiments, two input terminals of the comparison unit 150 are connected to adjacent data lines 110 corresponding to the pixel columns at the junction, and an output terminal of the comparison unit 150 is connected to a control terminal of the first transistor 140 .

[0080] When the display panel 100 includes the comparison unit 150 , the first transistor 140 is automatically controlled by the comparison unit 150 , and the picture detection module 230 is not required to control the first transistor 140 , thereby reducing the structural complexity of the picture detection module 230 .

[0081] It should be noted that the comparison unit 150 may be disposed on the display panel 100 , but is not limited thereto. The comparison unit 150 may also be disposed on the driving module 200 , depending on the specific situation.

[0082] In some embodiments, the picture detection module 230 is a timing controller, which includes a waveform recognition unit 231, which is connected to the common electrode of the display panel 100 and the polarity partition control module 240. When the common electrode voltage Vcom exceeds the preset interval, the waveform recognition unit 231 outputs a high-level control signal to form a polarity symmetric mode; when the common electrode voltage Vcom does not exceed the preset interval, the waveform recognition unit 231 outputs a low-level control signal to form a normal polarity mode.

[0083] It should be noted that the picture detection module 230 may be a timing controller, but is not limited thereto. The picture detection module 230 may also be an additional detection module, depending on the specific situation.

[0084] When the pixel voltage is offset during crosstalk, it will cause the common electrode voltage Vcom to fluctuate. In the waveform recognition unit 231, an interval value is set according to the common electrode voltage Vcom, that is, a positive and negative trigger value m1 and m2 are set, such as Fig. 9 As shown, when it is identified that the common electrode voltage Vcom exceeds the preset interval (greater than m1 and maintained for t1 time or less than m2 and maintained for t2 time, indicating serious crosstalk and poor picture effect), a high-level control signal is output to the polarity partition control module 240, and the display panel 100 switches to the polarity symmetric mode. The pixel voltage and common voltage coupling directions of the adjacent first display area 101 and second display area 102 are opposite, so that the coupling can be offset and the crosstalk can be improved or eliminated. On the contrary, when the common electrode voltage Vcom does not exceed the preset interval, a low-level control signal is output to the polarity partition control module 240, and the display panel 100 is in the normal polarity mode.

[0085] In some embodiments, the timing controller can detect the display screen and control the display panel 100 to a conventional polarity mode or a polarity symmetric mode according to the display screen. When using the timing controller to detect the display screen, some complex screens may not be detected, and the detection must be performed based on the pixel arrangement structure and number. The existing known crosstalk screens may not be complete. If a new screen has crosstalk later, then the pixel structure of this screen is different from the existing one, and the timing controller cannot detect it. In addition, the crosstalk phenomenon of different liquid crystals is inconsistent, and the unified setting cannot be fully compatible, which requires more debugging time.

[0086] In this embodiment, the waveform recognition unit 231 is connected to the common electrode of the display panel 100. The waveform recognition unit 231 outputs a control signal according to the common electrode voltage Vcom to switch the display panel 100 to a conventional polarity mode or a polarity symmetric mode. Compared with the solution of using a timing controller to detect the display screen, it can be generally used to detect different crosstalk phenomena.

[0087] The terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0088] In this application, unless otherwise clearly specified and limited, the terms "assembly", "connection" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0089] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0090] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A display panel, comprising a plurality of columns of data lines and a plurality of sub-pixels arranged in an array, wherein each column of the sub-pixels is arranged between two adjacent data lines, the sub-pixels in odd-numbered rows are connected to the data lines on a first side of the adjacent data lines, and the sub-pixels in even-numbered rows are connected to the data lines on a second side of the adjacent data lines, characterized in that: The data lines are used to connect a plurality of source driver chips, the source driver chips in odd columns control the first display area, and the source driver chips in even columns control the second display area, dual-controlled sub-pixels are arranged in the pixel columns at the junction of the first display area and the second display area, the dual-controlled sub-pixels are the sub-pixels in odd rows or even rows, and the dual-controlled sub-pixels are also connected to another data line other than the adjacent data line, the display panel also includes a plurality of selection units, each of the dual-controlled sub-pixels is connected to the corresponding data line through the selection unit, and the selection unit can control the data signal of one of the two data lines to be output to the dual-controlled sub-pixel, so that the polarity of the dual-controlled sub-pixel can be switched; When the dual-control sub-pixel is the sub-pixel in an odd row, the adjacent data line connected to the dual-control sub-pixel is the N+1th data line, and the other data line connected to the dual-control sub-pixel is the N+1+ath data line; When the dual-control sub-pixel is the sub-pixel in an even row, the adjacent data line connected to the dual-control sub-pixel is the Nth data line, and the other data line connected to the dual-control sub-pixel is the N-ath data line, where a is an odd number and N is an integer greater than or equal to 2.

2. The display panel according to claim 1, characterized in that: When the dual-controlled sub-pixels are the sub-pixels in odd-numbered rows or the sub-pixels in even-numbered rows, a is 1.

3. The display panel according to claim 1, characterized in that: The display panel further includes a first transistor, a first end of the first transistor is connected to the control ends of the plurality of selection units, a second end of the first transistor is connected to a control power supply, and the control end of the first transistor is used to connect to a driving module.

4. The display panel according to claim 1, characterized in that: The display panel also includes a first transistor, a first end of the first transistor is connected to the control end of the plurality of selection units, a second end of the first transistor is connected to a control power supply, the display panel also includes a comparison unit, two input ends of the comparison unit are connected to the adjacent data lines corresponding to the pixel columns, and an output end of the comparison unit is connected to the control end of the first transistor.

5. The display panel according to claim 4, characterized in that: The comparison unit includes a comparator, an XOR gate circuit or an XNOR gate circuit. When the comparison unit is the comparator or the XOR gate circuit, the first transistor is a P-type transistor. When the comparison unit is the XNOR gate circuit, the first transistor is an N-type transistor.

6. The display panel according to any one of claims 2 to 5, characterized in that: The selection unit includes a second transistor and a third transistor, the second transistor is a P-type transistor, the third transistor is an N-type transistor, the control end of the second transistor and the control end of the third transistor are the control ends of the selection unit, the two connection ends of the second transistor are connected to the dual-control sub-pixel and one of the adjacent data lines, and the two connection ends of the third transistor are connected to the dual-control sub-pixel and another data line other than the adjacent data line.

7. A display device, characterized in that: include: The display panel according to any one of claims 1 to 6; A driving module, the driving module includes a plurality of source driving chips, a picture detection module and a polarity partition control module, all the data lines of the display panel are connected to the plurality of source driving chips, the source driving chips in odd columns control the first display area, and the source driving chips in even columns control the second display area, the polarity partition control module is used to control the polarity of the second display area to be the same as or symmetrical with the polarity of the first display area, forming a conventional polarity mode and a polarity symmetry mode, the picture detection module is connected to the display panel and the polarity partition control module, and is used to control the operation of the polarity partition control module according to the detected crosstalk degree of the display picture.

8. The display device according to claim 7, characterized in that: The polarity partition control module includes a resistor and a fourth transistor, the source driver chip of the odd column is connected to the ground end, the source driver chip of the even column is connected to the first end of the fourth transistor, the second end of the fourth transistor is connected to the control power supply, the control end of the fourth transistor is connected to the picture detection module, and the resistor is connected to the ground end and the first end of the fourth transistor.

9. The display device according to claim 8, characterized in that: The display panel further includes a first transistor, a first end of the first transistor is connected to the control ends of the plurality of selection units, a second end of the first transistor is connected to the control power supply, and a control end of the first transistor is connected to the picture detection module.

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