Semiconductor device and semiconductor system relating to generation timing of

Abstract

The invention relates to a semiconductor device and a semiconductor system for compensating generation timing of an internal command. A semiconductor device includes a dividing circuit configured to generate a first divided clock and a second divided clock by dividing a frequency of a clock, and an internal command generation circuit configured to generate an internal command based on the command in synchronization with the first divided clock and the second divided clock, configured to lock a phase detection signal generated based on a timing when the command is received in the pipe latch, and configured to compensate for the generation timing of the internal command based on the phase detection signal that has been latched in the pipe latch.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0096426 filed on July 24, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to a semiconductor device and a semiconductor system, and more particularly to a semiconductor device and a semiconductor system configured to latch a phase detection signal generated by detecting an input timing of a command input synchronously with a clock in a pipe latch and configured to compensate for a generation timing of an internal command generated from the command based on the phase detection signal already latched in the pipe latch. Background Art

[0004] Typically, a semiconductor device including a double data rate synchronous DRAM (DDR SDRAM) performs internal operations in response to a command input by an external chipset. In order to enable the semiconductor device to perform such read and write operations, the semiconductor device needs to include various circuits. Various circuits include a pipe circuit for efficiently controlling more signals. Typically, a pipe circuit is a circuit configured to store each of a plurality of input signals at a desired timing and output each signal at a desired timing. The pipe circuit is included in a semiconductor device and can increase the transmission and reception of signals between the internal circuits of the semiconductor device or between an external device of the semiconductor device and the internal circuits of the semiconductor device.

[0005] In addition, the semiconductor device includes a shift circuit configured to shift commands by using a plurality of divided clocks generated by dividing the frequency of a clock. Such a semiconductor device includes a plurality of shift circuits implemented by a plurality of divided clocks, and can generate an internal command for performing an internal operation by shifting the command. Summary of the invention

[0006] In one embodiment, a semiconductor device may include a frequency division circuit and an internal command generation circuit, wherein the frequency division circuit is configured to receive a clock to generate a first divided clock and a second divided clock by dividing the frequency of the clock, the internal command generation circuit is configured to receive a command synchronously with the first divided clock and the second divided clock to generate an internal command based on the command received synchronously with the first divided clock and the second divided clock, is configured to latch a phase detection signal generated based on the timing when the command is received in a pipe latch, and is configured to compensate for the generation timing of the internal command based on the phase detection signal already latched in the pipe latch.

[0007] Furthermore, in one embodiment, a semiconductor system may include a controller and a semiconductor device, the controller being configured to output a clock that is periodically switched and being configured to output commands, addresses, and data, the semiconductor device being configured to sequentially latch a phase detection signal generated by detecting an input timing of a command input synchronously with the clock in a plurality of pipe latches, being configured to compensate for a generation timing of an internal command generated from a command based on the phase detection signal already latched in the plurality of pipe latches, and being configured to store data based on the internal command and the address. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram showing a configuration of a semiconductor system according to an embodiment of the present disclosure;

[0009] Figure 2 It shows that according to Figure 1 A block diagram showing a configuration of one embodiment of a semiconductor device included in a semiconductor system;

[0010] Figure 3 It shows that according to Figure 2 A block diagram showing a configuration of one embodiment of a frequency dividing circuit included in a semiconductor device shown;

[0011] Figure 4 Is used to describe Figure 3 A timing diagram showing an example of the operation of the frequency divider circuit is shown;

[0012] Figure 5 It shows that according to Figure 2 A block diagram showing a configuration of one embodiment of an internal command generation circuit included in a semiconductor device shown;

[0013] Figure 6 It shows that according to Figure 5 A block diagram showing a configuration of an embodiment of a phase detection circuit included in an internal command generation circuit shown;

[0014] Figure 7 It shows that according to Figure 5 A diagram showing a configuration of an embodiment of a synthesized command generation circuit included in an internal command generation circuit shown;

[0015] Figure 8 It shows that according to Figure 5 A block diagram showing a configuration of an embodiment of a shift circuit included in an internal command generation circuit shown;

[0016] Fig. 9 It shows that according to Figure 5 A block diagram showing a configuration of an embodiment of a selection signal generating circuit included in an internal command generating circuit shown;

[0017] Fig.10 It shows that according to Fig. 9 A block diagram showing a configuration of an embodiment of an input control signal generating circuit included in the selection signal generating circuit shown;

[0018] Fig.11 It shows that according to Fig. 9 A block diagram showing a configuration of an embodiment of an output control signal generating circuit included in a selection signal generating circuit shown;

[0019] Fig.12 It shows that according to Fig. 9 A block diagram showing the construction of an embodiment of a pipeline circuit included in a selection signal generating circuit shown;

[0020] Fig.13 It shows that according to Figure 5 A block diagram showing a configuration of an embodiment of a command phase control circuit included in an internal command generation circuit;

[0021] Fig.14 and Fig.15 is a timing diagram for describing the operation of a semiconductor device according to one embodiment of the present disclosure; and

[0022] Fig.16 It shows that according to Figure 1 and Fig.15 A diagram showing a configuration of one embodiment of an electronic system to which the semiconductor system shown has been applied. DETAILED DESCRIPTION

[0023] In the description of the following embodiments, the term "preset" indicates that the value of the parameter is predetermined when the parameter is used in a process or algorithm. According to one embodiment, the value of the parameter can be set at the beginning of the process or algorithm or while the process or algorithm is being executed.

[0024] Terms such as "first" and "second" used to distinguish among various components are not limited to the components. For example, a first component may be referred to as a second component, and vice versa.

[0025] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that the components may be directly coupled or connected to each other, or coupled or connected to each other through another component interposed therebetween. Conversely, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that the components are directly coupled or connected to each other without another component interposed therebetween.

[0026] "Logical high level" and "logical low level" are used to describe the logic level of a signal. A signal with a "logical high level" is different from a signal with a "logical low level". For example, when a signal with a first voltage corresponds to a signal with a "logical high level", a signal with a second voltage may correspond to a signal with a "logical low level". According to one embodiment, the "logical high level" may be set to a voltage higher than the "logical low level". According to one embodiment, the logic level of a signal may be set to a different logic level or an opposite logic level. For example, in some embodiments, a signal with a logical high level may be set to have a logical low level, and in some embodiments, a signal with a logical low level may be set to have a logical high level.

[0027] Hereinafter, the present disclosure will be described in more detail through examples. The examples are only used to illustrate the present disclosure, and the scope of the present disclosure is not limited by the examples.

[0028] Embodiments of the present disclosure provide a semiconductor device and a semiconductor system for latching a phase detection signal generated by detecting an input timing of a command input synchronously with a clock in a pipe latch, and compensating for a generation timing of an internal command generated from the command based on the phase detection signal already latched in the pipe latch.

[0029] According to one embodiment of the present disclosure, there is an effect that a phase detection signal generated by detecting the input timing of a command input synchronously with a clock can be latched in a pipe latch, and the generation timing of an internal command generated from the command can be compensated based on the phase detection signal already latched in the pipe latch.

[0030] In addition, according to one embodiment of the present disclosure, there is an effect of reducing the area and current consumption of a shift circuit for shifting an internal command by latching a phase detection signal generated by detecting the input timing of a command in a pipe latch, and compensating for the generation timing of the internal command by using a shift circuit based on the phase detection signal.

[0031] like Figure 1 As shown, the semiconductor system 1 according to an embodiment of the present disclosure may include a controller 10 and a semiconductor device 20. The semiconductor device 20 may include a frequency dividing circuit (DIV CT) 210 and an internal command generating circuit (ICMD GEN) 220.

[0032] The controller 10 may include a first control pin 11_1, a second control pin 11_2, a third control pin 11_3, and a fourth control pin 11_4. The semiconductor device 20 may include a first device pin 21_1, a second device pin 21_2, a third device pin 21_3, and a fourth device pin 21_4. The first transmission line L11 may be connected between the first control pin 11_1 and the first device pin 21_1. The second transmission line L12 may be connected between the second control pin 11_2 and the second device pin 21_2. The third transmission line L13 may be connected between the third control pin 11_3 and the third device pin 21_3. The fourth transmission line L14 may be connected between the fourth control pin 11_4 and the fourth device pin 21_4.

[0033] The controller 10 may transmit a clock CLK to the semiconductor device 20 through a first transmission line L11. The controller 10 may transmit a command CMD for controlling the semiconductor device 20 to the semiconductor device 20 through a second transmission line L12. The controller 10 may transmit an address ADD to the semiconductor device 20 through a third transmission line L13. The controller 10 may transmit data DATA to the semiconductor device 20 through a fourth transmission line L14. The controller 10 may receive data DATA from the semiconductor device 20 through the fourth transmission line L14. The clock CLK may be set as a signal that switches periodically so as to synchronize the operations of the controller 10 and the semiconductor device 20. The command CMD may be set as a signal for controlling the internal operation of the semiconductor device 20. The address ADD may include a plurality of bits and may be set as a signal for setting a location for storing the data DATA. The data DATA may include a plurality of bits. The plurality of bits may be serially input and output.

[0034] The frequency division circuit 210 can generate a first frequency division clock ( Figure 2 ICLK in) and the second divided clock ( Figure 2 The frequency division circuit 210 can generate a first frequency division clock ( Figure 2 The frequency dividing circuit 210 can generate a second frequency-divided clock (ICLK) including pulses by dividing the frequency of the clock CLK. Figure 2 The OCLK in the clock has a frequency of 1 / 2 of the clock CLK and is generated synchronously with the even pulses of the clock CLK. The frequency division circuit 210 can generate a first frequency division clock ( Figure 2 ICLK in) and the second divided clock ( Figure 2 1 (OCLK in ).

[0035] The internal command generation circuit 220 can be connected to the first frequency-divided clock ( Figure 2 ICLK in) and the second divided clock ( Figure 2 OCLK in the ) synchronously generates an internal command based on the command CMD ( Figure 2 The internal command generation circuit 220 can generate a phase detection signal (ICMD) based on the timing of the input of the command CMD. Figure 5 PD) is sequentially latched in multiple pipeline latches ( Fig.12 The internal command generation circuit 220 can be based on the phase detection signal ( Figure 5 PD in to compensate for the internal command ( Figure 2 Generation timing of ICMD).

[0036] The semiconductor device 20 can generate a phase detection signal ( Figure 5 PD) is sequentially latched in multiple pipeline latches ( Fig.12 The semiconductor device 20 can detect the phase of the pipeline latch based on the phase detection signal ( Figure 5 PD in to compensate for the internal command ( Figure 2 The semiconductor device 20 can generate timing of ICMD in the internal command ( Figure 2 ICMD in) and address ADD store data DATA in the memory circuit ( Figure 2 The semiconductor device 20 may be based on the internal command ( Figure 2 ICMD) and address ADD to output the data stored in the memory circuit ( Figure 2 The data DATA in 240).

[0037] like Figure 2 As shown, the semiconductor device 20 according to an embodiment of the present disclosure may include a frequency dividing circuit (DIVCT) 210 , an internal command generating circuit (ICMD GEN) 220 , an internal address generating circuit (IADD GEN) 230 , and a memory circuit 240 .

[0038] The frequency division circuit 210 can generate a first divided clock ICLK and a second divided clock OCLK by dividing the frequency of the clock CLK. The frequency division circuit 210 can generate a first divided clock ICLK including a pulse having 1 / 2 the frequency of the clock CLK and generated synchronously with the odd pulses of the clock CLK by dividing the frequency of the clock CLK. The frequency division circuit 210 can generate a second divided clock OCLK including a pulse having 1 / 2 the frequency of the clock CLK and generated synchronously with the even pulses of the clock CLK by dividing the frequency of the clock CLK. The frequency division circuit 210 can generate a first divided clock ICLK and a second divided clock OCLK having opposite phases by dividing the frequency of the clock CLK.

[0039] The internal command generation circuit 220 may generate an internal command ICMD based on the command CMD in synchronization with the first divided clock ICLK and the second divided clock OCLK. The internal command generation circuit 220 may generate the internal command ICMD by shifting the command CMD based on the first delay signal to the fourth delay signal LTC<1:4> in synchronization with the first divided clock ICLK and the second divided clock OCLK. The internal command generation circuit 220 may generate the phase detection signal ( Figure 5 PD) is sequentially latched in multiple pipeline latches ( Fig.12 The internal command generation circuit 220 can be based on the phase detection signal ( Figure 5 PD in the memory circuit 240 to compensate for the generation timing of the internal command ICMD. The first to fourth delay signals LTC<1:4> may be set as signals for setting a write delay, that is, the time taken to input the first data to the Nth data DATA<1:N> from the input timing of the command CMD after the write operation starts. The first to fourth delay signals LTC<1:4> may be set as signals generated from the mode register set MRS included in the semiconductor device 20. The internal command ICMD may be set as a signal for performing a write operation for storing the first data to the Nth data DATA<1:N> in the memory circuit 240. According to one embodiment, the internal command ICMD has been set as a signal for performing a write operation, but may be set as a signal for performing a read operation of outputting the first data to the Nth data DATA<1:N> already stored in the memory circuit 240. According to one embodiment, the internal command ICMD may be set as a signal for performing various operations, such as a precharge operation and a refresh operation of the semiconductor device 20.

[0040] The internal address generation circuit 230 may generate the first internal address to the Mth internal address IADD<1:M> based on the first address to the Lth address ADD<1:L> in synchronization with the clock CLK. The internal address generation circuit 230 may generate the first internal address to the Mth internal address IADD<1:M> by decoding the first address to the Lth address ADD<1:L> in synchronization with the clock CLK. According to one embodiment, the number of bits of the first address to the Lth address ADD<1:L> may be set to various numbers of bits. The number of bits "L" of the first address to the Lth address ADD<1:L> may be set to a positive integer. According to one embodiment, the number of bits of the first internal address to the Mth internal address IADD<1:M> may be set to various numbers of bits. The number of bits "M" of the first internal address to the Mth internal address IADD<1:M> may be set to a positive integer.

[0041] The memory circuit 240 may include a plurality of memory cells MC. When the internal command ICMD is generated after the start of a write operation, the memory circuit 240 may store the first to Nth data DATA<1:N> in the memory cells MC selected by the first to Mth internal addresses IADD<1:M>. When the internal command ICMD is generated after the start of a read operation, the memory circuit 240 according to one embodiment may output the first to Nth data DATA<1:N> that have been stored in the memory cells MC selected by the first to Mth internal addresses IADD<1:M>. The memory circuit 240 may be implemented by a common memory cell array including various internal circuits for inputting and outputting the first to Nth data DATA<1:N> after the start of a write operation and a read operation. The number of bits "N" of the first to Nth data DATA<1:N> may be set to a positive integer.

[0042] The semiconductor device 20 can generate a phase detection signal ( Figure 5 PD) is sequentially latched in multiple pipeline latches ( Fig.12 The semiconductor device 20 can detect the phase of the pipeline latch based on the phase detection signal ( Figure 5 The semiconductor device 20 may store the first to Nth data DATA<1:N> in the memory circuit 240 based on the internal command ICMD and the first to Lth addresses ADD<1:L> after the write operation starts. The semiconductor device 20 may output the stored first to Nth data DATA<1:N> based on the internal command ICMD and the first to Lth addresses ADD<1:L> after the read operation starts.

[0043] Figure 3 2 is a block diagram showing a configuration according to one embodiment of a frequency dividing circuit 210 included in a semiconductor device 20. The frequency dividing circuit 210 may include a first frequency-divided clock generating circuit (F / F) 211 and a second frequency-divided clock generating circuit (F / F) 212.

[0044] The first frequency-divided clock generation circuit 211 can be implemented by a trigger (F / F). The first frequency-divided clock generation circuit 211 can generate a first frequency-divided clock ICLK having a frequency of 1 / 2 of the clock CLK by dividing the frequency of the clock CLK. The first frequency-divided clock generation circuit 211 can latch the second frequency-divided clock OCLK for the logic low level interval of the clock CLK. The first frequency-divided clock generation circuit 211 can output the second frequency-divided clock OCLK that has been latched for a cycle interval of the clock CLK as the first frequency-divided clock ICLK. The first frequency-divided clock generation circuit 211 can generate a first frequency-divided clock ICLK including the following pulses: the pulse is generated by latching the second frequency-divided clock OCLK synchronously with the odd pulses of the clock CLK. The first frequency-divided clock generation circuit 211 can generate a first frequency-divided clock ICLK including a pulse having a pulse width of one cycle of the clock CLK.

[0045] The second frequency-divided clock generation circuit 212 can be implemented by a trigger (F / F). The second frequency-divided clock generation circuit 212 can generate a second frequency-divided clock OCLK having 1 / 2 the frequency of the clock CLK by dividing the frequency of the clock CLK. The second frequency-divided clock generation circuit 212 can latch the first frequency-divided clock ICLK for the logic low level interval of the clock CLK. The second frequency-divided clock generation circuit 212 can output the first frequency-divided clock ICLK that has been latched for one cycle interval of the clock CLK as the second frequency-divided clock OCLK. The second frequency-divided clock generation circuit 212 can generate a second frequency-divided clock OCLK including the following pulses: the pulse is generated by latching the first frequency-divided clock ICLK synchronously with the even pulses of the clock CLK. The second frequency-divided clock generation circuit 212 can generate a second frequency-divided clock OCLK including a pulse having a pulse width of one cycle of the clock CLK.

[0046] The following references Figure 4 The operation of the frequency dividing circuit 210 according to one embodiment of the present disclosure is described.

[0047] The first frequency-divided clock generating circuit 211 may latch the second frequency-divided clock OCLK for a logic low level interval of the clock CLK.

[0048] At timing T1, the first frequency-divided clock generation circuit 211 can generate the first pulse of the first frequency-divided clock ICLK by dividing the frequency of the clock CLK synchronously with the first pulse (first odd (ODD)) of the clock CLK. The first frequency-divided clock generation circuit 211 can output the latched second frequency-divided clock OCLK as the first pulse of the first frequency-divided clock ICLK during the pulse width of one cycle of the clock CLK. The first pulse (first odd) of the clock CLK can be set to the odd pulse of the clock CLK. The first pulse of the first frequency-divided clock ICLK can be generated from timing T1 to timing T3.

[0049] At timing T2 , the second frequency-divided clock generating circuit 212 may latch the first frequency-divided clock ICLK for a logic low level interval of the clock CLK.

[0050] At timing T3, the second frequency-divided clock generation circuit 212 can generate the first pulse of the second frequency-divided clock OCLK by dividing the frequency of the clock CLK synchronously with the second pulse (second even (EVEN)) of the clock CLK. The second frequency-divided clock generation circuit 212 can output the latched first frequency-divided clock ICLK as the first pulse of the second frequency-divided clock OCLK during the pulse width of one cycle of the clock CLK. The second pulse (second even) of the clock CLK can be set to the even pulse of the clock CLK. The first pulse of the second frequency-divided clock OCLK can be generated from timing T3 to timing T5.

[0051] At timing T4 , the first frequency-divided clock generating circuit 211 may latch the second frequency-divided clock OCLK for a logic low level interval of the clock CLK.

[0052] At timing T5, the first frequency-divided clock generation circuit 211 can generate a second pulse of the first frequency-divided clock ICLK by dividing the frequency of the clock CLK synchronously with the third pulse (third odd) of the clock CLK. The first frequency-divided clock generation circuit 211 can output the latched second frequency-divided clock OCLK as the second pulse of the first frequency-divided clock ICLK during the pulse width of one cycle of the clock CLK. The third pulse (third odd) of the clock CLK can be set to the odd pulse of the clock CLK. The second pulse of the first frequency-divided clock ICLK can be generated from timing T5 to timing T7.

[0053] At timing T6 , the second frequency-divided clock generating circuit 212 may latch the first frequency-divided clock ICLK for a logic low level interval of the clock CLK.

[0054] At timing T7, the second frequency-divided clock generation circuit 212 can generate a second pulse of the second frequency-divided clock OCLK by dividing the frequency of the clock CLK synchronously with the fourth pulse (fourth even) of the clock CLK. The second frequency-divided clock generation circuit 212 can output the latched first frequency-divided clock ICLK as the second pulse of the second frequency-divided clock OCLK during the pulse width of one cycle of the clock CLK. The fourth pulse (fourth even) of the clock CLK can be set to the even pulse of the clock CLK. The second pulse of the second frequency-divided clock OCLK can be generated from timing T7 to timing T8.

[0055] Figure 5 is a block diagram showing a configuration according to one embodiment of an internal command generation circuit 220 included in the semiconductor device 20. The internal command generation circuit 220 may include a phase detection circuit (PH DET) 310, a synthesized command generation circuit (SCMD GEN) 320, a shift circuit (SFT CT) 330, a selection signal generation circuit (SEL GEN) 340, and a command phase control circuit (CMD PH CTR) 350.

[0056] The phase detection circuit 310 can generate a phase detection signal PD and a first input command signal OCI by detecting the input timing of the command CMD in synchronization with the first divided clock ICLK and the second divided clock OCLK. The phase detection circuit 310 can generate a phase detection signal PD and a first input command signal OCI by latching the command CMD in synchronization with the first divided clock ICLK and the second divided clock OCLK. The phase detection circuit 310 can generate a phase detection signal PD by latching the command CMD in synchronization with the rising edge of the second divided clock OCLK. The phase detection circuit 310 can generate a phase detection signal PD that is enabled to a logic high level when the command CMD is input in synchronization with the rising edge of the second divided clock OCLK. The phase detection circuit 310 can generate a phase detection signal PD that is disabled to a logic low level when the command CMD is not input in synchronization with the rising edge of the second divided clock OCLK. The phase detection circuit 310 can generate a first input command signal OCI by latching the phase detection signal PD in synchronization with the rising edge of the first divided clock ICLK. The phase detection circuit 310 may generate a first input command signal OCI that is enabled to a logic high level when the phase detection signal PD is enabled in synchronization with a rising edge of the first divided clock ICLK. The phase detection circuit 310 may generate a first input command signal OCI that is disabled to a logic low level when the phase detection signal PD is disabled in synchronization with a rising edge of the first divided clock ICLK.

[0057] The synthesized command generation circuit 320 can generate a synthesized command SCMD by synthesizing the command CMD and the first input command signal OCI in synchronization with the first divided clock ICLK. The synthesized command generation circuit 320 can generate a synthesized command SCMD that is enabled to a logic high level when any one of the command CMD and the first input command signal OCI is enabled to a logic high level in synchronization with the rising edge of the first divided clock ICLK.

[0058] The shift circuit 330 may generate a shift signal SFT by shifting the synthesized command SCMD by a set interval in synchronization with the first divided clock ICLK. The shift circuit 330 may generate a shift signal SFT by shifting the synthesized command SCMD by a set interval based on the first to fourth delay signals LTC<1:4> in synchronization with the first divided clock ICLK. The set interval may be set as a write delay interval.

[0059] The selection signal generation circuit 340 may sequentially latch the phase detection signal PD in a plurality of pipe latches ( Fig.12 The selection signal generating circuit 340 may generate a selection signal SEL based on the phase detection signal PD that has been latched in the plurality of pipe latches in synchronization with the shift signal SFT.

[0060] The command phase control circuit 350 can generate the internal command ICMD by shifting the shift signal SFT in response to the selection signal SEL in synchronization with the clock CLK. When the selection signal SEL is disabled to a logic low level, the command phase control circuit 350 can generate the internal command ICMD based on the shift signal SFT in synchronization with the rising edge of the clock CLK. When the selection signal SEL is enabled to a logic high level, the command phase control circuit 350 can generate the internal command ICMD by shifting the shift signal SFT by one cycle of the clock CLK.

[0061] Figure 6 2 is a block diagram showing a configuration according to one embodiment of the phase detection circuit 310 included in the internal command generation circuit 220. The phase detection circuit 310 may include a first command input circuit (F / F) 311 and a second command input circuit (F / F) 312.

[0062] The first command input circuit 311 may be implemented by a flip-flop (F / F). The first command input circuit 311 may generate a phase detection signal PD by latching a command CMD in synchronization with a rising edge of the second frequency-divided clock OCLK. The first command input circuit 311 may generate a phase detection signal PD that is enabled to a logic high level when a command CMD having a logic high level is input in synchronization with a rising edge of the second frequency-divided clock OCLK. The first command input circuit 311 may generate a phase detection signal PD that is disabled to a logic low level when a command CMD having a logic low level is input in synchronization with a rising edge of the second frequency-divided clock OCLK.

[0063] The second command input circuit 312 may be implemented by a flip-flop (F / F). The second command input circuit 312 may generate a first input command signal OCI that is enabled to a logic high level when the phase detection signal PD is enabled to a logic high level in synchronization with a rising edge of the first frequency-divided clock ICLK. The second command input circuit 312 may generate a first input command signal OCI that is disabled to a logic low level when the phase detection signal PD is disabled to a logic low level in synchronization with a rising edge of the first frequency-divided clock ICLK.

[0064] Figure 7 is a diagram showing a configuration according to one embodiment of a synthesized command generation circuit 320 included in the internal command generation circuit 220. The synthesized command generation circuit 320 may include a third command input circuit (F / F) 321 and a signal synthesis circuit 322.

[0065] The third command input circuit 321 may be implemented by a flip-flop (F / F). The third command input circuit 321 may generate a second input command signal ICI that is enabled to a logic high level when a command CMD having a logic high level is input in synchronization with a rising edge of the first frequency-divided clock ICLK. The third command input circuit 321 may generate a second input command signal ICI that is disabled to a logic low level when a command CMD having a logic low level is input in synchronization with a rising edge of the first frequency-divided clock ICLK.

[0066] The signal synthesis circuit 322 can be connected through the OR gate 322 <1> The signal synthesis circuit 322 may generate a synthesized command SCMD by synthesizing the first input command signal OCI and the second input command signal ICI. The signal synthesis circuit 322 may generate a synthesized command SCMD that is enabled to a logic high level when any one of the first input command signal OCI and the second input command signal ICI is enabled to a logic high level.

[0067] Figure 8is a block diagram showing a configuration according to one embodiment of the shift circuit 330 included in the internal command generation circuit 220. The shift circuit 330 may include a transmission signal generation circuit 331 and a selection transmission circuit (SEL TR) 332.

[0068] The transmission signal generating circuit 331 may include first to sixth triggers 331_1, 331_2, 331_3, 331_4, 331_5, and 331_6. The first trigger 331_1 may output the synthesis command SCMD by shifting the synthesis command SCMD by one cycle interval of the first frequency-divided clock ICLK in synchronization with the rising edge of the first frequency-divided clock ICLK. The second trigger 331_2 may output the output signal of the first trigger 331_1 by shifting the output signal of the first trigger 331_1 by one cycle interval of the first frequency-divided clock ICLK in synchronization with the rising edge of the first frequency-divided clock ICLK. The third trigger 331_3 may generate the first transmission signal TS by shifting the output signal of the second trigger 331_2 by one cycle interval of the first frequency-divided clock ICLK in synchronization with the rising edge of the first frequency-divided clock ICLK. <1> The fourth trigger 331_4 can generate the first transmission signal TS in synchronization with the rising edge of the first frequency-divided clock ICLK. <1> The second transmission signal TS is generated by shifting the first frequency-divided clock ICLK by one cycle interval <2> The fifth trigger 331_5 can be synchronized with the rising edge of the first frequency-divided clock ICLK to generate the second transmission signal TS <2> The third transmission signal TS is generated by shifting the first frequency-divided clock ICLK by one cycle interval <3> The sixth trigger 331_6 can be synchronized with the rising edge of the first frequency-divided clock ICLK to generate the third transmission signal TS <3> The fourth transmission signal TS is generated by shifting the first frequency-divided clock ICLK by one cycle interval <4> According to one embodiment, the transmission signal generating circuit 331 has been implemented to include only the first to sixth flip-flops 331_1 , 331_2 , 331_3 , 331_4 , 331_5 , and 331_6 , but may be implemented to include various numbers of flip-flops.

[0069] The selection transmission circuit 332 may output a first transmission signal TS based on the first to fourth delay signals LTC<1:4>. <1> , the second transmission signal TS <2> , the third transmission signal TS <3> and the fourth transmission signal TS <4> As the shift signal SFT, any one of the first delay signal LTC <1> When enabled to a logic high level, the selection transmission circuit 332 may output a first transmission signal TS <1> As the shift signal SFT. <2> When enabled to a logic high level, the selection transmission circuit 332 may output a second transmission signal TS <2> As the shift signal SFT. <3> When enabled to a logic high level, the selection transmission circuit 332 may output a third transmission signal TS <3> As the shift signal SFT. <4> When enabled to a logic high level, the selection transmission circuit 332 may output a fourth transmission signal TS <4> As the shift signal SFT.

[0070] Fig. 9 is a block diagram showing a configuration according to one embodiment of a selection signal generation circuit 340 included in the internal command generation circuit 220. The selection signal generation circuit 340 may include an input control signal generation circuit (PIN GEN) 341, an output control signal generation circuit (POUT GEN) 342, and a pipe circuit (PIPE CT) 343.

[0071] The input control signal generation circuit 341 may generate the first to fourth input control signals PIN<1:4> that are sequentially enabled whenever the synthesized command SCMD is input. The input control signal generation circuit 341 may generate the first input control signal PIN<1:4> that is enabled when the synthesized command SCMD is input for the first time. <1> The input control signal generating circuit 341 may generate a second input control signal PIN which is enabled when the synthesized command SCMD is input for the second time. <2> The input control signal generating circuit 341 may generate a third input control signal PIN that is enabled when the synthesized command SCMD is input for the third time. <3> The input control signal generating circuit 341 may generate a fourth input control signal PIN that is enabled when the synthesis command SCMD is input for the fourth time. <4> The input control signal generating circuit 341 may generate a first input control signal PIN which is enabled when the synthesized command SCMD is input for the fifth time. <1> .

[0072] The output control signal generation circuit 342 may generate the first to fourth output control signals POUT<1:4> that are sequentially enabled whenever the shift signal SFT is input. The output control signal generation circuit 342 may generate the first output control signal POUT that is enabled when the shift signal SFT is first input. <1> The output control signal generating circuit 342 may generate a second output control signal POUT which is enabled when the shift signal SFT is input for the second time. <2> The output control signal generating circuit 342 may generate a third output control signal POUT that is enabled when the shift signal SFT is input for the third time. <3> The output control signal generating circuit 342 may generate a fourth output control signal POUT that is enabled when the shift signal SFT is input for the fourth time. <4> The output control signal generating circuit 342 may generate a first output control signal POUT which is enabled when the shift signal SFT is input for the fifth time. <1> .

[0073] The pipeline circuit 343 may include first to fourth pipeline latches ( Fig.12 343_1 to 343_4 in FIG. 343_2). When the first input control signal PIN <1> When enabled, the pipeline circuit 343 may latch the phase detection signal PD in the first pipeline latch ( Fig.12 When the first output control signal POUT <1> When enabled, the pipeline circuit 343 can output the data that has been latched in the first pipeline latch ( Fig.12 The phase detection signal PD in 343_1) is used as the selection signal SEL. When the second input control signal PIN <2> When enabled, the pipeline circuit 343 may latch the phase detection signal PD in the second pipeline latch ( Fig.12 343_2). When the second output control signal POUT <2> When enabled, the pipeline circuit 343 can output the data that has been latched in the second pipeline latch ( Fig.12 The phase detection signal PD in 343_2) is used as the selection signal SEL. When the third input control signal PIN <3> When enabled, the pipeline circuit 343 may latch the phase detection signal PD in the third pipeline latch ( Fig.12 When the third output control signal POUT <3> When enabled, the pipeline circuit 343 can output the output that has been latched in the third pipeline latch ( Fig.12 The phase detection signal PD in 343_3) is used as the selection signal SEL. When the fourth input control signal PIN <4> When enabled, the pipeline circuit 343 may latch the phase detection signal PD in the fourth pipeline latch ( Fig.12 When the fourth output control signal POUT <4> When enabled, the pipeline circuit 343 can output the output that has been latched in the fourth pipeline latch ( Fig.12 The phase detection signal PD in 343_4) is used as the selection signal SEL.

[0074] Fig.10 is a block diagram showing a configuration according to one embodiment of an input control signal generating circuit 341 included in a selection signal generating circuit 340. The input control signal generating circuit 341 may include seventh to tenth flip-flops (F / F) 341_1, 341_2, 341_3, and 341_4.

[0075] When the synthetic command SCMD having a logic high level is input, the seventh flip-flop 341_1 may be turned on based on the fourth input control signal PIN <4> Generate a first input control signal PIN <1> When the synthesized command SCMD having a logic high level is input, the seventh flip-flop 341_1 may output the fourth input control signal PIN <4> As the first input control signal PIN <1> .

[0076] When the synthetic command SCMD having a logic high level is input, the eighth flip-flop 341_2 may be turned on based on the first input control signal PIN <1> Generate a second input control signal PIN <2> When the synthesized command SCMD having a logic high level is input, the eighth flip-flop 341_2 may output the first input control signal PIN <1> As the second input control signal PIN <2> .

[0077] When the synthetic command SCMD having a logic high level is input, the ninth flip-flop 341_3 may be turned on based on the second input control signal PIN <2> Generate a third input control signal PIN <3> When the synthesized command SCMD having a logic high level is input, the ninth flip-flop 341_3 may output the second input control signal PIN <2> As the third input control signal PIN <3> .

[0078] When the synthetic command SCMD having a logic high level is input, the tenth flip-flop 341_4 may be turned on based on the third input control signal PIN <3> Generate a fourth input control signal PIN <4> When the synthesized command SCMD having a logic high level is input, the tenth flip-flop 341_4 may output the third input control signal PIN <3> As the fourth input control signal PIN <4> .

[0079] Fig.11 is a block diagram showing a configuration according to one embodiment of an output control signal generating circuit 342 included in a selection signal generating circuit 340. The output control signal generating circuit 342 may include eleventh to fourteenth flip-flops (F / F) 342_1, 342_2, 342_3, and 342_4.

[0080] When the shift signal SFT having a logic high level is input, the eleventh flip-flop 342_1 may output the fourth output control signal POUT based on the fourth output control signal POUT. <4> Generate a first output control signal POUT <1> When the shift signal SFT having a logic high level is input, the eleventh flip-flop 342_1 may output the fourth output control signal POUT <4> As the first output control signal POUT <1> .

[0081] When the shift signal SFT having a logic high level is input, the twelfth flip-flop 342_2 may output the first output control signal POUT based on the first output control signal POUT. <1> Generates the second output control signal POUT <2> When the shift signal SFT having a logic high level is input, the twelfth flip-flop 342_2 may output the first output control signal POUT <1> As the second output control signal POUT <2> .

[0082] When the shift signal SFT having a logic high level is input, the thirteenth flip-flop 342_3 may output the second output control signal POUT based on the second output control signal POUT. <2> Generate a third output control signal POUT <3> When the shift signal SFT having a logic high level is input, the thirteenth flip-flop 342_3 may output the second output control signal POUT <2> As the third output control signal POUT <3> .

[0083] When the shift signal SFT having a logic high level is input, the fourteenth flip-flop 342_4 may output the third output control signal POUT based on the third output control signal POUT. <3> Generate a fourth output control signal POUT <4> When the shift signal SFT having a logic high level is input, the fourteenth flip-flop 342_4 may output the third output control signal POUT <3> As the fourth output control signal POUT <4> .

[0084] Fig.12 is a block diagram showing a configuration according to one embodiment of a pipe circuit 343 included in a selection signal generating circuit 340. The pipe circuit 343 may include a first pipe latch 343_1, a second pipe latch 343_2, a third pipe latch 343_3, and a fourth pipe latch 343_4.

[0085] When the first input control signal PIN <1> When enabled, the first pipe latch 343_1 can latch the phase detection signal PD. <1> When enabled, the first pipe latch 343_1 may output the latched phase detection signal PD as the selection signal SEL.

[0086] When the second input control signal PIN <2> When enabled, the second pipe latch 343_2 can latch the phase detection signal PD. <2> When enabled, the second pipe latch 343_2 may output the latched phase detection signal PD as the selection signal SEL.

[0087] When the third input control signal PIN <3> When enabled, the third pipe latch 343_3 can latch the phase detection signal PD. <3> When enabled, the third pipe latch 343_3 may output the latched phase detection signal PD as the selection signal SEL.

[0088] When the fourth input control signal PIN <4> When enabled, the fourth pipe latch 343_4 can latch the phase detection signal PD. <4> When enabled, the fourth pipe latch 343_4 may output the latched phase detection signal PD as the selection signal SEL.

[0089] Fig.13 2 is a block diagram showing a configuration according to one embodiment of a command phase control circuit 350 included in the internal command generation circuit 220. The command phase control circuit 350 may include a transmission command generation circuit 351 and a command selection circuit (CMD SEL) 352.

[0090] The transfer command generation circuit 351 may include fifteenth to seventeenth flip-flops (F / F) 351_1 , 351_2 , and 351_3 .

[0091] The fifteenth flip-flop 351_1 may latch the shift signal SFT in synchronization with the rising edge of the clock CLK. The fifteenth flip-flop 351_1 may output the shift signal SFT latched by one cycle interval of the clock CLK as the first transfer command TCMD. <1> .

[0092] The sixteenth flip-flop 351_2 may latch the shift signal SFT in synchronization with the rising edge of the clock CLK. The sixteenth flip-flop 351_2 may output the shift signal SFT latched for one cycle interval of the clock CLK.

[0093] The seventeenth flip-flop 351_3 may latch the output signal of the sixteenth flip-flop 351_2 in synchronization with the rising edge of the clock CLK. The seventeenth flip-flop 351_3 may output the output signal of the sixteenth flip-flop 351_2 latched for one cycle interval of the clock CLK as the second transmission command TCMD. <2> .

[0094] The command selection circuit 352 may output a first transmission command TCMD in response to a selection signal SEL. <1> And the second transmission command TCMD <2> As the internal command ICMD. When the selection signal SEL is disabled to a logic low level, the command selection circuit 352 may output the first transmission command TCMD. <1> As the internal command ICMD. When the selection signal SEL is enabled to a logic high level, the command selection circuit 352 may output the second transmission command TCMD <2> As the internal command ICMD.

[0095] refer to Fig.14 and Fig.15 The write operation of the semiconductor system 1 according to one embodiment of the present disclosure is described, but the operation in which the command CMD is input to the fourth pulse (fourth even) of the clock CLK after being input to the first pulse (first odd) of the clock CLK is described below as an example.

[0096] At the timing T11 , the controller 10 may output the clock CLK that is periodically switched and the command CMD for performing a write operation.

[0097] At timing T12, the frequency division circuit 210 can generate a first frequency division clock ICLK including pulses by dividing the frequency of the clock CLK, the pulses having a 1 / 2 frequency of the clock CLK and being generated synchronously with the odd pulses of the clock CLK. The first frequency division clock ICLK can be periodically switched and generated at a 1 / 2 frequency of the clock CLK.

[0098] The third command input circuit 321 of the synthesized command generation circuit 320 may generate a second input command signal ICI that is enabled to a logic high level when a command CMD having a logic high level is input, in synchronization with a rising edge of the first frequency-divided clock ICLK.

[0099] The signal synthesizing circuit 322 of the synthesized command generating circuit 320 may generate the synthesized command SCMD enabled to a logic high level when the second input command signal ICI is enabled to a logic high level.

[0100] The input control signal generating circuit 341 of the selection signal generating circuit 340 may generate a first input control signal PIN that is enabled to a logic high level when the synthesized command SCMD is first input. <1> .

[0101] At timing T13, the frequency division circuit 210 can generate a second frequency division clock OCLK including pulses by dividing the frequency of the clock CLK, the pulses having 1 / 2 the frequency of the clock CLK and being generated synchronously with the even pulses of the clock CLK. The second frequency division clock OCLK can be periodically switched and generated at 1 / 2 the frequency of the clock CLK.

[0102] The phase detection circuit 310 may generate a phase detection signal PD having a logic low level by latching the command CMD in synchronization with the second frequency-divided clock OCLK.

[0103] When the first input control signal PIN <1> When enabled to a logic high level, the first pipe latch 343_1 of the pipe circuit 343 may latch the phase detection signal PD having a logic low level.

[0104] At the timing T14 , the controller 10 may output the clock CLK that is periodically switched and the command CMD for performing a write operation.

[0105] At the timing T15 , the frequency dividing circuit 210 may generate the second frequency-divided clock OCLK including pulses having ½ the frequency of the clock CLK and generated in synchronization with the even-numbered pulses of the clock CLK by dividing the frequency of the clock CLK.

[0106] The phase detection circuit 310 may generate a phase detection signal PD having a logic high level by latching the command CMD in synchronization with the second frequency-divided clock OCLK.

[0107] At the timing T16 , the phase detection circuit 310 may generate the first input command signal OCI by latching the phase detection signal PD in synchronization with the rising edge of the first frequency-divided clock ICLK.

[0108] The signal synthesizing circuit 322 of the synthesized command generating circuit 320 may generate a synthesized command SCMD enabled to a logic high level when the first input command signal OCI is enabled to a logic high level.

[0109] The input control signal generating circuit 341 of the selection signal generating circuit 340 may generate a second input control signal PIN enabled to a logic high level when the synthesized command SCMD is input for the second time. <2> .

[0110] When the second input control signal PIN <2> When enabled to a logic high level, the second pipe latch 343_2 of the pipe circuit 343 may latch the phase detection signal PD having a logic high level.

[0111] At the timing T17 , the shift circuit 330 may generate the shift signal SFT having a logic high level by shifting the synthesized command SCMD, which has been generated to have a logic high level at the timing T12 , by a write delay interval based on the first to fourth delay signals LTC<1:4>.

[0112] The output control signal generating circuit 342 of the selection signal generating circuit 340 may generate a first output control signal POUT that is enabled to a logic high level when the shift signal SFT is first input. <1> .

[0113] When the first output control signal POUT <1> When enabled to a logic high level, the first pipe latch 343_1 of the pipe circuit 343 may output the phase detection signal PD, which has been latched at a logic low level at the timing T13 , as the selection signal SEL.

[0114] The transmission command generation circuit 351 of the command phase control circuit 350 may latch the shift signal SFT having a logic high level in synchronization with the rising edge of the clock CLK, and may output the shift signal SFT having latched one cycle interval of the clock CLK as the first transmission command TCMD. <1> .

[0115] When the selection signal SEL is disabled to a logic low level, the command selection circuit 352 of the command phase control circuit 350 may output the first transmission command TCMD having a logic high level. <1> As the internal command ICMD.

[0116] When the internal command ICMD is generated after the write operation starts, the memory circuit 240 may store the first to Nth data DATA<1:N> in the memory cells MC selected by the first to Mth internal addresses IADD<1:M>.

[0117] At timing T18, the transmission command generation circuit 351 of the command phase control circuit 350 may output the shift signal SFT as the second transmission command TCMD by shifting the shift signal SFT of one cycle of the latched clock CLK. <2> .

[0118] At timing T19 , the shift circuit 330 may generate a shift signal SFT having a logic high level by shifting the synthesized command SCMD, which has been generated to have a logic high level at timing T16 , by a write delay interval based on the first to fourth delay signals LTC<1:4>.

[0119] The output control signal generating circuit 342 of the selection signal generating circuit 340 may generate a second output control signal POUT that is enabled to a logic high level when the shift signal SFT is input for the second time. <2> .

[0120] When the second output control signal POUT <2> When enabled to a logic high level, the second pipe latch 343_2 of the pipe circuit 343 may output the phase detection signal PD that has been latched at a logic high level at the timing T16 as the selection signal SEL.

[0121] The transmission command generation circuit 351 of the command phase control circuit 350 may latch the shift signal SFT having a logic high level in synchronization with the rising edge of the clock CLK, and may output the shift signal SFT having latched one cycle interval of the clock CLK as the first transmission command TCMD. <1> .

[0122] At timing T20, the transmission command generation circuit 351 of the command phase control circuit 350 may output the shift signal SFT as the second transmission command TCMD by shifting the shift signal SFT of one cycle of the latched clock CLK. <2> .

[0123] When the selection signal SEL is enabled to a logic high level, the command selection circuit 352 of the command phase control circuit 350 may output the second transmission command TCMD having a logic high level. <2> As the internal command ICMD.

[0124] When the internal command ICMD is generated after the write operation starts, the memory circuit 240 may store the first to Nth data DATA<1:N> in the memory cells MC selected by the first to Mth internal addresses IADD<1:M>.

[0125] The semiconductor system 1 according to one embodiment of the present disclosure may latch a phase detection signal PD generated by detecting the input timing of a command CMD input synchronously with a clock CLK in a pipe latch, and may compensate for the generation timing of an internal command ICMD generated from the command CMD based on the phase detection signal PD already latched in the pipe latch. In one embodiment, the semiconductor system 1 may reduce the area and current consumption of a shift circuit for shifting the internal command ICMD by latching the phase detection signal PD generated by detecting the input timing of the command CMD in the pipe latch, and compensating for the generation timing of the internal command ICMD by using one shift circuit based on the phase detection signal PD.

[0126] Fig.16 1 is a diagram showing a configuration of an electronic system 1000 according to an embodiment of the present disclosure. Fig.16 As shown, the electronic system 1000 may include a host 1100 and a semiconductor system 1200 .

[0127] The host 1100 and the semiconductor system 1200 may transmit signals to each other by using an interface protocol. The interface protocol used between the host 1100 and the semiconductor system 1200 may include a multimedia card (MMC), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a peripheral component interconnect-express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a serial attached SCSI (SAS), and a universal serial bus (USB).

[0128] The semiconductor system 1200 may include a controller 1300 and a semiconductor device 1400 (K: 1). The controller 1300 may control the semiconductor device 1400 (K: 1) so that the semiconductor device 1400 performs a write operation and a read operation respectively. Each of the semiconductor devices 1400 (K: 1) may latch a phase detection signal PD generated by detecting the input timing of the command CMD input synchronously with the clock CLK in a pipe latch, and may compensate for the generation timing of the internal command ICMD generated from the command CMD based on the phase detection signal PD already latched in the pipe latch. In one embodiment, each of the semiconductor devices 1400 (K: 1) may reduce the area and current consumption of a shift circuit for shifting the internal command ICMD by latching the phase detection signal PD generated by detecting the input timing of the command CMD in the pipe latch, and by using one shift circuit based on the phase detection signal PD to compensate for the generation timing of the internal command ICMD.

[0129] The controller 1300 may be implemented as Figure 1 The semiconductor devices 1400 (K:1) can each be implemented as Figure 1 The semiconductor device 20 is shown. According to one embodiment, the semiconductor devices 20 can each be implemented as one of the following: a dynamic random access memory (DRAM), a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and a ferroelectric random access memory (FRAM).

Claims

1. A semiconductor device, comprising: A frequency dividing circuit configured to receive a clock to generate a first frequency-divided clock and a second frequency-divided clock by dividing the frequency of the clock; as well as An internal command generation circuit is configured to receive a command in synchronization with the first frequency-divided clock and the second frequency-divided clock to generate an internal command based on the command received in synchronization with the first frequency-divided clock and the second frequency-divided clock, the internal command generation circuit is configured to latch a phase detection signal in a pipe latch, the phase detection signal is generated based on the timing when the command is received, and the internal command generation circuit is configured to compensate for the generation timing of the internal command based on the phase detection signal already latched in the pipe latch.

2. The semiconductor device according to claim 1, wherein the frequency dividing circuit generates the first frequency divided clock including pulses having a frequency of 1 / 2 of the clock and generated in synchronization with odd-numbered pulses of the clock, and The frequency dividing circuit generates the second frequency-divided clock including pulses having a frequency of 1 / 2 of the clock and generated in synchronization with even-numbered pulses of the clock. 3 . The semiconductor device according to claim 1 , wherein the frequency dividing circuit generates the first frequency-divided clock and the second frequency-divided clock having opposite phases by dividing the frequency of the clock.

4. The semiconductor device according to claim 1, wherein the internal command generation circuit comprises: a phase detection circuit configured to generate the phase detection signal and a first input command signal by latching the command in synchronization with the first frequency-divided clock and the second frequency-divided clock: a synthesized command generating circuit configured to generate a synthesized command by synthesizing the command and the first input command signal in synchronization with the first frequency-divided clock; a shift circuit configured to generate a shift signal by shifting the synthesized command by a set interval; a selection signal generating circuit configured to latch the phase detection signal in the pipe latch in synchronization with the synthesis command, and configured to generate a selection signal based on the phase detection signal already stored in the pipe latch in synchronization with the shift signal; as well as A command phase control circuit is configured to generate the internal command by shifting the shift signal in response to the selection signal in synchronization with the clock.

5. The semiconductor device according to claim 4, wherein the phase detection circuit comprises: a first command input circuit configured to generate the phase detection signal by latching the command in synchronization with the second frequency-divided clock; as well as The second command input circuit is configured to generate the first input command signal by latching the phase detection signal in synchronization with the first frequency-divided clock.

6. The semiconductor device according to claim 4, wherein the synthesized command generation circuit comprises: a third command input circuit configured to generate a second input command signal by latching the command in synchronization with the first frequency-divided clock; as well as The signal synthesis circuit is configured to generate the synthesis command by synthesizing the first input command signal and the second input command signal.

7. The semiconductor device according to claim 4, wherein the shift circuit comprises: a transmission signal generating circuit configured to generate a first transmission signal and a second transmission signal which are sequentially generated by shifting the synthesized command in synchronization with the first frequency-divided clock; as well as A selection transmission circuit is configured to output any one of the first transmission signal and the second transmission signal as the shift signal based on a first delay signal and a second delay signal, the first delay signal and the second delay signal including information on the set interval.

8. The semiconductor device according to claim 4, wherein the selection signal generating circuit comprises: an input control signal generating circuit configured to generate an input control signal enabled when the synthetic command is input; an output control signal generating circuit configured to generate an output control signal enabled when the shift signal is input; as well as The pipeline circuit is configured to latch the phase detection signal when the input control signal is generated, and is configured to generate the selection signal based on the latched phase detection signal when the output control signal is generated.

9. The semiconductor device according to claim 4, wherein the command phase control circuit comprises: a transfer command generating circuit configured to generate a first transfer command and a second transfer command which are sequentially generated by shifting the shift signal in synchronization with the clock; as well as The command selection circuit is configured to output any one of the first transfer command and the second transfer command as the internal command in response to the selection signal.

10. A semiconductor system comprising: a controller configured to output a clock that is periodically switched, and configured to output a command, an address, and data; as well as A semiconductor device configured to sequentially latch a phase detection signal in a plurality of pipe latches, the phase detection signal being generated by detecting an input timing of the command input in synchronization with the clock, the semiconductor device being configured to compensate for a generation timing of an internal command generated from the command based on the phase detection signal already latched in the plurality of pipe latches, and the semiconductor device being configured to store the data based on the internal command and the address.

11. The semiconductor system according to claim 10, wherein the semiconductor device comprises: A frequency dividing circuit is configured to generate a first frequency-divided clock and a second frequency-divided clock by dividing the frequency of the clock; an internal command generation circuit configured to generate the internal command based on the command in synchronization with the first frequency-divided clock and the second frequency-divided clock, configured to sequentially latch the phase detection signal generated based on the input timing of the command synchronized with the pulse of the clock in the plurality of pipe latches, and configured to compensate the generation timing of the internal command based on the phase detection signal already latched in the plurality of pipe latches; an internal address generation circuit configured to generate an internal address by decoding the address in synchronization with the clock; as well as The memory circuit is configured to store the data based on the internal address when the internal command is generated.

12. The semiconductor system according to claim 11, wherein the frequency dividing circuit generates the first frequency divided clock including pulses having a frequency of 1 / 2 of the clock and generated in synchronization with odd-numbered pulses of the clock, and The frequency dividing circuit generates the second frequency-divided clock including pulses having a frequency of 1 / 2 of the clock and generated in synchronization with even-numbered pulses of the clock. 13 . The semiconductor system according to claim 11 , wherein the frequency dividing circuit generates the first frequency-divided clock and the second frequency-divided clock having opposite phases by dividing the frequency of the clock.

14. The semiconductor system of claim 11, wherein: The internal command generation circuit latches the phase detection signal generated when the command is input in synchronization with the first pulse of the clock in a first pipe latch, and The internal command generation circuit latches the phase detection signal generated when the command is input in synchronization with a second pulse of the clock in a second pipe latch. 15 . The semiconductor system according to claim 14 , wherein the second pulse of the clock is a pulse generated after the first pulse of the clock is generated. 16 . The semiconductor system according to claim 14 , wherein the phase detection signal is a signal which is disabled in synchronization with the first frequency-divided clock when the command is input, and is enabled in synchronization with the second frequency-divided clock when the command is input.

17. The semiconductor system according to claim 11, wherein the internal command generation circuit comprises: a phase detection circuit configured to generate the phase detection signal and a first input command signal by latching the command in synchronization with the first frequency-divided clock and the second frequency-divided clock: a synthesized command generating circuit configured to generate a synthesized command by synthesizing the command and the first input command signal in synchronization with the first frequency-divided clock; a shift circuit configured to generate a shift signal by shifting the synthesized command by a set interval; a selection signal generating circuit configured to sequentially latch the phase detection signal in the plurality of pipe latches in synchronization with the synthesis command, and configured to generate a selection signal based on the phase detection signal already latched in the plurality of pipe latches in synchronization with the shift signal; as well as A command phase control circuit is configured to generate the internal command by shifting the shift signal in response to the selection signal in synchronization with the clock.

18. The semiconductor system according to claim 17, wherein the phase detection circuit comprises: a first command input circuit configured to generate the phase detection signal by latching the command in synchronization with the second frequency-divided clock; as well as The second command input circuit is configured to generate the first input command signal by latching the phase detection signal in synchronization with the first frequency-divided clock.

19. The semiconductor system according to claim 17, wherein the synthesized command generation circuit comprises: a third command input circuit configured to generate a second input command signal by latching the command in synchronization with the first frequency-divided clock; as well as The signal synthesis circuit is configured to generate the synthesis command by synthesizing the first input command signal and the second input command signal.

20. The semiconductor system according to claim 17, wherein the shift circuit comprises: a transmission signal generating circuit configured to generate a first transmission signal and a second transmission signal which are sequentially generated by shifting the synthesized command in synchronization with the first frequency-divided clock; as well as A selection transmission circuit is configured to output any one of the first transmission signal and the second transmission signal as the shift signal based on a first delay signal and a second delay signal, the first delay signal and the second delay signal including information on the set interval.

21. The semiconductor system according to claim 17, wherein the selection signal generating circuit comprises: an input control signal generating circuit configured to generate a first input control signal and a second input control signal which are sequentially enabled whenever the synthetic command is input; an output control signal generating circuit configured to generate a first output control signal and a second output control signal which are sequentially enabled whenever the shift signal is input; as well as A pipeline circuit is configured to latch the phase detection signal when the first input control signal and the second input control signal are generated, and is configured to output the latched phase detection signal as the selection signal when the first output control signal and the second output control signal are generated.

22. The semiconductor system of claim 21 , wherein the pipeline circuit comprises: a first pipe latch configured to latch the phase detection signal when the first input control signal is generated, and configured to output the latched phase detection signal as the selection signal when the first output control signal is generated; as well as The second pipe latch is configured to latch the phase detection signal when the second input control signal is generated, and is configured to output the latched phase detection signal as the selection signal when the second output control signal is generated.

23. The semiconductor system according to claim 17, wherein the command phase control circuit comprises: a transfer command generating circuit configured to generate a first transfer command and a second transfer command which are sequentially generated by shifting the shift signal in synchronization with the clock; as well as The command selection circuit is configured to output any one of the first transfer command and the second transfer command as the internal command in response to the selection signal.

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