Operation method of memory, memory and memory system

Abstract

The invention provides an operation method of a memory and the memory, and the operation method comprises the steps: carrying out first-direction bias voltage on two electrodes of a memory unit formed by connecting a first sub-memory unit and a second sub-memory unit in series in a memory array, so as to obtain a first threshold state or a second threshold state for the memory unit; and second-direction bias voltage is carried out on the two poles of the storage unit so as to obtain a third threshold state or a fourth threshold state for the storage unit, and the positive and negative directions of the first-direction bias voltage and the second-direction bias voltage on the two poles are opposite. According to the operation method of the memory, the memory and the memory system provided by the invention, not only can multi-level storage be achieved, but also the margin of the reading window can be increased, and better control consistency can be achieved, so that the problem of the margin of the reading window during multi-level storage can be solved.

Description

Technical Field

[0001] The present application generally relates to the field of electronic devices, and more particularly to a memory operating method, a memory and a storage system. Background Art

[0002] Memory is the foundation of information technology. As a candidate for the next generation of non-volatile semiconductor memory, phase change random access memory (PCM) has attracted widespread attention, especially 3D PCM, due to its advantages such as high-speed reading, high erasable times, non-volatility, small component size, low power consumption, and resistance to strong vibration and radiation.

[0003] However, with the increasing demand for storage capacity, multi-level storage of each storage unit has become a trend, but how to make the multi-level storage of phase change memory have sufficient read window margin (RWM) has always been a problem. Although the industry has remedies for this problem from many aspects, it has not yet been well solved. Summary of the invention

[0004] The purpose of the present application is to provide a memory operation method, a memory and a storage system to solve the read window margin problem in multi-level storage.

[0005] In a first aspect, the present application provides a memory operation method, the operation method comprising:

[0006] Applying a first direction bias to two electrodes of a memory cell formed by connecting a first sub-memory cell and a second sub-memory cell in series in a memory array, so as to obtain a first threshold state or a second threshold state for the memory cell; and

[0007] A second direction bias is applied to the two poles of the memory cell to obtain a third threshold state or a fourth threshold state of the memory cell, and the first direction bias and the second direction bias are opposite in positive and negative directions of the two poles.

[0008] Optionally, the operating method includes using a SOM memory device as the first sub-storage unit, and using a PCM memory device as the second sub-storage unit.

[0009] The step of performing a first direction bias comprises:

[0010] Applying a first bias voltage in a first direction to the memory cell to generate a 1-1-1 threshold voltage in the first sub-memory cell; and

[0011] Applying a second bias voltage in a first direction to the memory cell to generate a 1-2-1 threshold voltage or a 1-2-0 threshold voltage in the second sub-memory cell;

[0012] The 1-1-1th threshold voltage and the 1-2-1th threshold voltage constitute the first threshold state, and the 1-1-1th threshold voltage and the 1-2-0th threshold voltage constitute the second threshold state.

[0013] Optionally, the step of performing a second direction bias comprises:

[0014] Applying a first bias voltage in a second direction to the memory cell to generate a 2-1-0 threshold voltage in the first sub-memory cell; and

[0015] Applying a second bias voltage in a second direction to the memory cell to generate a 2-2-1 threshold voltage or a 2-2-0 threshold voltage in the second sub-memory cell;

[0016] The 2-1-0 threshold voltage and the 2-2-1 threshold voltage constitute the third threshold state, and the 2-1-0 threshold voltage and the 2-2-0 threshold voltage constitute the fourth threshold state.

[0017] Optionally, the step of applying the second bias voltage in the first direction includes:

[0018] Applying a first direction set bias to the memory cell to generate the 1-2-1th threshold voltage in the second sub-memory cell; or

[0019] A first direction reset bias is applied to the memory cell to generate the 1-2-0 threshold voltage in the second sub-memory cell.

[0020] Optionally, the step of applying a second bias in a second direction includes:

[0021] Applying a second direction set bias to the memory cell to generate the 2-2-1th threshold voltage in the second sub-memory cell; or

[0022] A second direction reset bias is applied to the memory cell to generate the 2-2-0 threshold voltage in the second sub-memory cell.

[0023] Optionally, the operation method further includes:

[0024] The 1-2-1th threshold voltage and the 2-2-1th threshold voltage are at the same threshold level, and the 1-2-0th threshold voltage and the 2-2-0th threshold voltage are at the same threshold level; and

[0025] The 1-1-1 threshold voltage is a set threshold voltage, the 1-2-1 threshold voltage is a set threshold voltage, the 1-2-0 threshold voltage is a reset threshold voltage, the 2-1-0 threshold voltage is a reset threshold voltage, the 2-2-1 threshold voltage is a set threshold voltage, and the 2-2-0 threshold voltage is a reset threshold voltage.

[0026] Optionally, the step of applying a first direction bias comprises: applying a first direction single bias to the memory cell to obtain a first threshold state or a second threshold state for the memory cell, and the step of applying a first direction single bias comprises:

[0027] Applying a first direction set bias to the memory cell to generate a 3-1-1th threshold voltage in the first sub-memory cell and a 3-2-1th threshold voltage in the second memory cell; or

[0028] Applying a first direction reset bias to the memory cell to generate a 3-1-1 threshold voltage in the first sub-memory cell and a 3-2-0 threshold voltage in the second memory cell;

[0029] Among them, the 3-1-1th threshold voltage and the 3-2-1th threshold voltage constitute the first threshold state, and the 3-1-1th threshold voltage and the 3-2-0th threshold voltage constitute the second threshold state.

[0030] Optionally, the step of applying the second direction bias includes: applying a second direction single bias to the memory cell to obtain a third threshold state or a fourth threshold state for the memory cell, and the step of applying the second direction single bias includes:

[0031] Applying a second direction set bias to the memory cell to generate a 4-1-0 threshold voltage in the first sub-memory cell and a 4-2-1 threshold voltage in the second memory cell; or

[0032] A second direction reset bias is applied to the memory cell to generate a 4-1-0 threshold voltage in the first sub-memory cell and a 4-2-0 threshold voltage in the second memory cell; the 4-1-0 threshold voltage and the 4-2-1 threshold voltage constitute the third threshold state, and the 4-1-0 threshold voltage and the 4-2-0 threshold voltage constitute the fourth threshold state.

[0033] Optionally, the operation method further includes:

[0034] The 3-2-1th threshold voltage and the 4-2-1th threshold voltage are at the same threshold level, and the 3-2-0th threshold voltage and the 4-2-0th threshold voltage are at the same threshold level; and

[0035] The 3-1-1 threshold voltage is set as the threshold voltage, the 3-2-1 threshold voltage is set as the threshold voltage, the 3-2-0 threshold voltage is reset as the threshold voltage, the 4-1-0 threshold voltage is reset as the threshold voltage, the 4-2-1 threshold voltage is set as the threshold voltage, and the 4-2-0 threshold voltage is reset as the threshold voltage.

[0036] In a second aspect, the present application provides a memory, the memory comprising:

[0037] A memory array, the memory array comprising memory cells arranged in a matrix of multiple rows and columns, the two poles of the memory cells being connected to a word line and a bit line respectively, and one of the memory cells comprising a first sub-memory cell and a second sub-memory cell connected in series between the two poles;

[0038] a peripheral circuit configured to bias two electrodes of the memory cell in a first direction so as to obtain a first threshold state or a second threshold state for the memory cell; and

[0039] A second direction bias is applied to the two poles of the memory cell to obtain a third threshold state or a fourth threshold state of the memory cell, and the first direction bias and the second direction bias are opposite in positive and negative directions of the two poles.

[0040] Optionally, the first sub-storage unit includes a SOM storage device, and the second sub-storage unit includes a PCM storage device.

[0041] Optionally, the peripheral circuit includes a word line driver, and the word line driver is used to apply a first bias voltage in a first direction to the memory cell to generate a 1-1-1 threshold voltage in the first sub-memory cell; and

[0042] Applying a second bias voltage in a first direction to the memory cell to generate a 1-2-1 threshold voltage or a 1-2-0 threshold voltage in the second sub-memory cell;

[0043] The 1-1-1th threshold voltage and the 1-2-1th threshold voltage constitute the first threshold state, and the 1-1-1th threshold voltage and the 1-2-0th threshold voltage constitute the second threshold state.

[0044] Optionally, the peripheral circuit further includes a bit line driver, the bit line driver being used to apply a first bias voltage in a second direction to the memory cell, so as to generate a 2-1-0 threshold voltage in the first sub-memory cell; and

[0045] Applying a second bias voltage in a second direction to the memory cell to generate a 2-2-1 threshold voltage or a 2-2-0 threshold voltage in the second sub-memory cell;

[0046] The 2-1-0 threshold voltage and the 2-2-1 threshold voltage constitute the third threshold state, and the 2-1-0 threshold voltage and the 2-2-0 threshold voltage constitute the fourth threshold state.

[0047] Optionally, the first direction second bias includes a first direction set bias or a first direction reset bias, and the second direction second bias includes a second direction set bias or a second direction reset bias.

[0048] Optionally, the 1-1-1 threshold voltage is a set threshold voltage, the 1-2-1 threshold voltage is a set threshold voltage, the 1-2-0 threshold voltage is a reset threshold voltage, the 2-1-0 threshold voltage is a reset threshold voltage, the 2-2-1 threshold voltage is a set threshold voltage, and the 2-2-0 threshold voltage is a reset threshold voltage.

[0049] Optionally, the peripheral circuit includes a word line driver, the word line driver is used to apply a single bias voltage in a first direction to the memory cell to obtain a first threshold state or a second threshold state for the memory cell, and the single bias voltage in the first direction includes:

[0050] A first direction setting bias is applied to the memory cell to generate a 3-1-1th threshold voltage in the first sub-memory cell and a 3-2-1th threshold voltage in the second sub-memory cell; or

[0051] A first direction reset bias is applied to the memory cell to generate a 3-1-1 threshold voltage in the first sub-memory cell and a 3-2-0 threshold voltage in the second sub-memory cell;

[0052] Among them, the 3-1-1 threshold voltage and the 3-2-1 threshold voltage constitute the first threshold state, and the 3-1-1 threshold voltage and the 3-2-0 threshold voltage constitute the second threshold state.

[0053] Optionally, the peripheral circuit further includes a bit line driver, the bit line driver is used to apply a second direction single bias to the memory cell to obtain a third threshold state or a fourth threshold state for the memory cell, and the second direction single bias includes:

[0054] A second direction bias is set to generate a 4-1-0 threshold voltage in the first sub-memory unit and a 4-2-1 threshold voltage in the second sub-memory unit; or

[0055] A second direction reset bias is provided to generate a 4-1-0 threshold voltage in the first sub-memory unit and a 4-2-0 threshold voltage in the second sub-memory unit;

[0056] The 4-1-0 threshold voltage and the 4-2-1 threshold voltage constitute the third threshold state, and the 4-1-0 threshold voltage and the 4-2-0 threshold voltage constitute the fourth threshold state.

[0057] Optionally, the 3-1-1th threshold voltage is a set threshold voltage, the 3-2-1th threshold voltage is a set threshold voltage, the 3-2-0th threshold voltage is a reset threshold voltage, the 4-1-0th threshold voltage is a reset threshold voltage, the 4-2-1th threshold voltage is a set threshold voltage, and the 4-2-0th threshold voltage is a reset threshold voltage.

[0058] In a third aspect, the present application provides a storage system, comprising: the memory as described above; and a controller, wherein the controller is electrically connected to the memory and is used to control the memory.

[0059] Through the memory operation method, memory and storage system provided in the present application, not only can multi-level storage be achieved, but also the read window margin can be increased, and better control uniformity can be achieved, thereby solving the read window margin problem in multi-level storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0061] Figure 1 is a functional module block diagram of a memory provided according to some embodiments of the present application;

[0062] Figure 2 is a schematic diagram of a storage array circuit of a memory provided according to some embodiments of the present application;

[0063] Figure 3 This is the structural intention of the phase change memory unit provided in some embodiments of the present application;

[0064] FIG. 4( a ) is a schematic diagram of the set and reset operations of a phase change memory cell provided in some embodiments of the present application;

[0065] FIG4( b ) is a schematic diagram of the operation of a bidirectional threshold switch provided in some embodiments of the present application;

[0066] FIG4( c ) is a schematic diagram of the operation of only a selector storage cell provided by some embodiments of the present application;

[0067] Figure 5 A flowchart of the operation method provided for some embodiments of the present application;

[0068] Figure 6 It is a schematic diagram of establishing the threshold voltage of multi-level storage provided by some embodiments of the present application;

[0069] Figure 7 is a schematic diagram of operating bias provided by some embodiments of the present application;

[0070] Figure 8 It is a schematic diagram of establishing a combination of threshold voltages for multi-level storage provided by some embodiments of the present application;

[0071] Fig. 9 is another operating bias schematic diagram provided by some embodiments of the present application;

[0072] Fig.10 is another schematic diagram of establishing a threshold voltage combination for multi-level storage provided by some embodiments of the present application;

[0073] Fig.11 It is a functional schematic block diagram of a storage system provided in some embodiments of the present application. DETAILED DESCRIPTION

[0074] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0075] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present application.

[0076] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0077] As used herein, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and a contact layer and one or more dielectric layers.

[0078] It should be noted that the illustrations provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0079] This article uses Cartesian coordinates to represent directions, with the substrate as the reference, "Z" represents the first direction, which is the direction perpendicular to the substrate; "X" represents the second direction parallel to the substrate; "Y" represents the third direction parallel to the substrate and perpendicular to X.

[0080] First, please refer to Figure 1 , Figure 1 The memory 200 is a functional schematic block diagram of a memory provided according to some embodiments of the present application. The memory 200 mainly includes a memory array 10 and a peripheral circuit 20 connected to and controlling the memory array 10 .

[0081] like Figure 1 As shown, the peripheral circuit 20 is connected to the memory array 10, and the peripheral circuit 20 generally includes at least a row decoder 240, a word line voltage generator 211, a word line driver 212, a column decoder 250, a bit line driver 251, a bit line voltage generator 271, a reference current generator 261, a sensitive amplifier current comparator 262, and a logic control module 230 connected to the aforementioned devices for receiving operation instructions and controlling the aforementioned devices.

[0082] The row decoder 240 receives a row address signal from a bus (not shown) and decodes the row address signal to select an addressed word line.

[0083] The word line driver 212 is connected to the plurality of word lines WL<0:m>, the word line voltage generator 211 and the row decoder 240. The word line driver 212 receives a row address selection signal and a word line driving voltage, and outputs the word line driving voltage to at least one word line WL<0:m> among the plurality of word lines WL<0:m> according to the row address selection signal. <m>At least one row of connected storage cells.

[0084] The bit line driver 251, the bit line voltage generator 271 and the column decoder 250 belong to the column driving circuit and are as shown in FIG. Figure 1 The bit line voltage generator 271 and the column decoder 250 are connected to the logic control module 230 to be controlled by the logic control module 230 .

[0085] The column decoder 250 receives the column address signal and decodes the column address signal to select the addressing bit line connected to the target memory cell. The bit line voltage generator 271 generates the clamping voltage required for each selected bit line and outputs the set clamping voltage to each corresponding selected bit line.

[0086] The bit line driver 251 is connected to a plurality of bit lines, a bit line voltage generator 271 and a column decoder 250. The bit line driver 251 receives a bit line voltage and a column address selection signal, and outputs a set clamped bit line voltage to at least one bit line BL<0:n> among the plurality of bit lines BL<0:n> according to the column address selection signal. <n>At least one column of connected storage cells.

[0087] The peripheral circuit 20 further includes a sensitive amplifier current comparator 262, a reference current generator 261, a data latch (not shown), etc. The sensitive amplifier current comparator 262 is connected to the reference current generator 261 and a plurality of bit lines BL<0:n> and is connected to the data latch 223. The sensitive amplifier current comparator 262 is used to compare the read current with the reference current generated by the reference current generator 261 after receiving the read current, determine the data stored in the selected storage unit, and then store the data in the data latch 280, and output it to the data bus through the input / output interface 290 together with the data read from other bit lines.

[0088] Based on the structural design of the peripheral circuit 20 of the above-mentioned memory, the operation on the memory may include an erase operation, a read operation and a program operation, or a set and reset operation.

[0089] Please refer to Figure 2 As shown, Figure 2 The circuit diagram is an example of a memory array 10 as a memory provided according to some embodiments of the present application. The memory array 10 includes a plurality of memory cells 11 arranged in a multi-row and multi-column array, and word lines WLn and bit lines BLn respectively connecting the plurality of memory cells 11 in the plurality of rows and columns. Each row of memory cells includes a plurality of memory cells 11 arranged along a row direction X. Each column of memory cells includes a plurality of memory cells 11 arranged along a column direction (i.e., a second direction Y). For example, Figure 2 Only the memory cells of three rows WLn-1 to WLn+1 and three columns BLn-1 to BLn+1 are shown. In practice, the number of rows and columns of memory cells included in the memory depends on its storage capacity. Figure 2 The memory cell exemplified is a phase change memory cell 11, which includes an Ovonic Threshold Switch (OTS) 111 and a PCM storage cell 112 connected in series between a word line WLn and a bit line BLn. The Ovonic Threshold Switch (OTS) 111 and the PCM storage cell 112 are both made of phase change materials. However, in some technologies, the phase change storage cell 112 is used as a threshold setting location for data storage. Therefore, in this embodiment, the two phase change materials in the memory cell 11 are first referred to as the Ovonic Threshold Switch (OTS) 111 and the PCM storage cell 112, respectively.

[0090] It should be understood that the memory cells in the memory array may be memory cells of various types of structures, such as floating gate memory cells, nitride layer structure (ONO) memory cells, resistive memory cells (RRAM), phase change structure memory cells (PCM / PCRAM / SOM), etc. The present application does not limit this, but the present application is particularly suitable for phase change structure memory cells. Therefore, the phase change structure memory cell PCM will be used as an example for illustration below, but it should be understood that it is not limited to this.

[0091] Figure 3 A schematic diagram of a storage unit provided in some embodiments of the present application. Figure 3 As shown, the structure of the phase change memory cell provided in some embodiments of the present application includes: a top electrode 11a and a bottom electrode 11b respectively connected to the word line WLn and the bit line BLn, and a phase change memory cell 112 located between the top electrode 11a and the bottom electrode 11b, an intermediate electrode 11c, and a bidirectional threshold switch (OTS) 111. It should be understood that in some embodiments, the intermediate electrode 11c may not be provided, so the present application is not limited to the structure disclosed here.

[0092] The phase change storage cell 112 includes one or more phase change materials such as materials based on germanium-antimony-tellurium (Ge-Sb-Te, GST), one example of which may be Ge2Sb2Te5. Currently, the phase change materials used by various institutions are chalcogenides (represented by Intel) and synthetic materials containing germanium, antimony, and tellurium (GST), such as Ge2Sb2Te5. Phase change materials can have a large resistivity contrast between different phases (such as crystalline phase and amorphous phase). For example, a phase change material can exhibit a relatively low resistivity in the crystalline phase, but a relatively high resistivity in the amorphous phase, and the resistivity of the phase change material in the amorphous phase can be hundreds to thousands of times higher than the resistivity in the crystalline phase. When heated, the phase change material can switch between different phases to achieve the writing of information (data) (including setting and resetting). In this embodiment, the electrodes 11a and 11c can heat the phase change memory cell 112 via the OTS 111 to change the phase of the heated region 112f in the phase change memory cell 112, thereby reducing the resistance of the phase change memory cell 112. In some embodiments, a heater (not shown) can also be added between the phase change memory cell 112 and the middle electrode 11c.

[0093] The top electrode 11 a and the bottom electrode 11 b are arranged opposite to each other, and their positions can be interchanged and overlapped with the outer bit line BLn and word line WLn, thereby forming a 3D phase change memory.

[0094] FIG4(a) is a bias diagram of the reset operation (reset) and the set operation (set) of the PCM storage cell provided in some embodiments of the present application, that is, it shows the working principle and operation bias diagram of the phase change storage cell 112. The basic storage principle of the phase change storage cell 112 is to apply voltage or current pulse signals of different widths and heights to the phase change storage cell, so that the phase change material undergoes a physical phase change in the heated area 1121f, that is, a reversible phase change occurs between the crystalline state (low resistance state) and the amorphous state (high resistance state), thereby realizing the information writing operation, or the information writing, including writing 1 (set) or 0 (reset). The mutual conversion process includes two processes: the amorphization transition from the crystalline state to the amorphous state, and the crystallization transition from the amorphous state to the crystalline state, wherein the former is called the amorphization process and the latter is called the crystallization process. Then, the information is read out by measuring and comparing the resistance difference between the two physical phases. This non-destructive reading process can ensure that the information stored in the device unit is accurately read out. The resistivity difference between the crystalline and amorphous states of phase change materials is several orders of magnitude, which gives them a high noise tolerance, sufficient to distinguish between the "0" state and the "1" state.

[0095] FIG4(b) shows a graph of logarithmic current versus voltage for a bidirectional threshold switch (OTS) 111 as a fast return selector or access element. Starting from a high resistance (reset) state under a low electric field, the current in the bidirectional threshold switch (OTS) 111 increases by a very small current value as the voltage increases until it reaches a threshold voltage V TH OTS until.

[0096] After the rapid return point 210, as long as it is higher than the holding current I H OTS When a current of 210 flows through the OTS 111, a highly conductive dynamic ON state 215 is maintained in the OTS 111. This transient highly conductive state is electronic in origin and does not involve any phase change in the OTS 111.

[0097] When the threshold voltage V of the bidirectional threshold switch (OTS) 111 is exceeded TH OTS When the bidirectional threshold switch (OTS) 111 is switched from the cut-off (OFF) state to the ON state, and current flows through the phase change memory cell 112 connected in series with the bidirectional threshold switch (OTS) 111. In the ON state, as the current flowing through the bidirectional threshold switch (OTS) 111 increases, the voltage across the bidirectional threshold switch (OTS) 112 remains close to the holding voltage (V H OTS ).

[0098] The OTS 111 may be kept in the ON state until the current through the OTS 111 is lower than the holding current (I H OTS ). Below this value, the OTS 111 may return to a high-resistance, non-conductive OFF state until V TH OTS or I TH OTS Whenever it is guided, the OTS can be repeatedly and reversibly switched between the OFF state and the ON state, but it does not crystallize.

[0099] In further research of the present application, it is understood that the threshold voltage Vth in OTS111 is affected by many factors, such as device structure changes, amplitude of applied pulses, pulse width, ramp rate and relaxation time. In further research, it is found that when the OTS device is composed of a phase change material such as Ge-Te-As-Si, the threshold voltage Vth of OTS111 will be controlled by the polarity of the applied voltage and change, more specifically, the threshold voltage changes with the change of the polarity of the applied voltage. As shown in Figure 4 (c), the Vth value in the current operation is greatly affected by the polarity of the previous pulse, resulting in two relatively stable Vth levels, namely Vth1 and Vth2, in the same pulse direction. In this work, the negative polarity Vth difference (ΔVth = |Vth1-Vth2|) is 260mV, and the external resistance is increased, further enhancing the ΔVth (Figure 4 (c)) by about 1V, and the positive ΔVth becomes more obvious. By utilizing this stable ΔVth, which can last for at least 1000 seconds (~17 minutes), the OTS device can be used independently as a binary storage device. Therefore, OTS111 is also called a SOM memory cell (selector only memory cell) or a SSM memory cell (self-selecting memory).

[0100] Therefore, in further research of this application, the SOM memory cell formed by OTS111 is connected in series with the phase change memory cell (PCM memory cell) 112, and the performance of the 1S1R memory cell is enhanced by providing a dual SET state and a dual RESET state. Each memory state will have a significant difference. By operating with voltages of different polarities, the originally small read window margin RWM (0.85V) is effectively expanded to ~1.7 and ~1.4V. The 1S1R memory cell exhibits a fairly long retention time (up to 1 month @25°C) and a retention time of more than 10 8 In addition, the significant differences between the four threshold states indicate that multi-level storage capabilities with four storage states or even more resistance states can be achieved. In other words, the storage states can be doubled through polarity manipulation of OTS devices or SOM memory cells.

[0101] Therefore, according to some embodiments of the present application, an operation method of a memory is proposed, wherein the OTS 111 and the phase change memory cell 112 as the only selected memory cell (SOM) are respectively referred to as the first sub-memory cell 111 and the second sub-memory cell 112 in the memory cell 11. The operation method is as follows: Figure 5 Shown include:

[0102] Applying a first direction bias to the two electrodes of a memory cell 11 formed by connecting a first sub-memory cell 111 and a second sub-memory cell 112 in series in a memory array, so as to obtain a first threshold state or a second threshold state for the memory cell 11 (step S1); and

[0103] A second direction bias is applied to the two poles of the memory cell 11 to obtain a third threshold state or a fourth threshold state for the memory cell 11, wherein the first direction bias and the second direction bias are opposite in positive and negative directions at the two poles (step S2).

[0104] Specifically, the operation method includes, for example, using a SOM storage cell as the first sub-storage cell, and using a PCM storage cell as the second sub-storage cell. Moreover, the storage value of the first sub-storage cell 111 (i.e., the SOM cell) represents one bit (e.g., the lower bit) of the two-digit value, and the storage value of the second sub-storage cell 112 (i.e., the PCM cell) represents the second bit (e.g., the upper bit) of the two-digit value. Then, the storage value of the first sub-storage cell 111 has two states, and the storage value of the second sub-storage cell 112 also has two states. Under the combination of the two phases, it can be as follows Figure 6 As shown, the memory cell 11 can store four numerical states of 11, 10, 01, and 00 respectively through the first threshold voltage (threshold state), the second threshold voltage (threshold state), the third threshold voltage (threshold state), and the fourth threshold voltage (threshold state) of different threshold states, and the reading window margin (RWM) or the reading voltage is between the threshold voltages representing the numerical values, including V1 between the numerical values ​​11 and 10, V2 between the numerical values ​​10 and 01, and V3 between the numerical values ​​01 and 00. When the gaps between the threshold voltages of the threshold states are distributed wider, a larger RWM can be obtained.

[0105] It should be understood here that the first to fourth four numerical states under a general MLC (multi-level storage unit) may be 11, 10, 01, and 00 in sequence as described in the previous paragraph, but in some places, the numerical value 01 is also referred to as the second threshold state, and the numerical value 10 is referred to as the third threshold state. Therefore, which numerical value applies to the second threshold state and which numerical value applies to the third threshold state should be a variable matter, which is only an expedient way of expression, does not affect the essence of this application, and is not limited here. That is, the second threshold state and the third threshold state are only used to represent different states, but the same sequence number threshold state can represent different numerical values ​​in different places. In addition, it is also optional to represent the first bit (low bit) or the second bit (high bit) of a two-digit numerical value with the storage value of the first sub-storage unit 111 (i.e., SOM cell). Although the storage value of the second sub-storage unit 112 (i.e., PCM cell) is used as an example in the previous paragraph to represent the second bit (high bit) of a two-digit numerical value, it can also represent the first bit (low bit) of a two-digit numerical value, which is not limited here.

[0106] For example, if the set (value 1) threshold voltage of the first sub-storage cell (OTS / SOM) 111 is 4V, the reset (value 0) threshold voltage is 4.7V, and the set (value 1) threshold voltage of the second sub-storage cell (PCM cell) 112 is 0V, and the reset (value 0) threshold voltage is 1.5V, then in some embodiments, the first threshold state (threshold state / storage state) may be 4V (value 11), the second threshold state may be 5.5V (value 01), the third threshold state may be 4.7V (value 10), and the fourth threshold state may be 6.2V (value 00). However, in other embodiments, the first threshold state (threshold state / storage state) may be 4V (value 11), the second threshold state may be 4.7V (value 10), the third threshold state may be 5.5V (value 01), and the fourth threshold state may be 6.2V (value 00). This is briefly shown in Table 1 below.

[0107] state Threshold state (voltage) Vt Status Name 11 4V First threshold voltage (threshold state) 10 4.7V Second / third threshold voltage (threshold state) 01 5.5V Third / Second Threshold Voltage (Threshold State) 00 6.2V Fourth threshold voltage (threshold state)

[0108] Table 1

[0109] In detail, in one embodiment, the first threshold state of 4V can be formed by combining the set (1) threshold voltage of 4V of the first sub-storage unit 111 and the set (1) threshold voltage of 0V of the second sub-storage unit 112; the second threshold state of 5.5V can be formed by combining the set (1) threshold voltage of 4V of the first sub-storage unit 111 and the reset (0) threshold voltage of 1.5V of the second sub-storage unit 112; the third threshold state of 4.7V can be formed by combining the reset (0) threshold voltage of 4.7V of the first sub-storage unit 111 and the set (1) threshold voltage of 0V of the second sub-storage unit 112; the fourth threshold state of 6.2V can be formed by combining the reset (0) threshold voltage of 4.7V of the first sub-storage unit 111 and the reset (0) threshold voltage of 1.5V of the second sub-storage unit 112. This can be summarized as shown in Table 2 below.

[0110] state Threshold state Vt Status Name PCM Vt SOM Vt 11 4V First threshold voltage (threshold state) 0V 4V 10 4.7V Third threshold voltage (threshold state) 0V 4.7V 01 5.5V Second threshold voltage (threshold state) 1.5V 4V 00 6.2V Fourth threshold voltage (threshold state) 1.5V 4.7V

[0111] Table 2

[0112] Therefore, according to some embodiments of the present application, the step of performing a first direction bias includes:

[0113] Applying a first bias voltage in a first direction to the memory cell to generate a 1-1-1 threshold voltage in the first sub-memory cell; and

[0114] Applying a second bias voltage in a first direction to the memory cell to generate a 1-2-1 threshold voltage or a 1-2-0 threshold voltage in the second sub-memory cell;

[0115] The 1-1-1 threshold voltage respectively forms the first threshold state and the second threshold state with the 1-2-1 threshold voltage and the 1-2-0 threshold voltage.

[0116] In a further embodiment, the step of applying the second bias voltage in the first direction comprises:

[0117] Applying a first direction set bias to the memory cell to generate the 1-2-1th threshold voltage in the second sub-memory cell; or

[0118] A first direction reset bias is applied to the memory cell to generate the 1-2-0 threshold voltage in the second sub-memory cell.

[0119] Specifically, Figure 7 and Figure 8 As shown, the first direction bias is the bias applied from the word line WL, and the first direction first bias is the first direction set conduction bias V111 for the SOM storage cell 111 as the first sub-storage unit, which will generate a 1-1-1 threshold voltage Vth111 in the SOM storage cell 111 as the first sub-storage unit. According to the threshold example in Table 2 above, it is 4V. The 1-1-1 threshold voltage Vth111 corresponds to the low-order value in the two-digit value, that is, the low-order "1" in "11" and "01", which is a set value 1.

[0120] The first direction second bias is a first direction set or reset bias V121 or V120 for the PCM storage cell 112 as the second sub-storage unit. This will generate a 0V 1-2-1 threshold voltage Vth121 or a 1.5V 1-2-0 threshold voltage Vth120 in the PCM storage cell 112 as the second sub-storage unit according to the threshold example in Table 2 above. The 1-2-1 threshold voltage Vth121 corresponds to the high-order value in the two-digit value, that is, the high-order "1" in "11"; and the 1-2-0 threshold voltage Vth120 also corresponds to the high-order value in the two-digit value, but corresponds to the high-order "0" in "01".

[0121] Furthermore, the first direction second bias is applied after the first direction first bias in time. Through such bias operation, the first direction first bias V111 can be combined with the first direction second bias V121 or V120, that is, the threshold voltage Vth111 of 4V can be combined with the threshold voltage Vth121V of 0V or the threshold voltage Vth120V of 1.5V, to generate the first threshold state "11" (4V) or the second threshold state "01" (5.5V) shown in Table 2 above.

[0122] Similarly, according to some embodiments of the present application, the step of performing a second direction bias includes:

[0123] Applying a first bias voltage in a second direction to the memory cell to generate a 2-1-0 threshold voltage in the first sub-memory cell; and

[0124] Applying a second bias voltage in a second direction to the memory cell to generate a 2-2-1 threshold voltage or a 2-2-0 threshold voltage in the second sub-memory cell;

[0125] The 2-1-0 threshold voltage respectively forms the third threshold state and the fourth threshold state with the 2-2-1 threshold voltage and the 2-2-0 threshold voltage.

[0126] In a further embodiment, the step of applying a second bias in a second direction comprises:

[0127] Applying a second direction set bias to the memory cell to generate the 2-2-1th threshold voltage in the second sub-memory cell; or

[0128] A second direction reset bias is applied to the memory cell to generate the 2-2-0 threshold voltage in the second sub-memory cell.

[0129] Specifically, as Figure 7 and Figure 8 As shown, the second direction bias is the bias applied from the bit line BL, and the second direction first bias is the second direction reset conduction bias V210 for the SOM memory cell 111 as the first sub-memory unit, which will generate a 2-1-0 threshold voltage Vth210 in the SOM memory cell 111 as the first sub-memory unit. According to the threshold example in the previous Table 2, it is 4.7V. This 2-1-0 threshold voltage Vth210 corresponds to the low-order value in the two-digit value, that is, the low-order "0" in "10" and "00", which is a reset value 0.

[0130] The second bias in the second direction is a second direction set or reset bias V221 or V220 for the PCM memory cell 112 as the second sub-memory unit. This will generate a 0V 2-2-1 threshold voltage Vth221 or a 1.5V 2-2-0 threshold voltage Vth220 in the PCM memory cell 112 as the second sub-memory unit according to the threshold example in Table 2 above. The 2-2-1 threshold voltage Vth221 corresponds to the high-order value in the two-digit value, that is, the high-order "1" in "10"; and the 2-2-0 threshold voltage Vth220 also corresponds to the high-order value in the two-digit value, but corresponds to the high-order "0" in "00".

[0131] Furthermore, the second bias voltage V221 / V220 in the second direction is also applied after the first bias voltage V210 in the second direction. Through such bias operation, the combination of the first bias voltage V210 in the second direction and the second bias voltage V221 or V220 in the first direction can generate a threshold voltage Vth210 of 4.7V and a threshold voltage Vth221 of 0V or a threshold voltage Vth220 of 1.5V, as shown in FIG. Figure 8 As shown, the third threshold state "10" (4.7V) or the fourth threshold state "00" (6.2V) shown in the previous Table 2 is generated.

[0132] Through the above operation method, it can be understood that the application of the second bias in the first direction and the application of the second bias in the second direction are preferably to make the 1-2-1 threshold voltage Vth121 and the 2-2-1 threshold voltage Vth221 at the same threshold level, and to make the 1-2-0 threshold voltage Vth120 and the 2-2-0 threshold voltage Vth220 at the same threshold level. In this way, better RWM control can be achieved between the threshold states of the memory cell 11. Moreover, the 1-1-1 threshold voltage is a set threshold voltage, the 1-2-1 threshold voltage is a set threshold voltage, the 1-2-0 threshold voltage is a reset threshold voltage, the 2-1-0 threshold voltage is a reset threshold voltage, the 2-2-1 threshold voltage is a set threshold voltage, and the 2-2-0 threshold voltage is a reset threshold voltage.

[0133] Specifically, as shown in Table 2 above, the 1-2-1 threshold voltage Vth121 is a set threshold voltage of 0V, the 2-2-1 threshold voltage Vth221 is a set threshold voltage of 0V, the 1-2-0 threshold voltage Vth120 is a reset threshold voltage of 1.5V, and the 2-2-0 threshold voltage Vth220 is a reset threshold voltage of 1.5V. However, it should be understood that in the above embodiments, although the threshold voltages are described by taking the reset threshold voltage and the set threshold voltage as examples, they can also be set to, for example, half the reset threshold voltage, or 3 / 4 the reset threshold voltage, etc., which is not limited here, as long as it is sufficient to make a read window margin between the threshold voltages.

[0134] The following further describes some other embodiments according to the present application. Fig. 9 and Fig.10 As shown, when a bias is applied from a first direction, that is, a first direction single bias is applied from the word line WL to the memory cell 11, the memory cell 11 can obtain a first threshold state and a second threshold state. The first direction single bias can include a first direction set bias V31, or a first direction reset bias V30.

[0135] Since the SOM memory cell 111 of the first sub-memory unit and the PCM memory cell 112 of the second sub-memory unit are biased at the same time, by appropriately selecting the bias magnitude of the first direction set bias V31 or the first direction reset bias V30, when the first direction set bias V31 is applied, a 3-1-1 threshold voltage Vth311 of, for example, 4V is generated in the first sub-memory unit 111, and a 3-2-1 threshold voltage Vth321 of 0V is generated in the second memory unit 112, thereby forming a 4V first threshold state in the memory cell 11. Similarly, when the first direction reset bias V30 is applied, since it is in the same direction as the first direction set bias V31, a 3-1-1 threshold voltage Vth311 of 4V is still generated in the first sub-memory unit 111, but a 3-2-0 threshold voltage Vth320 of 0.7V is generated in the second memory unit 112.

[0136] Through the above-mentioned operation, after applying a single bias voltage in the first direction, a first threshold state of, for example, 4V, which is composed of the 3-1-1 threshold voltage Vth311 plus the 3-2-0 threshold voltage Vth321, and this first threshold state represents the value "11", or a second threshold state of, for example, 4.7V, which is composed of the 3-1-1 threshold voltage Vth311 plus the 3-2-0 threshold voltage Vth320, and this second threshold state represents the value "10".

[0137] For example Fig. 9 and Fig.10 As shown, when a bias is applied from the second direction, that is, a second direction single bias is applied from the word line BL to the memory cell 11, the memory cell 11 can obtain a third threshold state or a fourth threshold state. The second direction single bias can also include a second direction set bias V41, or a second direction reset bias V40.

[0138] Since the SOM memory cell 111 of the first sub-memory unit and the PCM memory cell 112 of the second sub-memory unit are biased at the same time, the bias size of the second direction set bias V41 or the second direction reset bias V40 is appropriately selected. Since the combination of the second direction set bias V41 or the second direction reset bias V40 is opposite to the bias direction of the combination of the first direction set bias V31 or the first direction reset bias V30, when the second direction set bias V41 is applied, a 4-1-0 threshold voltage Vth410 of a reset state of, for example, 5.5V is generated in the first sub-memory unit 111, but a 4-2-1 threshold voltage Vth421 of a set state of, for example, 0V is generated in the second memory unit 112. Similarly, when the second direction reset bias V40 is applied, due to the second direction, the 4-1-0 threshold voltage Vth410 of, for example, a 5.5V reset state will still be generated in the first sub-storage unit 111, and the 4-2-0 threshold voltage Vth420 of, for example, a 0.7V reset state will be generated in the second storage unit 112.

[0139] Through the above-mentioned operation, after applying a single bias voltage in the second direction, a third threshold state of, for example, 5.5V, composed of the 4-1-0 threshold voltage Vth410 plus the 4-2-1 threshold voltage Vth421, and this third threshold state represents the value "01", or a fourth threshold state of, for example, 6.2V, composed of the 4-1-0 threshold voltage Vth410 plus the 4-2-1 threshold voltage Vth421, and this fourth threshold state represents the value "00", can be generated in the storage unit 11.

[0140] Table 3 below illustrates examples of the values ​​of the threshold voltages described above and the composition of the threshold states. It should be understood here that, as mentioned above, it is optional for the storage value of the first sub-storage unit 111 (i.e., the SOM cell) to represent the first bit (low bit) or the second bit (high bit) of a two-digit value. Although the previous embodiment exemplifies that the storage value of the second sub-storage unit 112 (i.e., the PCM cell) represents the second bit (high bit) of a two-digit value, it can also represent the first bit (low bit) of a two-digit value. Therefore, in this embodiment, the storage value of the second sub-storage unit 112 (i.e., the PCM cell) represents the first bit (low bit) of a two-digit value. Moreover, in this embodiment, the second threshold state corresponds to the value "10", rather than the value "01" in the previous embodiment.

[0141] state Threshold state Vt Status Name PCM Vt SOM Vt 11 4V First threshold voltage (threshold state) 0V 4V 10 4.7V Second threshold voltage (threshold state) 0.7V 4V 01 5.5V Third threshold voltage (threshold state) 0V 5.5V 00 6.2V Fourth threshold voltage (threshold state) 0.7V 5.5V

[0142] Table 3

[0143] Therefore, according to the above embodiment, the step of applying the first direction bias includes: applying a first direction single bias to the memory cell to obtain a first threshold state or a second threshold state for the memory cell 11, and the step of applying the first direction single bias includes:

[0144] Applying a first direction set bias voltage V31 to generate a 3-1-1 threshold voltage in the first sub-memory unit 111 and a 3-2-1 threshold voltage in the second memory unit; or

[0145] Applying a first direction reset bias voltage V30 to the memory cell 11 to generate a 3-1-1 threshold voltage in the first sub-memory cell 111 and a 3-2-0 threshold voltage in the second memory cell;

[0146] Among them, the 3-1-1 threshold voltage and the 3-2-1 threshold voltage constitute the first threshold state, and the 3-1-1 threshold voltage and the 3-2-0 threshold voltage constitute the second threshold state.

[0147] Moreover, according to the aforementioned embodiment, the step of applying the second direction bias includes: applying a second direction single bias to the memory cell 11 to obtain a third threshold state or a fourth threshold state for the memory cell, and the step of applying the second direction single bias includes:

[0148] Applying a second direction set bias voltage V41 to the memory cell 11 to generate a 4-1-0 threshold voltage in the first sub-memory cell 111 and a 4-2-1 threshold voltage in the second memory cell; or

[0149] A second direction reset bias V40 is applied to the memory cell 11 to generate a 4-1-0 threshold voltage in the first sub-memory cell 111 and a 4-2-0 threshold voltage in the second sub-memory cell; the 4-1-0 threshold voltage and the 4-2-1 threshold voltage constitute the third threshold state, and the 4-1-1 threshold voltage and the 4-2-0 threshold voltage constitute the fourth threshold state.

[0150] Incidentally, in some embodiments, the 3-2-1 threshold voltage and the 4-2-1 threshold voltage are at the same threshold level, and the 3-2-0 threshold voltage and the 4-2-0 threshold voltage are at the same threshold level. The 3-1-1 threshold voltage is a set threshold voltage, the 3-2-1 threshold voltage is a set threshold voltage, the 3-2-0 threshold voltage is a reset threshold voltage, the 4-1-0 threshold voltage is a reset threshold voltage, the 4-2-1 threshold voltage is a set threshold voltage, and the 4-2-0 threshold voltage is a reset threshold voltage. However, as mentioned above, each reset threshold voltage may also be a half-reset threshold voltage or a half-set threshold voltage, etc.

[0151] Through the memory operation method described above, not only can multi-level storage be achieved, but also the read window margin can be increased, and better control uniformity can be achieved, thereby solving the read window margin problem in multi-level storage.

[0152] Further, according to the memory operation method described above, and referring to Figure 1 and Figure 2 Some embodiments of the present application further provide a memory 200, wherein the memory 200 includes:

[0153] A memory array 10, the memory array comprising memory cells 11 arranged in a matrix of multiple rows and columns, the two poles of the memory cells 11 being connected to a word line WLn and a bit line BLn respectively, and one of the memory cells 11 comprising a first sub-memory cell 111 and a second sub-memory cell 112 connected in series between the two poles;

[0154] A peripheral circuit 20, wherein the peripheral circuit 20 is configured to bias the two electrodes of the memory cell 11 in a first direction so as to obtain a first threshold state or a second threshold state for the memory cell; and

[0155] A second direction bias is applied to the two poles of the memory cell 11 to obtain a third threshold state or a fourth threshold state for the memory cell, and the first direction bias and the second direction bias are opposite in positive and negative directions at the two poles.

[0156] In some embodiments, the first sub-memory unit includes a SOM memory cell (selector only memory cell), also known as an SSM memory cell (self-selecting memory cell), and the second sub-memory unit includes a PCM memory device. The phase change memory cell 112 includes one or more phase change materials such as materials based on germanium-antimony-tellurium (Ge-Sb-Te, GST), one example of which may be Ge2Sb2Te5. Currently, the more commonly used phase change materials by various institutions are chalcogenides (represented by Intel) and synthetic materials containing germanium, antimony, and tellurium (GST), such as Ge2Sb2Te5. The SOM memory cell is composed of phase change materials such as Ge-Te-As-Si.

[0157] Further references Figure 7 and Figure 8 In some embodiments, the peripheral circuit 20 includes a word line driver 212, and the word line driver 212 is used to apply a first bias voltage V111 in a first direction to the memory cell 11, so as to generate a 1-1-1 threshold voltage Vth111 in the first sub-memory cell 111; and

[0158] Applying a first direction second bias voltage V121 / V120 to the memory cell to generate a 1-2-1 threshold voltage Vth121 or a 1-2-0 threshold voltage Vth120 in the second sub-memory cell 112;

[0159] The 1-1-1th threshold voltage Vth111 and the 1-2-1th threshold voltage Vth121 or the 1-2-0th threshold voltage Vth120 respectively constitute the first threshold state and the second threshold state.

[0160] In some embodiments, the peripheral circuit 20 further includes a bit line driver 251, and the bit line driver 251 is used to apply a second direction first bias voltage V210 to the memory cell 11 to generate a second-1-0 threshold voltage Vth210 in the first sub-memory cell 111; and

[0161] Applying a second bias voltage V221 / V220 in a second direction to the memory cell 11 to generate a 2-2-1 threshold voltage Vth221 or a 2-2-0 threshold voltage Vth220 in the second sub-memory cell 112;

[0162] The 2-1-0 threshold voltage Vth210 and the 2-2-1 threshold voltage Vth221 or the 2-2-0 threshold voltage Vth220 respectively form the third threshold state or the fourth threshold state.

[0163] Specifically, the first direction second bias voltage V121 / V120 includes a first direction set bias voltage V121 or a first direction reset bias voltage V120. The second direction second bias voltage V221 / V220 includes a second direction set bias voltage V221 or a second direction reset bias voltage V220.

[0164] Further Fig. 9 and Fig.10 As shown, in some embodiments, Figure 1 The peripheral circuit 20 shown includes a word line driver 212, but the write bias applied by the word line driver 212 is a first direction single bias V31 applied to the memory cell 11 to obtain a first threshold state or a second threshold state for the memory cell, and the first direction single bias includes:

[0165] A first direction bias voltage V31 is applied to the memory cell 11 to generate a 3-1-1th threshold voltage in the first sub-memory cell 111 and a 3-2-1th threshold voltage in the second sub-memory cell 112; or

[0166] A first direction reset bias voltage V30 is applied to the memory cell 11 to generate a 3-1-1 threshold voltage in the first sub-memory cell 111 and a 3-2-0 threshold voltage in the second sub-memory cell 112;

[0167] Among them, the 3-1-1th threshold voltage and the 3-2-1th threshold voltage constitute the first threshold state, and the 3-1-1th threshold voltage and the 3-2-0th threshold voltage constitute the second threshold state.

[0168] In some embodiments, the peripheral circuit 20 includes a bit line driver 251, and the bit line driver 251 is used to apply a second direction single bias to the memory cell 11 to obtain a third threshold state or a fourth threshold state for the memory cell 11, and the second direction single bias includes:

[0169] A second direction bias is set to generate a 4-1-0 threshold voltage in the first sub-memory unit 111 and a 4-2-1 threshold voltage in the second sub-memory unit 112; or

[0170] A second direction reset bias is provided to generate a 4-1-0 threshold voltage in the first sub-memory unit 111 and a 4-2-0 threshold voltage in the second sub-memory unit 112;

[0171] The 4-1-0 threshold voltage and the 4-2-1 threshold voltage constitute the third threshold state, and the 4-1-0 threshold voltage and the 4-2-0 threshold voltage constitute the fourth threshold state.

[0172] In some embodiments, the 3-1-1 threshold voltage is a set threshold voltage, the 3-2-1 threshold voltage is a set threshold voltage, the 3-2-0 threshold voltage is a reset threshold voltage, the 4-1-0 threshold voltage is a reset threshold voltage, the 4-2-1 threshold voltage is a set threshold voltage, and the 4-2-0 threshold voltage is a reset threshold voltage. Such a configuration can not only achieve multi-level storage, but also increase the read window margin, and have better control uniformity, and can solve the read window margin problem in multi-level storage.

[0173] According to some embodiments of the present application, Fig.11 As shown, a storage system 400 is also provided, and the storage system 400 includes the memory 200 described above; and

[0174] The controller 40 is electrically connected to the memory 200 and is used to control the memory 200 .

[0175] The logic control module 230 in the memory 200 controls the word line driver 212 and the bit line driver 251 to perform the operation methods described in the above embodiments.

[0176] In some embodiments, the storage system may be implemented as a storage device such as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0177] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.< / n> < / m>

Claims

1. A method for operating a memory, characterized in that: The operation method comprises: Applying a first direction bias to two electrodes of a memory cell formed by connecting a first sub-memory cell and a second sub-memory cell in series in a memory array, so as to obtain a first threshold state or a second threshold state for the memory cell; and A second direction bias is applied to the two poles of the memory cell to obtain a third threshold state or a fourth threshold state of the memory cell, and the first direction bias and the second direction bias are opposite in positive and negative directions of the two poles.

2. The memory operation method according to claim 1, characterized in that: The operating method includes using a SOM memory device as the first sub-memory unit and using a PCM memory device as the second sub-memory unit.

3. The memory operation method according to claim 1, characterized in that: The step of applying a first direction bias comprises: Applying a first bias voltage in a first direction to the memory cell to generate a 1-1-1 threshold voltage in the first sub-memory cell; and Applying a second bias voltage in a first direction to the memory cell to generate a 1-2-1 threshold voltage or a 1-2-0 threshold voltage in the second sub-memory cell; The 1-1-1th threshold voltage and the 1-2-1th threshold voltage constitute the first threshold state, and the 1-1-1th threshold voltage and the 1-2-0th threshold voltage constitute the second threshold state.

4. The memory operation method according to claim 3, characterized in that: The step of applying a second bias voltage in the first direction comprises: Applying a first direction set bias to the memory cell to generate the 1-2-1th threshold voltage in the second sub-memory cell; or A first direction reset bias is applied to the memory cell to generate the 1-2-0 threshold voltage in the second sub-memory cell.

5. The memory operation method according to claim 3 or 4, characterized in that: The step of performing a second direction bias comprises: Applying a first bias voltage in a second direction to the memory cell to generate a 2-1-0 threshold voltage in the first sub-memory cell; and Applying a second bias voltage in a second direction to the memory cell to generate a 2-2-1 threshold voltage or a 2-2-0 threshold voltage in the second sub-memory cell; The 2-1-0 threshold voltage and the 2-2-1 threshold voltage constitute the third threshold state, and the 2-1-0 threshold voltage and the 2-2-0 threshold voltage constitute the fourth threshold state.

6. The memory operation method according to claim 5, characterized in that: The step of applying a second bias voltage in a second direction comprises: Applying a second direction set bias to the memory cell to generate the 2-2-1th threshold voltage in the second sub-memory cell; or A second direction reset bias is applied to the memory cell to generate the 2-2-0 threshold voltage in the second sub-memory cell.

7. The memory operation method according to claim 6, characterized in that: The operation method also includes: The 1-2-1th threshold voltage and the 2-2-1th threshold voltage are at the same threshold level, and the 1-2-0th threshold voltage and the 2-2-0th threshold voltage are at the same threshold level; and The 1-1-1 threshold voltage is a set threshold voltage, the 1-2-1 threshold voltage is a set threshold voltage, the 1-2-0 threshold voltage is a reset threshold voltage, the 2-1-0 threshold voltage is a reset threshold voltage, the 2-2-1 threshold voltage is a set threshold voltage, and the 2-2-0 threshold voltage is a reset threshold voltage.

8. The memory operation method according to claim 1, characterized in that: The step of applying a first direction bias comprises: applying a first direction single bias to the memory cell to obtain a first threshold state or a second threshold state for the memory cell, and the step of applying a first direction single bias comprises: Applying a first direction set bias to the memory cell to generate a 3-1-1th threshold voltage in the first sub-memory cell and a 3-2-1th threshold voltage in the second memory cell; or Applying a first direction reset bias to the memory cell to generate a 3-1-1 threshold voltage in the first sub-memory cell and a 3-2-0 threshold voltage in the second memory cell; Among them, the 3-1-1th threshold voltage and the 3-2-1th threshold voltage constitute the first threshold state, and the 3-1-1th threshold voltage and the 3-2-0th threshold voltage constitute the second threshold state.

9. The memory operation method according to claim 1 or 8, characterized in that: The step of applying the second direction bias comprises: applying a second direction single bias to the memory cell to obtain a third threshold state or a fourth threshold state for the memory cell, and the step of applying the second direction single bias comprises: Applying a second direction set bias to the memory cell to generate a 4-1-0 threshold voltage in the first sub-memory cell and a 4-2-1 threshold voltage in the second memory cell; or A second direction reset bias is applied to the memory cell to generate a 4-1-0 threshold voltage in the first sub-memory cell and a 4-2-0 threshold voltage in the second memory cell; the 4-1-0 threshold voltage and the 4-2-1 threshold voltage constitute the third threshold state, and the 4-1-0 threshold voltage and the 4-2-0 threshold voltage constitute the fourth threshold state.

10. The memory operation method according to claim 9, characterized in that: The operation method also includes: The 3-2-1th threshold voltage and the 4-2-1th threshold voltage are at the same threshold level, and the 3-2-0th threshold voltage and the 4-2-0th threshold voltage are at the same threshold level; and The 3-1-1 threshold voltage is set as the threshold voltage, the 3-2-1 threshold voltage is set as the threshold voltage, the 3-2-0 threshold voltage is reset as the threshold voltage, the 4-1-0 threshold voltage is reset as the threshold voltage, the 4-2-1 threshold voltage is set as the threshold voltage, and the 4-2-0 threshold voltage is reset as the threshold voltage.

11. A memory, characterized in that: The memory comprises: A memory array, the memory array comprising memory cells arranged in a matrix of multiple rows and columns, the two poles of the memory cells being connected to a word line and a bit line respectively, and one of the memory cells comprising a first sub-memory cell and a second sub-memory cell connected in series between the two poles; a peripheral circuit configured to bias two electrodes of the memory cell in a first direction so as to obtain a first threshold state or a second threshold state for the memory cell; and A second direction bias is applied to the two poles of the memory cell to obtain a third threshold state or a fourth threshold state of the memory cell, and the first direction bias and the second direction bias are opposite in positive and negative directions of the two poles.

12. The memory according to claim 11, characterized in that: The first sub-storage unit includes a SOM memory device, and the second sub-storage unit includes a PCM memory device.

13. The memory according to claim 11, characterized in that: The peripheral circuit includes a word line driver, and the word line driver is used to apply a first bias voltage in a first direction to the memory cell to generate a 1-1-1 threshold voltage in the first sub-memory cell; as well as Applying a second bias voltage in a first direction to the memory cell to generate a 1-2-1 threshold voltage or a 1-2-0 threshold voltage in the second sub-memory cell; The 1-1-1th threshold voltage and the 1-2-1th threshold voltage constitute the first threshold state, and the 1-1-1th threshold voltage and the 1-2-0th threshold voltage constitute the second threshold state.

14. The memory according to claim 13, characterized in that: The peripheral circuit further includes a bit line driver, the bit line driver is used to apply a first bias voltage in a second direction to the memory cell to generate a second-1-0 threshold voltage in the first sub-memory cell; as well as Applying a second bias voltage in a second direction to the memory cell to generate a 2-2-1 threshold voltage or a 2-2-0 threshold voltage in the second sub-memory cell; The 2-1-0 threshold voltage and the 2-2-1 threshold voltage constitute the third threshold state, and the 2-1-0 threshold voltage and the 2-2-0 threshold voltage constitute the fourth threshold state.

15. The memory according to claim 13, characterized in that: The first direction second bias includes a first direction set bias or a first direction reset bias, and the second direction second bias includes a second direction set bias or a second direction reset bias.

16. The memory according to claim 14, characterized in that: The 1-1-1 threshold voltage is a set threshold voltage, the 1-2-1 threshold voltage is a set threshold voltage, the 1-2-0 threshold voltage is a reset threshold voltage, the 2-1-0 threshold voltage is a reset threshold voltage, the 2-2-1 threshold voltage is a set threshold voltage, and the 2-2-0 threshold voltage is a reset threshold voltage.

17. The memory according to claim 11, characterized in that: The peripheral circuit includes a word line driver, and the word line driver is used to apply a first direction single bias to the memory cell to obtain a first threshold state or a second threshold state for the memory cell, and the first direction single bias includes: A first direction setting bias is applied to the memory cell to generate a 3-1-1th threshold voltage in the first sub-memory cell and a 3-2-1th threshold voltage in the second sub-memory cell; or A first direction reset bias is applied to the memory cell to generate a 3-1-1 threshold voltage in the first sub-memory cell and a 3-2-0 threshold voltage in the second sub-memory cell; Among them, the 3-1-1 threshold voltage and the 3-2-1 threshold voltage constitute the first threshold state, and the 3-1-1 threshold voltage and the 3-2-0 threshold voltage constitute the second threshold state.

18. The memory according to claim 17, characterized in that: The peripheral circuit further includes a bit line driver, the bit line driver is used to apply a second direction single bias voltage to the memory cell to obtain a third threshold state or a fourth threshold state for the memory cell, and the second direction single bias voltage includes: A second direction bias is set to generate a 4-1-0 threshold voltage in the first sub-memory unit and a 4-2-1 threshold voltage in the second sub-memory unit; or A second direction reset bias is provided to generate a 4-1-0 threshold voltage in the first sub-memory unit and a 4-2-0 threshold voltage in the second sub-memory unit; The 4-1-0 threshold voltage and the 4-2-1 threshold voltage constitute the third threshold state, and the 4-1-0 threshold voltage and the 4-2-0 threshold voltage constitute the fourth threshold state.

19. The memory according to claim 18, characterized in that: The 3-1-1th threshold voltage is a set threshold voltage, the 3-2-1th threshold voltage is a set threshold voltage, the 3-2-0th threshold voltage is a reset threshold voltage, the 4-1-0th threshold voltage is a reset threshold voltage, the 4-2-1th threshold voltage is a set threshold voltage, and the 4-2-0th threshold voltage is a reset threshold voltage.

20. A storage system, characterized in that: include: The memory according to claims 11 to 19; A controller is electrically connected to the memory and is used to control the memory.

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