Semiconductor process fluctuation monitoring method

Abstract

The invention provides a semiconductor process fluctuation monitoring method, which is characterized in that a polycrystalline silicon test structure is formed in a test area of a wafer, and the polycrystalline silicon test structure comprises a first polycrystalline silicon bonding pad, a polycrystalline silicon wire and a second polycrystalline silicon bonding pad which are connected in sequence, the polycrystalline silicon test resistance value of the wafer is obtained by measuring the resistance of the test structure, whether the polycrystalline silicon resistance fluctuation of the wafer reaches the standard or not is judged, meanwhile, the size data of the test structure are collected, whether the polycrystalline silicon size of the wafer reaches the standard or not is judged, and when both the size data and the size data reach the standard, a dielectric layer continues to be formed and CMP is carried out to obtain a target morphology surface. Collecting AFM test data of the target morphology surface; when any one of the film layers does not reach the standard, subsequent film layer deposition and data collection of the wafer are stopped; and then establishing a DFM chemical mechanical polishing model on the basis of the collected AFM test data. According to the semiconductor process fluctuation monitoring method, bad wafers can be recognized in time, cost waste is reduced, and meanwhile error data can be prevented from being brought into subsequent modeling in time.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a method for monitoring semiconductor process fluctuations. Background Art

[0002] In the semiconductor integrated circuit manufacturing process, in order to measure and evaluate whether the production process is stable and monitor whether there are abnormal process fluctuations during the tape-out process, a test structure (Testkey) is usually placed to verify the electrical test by measuring capacitance, resistance or leakage current. For example, in order to detect whether the morphology is qualified after chemical mechanical polishing (CMP), in some scenarios, the CMP process will be used on the dielectric layer or metal layer after polysilicon (Poly), and then the atomic force microscope (AFM) will be used to collect the topography data (i.e. the ups and downs of the product surface morphology), and then the design for manufacturing (Design For Manufacturing, DFM) CMP model will be created for early warning of hot spots. In this process, the data used to create the DFM CMP model comes from AFM. It must be ensured that the data source is a product with normal process fluctuations, so that subsequent modeling is meaningful.

[0003] However, currently, the polysilicon layer before the metal layer is deposited is verified by the critical dimension (Critical Dimension, CD) and thickness of the test structure (usually obtained by slicing the test structure, and only a representative sample of a certain type is sliced, the number is small, the coverage is small, and because the sliced ​​wafers cannot be used for subsequent processes, the cost is high) to ensure that its process meets the requirements, but it cannot fully reflect whether the surface morphology and thickness of the polysilicon are normal. Therefore, the data collected by AFM may come from wafers that exceed the normal process fluctuation range, and then be brought into the subsequent DFM CMP model construction for use, resulting in the model built based on unqualified data cannot be used well. This is because during research and development, short loop process requirements usually arise due to different research and development purposes. During the short loop process research and development process of single-layer polysilicon, whether the process of the polysilicon layer meets the standards is currently determined only by checking whether the CD of the polysilicon meets the standards. However, in the short loop, there is no CMP after the polysilicon layer. Instead, a dielectric layer is deposited directly after the polysilicon layer (or a metal layer is deposited at the same time), and then CMP is performed. AFM is then used to collect the morphology for the creation of a CMP model for manufacturability design. In fact, it is impossible to accurately know whether the polysilicon surface is flat. If the polysilicon process fluctuates, the subsequent inaccurate or erroneous data caused by the uneven polysilicon surface will also be brought into the created CMP model and cannot be identified. The created CMP model is based on the data of defective wafers, which in turn causes the created CMP model to be inaccurate, affecting normal use.

[0004] In addition, the resistance of polysilicon is measured through metal leads because the contact resistance of the probe is small when measuring through metal. However, measuring resistance through metal leads cannot be achieved in the polysilicon short ring process, resulting in the inability to identify defects in single-layer polysilicon in a timely manner.

[0005] Therefore, how to provide a semiconductor process fluctuation monitoring method to timely identify defective wafers, reduce cost waste, and promptly prevent erroneous data from being brought into subsequent modeling has become an important technical problem that technical personnel in this field need to solve urgently.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0007] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a semiconductor process fluctuation monitoring method to solve the problem that the existing semiconductor process fluctuation monitoring method is prone to cost waste and bring erroneous data into subsequent modeling due to the inability to timely identify defective wafers.

[0008] To achieve the above-mentioned object and other related objects, the present invention provides a semiconductor process fluctuation monitoring method, comprising the following steps:

[0009] Providing a wafer, the wafer comprising a device area and a test area divided according to a preset rule along a plane where the wafer is located;

[0010] Forming a polysilicon layer on the wafer, and patterning the polysilicon layer to obtain a test structure located in the test area, wherein the test structure includes a first polysilicon pad, a polysilicon line, and a second polysilicon pad connected in sequence;

[0011] Measuring the resistance of the test structure through the first polysilicon pad and the second polysilicon pad to obtain a polysilicon test resistance value of the wafer, and judging whether the polysilicon resistance fluctuation of the wafer meets the standard based on the test resistance value;

[0012] Collecting the size data of the test structure, and judging whether the size of the polysilicon of the wafer meets the standard based on the size data of the test structure;

[0013] When both the polysilicon resistance fluctuation and the polysilicon size of the wafer meet the standards, a dielectric layer is formed on the polysilicon layer, and the dielectric layer is chemically mechanically polished to obtain a target topography surface, and atomic force microscope test data of the target topography surface is collected; when either the polysilicon resistance fluctuation or the polysilicon size does not meet the standards, subsequent film layer deposition and atomic force microscope test data collection of the wafer are stopped;

[0014] The DFM chemical mechanical polishing model is created based on the collected atomic force microscope test data.

[0015] Optionally, before or after patterning the polysilicon layer, the method further includes a step of performing ion implantation on the polysilicon layer to enhance the conductivity of the polysilicon layer.

[0016] Optionally, the resistance R1 of the first polysilicon pad, the resistance R2 of the polysilicon line and the resistance R3 of the second polysilicon pad are all in the same order of magnitude, or satisfy: R1 / R2<1 / 10, R3 / R2<1 / 10.

[0017] Optionally, judging whether the polysilicon resistance fluctuation of the wafer meets the standard based on the test resistance value includes: calculating the difference between the test resistance value and a preset resistance value, and when the difference is within the range of ±10% of the preset resistance value, it is determined that the polysilicon resistance fluctuation of the wafer meets the standard, otherwise it is determined that it does not meet the standard.

[0018] Optionally, judging whether the polysilicon resistance fluctuation of the wafer meets the standard based on the test resistance value includes: obtaining polysilicon test resistance values ​​corresponding to multiple wafers from the same batch, and according to the 3σ principle of normal distribution, when the polysilicon test resistance value corresponding to a certain wafer is distributed within the range of (μ-3σ, μ+3σ), then the polysilicon resistance fluctuation of this wafer is judged to meet the standard, otherwise it is judged to be not up to standard, wherein σ is the standard deviation, and μ is the mean of the polysilicon test resistance values ​​corresponding to multiple wafers from the same batch.

[0019] Optionally, creating a DFM chemical mechanical polishing model based on the collected atomic force microscope test data includes:

[0020] Select multiple wafers whose polysilicon resistance fluctuation and polysilicon size meet the standards, collect the atomic force microscope test data corresponding to the multiple wafers for the same test point and take the average value;

[0021] A DFM chemical mechanical polishing model is created based on an average value of the atomic force microscope test data corresponding to a plurality of wafers.

[0022] Optionally, the dimension data of the test structure includes at least one of a width of the polysilicon line, a spacing between the polysilicon lines, a thickness of the first polysilicon pad, and a thickness of the second polysilicon pad.

[0023] Optionally, a tool used to measure the resistance of the test structure includes a probe, and a material of a portion of the probe in contact with the polysilicon pad includes titanium boron nitride.

[0024] Optionally, the polysilicon line includes an X-direction extension line and a Y-direction extension line that are alternately arranged in a non-closed loop and connected end to end, the X-direction extension line is perpendicular to the Y-direction extension line, the length of the X-direction extension line is greater than the length of the Y-direction extension line, and the ends of the extension lines at the two ends are respectively connected to the first polysilicon pad and the second polysilicon pad.

[0025] Optionally, a tool used to measure the resistance of the test structure includes a probe card, and a center line connecting the first polysilicon pad and the second polysilicon pad is parallel to the Y-direction extension line.

[0026] As described above, the semiconductor process fluctuation monitoring method of the present invention forms a polysilicon test structure in the test area of ​​the wafer, and the test structure includes a first polysilicon pad, a polysilicon line and a second polysilicon pad connected in sequence. The resistance of the test structure is measured through the first and second polysilicon pads to obtain the polysilicon test resistance value of the wafer and determine whether the polysilicon resistance fluctuation of the wafer meets the standard. Whether the polysilicon size of the wafer meets the standard is determined by collecting the size data of the test structure. When both the polysilicon resistance fluctuation and the polysilicon size of the wafer meet the standard, a dielectric layer continues to be formed on the polysilicon layer, and the dielectric layer is chemically mechanically polished to obtain a target morphology surface, and atomic force microscope test data of the target morphology surface is collected. When any one of the polysilicon resistance fluctuation and the polysilicon size does not meet the standard, the subsequent film layer deposition and atomic force microscope test data collection of the wafer are stopped; and then a DFM chemical mechanical polishing model is created based on the collected atomic force microscope test data. The semiconductor process fluctuation monitoring method of the present invention uses the polysilicon resistance fluctuation and polysilicon size meeting the requirements as the judgment standard for good wafers, and can timely identify bad wafers, that is, wafers whose polysilicon layer surface flatness does not meet the requirements, and thus can ensure that the data required for modeling comes from good wafers with better polysilicon layer deposition, and ensure that the data of bad wafers caused by excessive process fluctuations will not be used for modeling, that is, it prevents bad wafers with uneven polysilicon surfaces from being used as the source of later data collection, which helps to improve the stability of the polysilicon process, reduce cost waste, and can timely prevent erroneous data from being brought into subsequent modeling. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Shown is a flow chart of a semiconductor process fluctuation monitoring method according to the present invention.

[0028] Figure 2 A planar layout diagram of a test structure formed in the semiconductor process fluctuation monitoring method of the present invention is shown.

[0029] Figure 3 Another planar layout diagram of a test structure formed in the semiconductor process variation monitoring method of the present invention is shown.

[0030] Description of Reference Numerals

[0031] S1-S7 Step 101 First polysilicon pad

[0032] 102 Polysilicon Line

[0033] 103 second polysilicon pad DETAILED DESCRIPTION

[0034] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] See also Figures 1 to 3 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0036] The present invention provides a semiconductor process fluctuation monitoring method, please refer to Figure 1 , which is a flow chart of the semiconductor process fluctuation monitoring method, comprising the following steps:

[0037] S1: providing a wafer, wherein the wafer comprises a device area and a test area divided according to a preset rule along a plane where the wafer is located;

[0038] S2: forming a polysilicon layer on the wafer, and patterning the polysilicon layer to obtain a test structure located in the test area, wherein the test structure includes a first polysilicon pad, a polysilicon line, and a second polysilicon pad connected in sequence;

[0039] S3: measuring the resistance of the test structure through the first polysilicon pad and the second polysilicon pad to obtain a polysilicon test resistance value of the wafer, and judging whether the polysilicon resistance fluctuation of the wafer meets the standard based on the test resistance value;

[0040] S4: collecting the size data of the test structure, and judging whether the size of the polysilicon of the wafer meets the standard based on the size data of the test structure;

[0041] S5: when both the polysilicon resistance fluctuation and the polysilicon size of the wafer meet the standards, a dielectric layer is formed on the polysilicon layer, and the dielectric layer is chemically mechanically polished to obtain a target topography surface, and atomic force microscope test data of the target topography surface is collected; when either the polysilicon resistance fluctuation or the polysilicon size does not meet the standards, subsequent film layer deposition and atomic force microscope test data collection of the wafer are stopped;

[0042] S6: Create a DFM chemical mechanical polishing model based on the collected atomic force microscope test data.

[0043] Specifically, in step S1, the wafer may be a silicon wafer, a germanium wafer, a silicon-on-insulator wafer, a silicon carbide wafer, a III-V compound wafer or other suitable semiconductor material wafer, and the required components, such as a well region, an isolation structure, etc., may be pre-fabricated in the wafer.

[0044] As an example, the test area may be located in a scribe line area of ​​a wafer.

[0045] Specifically, in the step S2 , the method of forming the polysilicon layer on the wafer may be chemical vapor deposition or other suitable methods.

[0046] In one embodiment, before patterning the polysilicon layer, the step of ion implantation into the polysilicon layer is further included to enhance the conductivity of the polysilicon layer. For example, boron ions or phosphorus ions may be implanted into the polysilicon layer, and the specific implantation dose may be set according to actual needs.

[0047] In another embodiment, ion implantation may be performed on the polysilicon layer after patterning the polysilicon layer to enhance the conductivity of the polysilicon layer.

[0048] As an example, patterning the polysilicon layer includes the following steps:

[0049] (1) forming a photoresist layer on the polysilicon layer;

[0050] (2) patterning the photoresist layer using processes such as photolithography and development;

[0051] (3) Etching the polysilicon layer using the patterned photoresist layer as a mask to obtain a test structure located in the test area.

[0052] As an example, see Figure 2 , showing a planar layout diagram of the test structure, including a first polysilicon pad 101, a polysilicon line 102 and a second polysilicon pad 103 connected in sequence, and the polysilicon line 102 is in a meandering shape.

[0053] Specifically, the polysilicon line 102 serves as the main part of the test structure, and its meandering shape is to maximize the resistance of the main part within a limited area. At the same time, the shape and size of the first polysilicon pad 101 and the second polysilicon pad 103 are set so that the resistance of the polysilicon pad is much smaller than or is at the same order of magnitude as the resistance of the main part of the test structure. In other words, the resistance of the polysilicon pad cannot be too large relative to the resistance of the polysilicon line to ensure that the resistance of the pad does not affect the fluctuation display of the resistance of the test structure.

[0054] In one embodiment, the resistance R1 of the first polysilicon pad 101, the resistance R2 of the polysilicon line 102, and the resistance R3 of the second polysilicon pad 103 are all at the same order of magnitude, or satisfy: R1 / R2<1 / 10, R3 / R2<1 / 10.

[0055] As an example, the shapes of the first polysilicon pad 101 and the second polysilicon pad 103 may be as follows: Figure 2 In other embodiments, the shapes of the first polysilicon pad 101 and the second polysilicon pad 103 may also be circular or other suitable shapes as required.

[0056] It should be pointed out that because the resistance test of polysilicon is performed in the short loop process, the pad is a polysilicon pad and cannot be a metal pad because this step does not perform a metal deposition or electroplating step.

[0057] As an example, the polysilicon line 102 may be as follows Figure 2 The polysilicon line 102 is bent at a right angle, and each section after the bend is straight, that is, the polysilicon line includes an X-direction extension line and a Y-direction extension line that are alternately arranged in a non-closed loop and connected end to end, the X-direction extension line is perpendicular to the Y-direction extension line, the length of the X-direction extension line is greater than the length of the Y-direction extension line, and the ends of the extension lines at the two ends are respectively connected to the first polysilicon pad and the second polysilicon pad. In other embodiments, the polysilicon line 102 can also be bent in a curve or other suitable bending forms.

[0058] Specifically, in step S3, the resistance of the test structure is measured through the first polysilicon pad 101 (the pad is also called pad, which is the contact part with the probe) and the second polysilicon pad 103 to obtain the polysilicon test resistance value of the wafer, and whether the polysilicon resistance fluctuation of the wafer meets the standard is determined based on the test resistance value.

[0059] As an example, the tool used to measure the resistance of the test structure includes a probe. In order to improve the accuracy of the test, it is best to use a probe with low contact resistance, because the semiconductor properties of polysilicon will cause the metal probe to generate a very large contact resistance when it is in direct contact with the polysilicon, resulting in a lot of noise in the resistance test, affecting the accuracy of the test result, and using a probe with low contact resistance can improve this problem. In one embodiment, the material of the portion of the probe that contacts the polysilicon pad includes titanium boron nitride (TiB x N y), where x is the atomic component of B, y is the atomic component of N, x and y are both greater than 0, and their specific values ​​can be set as needed. In this embodiment, the metal probe for measuring resistance is replaced with a titanium boron nitride probe directly acting on polysilicon, which can make the test structure resistance (about several thousand ohms) much larger than the contact resistance, thereby effectively reducing the error.

[0060] As an example, see Figure 3 If a titanium boron nitride pin card is used to measure the resistance of the test structure, the center line between the first polysilicon pad 101 and the second polysilicon pad 103 can be designed to be parallel to the Y-direction extension line to adapt to the measurement method of the pin card.

[0061] Specifically, after measuring the resistance of the test structure by the first polysilicon pad 101 and the second polysilicon pad 103 to obtain the polysilicon test resistance value of the wafer, it is determined whether the polysilicon resistance fluctuation of the wafer meets the standard based on the test resistance value. Compared with the method of determining process fluctuation by obtaining the polysilicon thickness by slicing in the prior art, the method of the present invention does not require scrapping of wafers, and subsequent film deposition can continue.

[0062] Specifically, judging whether the polysilicon resistance fluctuation of the wafer meets the standard based on the test resistance value is for single-layer polysilicon, and whether the process of the single-layer polysilicon layer is qualified can be judged.

[0063] Specifically, judging whether the polysilicon resistance fluctuation of the wafer meets the standard based on the test resistance value is not limited to one method. For example, in one embodiment, when resources are limited, only a single chip and a preset value are used for comparison to judge process fluctuations, wherein judging whether the polysilicon resistance fluctuation of the wafer meets the standard based on the test resistance value includes: calculating the difference between the test resistance value and the preset resistance value, when the difference is within the range of ±10% of the preset resistance value, it is judged that the polysilicon resistance fluctuation of the wafer meets the standard, otherwise it is judged that it does not meet the standard.

[0064] In the present invention, a wafer whose polysilicon resistance fluctuation and polysilicon size meet the standards can be judged as a good wafer and can continue to proceed to the subsequent process. This method can detect whether a single wafer is a bad wafer. When the polysilicon resistance fluctuation is large, it means that the surface flatness of the deposited polysilicon layer is poor, and it should not continue to proceed to the subsequent process and cannot be used for subsequent modeling.

[0065] As an example, the preset resistance value is obtained based on an acceptable process. For example, an acceptable resistance value obtained through simulation can be used as the preset resistance value, or an average value of resistances measured through a large number of wafer fabrications can be used as the preset resistance value.

[0066] In another embodiment, judging whether the polysilicon resistance fluctuation of the wafer meets the standard based on the test resistance value can also be applied to a batch of multiple wafers, wherein the number of multiple wafers in the same batch (lot) is not specifically limited and can be configured according to actual production needs.

[0067] It should be noted that the CD (critical dimension) of polysilicon is currently collected through inline measurement, but whether the surface of the polysilicon is flat and whether the fluctuation of the surface flatness caused by the process exceeds a reasonable range cannot be monitored through image monitoring means. Therefore, in the short loop, CMP will not be performed after the deposition of the polysilicon layer, resulting in the failure to detect the defective polysilicon layer in time, and then the defective data is brought into the DFM modeling process, resulting in inaccurate modeling data. The present invention constructs a set of test methods that can evaluate whether the polysilicon deposition is qualified after the polysilicon layer is deposited. It can judge whether the polysilicon layer deposition process of the batch of wafers is qualified through the fluctuation of the resistance of the polysilicon layer of different wafers in the same batch, and then select the wafers used for AFM data collection.

[0068] As an example, multiple wafers of the same batch can be numbered, and the polysilicon test resistance values ​​corresponding to the multiple wafers of the same batch are first obtained, such as R1, R2, ..., R M , where M is the preset maximum number of wafers from the same batch. Then, according to the 3σ principle of normal distribution, when the polysilicon test resistance value corresponding to a certain wafer is distributed in the range of (μ-3σ, μ+3σ), it is determined that the polysilicon resistance fluctuation of this wafer meets the standard, otherwise it does not meet the standard. Where σ is the standard deviation, and μ is the mean of the polysilicon test resistance values ​​corresponding to multiple wafers from the same batch.

[0069] Specifically, the normal distribution is also called the Gaussian distribution. The normal distribution is a probability distribution. The normal distribution is the distribution of a continuous random variable with two parameters μ (mathematical expectation) and σ (standard deviation). The first parameter μ is the mean of the random variable that follows the normal distribution, and the second parameter σ is the variance of this random variable, so the normal distribution is recorded as N(μ, σ). The characteristics of the density function of the normal distribution are: symmetric about μ, reaching the maximum value at μ, taking the value of 0 at positive (negative) infinity, and having an inflection point at μ±σ. Its shape is high in the middle and low on both sides, and the image is a bell-shaped curve located above the x-axis. When μ=0, σ=1, it is called the standard normal distribution, recorded as N(0, 1). The 3σ principle means that the probability of a value being distributed in (μ—σ, μ+σ) is 0.6826, the probability of a value being distributed in (μ—2σ, μ+2σ) is 0.9544, and the probability of a value being distributed in (μ—3σ, μ+3σ) is 0.9974.

[0070] Specifically, for multiple wafers of the same batch, wafers whose polysilicon test resistance values ​​do not meet the range of (μ-3σ, μ+3σ) will be eliminated, and only several wafers whose polysilicon test resistance values ​​meet the range of (μ-3σ, μ+3σ) and whose polysilicon size meets the standard will be selected for subsequent processes. Here, several means that all wafers that meet the conditions can be selected, or some samples can be selected again from these wafers that meet the conditions according to actual needs. Among them, the better solution is to select all wafers that meet the conditions, because the larger the sample size, the more accurate the data used for modeling.

[0071] Specifically, in step S4: the dimensional data of the test structure collected may include at least one of the width of the polysilicon line, the spacing between the polysilicon lines, the thickness of the first polysilicon pad and the thickness of the second polysilicon pad, and may be set according to actual production requirements.

[0072] It should be pointed out that the execution order of step S3 of determining whether the polysilicon resistance fluctuation of the wafer meets the standard and step S4 of determining whether the polysilicon size of the wafer meets the standard can be interchanged.

[0073] Specifically, in step S5, when both the polysilicon resistance fluctuation and the polysilicon size of the wafer meet the standards, a dielectric layer is formed on the polysilicon layer, and the dielectric layer is chemically mechanically polished to obtain a target morphology surface, and atomic force microscope test data of the target morphology surface is collected. When either the polysilicon resistance fluctuation or the polysilicon size of the wafer does not meet the standards, subsequent film layer deposition and atomic force microscope test data collection of the wafer are stopped, thereby helping to identify defective wafers as early as possible and reduce cost waste. At the same time, the data of defective wafers will not be used as the basis for modeling, thereby preventing inaccurate modeling data.

[0074] As an example, the step S6 creates a design for manufacturing (DFM) chemical mechanical polishing model based on the collected atomic force microscope test data, including first selecting multiple wafers whose polysilicon resistance fluctuation and polysilicon size meet the standards, collecting the atomic force microscope test data corresponding to multiple wafers for the same test point and taking the average value, and then creating a DFM chemical mechanical polishing model based on the average value of the atomic force microscope test data corresponding to multiple wafers.

[0075] In summary, the semiconductor process fluctuation monitoring method of the present invention forms a polysilicon test structure in the test area of ​​the wafer, and the test structure includes a first polysilicon pad, a polysilicon line and a second polysilicon pad connected in sequence, and the polysilicon line is meandering back and forth, and the resistance of the test structure is measured through the first and second polysilicon pads to obtain the polysilicon test resistance value of the wafer and judge whether the polysilicon resistance fluctuation of the wafer meets the standard, and judge whether the polysilicon size of the wafer meets the standard by collecting the size data of the test structure. When both the polysilicon resistance fluctuation and the polysilicon size of the wafer meet the standard, continue to form a dielectric layer on the polysilicon layer, and perform chemical mechanical polishing on the dielectric layer to obtain a target morphology surface, collect atomic force microscope test data of the target morphology surface, and when any one of the polysilicon resistance fluctuation and the polysilicon size does not meet the standard, stop the subsequent film layer deposition and atomic force microscope test data collection of the wafer; then, create a DFM chemical mechanical polishing model based on the collected atomic force microscope test data. The semiconductor process fluctuation monitoring method of the present invention uses the polysilicon resistance fluctuation and polysilicon size meeting the requirements as the judgment criteria for good wafers, and can timely identify bad wafers, that is, wafers whose polysilicon layer surface flatness does not meet the requirements, and then can ensure that the data required for modeling comes from good wafers with good polysilicon layer deposition, and ensure that the data of bad wafers caused by excessive process fluctuations will not be used for modeling, that is, it prevents bad wafers with uneven polysilicon surfaces from being used as the source of later data collection, which helps to improve the stability of the polysilicon process, reduce cost waste, and can timely prevent erroneous data from being brought into subsequent modeling. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0076] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A semiconductor process fluctuation monitoring method, characterized in that: The following steps are involved: Providing a wafer, wherein the wafer comprises a device area and a test area divided according to a preset rule along a plane where the wafer is located; Forming a polysilicon layer on the wafer, and patterning the polysilicon layer to obtain a test structure located in the test area, wherein the test structure includes a first polysilicon pad, a polysilicon line, and a second polysilicon pad connected in sequence; Measuring the resistance of the test structure through the first polysilicon pad and the second polysilicon pad to obtain a polysilicon test resistance value of the wafer, and judging whether the polysilicon resistance fluctuation of the wafer meets the standard based on the test resistance value; Collecting the size data of the test structure, and judging whether the size of the polysilicon of the wafer meets the standard based on the size data of the test structure; When both the polysilicon resistance fluctuation and the polysilicon size of the wafer meet the standards, a dielectric layer is formed on the polysilicon layer, and the dielectric layer is chemically mechanically polished to obtain a target topography surface, and atomic force microscope test data of the target topography surface is collected; when either the polysilicon resistance fluctuation or the polysilicon size does not meet the standards, subsequent film layer deposition and atomic force microscope test data collection of the wafer are stopped; The DFM chemical mechanical polishing model is created based on the collected atomic force microscope test data.

2. The semiconductor process fluctuation monitoring method according to claim 1, characterized in that: Before or after patterning the polysilicon layer, the method further includes a step of implanting ions into the polysilicon layer to enhance the conductivity of the polysilicon layer.

3. The semiconductor process fluctuation monitoring method according to claim 1, characterized in that: The resistance value R1 of the first polysilicon pad, the resistance value R2 of the polysilicon line and the resistance value R3 of the second polysilicon pad are all in the same order of magnitude, or satisfy: R1 / R2<1 / 10, R3 / R2<1 / 10.

4. The semiconductor process fluctuation monitoring method according to claim 1, characterized in that: Judging whether the polysilicon resistance fluctuation of the wafer meets the standard based on the test resistance value includes: calculating the difference between the test resistance value and the preset resistance value, and when the difference is within the range of ±10% of the preset resistance value, it is determined that the polysilicon resistance fluctuation of the wafer meets the standard, otherwise it does not meet the standard.

5. The semiconductor process fluctuation monitoring method according to claim 1, characterized in that: Judging whether the polysilicon resistance fluctuation of the wafer meets the standard based on the test resistance value includes: obtaining polysilicon test resistance values ​​corresponding to multiple wafers from the same batch, and according to the 3σ principle of normal distribution, when the polysilicon test resistance value corresponding to a certain wafer is distributed within the range of (μ-3σ, μ+3σ), it is judged that the polysilicon resistance fluctuation of this wafer meets the standard, otherwise it is judged that it does not meet the standard, wherein σ is the standard deviation, and μ is the mean of the polysilicon test resistance values ​​corresponding to multiple wafers from the same batch.

6. The semiconductor process fluctuation monitoring method according to claim 1, characterized in that: The DFM chemical mechanical polishing model creation based on the collected atomic force microscope test data includes: Select multiple wafers whose polysilicon resistance fluctuation and polysilicon size meet the standards, collect the atomic force microscope test data corresponding to the multiple wafers for the same test point and take the average value; A DFM chemical mechanical polishing model is created based on an average value of the atomic force microscope test data corresponding to a plurality of wafers.

7. The semiconductor process fluctuation monitoring method according to claim 1, characterized in that: The size data of the test structure includes at least one of a width of the polysilicon line, a pitch of the polysilicon line, a thickness of the first polysilicon pad, and a thickness of the second polysilicon pad.

8. The semiconductor process fluctuation monitoring method according to claim 1, characterized in that: The tool used to measure the resistance of the test structure includes a probe, and the material of the portion of the probe contacting the polysilicon pad includes titanium boronitride.

9. The semiconductor process fluctuation monitoring method according to claim 1, characterized in that: The polysilicon line includes an X-direction extension line and a Y-direction extension line which are alternately arranged in a non-closed loop and connected end to end. The X-direction extension line is perpendicular to the Y-direction extension line. The length of the X-direction extension line is greater than the length of the Y-direction extension line. The ends of the extension lines at the two ends are respectively connected to the first polysilicon pad and the second polysilicon pad.

10. The semiconductor process fluctuation monitoring method according to claim 9, characterized in that: A tool used to measure the resistance of the test structure includes a probe card, and a center line connecting the first polysilicon pad and the second polysilicon pad is parallel to the Y-direction extension line.

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