Chip structure, preparation method thereof and packaging structure

Abstract

The invention relates to a chip structure, a preparation method thereof and a packaging structure. The chip structure comprises a substrate; the alignment marks are located on the front face and / or the back face of the substrate, each alignment mark comprises a coordinate axis and scales, and the multiple scales are arranged along the coordinate axis at intervals. According to the alignment mark, the preparation method thereof and the packaging structure, the alignment mark is arranged on the front face and / or the back face of the substrate, and the alignment mark comprises the coordinate axis and the scale. When the position of the chip structure is adjusted by using the alignment mark, the position of the chip structure can be finely adjusted according to the numerical value displayed by the scale, so that the efficiency of aligning a plurality of chip structures is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a chip structure and a preparation method and a packaging structure thereof. Background Art

[0002] With the development of semiconductor packaging technology, multi-layer vertical stacking packaging is becoming more and more popular. For vertically stacked packaging products, bumps are usually provided on the surface of the chip structure, so as to realize interconnection between the chip structures through the bumps.

[0003] However, during the packaging production process, the bumps are blocked by the top chip structure, which can easily cause the bumps of adjacent chip structures to be misaligned. Summary of the invention

[0004] Based on this, it is necessary to provide an alignment mark and a preparation method thereof, and a packaging structure to address the problem of misalignment of bumps of adjacent chip structures in the prior art during the packaging production process.

[0005] In order to achieve the above object, on the one hand, the present invention provides a chip structure, comprising:

[0006] substrate;

[0007] The alignment mark is located on the front side and / or the back side of the substrate. The alignment mark includes a coordinate axis and scales. A plurality of scales are arranged at intervals along the coordinate axis.

[0008] In one embodiment, the chip structure further includes: a first dielectric layer located between the coordinate axis and the scale.

[0009] In one embodiment, the chip structure includes a first metal layer, the first metal layer includes a metal pad and the scale, and the first metal layer is the outermost metal layer away from the substrate on the side of the substrate where the alignment mark is provided;

[0010] The first dielectric layer is provided with a first groove on a side away from the substrate, and the first metal layer is located in the first groove.

[0011] In one embodiment, the scale includes a scale head and a scale bottom connected to each other, the scale head extends inward from the surface of the first medium layer away from the substrate, the scale bottom is located between the scale head and the coordinate axis, and the size of the scale head is larger than the size of the scale bottom.

[0012] In one embodiment, the chip structure further includes:

[0013] A second metal layer, including the coordinate axis, is located on a side of the substrate where the alignment mark is provided, and the second metal layer is a subsurface metal layer away from the substrate;

[0014] The second dielectric layer is provided with a second groove on a side away from the substrate, and the second metal layer is located in the second groove.

[0015] In one embodiment, the alignment mark further includes a rotation axis, and the rotation axis and the coordinate axis share a coordinate origin.

[0016] In one embodiment, the rotation axis and the coordinate axis are arranged at the same level.

[0017] The present invention also provides a packaging structure, comprising at least two stacked chip structures as described above.

[0018] The present invention also provides a method for preparing a chip structure, comprising the following steps:

[0019] providing a substrate;

[0020] An alignment mark is formed on the front side and / or the back side of the substrate, wherein the alignment mark comprises a coordinate axis and scales, and a plurality of scales are arranged at intervals along the coordinate axis.

[0021] In one embodiment, forming alignment marks on the front side and / or the back side of the substrate comprises:

[0022] forming a coordinate axis on the front side and / or the back side of the substrate;

[0023] forming a first dielectric layer covering the coordinate axis;

[0024] The scale is formed on the surface of the first dielectric layer.

[0025] In one embodiment, forming the scale on the surface of the first dielectric layer includes:

[0026] Etching the first dielectric layer to form a first trench;

[0027] A first metal layer including a metal pad and the scale is formed in the first groove. On the side of the substrate where the alignment mark is provided, the first metal layer is the outermost metal layer away from the substrate and includes the metal pad and the scale.

[0028] In one embodiment, the first groove comprises a scale groove, the scale groove comprises a first sub-groove and a second sub-groove connected to each other, the first sub-groove extends inward from the upper surface of the first dielectric layer, the second sub-groove is located at the bottom of the first sub-groove, and the size of the first sub-groove is larger than the size of the second sub-groove;

[0029] The first metal layer including the metal pad and the scale is formed in the first groove, comprising:

[0030] The scale groove is filled to form the scale.

[0031] In one embodiment, forming a coordinate axis on the front side and / or the back side of the substrate comprises:

[0032] forming a second dielectric layer on the front side and / or the back side of the substrate;

[0033] forming a second trench in the second dielectric layer;

[0034] A second metal layer is filled in the second trench, wherein the second metal layer includes the coordinate axis.

[0035] In one embodiment, the second metal layer further includes a rotation axis, and the rotation axis and the coordinate axis share a coordinate origin.

[0036] In the alignment mark and preparation method thereof and the packaging structure of the present invention, the front and / or back of the substrate is provided with an alignment mark, and the alignment mark includes a coordinate axis and a scale. When the alignment mark is used to adjust the position of the chip structure, the position of the chip structure can be finely adjusted according to the value displayed on the scale, thereby improving the efficiency of aligning multiple chip structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 A schematic diagram of a packaging structure provided in an embodiment;

[0039] Figure 2 A schematic diagram of a packaging structure provided in another embodiment;

[0040] Figure 3 is a schematic diagram of an alignment mark provided in an embodiment;

[0041] Figure 4 A schematic diagram of a coordinate axis provided in an embodiment;

[0042] Figure 5 A schematic diagram of a coordinate axis provided in another embodiment;

[0043] Figure 6A schematic diagram of coordinate axes provided in yet another embodiment;

[0044] Figure 7a A schematic diagram of scale lines provided in an embodiment;

[0045] Figure 7b A schematic diagram of scale lines provided in another embodiment;

[0046] Figure 8 A schematic diagram of a chip structure provided in an embodiment;

[0047] Fig. 9 A flow chart of chip structure preparation provided in an embodiment;

[0048] Fig.10 A schematic diagram of an alignment mark design provided in an embodiment;

[0049] Fig.11 A side view of a coordinate axis provided in one embodiment;

[0050] Fig.12 is a schematic diagram of a first groove provided in an embodiment;

[0051] Fig.13 A top view of a first groove provided in an embodiment;

[0052] Fig.14 A schematic diagram of filling a first trench provided in an embodiment;

[0053] Fig.15 A schematic diagram of forming a scale provided in an embodiment;

[0054] Fig.16 FIG. 4 is a top view of an alignment mark provided in an embodiment.

[0055] Explanation of the reference numerals: packaging structure-100; chip structure-110; substrate-111; alignment mark-112; first metal material layer-1120; coordinate axis-1121; scale-1122; rotation axis-1123; scale head-1122a; scale bottom-1122b; first dielectric layer-113; second dielectric layer-114; bump-121; first groove-200; first sub-groove-210; second sub-groove-220. DETAILED DESCRIPTION

[0056] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0058] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" another element or layer, it can be directly on, adjacent to, or connected to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," or "directly connected to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be represented as a second element, component, region, layer, or portion without departing from the teachings of the present invention.

[0059] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0060] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0061] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of idealized embodiments (and intermediate structures) of the invention, and variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, embodiments of the invention should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the invention.

[0062] See also Figure 1 and Figure 2 In one embodiment, a package structure 100 is provided. The package structure 100 includes at least two chip structures 110 stacked together.

[0063] As an example, a bump 121 is provided on the surface of the chip structure 110. Adjacent chip structures 110 are connected by the bumps 121, and the bump 121 of one chip structure 110 is butted against the bump 121 of another chip structure 110, thereby forming a stacked structure. The material of the bump 121 may include a metal material. For example, the material of the bump 121 is aluminum or copper.

[0064] The bumps 121 can interconnect adjacent chip structures 110 by bonding or welding. As an example, when bonding adjacent chip structures 110, the bumps 121 can be metal pads. When welding adjacent chip structures 110, the bumps 121 can be pads.

[0065] In one embodiment, see Figure 3 The chip structure 110 may include a substrate 111 and an alignment mark 112 .

[0066] The alignment mark 112 may be located on the front side or the back side of the substrate 111. Of course, the alignment mark 112 may also be located on both the front side and the back side of the substrate 111.

[0067] As an example, the alignment mark 112 may be located in a central region of the chip structure 110 , or may be located in an edge region of the chip structure 110 .

[0068] The alignment mark 112 includes a coordinate axis 1121 and a plurality of scales 1122 . The plurality of scales 1122 may be arranged at intervals along the coordinate axis 1121 .

[0069] The coordinate axis 1121 may include two intersecting and mutually perpendicular line segments, and the intersection position may be set as the coordinate origin. Figure 4 , Figure 5 as well as Figure 6 , the figure shows different forms of the coordinate axis 1121. For example, Figure 4 The coordinate axis 1121 shown in the figure may be a cross shape. Figure 6 The coordinate axis 1121 shown in the figure may be in an "L" shape. The coordinate axis 1121 is provided with a preset direction. The preset direction may be a direction away from the origin of the coordinate.

[0070] See also Figure 7a As an example, the gap width d1 between the scales 1122 can be set smaller than the width d2 of the scales 1122, and the gap between the scales 1122 is used as a scale line for measuring the coordinate value, and the scales 1122 are used as the gap between the scale lines.

[0071] In actual processes, it is usually more difficult to miniaturize the width of a line pattern than the gap between lines. Therefore, it is more difficult to miniaturize the width of the scale 1122 than the gap between the scales 1122. Therefore, by using the gap between the scales 1122 as a scale line for measuring the coordinate value, a scale line with a smaller line width can be obtained, so that the scale value can be determined more accurately.

[0072] The line width d2 of the scale 1122 may be greater than 0.5 μm, for example. For example, the line width d2 of the scale 1122 is 0.9 μm. The gap width d1 between the scales 1122 may be in the range of 10 nm-100 nm, for example. For example, the gap width d1 between the scales 1122 is 50 nm.

[0073] Of course, in other examples, the scale 1122 can also be used as a scale line for measuring the coordinate value, and the gap between the scales 1122 can be used as the gap between the scale lines. Figure 7b At this time, there is no restriction on the size relationship between d1 and d2.

[0074] The distance between the position of each scale mark 1122 (or the gap between each scale mark 1122 ) as a scale line and the coordinate origin may be a preset distance.

[0075] When stacking and packaging adjacent chip structures 110 , a detection device such as an X-ray (X-RAY) or infrared (IR) microscope may be used to scan the alignment marks 112 on the adjacent chip structures 110 , thereby obtaining a pattern of the alignment marks 112 .

[0076] As an example, the adjacent chip structures 110 include a chip structure located at an upper layer and a chip structure located at a lower layer. At this time, the lower chip structure can be fixed, and the upper chip structure is aligned with the lower chip structure by moving the upper chip structure.

[0077] At this time, after scanning the alignment mark 112 on the adjacent chip structure 110, the images of the alignment mark 112 of the lower chip structure and the alignment mark 112 of the upper chip structure can be obtained, and then the coordinates of the origin of the coordinate of the upper alignment mark 112 on the coordinate axis of the lower alignment mark 112 can be obtained through the scale 1122 of the lower chip structure. At this time, the coordinates of the origin of the coordinate of the upper alignment mark 112 on the coordinate axis of the lower alignment mark 112 can be determined through the coordination of the coordinate axis of the upper alignment mark 112 and the scales 1122 (or the gaps between the scales 1122) of the lower alignment mark 112 as scale lines.

[0078] Alternatively, after scanning the alignment mark 112 on the adjacent chip structure 110, images of the alignment mark 112 of the lower chip structure and the alignment mark 112 of the upper chip structure can be obtained, and the coordinates of the origin of the coordinate of the alignment mark 112 of the lower chip structure on the coordinate axis of the upper alignment mark 112 can be obtained through the scale 1122 of the upper alignment mark 112. At this time, the coordinates of the origin of the coordinate of the lower alignment mark 112 on the coordinate axis of the upper alignment mark 112 are determined by matching the coordinate axis of the lower alignment mark 112 with the scales 1122 of the upper alignment mark 112 (or the gaps between the scales 1122) serving as scale lines.

[0079] According to the coordinates obtained in the above steps, the specific distances that the upper chip structure needs to move in different directions can be obtained. Finally, the upper chip structure is moved according to the above distances, so that the upper chip structure and the lower chip structure are accurately aligned.

[0080] When the front side (or back side) of the substrate 111 is used to connect with other chip structures 110, alignment marks 112 may be provided on the front side (or back side) of the substrate 111. When both the front side and back side of the substrate 111 may be used to connect with other chip structures 110, alignment marks 112 may be provided on both the front side and back side of the substrate 111. At this time, the two layers of alignment marks 112 are close in position in the vertical direction, so that it is convenient to form clear images of the two layers of alignment marks 112 through detection devices such as X-rays or infrared microscopes.

[0081] As an example, the scales 1122 (or the gaps between the scales 1122) as scale lines can be arranged evenly so that the upper chip structure can move evenly. At this time, each scale 1122 (or the gaps between the scales 1122) as scale lines can be marked with a corresponding value, and the distances between adjacent scales 1122 (or the gaps between the scales 1122) as scale lines can also be set to a default unit distance, so that there is no need to mark specific values.

[0082] As another example, the scales 1122 (or the gaps between the scales 1122) as scale lines can also be set to be arranged more closely near the coordinate origin and more sparsely away from the coordinate origin, so as to adapt to the different distances of movement of the adjustment chip structure 110. For example, when the upper chip structure needs to move a long distance, the scales 1122 (or the gaps between the scales 1122) with a looser arrangement can be referred to first to roughly move the upper chip structure. When the coordinate origin of the upper chip structure is close to the coordinate origin of the lower chip structure, the scales 1122 (or the gaps between the scales 1122) with a tighter arrangement can be referred to to achieve a finer movement of the upper chip structure.

[0083] As an example, the coordinate axis 1121 and the scale 1122 may be made of metal material. The metal material may be, for example, titanium, tungsten, copper or aluminum. At this time, when the alignment mark 112 is scanned by an X-ray or infrared microscope, the metal material may better reflect the light to obtain a clearer alignment mark 112 pattern.

[0084] In this embodiment, since the alignment mark 112 of the chip structure 110 includes a coordinate axis 1121 and a plurality of scales 1122, the distance that needs to be adjusted for the chip structure 110 can be directly observed. When two chip structures 110 need to be aligned, the scale 1122 can be scanned by a device such as an X-ray or infrared microscope to obtain the precise distance that any chip structure 110 needs to move, so as to accurately adjust the position of the chip structure 110. In this way, the chip structure 110 can be accurately moved based on the scale 1122, so that the two chip structures 110 can be better packaged by bonding or welding, etc., and the damage to the packaging or bonding structure caused by the misalignment of the chip structure 110 is reduced.

[0085] At the same time, since the precise distance that the chip structure 110 needs to move can be obtained, the chip structures 110 can be aligned by moving the chip structures once or a few times, thereby improving work efficiency.

[0086] In one embodiment, the chip structure 110 includes a first dielectric layer 113 .

[0087] The first dielectric layer 113 is located between the coordinate axis 1121 and the scale 1122. At this time, the coordinate axis 1121 and the scale 1122 are located in different film layers and are independent of each other, so as to facilitate process processing.

[0088] As an example, the coordinate axis 1121 may also be located on a side of the first dielectric layer 113 close to the substrate 111 , and the scale 1122 may be located on a side of the first dielectric layer 113 far from the substrate 111 .

[0089] Of course, the coordinate axis 1121 may be located on the side of the first dielectric layer 113 away from the substrate 111, and the scale 1122 may be located on the side of the first dielectric layer 113 close to the substrate 111. This embodiment does not limit the specific positional relationship between the coordinate axis 1121, scale 1122, first dielectric layer 113 and substrate 111.

[0090] The material of the first dielectric layer 113 may include insulating materials such as transparent silicon oxide, which facilitates observation of the coordinate axis 1121 or the scale 1122 located below the first dielectric layer 113 .

[0091] In one embodiment, the chip structure 110 includes a first metal layer. The first metal layer is the outermost metal layer away from the substrate 111. The first metal layer includes scales 1122 and metal pads (not shown).

[0092] At this time, the coordinate axis 1121 is located on a side of the first dielectric layer 113 close to the substrate 111 , and the scale 1122 is located on a side of the first dielectric layer 113 far from the substrate 111 .

[0093] When the alignment mark 112 is located on the front side of the substrate 111, the first metal layer is also located on the front side of the substrate 111. When the alignment mark 112 is located on the back side of the substrate 111, the first metal layer is also located on the back side of the substrate 111. Alternatively, when the alignment mark 112 is located on both the front side and the back side of the substrate 111, the first metal layer may also be located on both the front side and the back side of the substrate 111.

[0094] Meanwhile, a first trench 200 is provided on the first dielectric layer 113 at a side away from the substrate, and the first metal layer is located in the first trench 200 .

[0095] As an example, the first dielectric layer 113 includes a plurality of first trenches 200 , the first metal layer located in a portion of the first trenches 200 is a metal pad, and the first metal layer located in another portion of the first trenches 200 is a scale 1122 .

[0096] At this time, the chip structures 110 can be stacked by bonding. The metal pads, scales 1122 and first dielectric layer 113 of adjacent chip structures 110 can be hybrid bonded.

[0097] See also Fig.14 and Fig.15 When preparing the first metal layer in the first groove 200 , a grinding method can be used to flatten the upper surface of the first metal material layer 1120 and the upper surface of the first dielectric layer 113 to obtain a relatively flat surface of the chip structure 110 , thereby making it easier to bond adjacent chip structures 110 .

[0098] In this embodiment, since the first metal layer includes the metal pad and the scale 1122, the scale 1122 can be obtained at the same time as the metal pad, and the step of separately preparing the scale 1122 is omitted, saving the time cost of preparing the alignment scale 112. Moreover, the scale 1122 is located in the outermost metal layer, so it is easy to detect and identify by X-ray or infrared microscope.

[0099] Of course, in other embodiments, the coordinate axis 1121 is located on the side of the first dielectric layer 113 away from the substrate 111, the scale 1122 is located on the side of the first dielectric layer 113 close to the substrate 111, and the first metal layer may also include the coordinate axis 1121 and the metal pad. The device of the outermost first metal layer is not limited here.

[0100] In one embodiment, see Figure 8 The scale 1122 includes a scale head 1122a and a scale bottom 1122b that are connected to each other.

[0101] The scale head 1122a extends inward from the surface of the first dielectric layer 113 away from the substrate, and the scale bottom 1122b is located between the scale head 1122a and the coordinate axis 1121. The scale bottom 1122b may be separated from the coordinate axis 1121 by the first dielectric layer 113, and of course, the scale bottom 1122b may also be connected to the coordinate axis 1121.

[0102] The size of the scale head 1122a is larger than the size of the scale bottom 1122b. At this time, the larger scale head 1122a can be easily identified by equipment such as X-rays or infrared microscopes. Moreover, the materials of the scale head 1122a and the scale bottom 1122b can be metal. When using equipment such as X-rays or infrared microscopes to identify, the scale bottom 1122b enhances the reflected light on the surface of the scale head 1122a, so that the X-ray or infrared microscope can receive more reflected light, thereby increasing the pattern clarity of the entire scale 1122.

[0103] Of course, in other embodiments, the size of the scale head 1122a may be smaller than the size of the scale bottom 1122b. In this case, the entire scale 1122 is narrow at the top and wide at the bottom. Alternatively, the size of the scale head 1122a is the same as the size of the scale bottom 1122b, so that the more regular shape is more convenient for the preparation of the scale 1122.

[0104] As an example, the cross-sectional shape of the scale 1122 may be circular or elliptical. The scale 1122 with a circular or elliptical cross-sectional shape has no corners, and the preparation process is simple, and there will be no cracks due to uneven stress of the scale 1122 caused by setting corners.

[0105] Of course, this embodiment does not limit the cross-sectional shape of the scale 1122. The cross-sectional shape of the scale 1122 may also be set to a square, an angular shape, an irregular shape, etc.

[0106] In one embodiment, the chip structure 110 includes a second dielectric layer 114 and a second metal layer (not shown). The second metal layer includes a coordinate axis 1121 .

[0107] On the side of the substrate 111 where the alignment mark 1121 is provided, the second metal layer is a subsurface metal layer away from the substrate 111. Meanwhile, the second dielectric layer 114 and the second metal layer may be located on the side of the first dielectric layer 113 close to the substrate 111.

[0108] The second dielectric layer 114 is provided with a second groove on a side away from the substrate, and the second metal layer is located in the second groove, that is, the second metal layer is embedded in the second dielectric layer 114. The second dielectric layer 114 includes a plurality of second grooves, and the second metal layer located in some of the second grooves is a structure such as conductive wiring, and the second metal layer located in another part of the second grooves is a coordinate axis 1121.

[0109] The material of the second dielectric layer 114 may include insulating materials such as silicon oxide and silicon nitride. The material of the second metal layer may include conductive materials such as copper, aluminum or tungsten.

[0110] When preparing the chip structure 110 , the second metal layer includes the coordinate axis 1121 and the conductive wiring and other structures, so that the coordinate axis 1121 is prepared at the same time as the conductive wiring and other structures are prepared, without adding a process for preparing the coordinate axis 1121 separately.

[0111] In one embodiment, see Figure 3 The alignment mark 112 further includes a rotation axis 1123. The rotation axis 1123 is a plurality of line segments that can measure the rotation angle.

[0112] The coordinate axis 1121 may include a horizontal axis and a vertical axis that intersect and are perpendicular to each other, and the rotation axis 1123 may form a plurality of different angles with the horizontal axis or the vertical axis.

[0113] As an example, the rotation axis 1123 may share a coordinate origin with the coordinate axis 1121 .

[0114] When stacking and packaging adjacent chip structures 110, the adjacent chip structures 110 include a chip structure located at an upper layer and a chip structure located at a lower layer. At this time, after scanning the upper chip structure and the lower chip structure using an X-ray or infrared microscope or other equipment, the coordinate axis 1121 (horizontal axis or vertical axis) of the lower chip structure can be used as a reference. When the horizontal axis of the upper chip structure and the horizontal axis (or vertical axis) of the lower chip structure have different directions, it is necessary to refer to the rotation axis 1123 of the lower alignment mark to determine the angle at which the upper chip structure needs to be rotated, and rotate the upper chip structure according to the specific angle so that the horizontal axis of the upper chip structure and the horizontal axis of the lower chip structure have the same direction.

[0115] The upper chip structure may be rotated according to the rotation axis 1123 first and then moved to a suitable position according to the coordinate axis 1121 , or the upper chip structure may be moved to a suitable position according to the coordinate axis 1121 first and then rotated according to the rotation axis 1123 .

[0116] In another example, the rotation axis 1123 may also be separated from the coordinate axis 1121 , that is, the rotation axis 1123 and the coordinate axis 1121 have different coordinate origins.

[0117] For example, the rotation axis 1123 includes at least one reference axis and multiple angle axes. The reference axis has a set direction. When the reference axis of the upper chip structure and the reference axis of the lower chip structure have the same direction, it is considered that the upper chip structure and the lower chip structure do not need to rotate.

[0118] The reference axis and the multiple angle axes have a common intersection, which is the coordinate origin of the rotation axis 1123. The angle between the angle axis and the reference axis is the angle displayed by the rotation axis 1123. When the reference axis of the upper chip structure is inconsistent with the reference axis of the lower chip structure, the upper reference axis is rotated to an angle consistent with the direction of the lower reference axis based on the multiple angle axes, and then the upper chip structure is rotated to better package or bond the upper chip structure with the lower chip structure.

[0119] In another example, the rotation axis 1123 and the coordinate axis 1121 are separated, so that the angle to be rotated and the position to be moved can be observed more clearly. At this time, the upper chip structure can be rotated using the rotation axis 1123 so that the two reference axes are in the same direction, and then the upper chip structure can be moved using the coordinate axis 1121. The upper chip structure can also be moved using the coordinate axis 1121 first, and then the upper chip structure can be rotated using the rotation axis 1123 so that the two reference axes are in the same direction. Ultimately, the accuracy of bonding or packaging the upper chip structure and the lower chip structure can be improved.

[0120] As an example, the multiple axes of the rotation axis 1123 can show angles such as 30 degrees, 45 degrees, 60 degrees and 120 degrees. The above data are only used as examples. In actual embodiments, the angle of the rotation axis 1123 is not limited to the above data. At this time, the rotation axis 1123 can be set with a specific angle mark for each axis, or it can be considered that the angles between adjacent rotation axes are the same so that no specific angle mark is set. For example, the angles between adjacent rotation axes are all 30 degrees, or the angles between adjacent axes are all 15 degrees or 45 degrees, etc.

[0121] As an example, the rotation axis 1123 can be disposed in the same layer as the coordinate axis 1121. For example, the rotation axis 1123 and the coordinate axis 1121 are located in the second metal layer. Of course, the rotation axis 1123 and the coordinate axis 1121 can also be located in different film layers, which is not limited here.

[0122] In this embodiment, a rotation axis 1123 is provided in the alignment mark 112 . When the chip structures 110 are stacked, the specific angle at which the chip structures 110 need to be rotated can be obtained according to the rotation axis 1123 , thereby aligning the chip structures 110 .

[0123] Based on the same inventive concept, please refer to Fig. 9 In one embodiment, a method for preparing a chip structure 110 is provided, comprising the following steps:

[0124] Step S100: providing a substrate 111 .

[0125] Step S200 : forming an alignment mark 112 on the front and / or back side of the substrate 111 , wherein the alignment mark 112 comprises a coordinate axis 1121 and scales 1122 , and a plurality of scales 1122 are arranged at intervals along the coordinate axis 1121 .

[0126] In step S100, the base 111 may include a substrate and a plurality of film layers located on the substrate. Fig.10 Before the process is performed on the substrate, the position of the alignment mark 112 can be reserved on the base 111 in advance. Fig.16 In the final chip structure, the alignment mark 112 is located at the reserved position, so that the visual interference caused by other structures of the film layer when measuring the alignment mark 112 can be eliminated. For example, the reserved area of ​​the alignment mark 112 can be a square with a side length of about 10um to 20um. The above data is only for example display, and the area shape and size of the alignment mark 112 shall be subject to the specific implementation.

[0127] In step S200, refer to Figure 3The alignment mark 112 is formed on the front or back of the substrate 111, or the alignment mark 112 is formed on the front and back of the substrate 111. As an example, when the front of the substrate 111 is used for packaging, the alignment mark 112 is formed on the front of the substrate 111.

[0128] See also Figure 3 , the alignment mark 112 includes a coordinate axis 1121 and a plurality of scales 1122. The plurality of scales 1122 are arranged at intervals along the coordinate axis 1121. The coordinate axis 1121 may include at least two intersecting and mutually perpendicular line segments, and the intersection position is the coordinate origin. The coordinate axis 1121 may include a horizontal axis and a vertical axis. Both the horizontal axis and the vertical axis may be provided with a positive direction.

[0129] When stacking and packaging adjacent chip structures 110 , a detection device such as an X-ray machine or an infrared microscope may be used to scan the alignment marks 112 on the adjacent chip structures 110 to obtain patterns of two alignment marks 112 of the adjacent chip structures 110 .

[0130] See also Figure 4 , Figure 5 as well as Figure 6 , the figure shows different forms of the coordinate axis 1121. For example, Figure 4 The coordinate axis 1121 shown in the figure may be a cross shape. Figure 6 The coordinate axis 1121 shown in the figure can be "L" shaped.

[0131] Each scale 1122 may represent the distance between the position and the origin of the coordinate axis 1121. As an example, multiple scales 1122 may be arranged evenly, and in this case, the chip structure 110 may move evenly. Multiple scales 1122 may also be arranged more closely near the origin of the coordinate axis 1121 and more sparsely away from the origin of the coordinate axis 1121, so as to adapt to different distances of movement of the chip structure 110.

[0132] For example, the adjacent chip structure 110 includes a chip structure located at the upper layer and a chip structure located at the lower layer. When scanning the alignment marks 112 of the adjacent chip structures, the image shows that the two alignment marks 112 are misaligned. At this time, the coordinates of the coordinate origin of the upper alignment mark 112 on the coordinate axis of the lower alignment mark 112 are obtained through the scale 1122 of the lower chip structure. At this time, the coordinates of the coordinate origin of the upper alignment mark 112 on the coordinate axis of the lower alignment mark 112 are determined by matching the coordinate axis of the upper alignment mark 112 with the scale of the lower alignment mark 112. According to the coordinates, the specific distances that the upper chip structure needs to move in different directions can be obtained, and finally the upper chip structure is moved according to the aforementioned distance. When the two alignment marks 112 overlap, it can be considered that the upper chip structure and the lower chip structure are aligned.

[0133] In this process, when multiple scales 1122 are evenly arranged, the upper chip structure can be evenly moved. When multiple scales 1122 are unevenly arranged, the upper chip structure can be roughly moved by referring to the scales 1122 that are more sparsely arranged. When the coordinate origin of the upper chip structure is close to the coordinate origin of the lower chip structure, the scales 1122 that are more densely arranged can be referred to to achieve a more precise movement of the upper chip structure.

[0134] At the same time, since the coordinate axis 1121 includes a horizontal axis and a vertical axis, each of the horizontal axis and the vertical axis can be provided with a positive direction or a negative direction. Exemplarily, after obtaining the coordinate of the origin of the coordinate of the upper alignment mark 112 on the coordinate axis of the lower alignment mark 112 through the scale 1122 of the lower chip structure, the coordinate of the origin of the coordinate of the upper alignment mark 112 on the coordinate axis of the lower alignment mark 112 in the positive direction or the negative direction can be determined based on the positive direction or the negative direction.

[0135] The alignment mark 112 can be located at the center of the front or back of the substrate 111, so as to confirm the overall position of the chip structure 110 during the production process of the chip structure 110, thereby moving the chip structure 110. Of course, the alignment mark 112 can also be located at a corner of the front or back of the substrate 111.

[0136] In this embodiment, since the alignment mark 112 of the chip structure 110 includes a coordinate axis 1121 and a plurality of scales 1122, when packaging or bonding the chip structure 110, the distance that the chip structure 110 needs to be moved can be directly observed based on the coordinate axis 1121 and the plurality of scales 1122, and the chip structure 110 can be accurately moved to an appropriate position, so as to better package the two chip structures 110 by bonding or welding. In this embodiment, there is no need to repeatedly scan the chip structure 110 and repeatedly move the chip structure 110, thereby improving the efficiency of aligning the chip structure 110.

[0137] In one embodiment, step S200 includes:

[0138] Step S210 : forming a coordinate axis 1121 on the front surface and / or the back surface of the substrate 111 .

[0139] Step S220 : forming a first dielectric layer 113 covering the coordinate axis 1121 .

[0140] Step S230 : forming scales 1122 on the surface of the first dielectric layer 113 .

[0141] In step S210, the coordinate axis 1121 and the scale 1122 may be located in different film layers and are independent of each other, thereby facilitating process processing.

[0142] See also Fig.11 The coordinate axis 1121 may be formed on the front or back side of the substrate 111, or the coordinate axis 1121 may be formed on the front and back side of the substrate 111. The material of the coordinate axis 1121 may include metal.

[0143] In step S220, refer to Fig.12 , the first dielectric layer 113 is deposited on the entire surface of the coordinate axis 1121 , so that the first dielectric layer 113 covers the coordinate axis 1121 .

[0144] In step S230 , a scale 1122 is formed on the surface of the first dielectric layer 113 to achieve a layered arrangement of the scale 1122 and the coordinate axis 1121 .

[0145] In this embodiment, since the scale 1122 is relatively small and the coordinate axis 1121 is relatively large, the scale 1122 and the coordinate axis 1121 are arranged in layers, and the first dielectric layer 113 is used to isolate the scale 1122 and the coordinate axis 1121, which can facilitate process processing.

[0146] Of course, in other cases, the scale 1122 may be formed first, and then the first dielectric layer 113 may be formed on the scale 1122, and the coordinate axis 1121 may be formed on the first dielectric layer 113. Similarly, the scale 1122 and the coordinate axis 1121 may be arranged in layers.

[0147] In one embodiment, step S230 includes:

[0148] Step S231 : etching the first dielectric layer 113 to form a first trench 200 .

[0149] Step S232 : forming a first metal layer including a metal pad and a scale 1122 in the first trench 200 , and providing an alignment mark 112 on the substrate 111 . The first metal layer is the outermost metal layer away from the substrate 111 .

[0150] In step S231, refer to Fig.12 and Fig.13 The first dielectric layer 113 may be etched using any one of reactive ion etching, inductively coupled plasma etching, or high concentration plasma etching methods.

[0151] In step S232, refer to Fig.16 , the first trench 200 may be filled to form a first metal layer.

[0152] At this time, the chip structures 110 can be stacked by bonding. The first metal layer includes scales 1122 and metal pads. The metal pads, scales 1122 and first dielectric layers 113 of adjacent chip structures 110 can be hybrid bonded.

[0153] When the first trench 200 is filled, the scale 1122 and the metal pad are formed at the same time, so that the scale 1122 does not need to be prepared separately, thus saving time for preparing the scale 1122 .

[0154] As an example, see Fig.14 , a first metal material layer 1120 can be deposited in the first groove 200 and on the entire surface of the first dielectric layer 113. The deposition process may include, but is not limited to, one or more of a chemical vapor deposition process, an atomic layer deposition process, a high-density plasma deposition process, a plasma enhanced deposition process, and a spin-coated dielectric layer. Afterwards, please refer to Figure 16, and then the first metal material layer 1120 located on the upper surface of the first dielectric layer 113 is removed by grinding or the like, and the first metal material layer 1120 located in the first groove 200 is retained to form a scale 1122. At the same time, after grinding, a flat upper surface of the first dielectric layer 113 and an upper surface of the scale 1122 can be obtained, which is convenient for connection with other chip structures 110. The scale 1122 is only shown in the figure as an example. It should be understood that a plurality of metal pads are provided at different positions of the same film layer as the scale 1122.

[0155] In one embodiment, see Fig.12 and Fig.13 The first groove 200 includes a scale groove. Of course, the first groove 200 also includes a metal pad groove. The scale groove includes a first sub-groove 210 and a second sub-groove 220 that are connected. The first sub-groove 210 extends inward from the upper surface of the first dielectric layer 113, and the second sub-groove 220 is located at the bottom of the first sub-groove 210.

[0156] At this time, step S232 includes:

[0157] Step S2320: Fill the scale groove to form scale 1122.

[0158] Filling the scale grooves means filling the first sub-grooves 210 and the second sub-grooves 220 to form interconnected scales 1122. Figure 8 The partial scale 1122 located in the first sub-groove 210 is a scale head 1122a, and the partial scale 1122 located in the second sub-groove 220 is a scale bottom 1122b.

[0159] When forming the first groove 200, the first sub-groove 210 is first etched, and then the second sub-groove 220 is etched. When forming the second sub-groove 220, the first dielectric layer 113 at the bottom of the second sub-groove 220 can be retained, that is, the first dielectric layer 113 can be separated between the scale bottom 1122b and the coordinate axis 1121. Of course, the second sub-groove 220 can also penetrate the first dielectric layer 113, that is, the scale bottom 1122b is in contact with the coordinate axis 1121.

[0160] The size of the first sub-groove 210 can be larger than the size of the second sub-groove 220, so that the size of the scale head 1122a is larger than the size of the scale bottom 1122b. The larger scale head 1122a can be easily identified by equipment such as X-rays or infrared microscopes. Moreover, the materials of the scale head 1122a and the scale bottom 1122b can be metal, and the scale bottom 1122b enhances the reflected light on the surface of the scale head 1122a, so that the X-ray or infrared microscope can receive more reflected light, thereby increasing the pattern clarity of the entire scale 1122.

[0161] Of course, the size of the first sub-groove 210 can also be smaller than the size of the second sub-groove 220. In this case, the entire scale 1122 is narrow at the top and wide at the bottom. Alternatively, the size of the first sub-groove 210 is the same as the size of the second sub-groove 220, so that a more regular shape is more convenient for preparing the scale 1122.

[0162] The cross-sectional shape of the first sub-groove 210 and the second sub-groove 220 can be circular or elliptical, so that the process of preparing the first sub-groove 210 and the second sub-groove 220 is relatively simple, and when filling the first sub-groove 210 and the second sub-groove 220, there will be no cracks due to uneven stress of the material caused by setting the corners.

[0163] Of course, this embodiment does not limit the cross-sectional shapes of the first sub-groove 210 and the second sub-groove 220. For example, the cross-sectional shapes of the first sub-groove 210 and the second sub-groove 220 may also be square, angular, or irregular.

[0164] In one embodiment, step S210 includes:

[0165] Step S211 : forming a second dielectric layer 114 on the front side and / or the back side of the substrate 111 .

[0166] Step S212 : forming a second trench in the second dielectric layer 114 .

[0167] Step S213 : Filling the second trench with a second metal layer, wherein the second metal layer includes a coordinate axis 1121 .

[0168] In step S211 , a second dielectric layer 114 is formed on the front side or the back side of the substrate 111 , or the second dielectric layer 114 is formed on both the front side or the back side of the substrate 111 .

[0169] The material of the second dielectric layer 114 may include insulating materials such as silicon oxide, silicon nitride, aluminum oxide or silicon oxynitride.

[0170] In step S212 , the method of forming the second trench may be similar to the method of forming the first trench 200 , and will not be described in detail herein.

[0171] In step S213, the second groove is filled to form the coordinate axis 1121. As an example, when the second groove is filled to form the coordinate axis 1121, the second metal material layer can be first deposited on the entire surface. Then, the second metal material layer outside the second groove is removed, and the second metal material layer inside the second groove is retained to form the coordinate axis 1121. At this time, the first metal layer is the outermost metal layer, and the second metal layer is the sub-surface metal layer.

[0172] The second metal layer includes not only the coordinate axis 1121, but also other conductive structures (e.g., conductive wiring) in the same layer. It can be understood that the other conductive structures in the same layer are formed simultaneously with the coordinate axis 1121, so that the coordinate axis 1121 is also prepared while the conductive wiring and other structures are prepared, without adding a process for preparing the coordinate axis 1121 separately.

[0173] The second grooves may include not only vertical grooves but also rotation grooves. The vertical grooves are filled to form a vertical coordinate axis 1121, and the rotation grooves are filled to form a rotation axis 1123. At this time, the coordinate axis 1121 and the rotation axis 1123 are arranged at the same layer.

[0174] Of course, the coordinate axis 1121 and the rotation axis 1123 may also be located in different layers. In this case, it is necessary to respectively etch grooves in different layers and then fill the grooves to form the coordinate axis 1121 and the rotation axis 1123 .

[0175] The rotation axis 1123 may share a coordinate origin with the coordinate axis 1121 , or the rotation axis 1123 may be separated from the coordinate axis 1121 , that is, the rotation axis 1123 and the coordinate axis 1121 have different coordinate origins.

[0176] As an example, the rotation axis 1123 can show angles such as 30 degrees, 45 degrees, 60 degrees, and 120 degrees. The above data are only used as examples. In actual embodiments, the angle of the rotation axis 1123 is not limited to the above data. At this time, the rotation axis 1123 can be set with a specific angle mark for each axis, or it can be considered that the angles between adjacent axes are the same so that no specific angle mark is set. For example, the angles between adjacent axes are all 30 degrees, or the angles between adjacent axes are all 45 degrees.

[0177] It should be understood that although Fig. 9 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Fig. 9At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0178] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0179] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A chip structure, characterized in that: include: substrate; The alignment mark is located on the front side and / or the back side of the substrate. The alignment mark includes a coordinate axis and scales. A plurality of scales are arranged at intervals along the coordinate axis.

2. The chip structure according to claim 1, characterized in that: The chip structure also includes: The first dielectric layer is located between the coordinate axis and the scale.

3. The chip structure according to claim 2, characterized in that: The chip structure comprises a first metal layer, the first metal layer comprises a metal pad and the scale, and the first metal layer is the outermost metal layer away from the substrate on the side of the substrate where the alignment mark is provided; The first dielectric layer is provided with a first groove on a side away from the substrate, and the first metal layer is located in the first groove.

4. The chip structure according to claim 3, characterized in that: The scale includes a scale head and a scale bottom connected to each other. The scale head extends inward from a surface of the first dielectric layer away from the substrate. The scale bottom is located between the scale head and the coordinate axis. The size of the scale head is larger than that of the scale bottom.

5. The chip structure according to claim 3, characterized in that: The chip structure also includes: A second metal layer, including the coordinate axis, is located on a side of the substrate where the alignment mark is provided, and the second metal layer is a subsurface metal layer away from the substrate; The second dielectric layer is provided with a second groove on a side away from the substrate, and the second metal layer is located in the second groove.

6. The chip structure according to claim 1, characterized in that: The alignment mark further includes a rotation axis, and the rotation axis and the coordinate axis share a coordinate origin.

7. The chip structure according to claim 6, characterized in that: The rotation axis and the coordinate axis are arranged at the same layer.

8. The chip structure according to claim 1, characterized in that: The cross-sectional shape of the scale is circular or elliptical.

9. A packaging structure, characterized in that: The invention comprises at least two chip structures as claimed in any one of claims 1 to 8 which are stacked.

10. A method for preparing a chip structure, characterized in that: The steps include: providing a substrate; An alignment mark is formed on the front side and / or the back side of the substrate, wherein the alignment mark comprises a coordinate axis and scales, and a plurality of scales are arranged at intervals along the coordinate axis.

11. The method for preparing a chip structure according to claim 10, characterized in that: The step of forming an alignment mark on the front side and / or the back side of the substrate comprises: forming a coordinate axis on the front side and / or the back side of the substrate; forming a first dielectric layer covering the coordinate axis; The scale is formed on the surface of the first dielectric layer.

12. The method for preparing a chip structure according to claim 11, characterized in that: The step of forming the scale on the surface of the first dielectric layer comprises: Etching the first dielectric layer to form a first trench; A first metal layer including a metal pad and the scale is formed in the first groove. On the side of the substrate where the alignment mark is provided, the first metal layer is the outermost metal layer away from the substrate.

13. The method for preparing a chip structure according to claim 12, characterized in that: The first groove comprises a scale groove, the scale groove comprises a first sub-groove and a second sub-groove connected to each other, the first sub-groove extends inward from the upper surface of the first dielectric layer, the second sub-groove is located at the bottom of the first sub-groove, and the size of the first sub-groove is larger than the size of the second sub-groove; The first metal layer including the metal pad and the scale is formed in the first groove, comprising: The scale groove is filled to form the scale.

14. The method for preparing a chip structure according to claim 11, characterized in that: The forming of a coordinate axis on the front side and / or the back side of the substrate comprises: forming a second dielectric layer on the front side and / or the back side of the substrate; forming a second trench in the second dielectric layer; A second metal layer is filled in the second trench, wherein the second metal layer includes the coordinate axis.

15. The method for preparing a chip structure according to claim 14, characterized in that: The second metal layer further includes a rotation axis, and the rotation axis and the coordinate axis share a coordinate origin.

Images