Packaging structure and packaging method

Abstract

The invention discloses a packaging structure and a packaging method, and the packaging structure comprises a first substrate which comprises a first surface, and one or more first chips are bonded on the first surface; the second substrate is stacked on the first surface of the first substrate, the second substrate comprises a second surface facing the first surface and a third surface arranged back to the second surface, and one or more second chips are bonded on the third surface; the first heat dissipation structure is located between the first substrate and the second substrate and connected with the first substrate and the second substrate. According to the embodiment of the invention, the first heat dissipation structure is respectively connected with the first substrate and the second substrate, so that when the first chip works, the first heat dissipation structure can conduct heat generated by the first chip to the first substrate and the second substrate, heat dissipation is realized through the first substrate and the second substrate, the heat dissipation performance of the first chip is improved, and the service life of the first chip is prolonged. Therefore, the performance of the first chip can be improved, and the performance of the packaging structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a packaging structure and a packaging method. Background Art

[0002] In today's era of rapid technological development, chips play a key role in high-performance computing, artificial intelligence, communications, etc. As people's demand for computing power, data processing speed and intelligence continues to increase, the power consumption of chips is also increasing.

[0003] In some complex systems, multiple chips and modules may need to be integrated into one package to achieve higher performance and functional integration. However, existing chip manufacturing technology has limitations in heat dissipation, which restricts the placement of multiple chips in one package.

[0004] How to reduce the chip packaging size and make the chip obtain good heat dissipation effect and performance has become a problem that needs to be solved urgently. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a packaging structure and a packaging method to reduce the size of the packaging structure and improve the heat dissipation effect and performance of the packaging structure.

[0006] To solve the above problems, an embodiment of the present invention provides a packaging structure, including: a first substrate, including a first surface, on which one or more first chips are bonded; a second substrate, stacked on the first surface of the first substrate, the second substrate including a second surface facing the first surface, and a third surface arranged opposite to the second surface, on which one or more second chips are bonded; a first heat dissipation structure, located between the first substrate and the second substrate, and connected to the first substrate and the second substrate respectively.

[0007] Correspondingly, an embodiment of the present invention also provides a packaging method, including: providing a first substrate and a second substrate, the first substrate including a first surface, one or more first chips bonded to the first surface, and the second substrate including a second surface and a third surface arranged opposite to each other; the second surface of the second substrate is facing the first surface of the first substrate, and the second substrate is stacked on the first surface of the first substrate; a first heat dissipation structure is arranged between the first substrate and the second substrate, the first heat dissipation structure is respectively connected to the first substrate and the second substrate; and one or more second chips are bonded to the third surface of the second substrate.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] The packaging structure provided in an embodiment of the present invention includes: a first substrate, a second substrate, and a first heat dissipation structure located between the first substrate and the second substrate. One or more first chips are bonded to the first surface of the first substrate. The first heat dissipation structure is respectively connected to the first substrate and the second substrate, so that when the first chip is working, the first heat dissipation structure can conduct the heat generated by the first chip to the first substrate and the second substrate, so as to achieve heat dissipation through the first substrate and the second substrate, thereby improving the heat dissipation performance of the first chip, which is beneficial to improving the performance of the first chip, and further beneficial to improving the performance of the packaging structure.

[0010] In the packaging method provided in an embodiment of the present invention, a first substrate and a second substrate are provided, a first chip is bonded to the first surface of the first substrate, the second surface of the second substrate is facing the first surface of the first substrate, and the second substrate is stacked on the first surface of the first substrate, and a first heat dissipation structure is provided between the first substrate and the second substrate, the first heat dissipation structure is respectively connected to the first substrate and the second substrate, so that when the first chip is working, the first heat dissipation structure can conduct the heat generated by the first chip to the first substrate and the second substrate, so as to achieve heat dissipation through the first substrate and the second substrate, thereby improving the heat dissipation performance of the first chip, which is beneficial to improving the performance of the first chip, and further beneficial to improving the performance of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a structural schematic diagram of an embodiment of a packaging structure of the present invention;

[0012] Figure 2 yes Figure 1 A local enlarged view of area A;

[0013] Figure 3 A schematic diagram of metal connectors being discretely arranged around the first chip;

[0014] Figures 4 to 11 is a schematic structural diagram corresponding to each step in the first embodiment of the packaging method of the present invention;

[0015] Figures 12 to 15 is a schematic structural diagram corresponding to each step in the second embodiment of the packaging method of the present invention;

[0016] Fig.16 is a top view of the positioning plate;

[0017] Fig.17 yes Fig.16 A partial enlarged view of area B. DETAILED DESCRIPTION

[0018] As can be seen from the background technology, the size, heat dissipation effect and performance of the current packaging structure still need to be improved.

[0019] In order to solve the above technical problems, an embodiment of the present invention provides a packaging structure, including: a first substrate, including a first surface, on which one or more first chips are bonded; a second substrate, stacked on the first surface of the first substrate, the second substrate including a second surface facing the first surface, and a third surface arranged opposite to the second surface, on which one or more second chips are bonded; a first heat dissipation structure, located between the first substrate and the second substrate, and connected to the first substrate and the second substrate respectively.

[0020] The scheme disclosed in the embodiment of the present invention includes: a first substrate, a second substrate, and a first heat dissipation structure located between the first substrate and the second substrate. One or more first chips are bonded to the first surface of the first substrate. The first heat dissipation structure is respectively connected to the first substrate and the second substrate, so that when the first chip is working, the first heat dissipation structure can conduct the heat generated by the first chip to the first substrate and the second substrate, so as to achieve heat dissipation through the first substrate and the second substrate, thereby improving the heat dissipation performance of the first chip, which is beneficial to improving the performance of the first chip, and further beneficial to improving the performance of the packaging structure.

[0021] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0022] Figure 1 is a schematic structural diagram of an embodiment of a packaging structure of the present invention, Figure 2 yes Figure 1 A partial enlarged view of area A. Figure 3 Schematic diagram of metal connectors discretely arranged around the first chip.

[0023] refer to Figure 1 In this embodiment, the packaging structure includes: a first substrate 100, including a first surface 101, on which one or more first chips 110 are bonded; a second substrate 200, stacked on the first surface 101 of the first substrate 100, the second substrate 200 includes a second surface 201 facing the first surface 101, and a third surface 202 arranged opposite to the second surface 201, on which one or more second chips 210 are bonded; a first heat dissipation structure 300, located between the first substrate 100 and the second substrate 200, and connected to the first substrate 100 and the second substrate 200, respectively.

[0024] The first substrate 100 and the second substrate 200 are used to provide a process basis for forming a packaging structure.

[0025] In this embodiment, the first substrate 100 and the second substrate 200 are organic substrates.

[0026] The first surface 101 is used to realize bonding between the first chip 110 and the first substrate 100 ; the third surface 202 is used to realize bonding between the second chip 210 and the second substrate 200 .

[0027] The first chip 110 and the second chip 210 are packaged together and electrically connected to each other to achieve specific functions.

[0028] In this embodiment, the first chip 110 and the first substrate 100, and the second chip 210 and the second substrate 200 are connected by solder balls (not shown) or bumps (not shown). As an embodiment, the material of the solder balls includes tin. In other embodiments, other feasible methods can also be used for connection, which are not limited here.

[0029] In this embodiment, one or both of the first substrate 100 and the second substrate 200 have a first pseudo wiring structure 330. When the first substrate 100 has the first pseudo wiring structure 330, the first surface 101 exposes the first connection end 331 of the first pseudo wiring structure 330 located on one side of the first surface 101. When the second substrate 200 has the first pseudo wiring structure 330, the second surface 201 exposes the first connection end 331 of the first pseudo wiring structure 330 located on one side of the second surface 201.

[0030] The first connection end 331 of the first dummy wiring structure 330 is used to bond with the metal connection component of the first heat dissipation structure 300 .

[0031] In a specific embodiment, the second substrate 200 has a first dummy wiring structure 330 , and the third surface 202 exposes a second connection end 332 of the first dummy wiring structure 330 located at one side of the third surface 202 .

[0032] The second connection end 332 of the first dummy wiring structure 330 is used to bond with the heat dissipation pin of the second heat dissipation structure.

[0033] It should be noted that the first pseudo wiring structure 330 includes an interconnection layer (not marked) extending in the transverse direction, an interconnection through-hole structure (not marked) extending in the longitudinal direction, and a connection terminal (pad), and the interconnection layers of different layers, as well as the interconnection layers and the connection terminals are electrically connected through the interconnection through-hole structure.

[0034] In this embodiment, the first substrate 100 has a second pseudo wiring structure 340, and the first surface 101 exposes the third connection end 341 of the second pseudo wiring structure 340 located on one side of the first surface 101; the first chip 110 is located above the second pseudo wiring structure 340, and some pins of the first chip 110 are bonded to the third connection end 341; the second substrate 200 has a third pseudo wiring structure 345, and the third surface 202 exposes the fourth connection end 342 of the third pseudo wiring structure 345 located on one side of the third surface 202; the second chip 210 is located above the third pseudo wiring structure 345, and some pins of the second chip 210 are bonded to the fourth connection end 342.

[0035] Some pins of the first chip 110 are bonded to the third connection end 341 of the second dummy wiring structure 340 , so that the heat generated by the first chip 110 during operation can be transferred to the first substrate 100 through the second dummy wiring structure 340 , thereby further improving the heat dissipation performance of the first chip 110 .

[0036] Some pins of the second chip 210 are bonded to the fourth connection end 342 of the third pseudo wiring structure 345, so that the heat generated by the second chip 210 during operation can be conducted to the second substrate 200 through the third pseudo wiring structure 345, and the heat can also be conducted to the external environment through the second heat dissipation structure 310, which is beneficial to improving the heat dissipation performance of the second chip 210.

[0037] It should be noted that the second pseudo wiring structure 340 and the third pseudo wiring structure 345 both include an interconnection layer (not marked) extending in the transverse direction, an interconnection through-hole structure (not marked) extending in the longitudinal direction, and a connection end, and the interconnection layers of different layers, as well as the interconnection layers and the connection ends are electrically connected through the interconnection through-hole structure.

[0038] It can be understood that both the first substrate 100 and the second substrate 200 have wiring structures (not shown) for realizing the function of electrical connection with an external circuit.

[0039] The first heat dissipation structure 300 is respectively connected to the first substrate 100 and the second substrate 200, so that when the first chip 110 is working, the first heat dissipation structure 300 can conduct the heat generated by the first chip 110 to the first substrate 100 and the second substrate 200, so as to dissipate heat to the external environment through heat conduction of the first substrate 100 and the second substrate 200, thereby improving the heat dissipation performance of the first chip 110, which is beneficial to improving the performance of the first chip 110, and further beneficial to improving the performance of the packaging structure.

[0040] In other embodiments, the first substrate has a second pseudo wiring structure, the first surface exposes the third connection end of the second pseudo wiring structure located on one side of the first surface; the first chip is located above the second pseudo wiring structure, and some pins of the first chip are bonded to the third connection end; or, the second substrate has a third pseudo wiring structure, the third surface exposes the fourth connection end of the third pseudo wiring structure located on one side of the third surface; the second chip is located above the third pseudo wiring structure, and some pins of the second chip are bonded to the fourth connection end.

[0041] In this embodiment, the first heat dissipation structure 300 includes: a metal connector 301 located at a side of the first chip 110 , and the metal connector 301 is bonded to a first connection end 331 of the first dummy wiring structure 330 .

[0042] Among them, the metal connector 301 can be a block structure or a columnar structure; when the aspect ratio of the metal connector 301 is less than or equal to 2, the metal connector 301 is a block structure, and when the aspect ratio of the metal connector 301 is greater than 2, the metal connector 301 is a columnar structure.

[0043] The bonding of the first dummy wiring structure 330 and the metal connector 301 is beneficial to better conduct the heat generated by the first chip 110 during operation to the first substrate 100 or the second substrate 200, thereby further improving the heat dissipation performance of the first chip.

[0044] As an example, the material of the metal connecting member 301 includes copper.

[0045] Copper has good thermal conductivity and is inexpensive, and can quickly transfer the heat generated by the first chip 110 , that is, can effectively disperse and transfer the heat, thereby further improving the heat dissipation performance of the first chip 110 .

[0046] Specifically, the number of the metal connectors 301 on each side of the first chip 110 is multiple, and the metal connectors 301 are discretely arranged around the first chip 110 (eg Figure 3 As shown), it is beneficial to better conduct the heat generated by the first chip 110 to the first substrate 100 and the second substrate 200 through the metal connector 301; moreover, the metal connector 301 is discretely arranged around the first chip 110, which is beneficial to reduce the changes to the existing process.

[0047] More specifically, the metal connectors 301 are arranged in a matrix around the first chip 110, or, on either side of the first chip 110, the metal connectors 301 include a first type of metal connectors (not marked) and a second type of metal connectors (not marked) having different lateral dimensions, and the second type of metal connectors and the first type of metal connectors are arranged alternately, which helps to increase the number of the metal connectors 301, thereby improving the effect of conducting the heat generated by the first chip 110 to the first substrate 100 and the second substrate 200 through the metal connectors 301, and also helps to reduce changes to the existing process flow.

[0048] Moreover, the metal connectors 301 are arranged in a matrix around the first chip 110, or the first type of metal connectors and the second type of metal connectors with different lateral sizes are arranged alternately on either side of the first chip 110, so that when a plastic sealing layer is formed between the first substrate 100 and the second substrate 200, it is convenient to fill the plastic sealing layer. It should be noted that the plastic sealing layer can be a heat-conducting plastic sealing layer or a plastic sealing layer having only a plastic sealing function.

[0049] It should be noted that the spacing P between adjacent metal connectors 301 (eg Figure 3 If the spacing P between adjacent metal connectors 301 is too small, it is easy to increase the process difficulty of forming the metal connectors 301 on the side of the first chip. Therefore, in this embodiment, there are multiple metal connectors 301 on one side of the first chip 110, and the spacing P between adjacent metal connectors 301 is greater than 50 microns.

[0050] It should also be noted that the distance S (eg, Figure 3 If the distance S between the metal connector 301 on one side of the first chip 110 and the first chip 110 is too small, it is easy to increase the process difficulty of forming the metal connector 301. Therefore, in this embodiment, the distance S between the metal connector 301 on one side of the first chip 110 and the first chip 110 is greater than 50 microns.

[0051] As an example, the number of the metal connectors 301 on one side of the first chip 110 is greater than 4, which is conducive to better conducting the heat generated by the first chip 110 to the first substrate 100 and the second substrate 200 through the metal connectors 301.

[0052] In this embodiment, the metal connector 301 and the first connection end 331 are connected via a solder ball (not shown) or a bump (not shown). In other embodiments, other feasible connection methods may also be used, which are not limited here.

[0053] In this embodiment, the first heat dissipation structure 300 further includes: a thermally conductive plastic sealing layer 302 filled between the first substrate 100 and the second substrate 200 , and the thermally conductive plastic sealing layer 302 covers the side wall of the metal connector 301 .

[0054] The thermally conductive plastic layer 302 is filled between the first substrate 100 and the second substrate 200 , and can further conduct the heat generated by the first chip 110 during operation to the first substrate 100 and the second substrate 200 , thereby further improving the heat dissipation performance of the first chip 110 .

[0055] Specifically, the material of the thermal conductive plastic layer 302 includes epoxy molding compound (EMC) containing aluminum oxide (Al 2 O 3 ).

[0056] Epoxy molding compounds containing alumina have good thermal conductivity and are commonly used filling materials in packaging structures.

[0057] It should be noted that the material of the thermal conductive plastic sealing layer 302 may also be other plastic sealing materials with high thermal conductivity, wherein the plastic sealing material with high thermal conductivity refers to a plastic sealing material with a thermal conductivity greater than or equal to 3W / (m·k).

[0058] It is understandable that the first heat dissipation structure 300 may include a metal connector 301 and a thermally conductive plastic sealing layer 302 , or may only include a metal connector.

[0059] In other embodiments, a plastic encapsulation layer is filled between the first substrate and the second substrate, and the plastic encapsulation layer covers the side walls of the metal connector.

[0060] In this embodiment, the packaging structure also includes a second heat dissipation structure 310, bonded to the third surface 202 of the second substrate 200, and the second heat dissipation structure 310 includes: a heat dissipation cover plate 311, located above the second chip 210; a heat dissipation pin 312, located between the heat dissipation cover plate 311 and the second substrate 200, and located on the side of the second chip 210, and the heat dissipation pin 312 is bonded to the second connection end 332 exposed on the third surface 202.

[0061] The heat dissipation pins 312 of the second heat dissipation structure 310 are bonded to the second connection ends 332 exposed on the third surface 202, which is conducive to transferring the heat transferred to the second substrate 200 through the first dummy wiring structure 330 to the external environment through the second heat dissipation structure 310, thereby facilitating further improving the heat dissipation performance of the first chip 110. Moreover, the heat dissipation pins 312 are located on the side of the second chip 210, which can also transfer the heat generated by the second chip 210 during operation to the external environment through the second heat dissipation structure 310, thereby facilitating also improving the heat dissipation performance of the second chip 210.

[0062] As an example, there are multiple second chips 210, and the heat dissipation pins 312 are located around each of the second chips 210, which is beneficial to further improve the heat dissipation performance of the second chip 210. In other embodiments, there are multiple second chips, and the heat dissipation pins are located around a chipset consisting of several second chips.

[0063] Specifically, Figure 2 As shown, the bottom of the heat dissipation pin 312 has one or more notches 3121 ; the packaging structure also includes: a welding material 315 located between the heat dissipation pin 312 and the second connection end 332 exposed on the third surface 202 , and the welding material 315 is also filled in the notch 3121 .

[0064] The bottom of the heat dissipation pin 312 has one or more notches 3121, which is beneficial to increase the contact area between the bottom of the heat dissipation pin 312 and the welding material 315, thereby helping to increase the bonding strength between the heat dissipation pin 312 and the second connecting end 332, and correspondingly helps to increase the bonding strength between the heat dissipation pin 312 and the second substrate 200, and further helps to balance the warping of the second substrate 200 through the rigidity of the second heat dissipation structure 310.

[0065] Moreover, compared with the solution in which the recess is formed on the side wall of the heat dissipation pin, the processing technology of forming one or more recesses 3121 at the bottom of the heat dissipation pin 312 is simple, which is conducive to improving the process efficiency.

[0066] More specifically, the shape of the notch 3121 includes one or both of a cone and a quadrangular pyramid, which is conducive to further reducing the difficulty of forming the notch 3121 at the bottom of the heat dissipation pin 312 .

[0067] In this embodiment, the packaging structure further includes: a passive component 350 , which is bonded to the first surface 101 of the side of the first chip 110 and to the second surface 201 .

[0068] The passive component 350 is used to play a specific role in the operation of the first chip 110 and the second chip 210 .

[0069] Specifically, the passive component 350 may be one or more of a resistor, a capacitor or an inductor.

[0070] It should be noted that the passive component 350 is bonded to the first surface 101 or the second surface 201 through a bump. In other embodiments, other feasible bonding methods may also be adopted.

[0071] In this embodiment, the packaging structure further includes an inter-board connector 351 located between the first substrate 100 and the second substrate 200 and located on the side of the first heat dissipation structure 300. The inter-board connector 351 is electrically connected to the first substrate 100 and the second substrate 200 respectively.

[0072] The second substrate 200 is bonded to the first substrate 100 through the inter-board connector 351 to achieve electrical connection between the first substrate 100 and the second substrate 200, which is beneficial to reducing the difficulty of bonding the first substrate 100 and the second substrate 200, and also beneficial to reducing the difficulty of electrical connection between the first substrate 100 and the second substrate 200.

[0073] It should be noted that the inter-board connector 351 includes one or more of a conductive bump, a conductive column and an adapter board, which is conducive to selecting one or more of the conductive bump, the conductive column and the adapter board as the inter-board connector 351 according to the heat dissipation requirements of the first chip 110, the thickness of the first chip 110, and the electrical connection requirements between the first substrate 100 and the second substrate 200.

[0074] For example: when a high-density electrical connection is required between the first substrate 100 and the second substrate 200, the inter-board connector 351 is a transfer board; when the heat dissipation requirement of the first chip 110 is high and the thickness of the first chip 110 is small, the inter-board connector 351 is a conductive bump; when the heat dissipation requirement of the first chip 110 is high and the thickness of the first chip 110 is large, the inter-board connector 351 is a conductive column.

[0075] In addition, when the inter-board connector 351 includes an adapter board, the adapter board is electrically connected to the first substrate 100 and the second substrate 200 respectively through solder balls or bumps.

[0076] Correspondingly, in other embodiments, the plastic sealing layer also covers the side walls of the inter-board connector.

[0077] In this embodiment, the first substrate 100 further includes a fourth surface 102 disposed opposite to the first surface 101 . Solder balls (not shown) are disposed on the fourth surface 102 . The solder balls are bonded to the dummy wiring structure and the wiring structure in the first substrate 100 .

[0078] The solder balls are used to electrically connect the first substrate 100 to other external circuits, and are also used to transfer the heat of the first substrate 100 to other external circuits through the solder balls, thereby improving the heat dissipation performance of the first substrate 100 .

[0079] Correspondingly, the present invention also provides a packaging method. Figures 4 to 11 It is a schematic structural diagram corresponding to each step in the first embodiment of the packaging method of the present invention.

[0080] refer to Figures 4 to 5 , providing a first substrate 100 and a second substrate 200, wherein the first substrate 100 includes a first surface 101, and one or more first chips 110 (such as Figure 4 As shown), the second substrate 200 includes a second surface 201 and a third surface 202 (as shown) disposed opposite to each other. Figure 5 shown).

[0081] The first substrate 100 and the second substrate 200 are used to provide a process basis for forming a packaging structure.

[0082] In this embodiment, the first substrate 100 and the second substrate 200 are organic substrates.

[0083] The first surface 101 is used to realize bonding between the first chip 110 and the first substrate 100 ; the third surface 202 is used to realize bonding between the second chip and the second substrate 200 later.

[0084] The first chip 110 and the second chip subsequently bonded to the third surface 202 form a packaging structure and are electrically connected to each other, thereby achieving specific functions.

[0085] In this embodiment, the first chip 110 and the first substrate 100 are connected by a solder ball (not shown) or a bump (not shown). As an embodiment, the material of the solder ball includes tin. In other embodiments, other feasible methods can also be used for connection, which are not limited here.

[0086] In this embodiment, in the step of providing the first substrate 100 and the second substrate 200, one or both of the first substrate 100 and the second substrate 200 have a first pseudo wiring structure 330, and a metal connector 301 is arranged on the first surface 101 of the first substrate 100 or the second surface 201 of the second substrate 200; wherein, in the case where the first substrate 100 has the first pseudo wiring structure 330, the first surface 101 exposes the first connection end 331 of the first pseudo wiring structure 330 located on one side of the first surface 101, and in the case where the second substrate 200 has the first pseudo wiring structure 330, the second surface 201 exposes the first connection end 331 of the first pseudo wiring structure 330 located on one side of the second surface 201, and the metal connector 301 is bonded to the first connection end 331 of the first pseudo wiring structure 330.

[0087] Among them, the metal connector 301 can be a block structure or a columnar structure; when the aspect ratio of the metal connector 301 is less than or equal to 2, the metal connector 301 is a block structure, and when the aspect ratio of the metal connector 301 is greater than 2, the metal connector 301 is a columnar structure.

[0088] The metal connector 301 is used to bond with the first connection end 331 of the first dummy wiring structure 330 .

[0089] In this embodiment, in the step of providing the second substrate 200 , a plurality of second substrates 200 are provided, and each of the second substrates 200 includes a unit structure (not marked).

[0090] Specifically, a plurality of second substrates 200 are provided, each of which includes a unit structure; or, a second substrate 200 is provided, the second substrate 200 includes a plurality of unit structures, and the plurality of unit structures are singulated to separate the individual unit structures to form a plurality of second substrates 200, each of which includes a unit structure.

[0091] More specifically, a second substrate 200 is provided, and after the second substrate 200 includes a plurality of unit structures and before the plurality of unit structures are singulated, it also includes: forming solder balls or bumps on the second surface 201 of the second substrate 200; in the step of singulating the plurality of unit structures and separating the individual unit structures, each unit structure includes a solder ball or a bump.

[0092] In a specific embodiment, in the step of providing the second substrate 200 , the second substrate 200 has a first dummy wiring structure 330 , and the third surface 202 exposes a second connection end 332 of the first dummy wiring structure 330 located at one side of the third surface 202 .

[0093] The second connection end 332 of the first dummy wiring structure 330 is used for subsequent bonding with the heat dissipation pin of the second heat dissipation structure.

[0094] It should be noted that the first pseudo wiring structure 330 includes an interconnection layer (not marked) extending in the transverse direction, an interconnection through-hole structure (not marked) extending in the longitudinal direction, and a connection end, and the interconnection layers of different layers, and the interconnection layers and the connection ends are electrically connected through the interconnection through-hole structure.

[0095] In this embodiment, in the step of providing the first substrate 100 and the second substrate 200, the first substrate 100 has a second dummy wiring structure 340, the first surface 101 exposes a third connection end 341 of the second dummy wiring structure 340 located on one side of the first surface 101, and the second substrate 200 has a third dummy wiring structure 345 ， The third surface 202 exposes a fourth connection end 342 of the third dummy wiring structure 345 located on one side of the third surface 202 . The first chip 110 is located above the second dummy wiring structure 340 , and some pins of the first chip 110 are bonded to the third connection end 341 .

[0096] Some pins of the first chip 110 are bonded to the third connection end 341 of the second dummy wiring structure 340 , so that the heat generated by the subsequent operation of the first chip 110 can be transferred to the first substrate 100 through the second dummy wiring structure 340 , thereby further improving the heat dissipation performance of the first chip 110 .

[0097] The fourth connection end 342 of the third dummy wiring structure 345 is used for subsequent bonding with some pins of the second chip.

[0098] It should be noted that the second pseudo wiring structure 340 and the third pseudo wiring structure 345 both include an interconnection layer (not marked) extending in the transverse direction, an interconnection through-hole structure (not marked) extending in the longitudinal direction, and a connection end, and the interconnection layers of different layers, as well as the interconnection layers and the connection ends are electrically connected through the interconnection through-hole structure.

[0099] It can be understood that both the first substrate 100 and the second substrate 200 have wiring structures (not shown) for realizing the function of electrical connection with an external circuit.

[0100] In other embodiments, in the step of providing the first substrate, the first substrate has a second pseudo wiring structure, the first surface exposes the third connection end of the second pseudo wiring structure located on one side of the first surface, the first chip is located above the second pseudo wiring structure, and some pins of the first chip are bonded to the third connection end; or, in the step of providing the second substrate, the second substrate has a third pseudo wiring structure, and the third surface exposes the fourth connection end of the third pseudo wiring structure located on one side of the third surface.

[0101] In the step of providing the first substrate 100 and the second substrate 200, a passive component 350 (eg, Figure 4 ), and a passive component 350 (as shown) is bonded to the second surface of the second substrate 200 Figure 5 shown).

[0102] The passive component 350 is used to play a specific role in the operation of the first chip 110 and the second chip.

[0103] Specifically, the passive component 350 may be one or more of a resistor, a capacitor or an inductor.

[0104] It should be noted that the passive component 350 is bonded to the first surface 101 or the second surface 201 through a bump. In other embodiments, other feasible bonding methods may also be adopted.

[0105] refer to Figure 6 , the second surface 201 of the second substrate 200 faces the first surface 101 of the first substrate 100 , and the second substrate 200 is stacked on the first surface 101 of the first substrate 100 .

[0106] The second substrate 200 is stacked on the first surface 101 of the first substrate 100 to provide a space for disposing a first heat dissipation structure 300 between the first substrate 100 and the second substrate 200 .

[0107] In this embodiment, the step of stacking the second substrate 200 on the first surface 101 of the first substrate 100 includes: setting an inter-board connector 351 on the first substrate 100 or the second substrate 200, and the inter-board connector 351 electrically connects the first substrate 100 or the second substrate 200; bonding the second substrate 200 to the first substrate 100 through the inter-board connector 351, so that the inter-board connector 351 is electrically connected to the first substrate 100 and the second substrate 200 respectively.

[0108] The second substrate 200 is bonded to the first substrate 100 through the inter-board connector 351 to achieve electrical connection between the first substrate 100 and the second substrate 200, which is beneficial to reducing the difficulty of bonding the first substrate 100 and the second substrate 200, and also beneficial to reducing the difficulty of electrical connection between the first substrate 100 and the second substrate 200.

[0109] As an example, an inter-board connector 351 is provided on the first surface 101 of the first substrate 100, and the inter-board connector 351 is electrically connected to the first substrate 100; in the process of bonding the second substrate 200 to the first substrate 100, the second substrate 200 is bonded to the surface of the inter-board connector 351 facing away from the first substrate 100.

[0110] It should be noted that the inter-board connector 351 includes one or more of a conductive bump, a conductive column and an adapter board, which is conducive to selecting one or more of a conductive bump, a conductive column and an adapter board as the inter-board connector 351 according to the heat dissipation requirements of the first chip 110, the thickness of the first chip 110, and the electrical connection requirements between the first substrate 100 and the second substrate 200.

[0111] For example: when a high-density electrical connection is required between the first substrate 100 and the second substrate 200, the inter-board connector 351 is a transfer board; when the heat dissipation requirement of the first chip 110 is high and the thickness of the first chip 110 is small, the inter-board connector 351 is a conductive bump; when the heat dissipation requirement of the first chip 110 is high and the thickness of the first chip 110 is large, the inter-board connector 351 is a conductive column.

[0112] In addition, when the inter-board connector 351 includes an adapter board, the adapter board is electrically connected to the first substrate 100 and the second substrate 200 respectively through solder balls or bumps.

[0113] In this embodiment, the step of stacking the second substrate 200 on the first surface 101 of the first substrate 100 includes: setting an inter-board connector 351 on the first substrate 100 or the second substrate 200, wherein the inter-board connector 351 is a columnar structure, and the inter-board connector 351 is electrically connected to the first substrate 100 or the second substrate 200; bonding the second substrate 200 to the first substrate 100 through the inter-board connector 351, so that the inter-board connector 351 is electrically connected to the first substrate 100 and the second substrate 200 respectively; wherein the metal connector 301 is a columnar structure, and a columnar structure used as the metal connector 301 and a columnar structure used as the inter-board connector 351 are set in the same step.

[0114] The inter-board connector 351 being a columnar structure means that the inter-board connector 351 is a conductive column.

[0115] When both the inter-board connector 351 and the metal connector 301 are columnar structures, providing a columnar structure for serving as the metal connector 301 and a columnar structure for serving as the inter-board connector 351 in the same step is beneficial for saving process steps and improving the bonding output per hour (Units Per Hour, UPH).

[0116] refer to Figures 7 and 8 , and combined with reference Figure 6 A first heat dissipation structure 300 is provided between the first substrate 100 and the second substrate 200 , and the first heat dissipation structure 300 is connected to the first substrate 100 and the second substrate 200 , respectively.

[0117] The first heat dissipation structure 300 is respectively connected to the first substrate 100 and the second substrate 200, so that when the first chip 110 is working, the first heat dissipation structure 300 can conduct the heat generated by the first chip 110 to the first substrate 100 and the second substrate 200, so as to dissipate heat to the external environment through heat conduction of the first substrate 100 and the second substrate 200, thereby improving the heat dissipation performance of the first chip 110, which is beneficial to improving the performance of the first chip 110, and further beneficial to improving the performance of the packaging structure.

[0118] In this embodiment, in the step of providing the first substrate 100 and the second substrate 200, one or both of the first substrate 100 and the second substrate 200 has a first pseudo wiring structure 330, and a metal connector 301 is provided on the first surface 101 of the first substrate 100 or the second surface 201 of the second substrate 200; accordingly, the step of providing the first heat dissipation structure 300 between the first substrate 100 and the second substrate 200 includes: in the process of stacking the second substrate 200 on the first surface 101 of the first substrate 100, the metal connector 301 is located between the first substrate 100 and the second substrate 200, and is connected to the first substrate 100 and the second substrate 200 respectively, and the metal connector 301 serves as the first heat dissipation structure 300. And the metal connector 301 is bonded to the first connection end 331 of the first pseudo wiring structure 330.

[0119] The metal connector 301 is bonded to the first dummy wiring structure 330 , which is beneficial to better conduct the heat generated by the first chip 110 during operation to the first substrate 100 or the second substrate 200 , thereby further improving the heat dissipation performance of the first chip.

[0120] As an example, the material of the metal connecting member 301 includes copper.

[0121] Copper has good thermal conductivity and is inexpensive, and can quickly transfer the heat generated by the first chip 110 , that is, can effectively disperse and transfer the heat, thereby further improving the heat dissipation performance of the first chip 110 .

[0122] Specifically, the number of the metal connectors 301 on each side of the first chip 110 is multiple, and the metal connectors 301 are discretely arranged around the first chip 110 (eg Figure 3 As shown), it is beneficial to better conduct the heat generated by the first chip 110 to the first substrate 100 and the second substrate 200 through the metal connector 301; moreover, the metal connector 301 is discretely arranged around the first chip 110, which is beneficial to reduce the changes to the existing process.

[0123] More specifically, the metal connectors 301 are arranged in a matrix around the first chip 110, or, on either side of the first chip 110, the metal connectors 301 include a first type of metal connector (not indicated) and a second type of metal connector (not indicated) having different lateral dimensions, and the second type of metal connectors and the first type of metal connectors are arranged alternately, which is beneficial to increase the number of the metal connectors 301, thereby improving the effect of conducting the heat generated by the first chip 110 to the first substrate 100 and the second substrate 200 through the metal connectors 301, and is also beneficial to reduce the modification of the existing process.

[0124] Moreover, the metal connectors 301 are arranged in a matrix around the first chip 110, or the first type of metal connectors and the second type of metal connectors with different lateral sizes are arranged alternately on either side of the first chip 110, so that when a plastic sealing layer is formed between the first substrate 100 and the second substrate 200, it is beneficial to fill the plastic sealing layer. It should be noted that the plastic sealing layer can be a heat-conducting plastic sealing layer or a plastic sealing layer having only a plastic sealing function.

[0125] It should be noted that the spacing P between adjacent metal connectors 301 should not be too small. If the spacing P between adjacent metal connectors 301 is too small, it is easy to increase the process difficulty of forming the metal connectors 301 on the side of the first chip. Therefore, in this embodiment, the number of metal connectors 301 on one side of the first chip 110 is multiple, and the spacing P between adjacent metal connectors 301 is greater than 50 microns.

[0126] It should also be noted that the distance S between the metal connector 301 on one side of the first chip 110 and the first chip 110 should not be too small or too large. If the distance S between the metal connector 301 on one side of the first chip 110 and the first chip 110 is too small, it is easy to increase the process difficulty of forming the metal connector 301. Therefore, in this embodiment, the distance S between the metal connector 301 on one side of the first chip 110 and the first chip 110 is greater than 50 microns.

[0127] As an example, the number of the metal connectors 301 on one side of the first chip 110 is greater than 4, which is conducive to better conducting the heat generated by the first chip 110 to the first substrate 100 and the second substrate 200 through the metal connectors 301.

[0128] In this embodiment, the step of setting up a first heat dissipation structure 300 located between the first substrate 100 and the second substrate 200 includes: after the second substrate 200 is bonded to the first substrate 100 through the inter-board connector 351, a thermal conductive plastic sealing layer 302 is filled between the first substrate 100 and the second substrate 200, and the thermal conductive plastic sealing layer 302 covers the side wall of the metal connector 301 and the side wall of the inter-board connector 351, and the thermal conductive plastic sealing layer 302 serves as the first heat dissipation structure 300.

[0129] The thermally conductive plastic layer 302 is filled between the first substrate 100 and the second substrate 200 , and can further conduct the heat generated by the first chip 110 during operation to the first substrate 100 and the second substrate 200 , thereby further improving the heat dissipation performance of the first chip 110 .

[0130] Specifically, the material of the thermal conductive plastic sealing layer 302 is an epoxy plastic sealing compound containing aluminum oxide.

[0131] Epoxy molding compounds containing alumina have good thermal conductivity and are commonly used filling materials in packaging structures.

[0132] It should be noted that the material of the thermal conductive plastic sealing layer 302 may also be other plastic sealing materials with high thermal conductivity, wherein the plastic sealing material with high thermal conductivity refers to a plastic sealing material with a thermal conductivity greater than or equal to 3W / (m·k).

[0133] It should also be noted that in the step of providing the second substrate 200, a plurality of second substrates 200 are provided, each of which includes a unit structure. Accordingly, in the step of forming the thermal conductive plastic sealing layer 302, the thermal conductive plastic sealing layer 302 is also located between adjacent unit structures.

[0134] It is understandable that the first heat dissipation structure 300 may include a metal connector 301 and a thermally conductive plastic sealing layer 302 , or may only include a metal connector.

[0135] In other embodiments, after the second substrate is bonded to the first substrate through the inter-board connector, a plastic encapsulation layer is filled between the first substrate and the second substrate, and the plastic encapsulation layer covers the side walls of the metal connector and the side walls of the inter-board connector. Accordingly, when multiple second substrates 200 are provided, each of which includes a unit structure, the plastic encapsulation layer is also located between adjacent unit structures.

[0136] In this embodiment, in the step of providing the second substrate 200, a plurality of second substrates 200 are provided, each of which includes a unit structure. Accordingly, after providing the first heat dissipation structure 300 between the first substrate 100 and the second substrate 200, the packaging method further includes: cutting the first substrate 100 and the thermally conductive plastic sealing layer 302 to form a plurality of independent packaging units, wherein the packaging unit includes one or more first chips 110 and the first heat dissipation structure 300.

[0137] The packaging unit is used to provide a basis for subsequently forming a packaging structure.

[0138] refer to Fig. 9 , one or more second chips 210 are bonded on the third surface 202 of the second substrate 200 .

[0139] In this embodiment, after the first substrate 100 and the thermally conductive plastic sealing layer 302 are cut, one or more second chips 210 are bonded on the third surface 202 of the second substrate 200 to facilitate the transfer of the cut packaging structure to a tray in an automated manner.

[0140] In other embodiments, after one or more second chips are bonded on the third surface of the second substrate, the first substrate and the thermal conductive plastic sealing layer may be cut to form a plurality of independent packaging units.

[0141] In this embodiment, in the step of providing the first substrate 100 and the second substrate 200, the first substrate 100 has a second dummy wiring structure 340, the first surface 101 exposes a third connection end 341 of the second dummy wiring structure 340 located on one side of the first surface 101, and the second substrate 200 has a third dummy wiring structure 345 ，The third surface 202 exposes the fourth connection end 342 of the third dummy wiring structure 345 located on one side of the third surface 202, the first chip 110 is located above the second dummy wiring structure 340, and some pins of the first chip 110 are bonded to the third connection end 341. Accordingly, in the step of bonding one or more second chips 210 on the third surface 202 of the second substrate 200, the second chip 210 is located above the third dummy wiring structure 345, and some pins of the second chip 210 are bonded to the fourth connection end 342.

[0142] Some pins of the second chip 210 are bonded to the fourth connection end 342 of the third pseudo wiring structure 345, so that the heat generated by the second chip 210 during operation can be conducted to the second substrate 200 through the third pseudo wiring structure 345, and the heat can also be conducted to the external environment through the second heat dissipation structure formed subsequently, which is beneficial to improving the heat dissipation performance of the second chip 210.

[0143] In other embodiments, in the step of providing the second substrate, the second substrate has a third pseudo wiring structure, and the third surface exposes a fourth connection end of the third pseudo wiring structure located on one side of the third surface; correspondingly, in the step of bonding one or more second chips on the third surface of the second substrate, the second chip is located above the third pseudo wiring structure, and some pins of the second chip are bonded to the fourth connection end.

[0144] refer to Fig.10 In this embodiment, after bonding one or more second chips 210 to the third surface 202 of the second substrate 200, the packaging method further includes: bonding a second heat dissipation structure 310 to the third surface 202 of the second substrate 200, the second heat dissipation structure including 310: a heat dissipation cover plate 311, located above the second chip 210; heat dissipation pins 312, located between the heat dissipation cover plate 311 and the second substrate 200, and located on the side of the second chip 210; in the step of bonding the second heat dissipation structure 310 to the third surface 202 of the second substrate 200, the heat dissipation pins 312 are bonded to the second connection ends 332 exposed on the third surface 202.

[0145] The heat dissipation pins 312 of the second heat dissipation structure 310 are bonded to the second connection ends 332 exposed on the third surface 202, which is conducive to transferring the heat transferred to the second substrate 200 through the first dummy wiring structure 330 to the external environment through the second heat dissipation structure 310, thereby facilitating further improving the heat dissipation performance of the first chip 110. Moreover, the heat dissipation pins 312 are located on the side of the second chip 210, which can also transfer the heat generated by the second chip 210 during operation to the external environment through the second heat dissipation structure 310, thereby facilitating also improving the heat dissipation performance of the second chip 210.

[0146] As an example, there are multiple second chips 210, and the heat dissipation pins 312 are located around each of the second chips 210, which is beneficial to further improve the heat dissipation performance of the second chip 210. In other embodiments, there are multiple second chips, and the heat dissipation pins are located around a chipset consisting of several second chips.

[0147] Specifically, Figure 2 As shown, the bottom of the heat dissipation pin 312 has one or more notches 3121 ; the heat dissipation pin 312 is bonded to the second connection end 332 exposed on the third surface 202 by welding material 315 , and the welding material 315 is also filled in the notches 3121 .

[0148] The bottom of the heat dissipation pin 312 has one or more notches 3121, which is beneficial to increase the contact area between the bottom of the heat dissipation pin 312 and the welding material 315, thereby helping to increase the bonding strength between the heat dissipation pin 312 and the second connecting end 332, and correspondingly helps to increase the bonding strength between the heat dissipation pin 312 and the second substrate 200, and further helps to balance the warping of the second substrate 200 through the rigidity of the second heat dissipation structure 310.

[0149] Moreover, compared with the solution in which the recess is formed on the side wall of the heat dissipation pin, the processing technology of forming one or more recesses 3121 at the bottom of the heat dissipation pin 312 is simple, which is conducive to improving the process efficiency.

[0150] More specifically, the shape of the notch 3121 includes one or both of a cone and a quadrangular pyramid, which is conducive to further reducing the difficulty of forming the notch 3121 at the bottom of the heat dissipation pin 312 .

[0151] refer to Fig.11 In this embodiment, in the step of providing the first substrate 100, the first substrate 100 further includes a fourth surface 102 (eg, Figure 4After bonding the second heat dissipation structure 310 on the third surface 202 of the second substrate 200, it also includes: setting solder balls (not shown) on the fourth surface 102, and the solder balls are bonded to the pseudo wiring structure and the wiring structure in the first substrate 100.

[0152] The solder balls are used to electrically connect the first substrate 100 to other external circuits, and are also used to transfer the heat of the first substrate 100 to other external circuits through the solder balls, thereby improving the heat dissipation performance of the first substrate 100 .

[0153] Figures 12 to 15 is a schematic diagram of the structure corresponding to each step in the second embodiment of the packaging method of the present invention, Fig.16 is a top view of the positioning plate. Fig.17 yes Fig.16 A partial enlarged view of area B.

[0154] It should be noted that in order to clearly display the package structure, Figures 12 to 15 Only one region for forming a packaging structure is shown.

[0155] The similarities between the second embodiment and the above embodiment are not described in detail here. Figures 12 to 17 In the case where a metal connector and an inter-board connector are provided on the first substrate 500, the metal connector and the inter-board connector are both columnar structures 701; the step of providing a columnar structure on the first substrate 500 includes: after providing the first substrate 500 bonded with the first chip 510, a positioning plate 520 is provided above the first substrate 500, and the positioning plate 520 has a positioning hole 521 and a first window 522 (such as Fig.16 and Fig.17 As shown), the positioning hole 521 corresponds to the position on the first surface 501 for setting the columnar structure, and the first window 522 exposes the top of the first chip 510; the columnar structure 701 is placed on the first surface 501 of the first substrate 500 through the positioning hole 521; the columnar structure 701 is bonded to the first surface 501 of the first substrate 500; after the columnar structure 701 is bonded to the first surface 501 of the first substrate 500, the positioning plate 520 is removed.

[0156] A positioning plate 520 is firstly arranged above the first substrate 500, and then the columnar structure 701 is placed on the first surface 501 of the first substrate 500 through the positioning hole 521, so that when the height of the columnar structure 701 is relatively large, the columnar structure 701 can still obtain better positioning accuracy when placed on the first surface 501, which is beneficial to reduce the probability of position deviation of the columnar structure 701 during the process of bonding the columnar structure 701 to the first surface 501 of the first substrate 500.

[0157] It is understandable that when the thickness of the first chip 510 is relatively large, when a positioning plate 520 is arranged above the first substrate 500, a bump (not shown) may also be arranged at the bottom of the positioning plate 520 to increase the overall height of the positioning plate 520 and reduce the probability of the bottom of the positioning plate 520 causing damage to the top of the first chip 510.

[0158] It should be noted that the step of providing the first substrate 500 bonded with the first chip 510 includes: Fig.12 As shown, a first substrate 500 is provided, wherein the first substrate 500 includes a first surface 501; Fig.13 As shown, welding material 715 is coated at the preset positions of the first chip 510 and the columnar structure on the first surface 501 , and the welding material 715 includes solder paste or flux; and the first chip 510 is bonded at the preset position of the first chip 510 .

[0159] Specifically, after the columnar structure 701 is placed on the first surface 501 of the first substrate 500 through the positioning hole 521, before the positioning plate 520 is removed, it also includes: covering the columnar structure 701 with a bonding cover plate 530; after covering the bonding cover plate 530, bonding the columnar structure 701 to the first surface 501 of the first substrate 500; after bonding the columnar structure 701 to the first surface 501 of the first substrate 500, it also includes: removing the bonding cover plate 530.

[0160] After the gold columnar structure 701 is placed on the first surface 501 of the first substrate 100 through the positioning hole 521, the bonding cover plate 530 is covered on the columnar structure 701, which is beneficial to further improve the positioning accuracy of the columnar structure 701 on the first surface 501, and can make the columnar structure 701 fully contact with the first surface 501, so that the columnar structure 701 is better bonded to the first surface 501.

[0161] As an example, in the step of covering the bonding cover plate 530 on the columnar structure 701, the bonding cover plate 530 has a second window 531 (eg, Fig.15As shown), it is helpful to reduce the probability of the bottom of the bonding cover plate 530 being damaged to the top of the first chip 510.

[0162] As another example, the steps of providing a first substrate 500 bonded with the first chip 510, and setting a columnar structure on the first substrate 500 further include: before bonding the first chip 510 on the first surface 501, placing the first substrate 500 on a carrier plate 540; after placing the first substrate 500 on the carrier plate 540, setting an anti-deformation cover plate 550 on the carrier plate 540 and the first substrate 500, the anti-deformation cover plate 550 being pressed against the carrier plate 540, and the anti-deformation cover plate 550 exposing the center position of the first substrate 500 (such as Fig.14 As shown); in the step of disposing a positioning plate 520 above the first substrate 500, the positioning plate 520 is disposed on the anti-deformation cover plate 550 and the first substrate 500.

[0163] The center position of the first substrate 500 refers to: an area on the first substrate 500 for forming a packaging structure. The center position of the first substrate 500 can be used to form one or more packaging structures.

[0164] The carrier plate 540 and the anti-deformation cover plate 550 pressed against the carrier plate 540 are used to reduce the probability of deformation of the first substrate 500, thereby reducing the probability of deformation of the subsequently formed packaging structure.

[0165] It should be noted that the packaging structure can be formed by the forming method described in the above embodiment, or by other forming methods. For the specific description of the packaging structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0166] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A packaging structure, characterized in that: include: A first substrate, comprising a first surface, wherein one or more first chips are bonded to the first surface; A second substrate, stacked on the first surface of the first substrate, the second substrate comprising a second surface facing the first surface, and a third surface disposed opposite to the second surface, one or more second chips being bonded to the third surface; The first heat dissipation structure is located between the first substrate and the second substrate and is connected to the first substrate and the second substrate respectively.

2. The packaging structure according to claim 1, characterized in that: One or both of the first substrate and the second substrate has a first pseudo wiring structure, and when the first substrate has the first pseudo wiring structure, the first surface exposes a first connection end of the first pseudo wiring structure located on one side of the first surface, and when the second substrate has the first pseudo wiring structure, the second surface exposes a first connection end of the first pseudo wiring structure located on one side of the second surface; The first heat dissipation structure includes: a metal connector located at a side of the first chip, and the metal connector is bonded to a first connection end of the first dummy wiring structure.

3. The packaging structure according to claim 2, characterized in that: The material of the metal connecting member includes copper.

4. The packaging structure according to claim 2, characterized in that: The first heat dissipation structure further includes: a thermally conductive plastic sealing layer filled between the first substrate and the second substrate, and the thermally conductive plastic sealing layer covers the side wall of the metal connector.

5. The packaging structure according to claim 4, characterized in that: The material of the thermal conductive plastic packaging layer includes epoxy plastic packaging material containing aluminum oxide.

6. The packaging structure according to claim 2, characterized in that: There are multiple metal connectors on each side of the first chip, and the metal connectors are discretely arranged around the first chip.

7. The packaging structure according to claim 6, characterized in that: The metal connectors are arranged in a matrix around the first chip, or, on either side of the first chip, the metal connectors include first-type metal connectors and second-type metal connectors with different lateral dimensions, and the second-type metal connectors and the first-type metal connectors are arranged alternately.

8. The packaging structure according to claim 2, characterized in that: There are multiple metal connectors on one side of the first chip, and the spacing between adjacent metal connectors is greater than 50 microns.

9. The packaging structure according to claim 2, characterized in that: The distance between the metal connecting piece on one side of the first chip and the first chip is greater than 50 micrometers.

10. The packaging structure according to any one of claims 1 to 9, characterized in that: The second substrate has a first dummy wiring structure, and the third surface exposes a second connection end of the first dummy wiring structure located on one side of the third surface; The packaging structure also includes a second heat dissipation structure bonded to the third surface of the second substrate, the second heat dissipation structure including: a heat dissipation cover plate located above the second chip; heat dissipation pins located between the heat dissipation cover plate and the second substrate and located on the side of the second chip, the heat dissipation pins bonded to the second connection ends exposed on the third surface.

11. The packaging structure according to claim 10, characterized in that: The bottom of the heat dissipation pin has one or more notches; The packaging structure further includes: a welding material located between the heat dissipation pin and the second connection end exposed on the third surface, and the welding material is also filled in the recess.

12. The packaging structure according to any one of claims 1 to 9, characterized in that: The first substrate has a second pseudo wiring structure, and the first surface exposes a third connection end of the second pseudo wiring structure located on one side of the first surface; the first chip is located above the second pseudo wiring structure, and some pins of the first chip are bonded to the third connection end; The second substrate has a third pseudo wiring structure, and the third surface exposes a fourth connection end of the third pseudo wiring structure located on one side of the third surface; the second chip is located above the third pseudo wiring structure, and some pins of the second chip are bonded to the fourth connection end; or, The first substrate has a second pseudo wiring structure, and the first surface exposes a third connection end of the second pseudo wiring structure located on one side of the first surface; the first chip is located above the second pseudo wiring structure, and some pins of the first chip are bonded to the third connection end; or, The second substrate has a third pseudo wiring structure, and the third surface exposes a fourth connection end of the third pseudo wiring structure located on one side of the third surface; the second chip is located above the third pseudo wiring structure, and some pins of the second chip are bonded to the fourth connection end.

13. The packaging structure according to any one of claims 1 to 9, characterized in that: The packaging structure further includes an inter-board connector, which is located between the first substrate and the second substrate and located at a side of the first heat dissipation structure. The inter-board connector is electrically connected to the first substrate and the second substrate respectively.

14. The packaging structure according to claim 13, characterized in that: The inter-board connector includes one or more of a conductive bump, a conductive column and a transfer board.

15. A packaging method, characterized in that: include: Providing a first substrate and a second substrate, the first substrate comprising a first surface, one or more first chips being bonded to the first surface, and the second substrate comprising a second surface and a third surface disposed opposite to each other; The second surface of the second substrate faces the first surface of the first substrate, and the second substrate is stacked on the first surface of the first substrate; Disposing a first heat dissipation structure between the first substrate and the second substrate, wherein the first heat dissipation structure is connected to the first substrate and the second substrate respectively; One or more second chips are bonded on the third surface of the second substrate.

16. The packaging method according to claim 15, characterized in that: In the step of providing the first substrate and the second substrate, one or both of the first substrate and the second substrate has a first dummy wiring structure, and a metal connector is disposed on the first surface of the first substrate or the second surface of the second substrate; The step of providing a first heat dissipation structure between the first substrate and the second substrate comprises: in a process of stacking the second substrate on the first surface of the first substrate, the metal connector is located between the first substrate and the second substrate and is connected to the first substrate and the second substrate respectively, and the metal connector serves as the first heat dissipation structure; In which, when the first substrate has the first pseudo wiring structure, the first surface exposes the first connection end of the first pseudo wiring structure located on one side of the first surface; when the second substrate has the first pseudo wiring structure, the second surface exposes the first connection end of the first pseudo wiring structure located on one side of the second surface, and the metal connector is bonded to the first connection end of the first pseudo wiring structure.

17. The packaging method according to claim 15 or 16, characterized in that: In the step of providing the second substrate, the second substrate has a first dummy wiring structure, and the third surface exposes a second connection end of the first dummy wiring structure located on one side of the third surface; After bonding one or more second chips on the third surface of the second substrate, the packaging method further includes: bonding a second heat dissipation structure on the third surface of the second substrate, the second heat dissipation structure including: a heat dissipation cover plate, located above the second chip; and heat dissipation pins, located between the heat dissipation cover plate and the second substrate and located on the side of the second chip; In the step of bonding the second heat dissipation structure on the third surface of the second substrate, the heat dissipation pin is bonded to the second connection end exposed on the third surface.

18. The packaging method according to claim 17, characterized in that: The bottom of the heat dissipation pin has one or more notches; The heat dissipation pin is bonded to the second connection end exposed on the third surface by welding material, and the welding material is also filled in the recess.

19. The packaging method according to claim 15 or 16, characterized in that: In the step of providing the first substrate and the second substrate, the first substrate has a second pseudo wiring structure, the first surface exposes a third connection end of the second pseudo wiring structure located on one side of the first surface, the second substrate has a third pseudo wiring structure, the third surface exposes a fourth connection end of the third pseudo wiring structure located on one side of the third surface, the first chip is located above the second pseudo wiring structure, and some pins of the first chip are bonded to the third connection end; In the step of bonding one or more second chips on the third surface of the second substrate, the second chip is located above the third dummy wiring structure, and some pins of the second chip are bonded to the fourth connection end; or, In the step of providing the first substrate, the first substrate has a second pseudo wiring structure, the first surface exposes a third connection end of the second pseudo wiring structure located on one side of the first surface, the first chip is located above the second pseudo wiring structure, and some pins of the first chip are bonded to the third connection end; or, In the step of providing the second substrate, the second substrate has a third dummy wiring structure, and the third surface exposes a fourth connection end of the third dummy wiring structure located at one side of the third surface; In the step of bonding one or more second chips on the third surface of the second substrate, the second chip is located above the third dummy wiring structure, and some pins of the second chip are bonded to the fourth connection end.

20. The packaging method according to claim 15 or 16, characterized in that: The step of stacking the second substrate on the first surface of the first substrate comprises: Disposing an inter-board connector on the first substrate or the second substrate, wherein the inter-board connector is electrically connected to the first substrate or the second substrate; The second substrate is bonded to the first substrate through the inter-board connector, so that the inter-board connector is electrically connected to the first substrate and the second substrate respectively.

21. The packaging method according to claim 20, characterized in that: The step of setting up a first heat dissipation structure located between the first substrate and the second substrate includes: after bonding the second substrate to the first substrate through the inter-board connector, filling a thermally conductive plastic sealing layer between the first substrate and the second substrate, the thermally conductive plastic sealing layer covers the side walls of the metal connector and the side walls of the inter-board connector, and the thermally conductive plastic sealing layer serves as the first heat dissipation structure.

22. The packaging method according to claim 21, characterized in that: In the step of providing the second substrate, a plurality of second substrates are provided, each of the second substrates comprising a unit structure; After setting the first heat dissipation structure between the first substrate and the second substrate, the packaging method further includes: cutting the first substrate and the thermal conductive plastic layer to form a plurality of independent packaging units, wherein the packaging unit includes one or more first chips and a first heat dissipation structure.

23. The packaging method according to claim 22, characterized in that: After cutting the first substrate and the thermally conductive plastic sealing layer, one or more second chips are bonded on the third surface of the second substrate.

24. The packaging method according to claim 20, characterized in that: The inter-board connector includes one or more of a conductive bump, a conductive column and a transfer board.

25. The packaging method according to claim 16, characterized in that: The step of stacking the second substrate on the first surface of the first substrate includes: arranging an inter-board connector on the first substrate or the second substrate, the inter-board connector being a columnar structure, and the inter-board connector electrically connecting the first substrate or the second substrate; bonding the second substrate to the first substrate through the inter-board connector, so that the inter-board connector is electrically connected to the first substrate and the second substrate respectively; Wherein, the metal connector is a columnar structure, and the columnar structure used as the metal connector and the columnar structure used as the inter-plate connector are provided in the same step.

26. The packaging method according to claim 25, characterized in that: In the case where a metal connector and an inter-board connector are provided on the first substrate, both the metal connector and the inter-board connector are columnar structures; the step of providing a columnar structure on the first substrate includes: After providing a first substrate bonded with the first chip, a positioning plate is arranged above the first substrate, wherein the positioning plate has a positioning hole and a first window, wherein the positioning hole corresponds to a position on the first surface for arranging a columnar structure, and the first window exposes the top of the first chip; Placing the columnar structure on the first surface of the first substrate via the positioning hole; bonding the columnar structure to the first surface of the first substrate; After the columnar structure is bonded to the first surface of the first substrate, the positioning plate is removed.

27. The packaging method according to claim 26, characterized in that: After placing the columnar structure on the first surface of the first substrate via the positioning hole and before removing the positioning plate, the method further includes: covering the columnar structure with a bonding cover plate; After covering the bonding cover plate, bonding the columnar structure to the first surface of the first substrate; After bonding the columnar structure to the first surface of the first substrate, the method further includes: removing the bonding cover plate.

28. The packaging method according to claim 27, characterized in that: In the step of covering the columnar structure with a bonding cover plate, the bonding cover plate has a second window exposing the top of the first chip.

29. The packaging method according to claim 27, characterized in that: The step of providing a first substrate bonded with the first chip, and arranging a columnar structure on the first substrate further comprises: placing the first substrate on a carrier before bonding the first chip on the first surface; after placing the first substrate on the carrier, arranging an anti-deformation cover on the carrier and the first substrate, the anti-deformation cover being pressed against the carrier, and the anti-deformation cover exposing the center position of the first substrate; In the step of disposing a positioning plate above the first substrate, the positioning plate is disposed on the deformation prevention cover plate and the first substrate.

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