Three-dimensional packaging structure based on miniaturized broadband power divider

Abstract

The present invention provides a three-dimensional packaging structure based on a miniaturized broadband power divider. The structure comprises an upper chip module, a middle chip module, and a lower chip module, arranged sequentially from top to bottom, as well as a packaging medium and a vertically interconnected power divider. One end of the upper chip module is connected to the upper end of the vertically interconnected power divider, one end of the lower chip module is connected to the lower end of the vertically interconnected power divider, and the middle end of the vertically interconnected power divider is connected to one end of the middle chip module. The middle chip module is located within the packaging medium. The present invention distributes power between the upper and lower chip modules via the vertically interconnected power divider, eliminating the need for a planar power divider structure. This significantly reduces the package size and transmission loss, facilitating package miniaturization and chip layout flexibility.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency packaging, and in particular to a three-dimensional packaging structure based on a miniaturized broadband power divider. Background Art

[0002] Packaging technology emerged alongside the invention of integrated circuits. Its primary functions are power distribution, signal distribution, heat dissipation, and protection. Along with the advancement of chip technology, packaging technology has continued to innovate. Package interconnect density continues to increase, package thickness continues to decrease, and three-dimensional packaging and system packaging methods continue to evolve. In the microwave and millimeter wave frequency bands, an increasing number of chip modules are being integrated within the packaging dielectric material. When two chip modules on different layers need to be connected to a chip module located in an intermediate dielectric layer, the common practice is to connect the upper and lower chip modules to the intermediate metal layer via vertical interconnects. These interconnects are then connected via transmission lines to a planar Wilkinson power divider, and finally to the input of the intermediate chip. This not only increases the package size and processing complexity, but is also limited by the bandwidth limitations of the frequency-dependent quarter-wavelength transmission line. Furthermore, most power dividers based on three-dimensional packaging have symmetrical output ports located on the same horizontal plane and feature long quarter-wavelength transmission lines, which hinder package miniaturization and chip layout flexibility. Summary of the Invention

[0003] In order to solve the technical problems existing in the prior art, the present invention provides a three-dimensional packaging structure based on a miniaturized broadband power divider, which distributes power between the upper chip module and the lower chip module through vertically interconnected power dividers, without the need for a planar power divider structure, thereby greatly reducing the package size and transmission loss, which is conducive to the miniaturization of the package and the flexibility of the chip layout.

[0004] The present invention provides a three-dimensional packaging structure based on a miniaturized broadband power divider, comprising an upper chip module, a middle chip module, and a lower chip module, which are arranged in sequence from top to bottom, as well as a packaging medium and a vertical interconnection power divider; one end of the upper chip module is connected to the upper end of the vertical interconnection power divider, one end of the lower chip module is connected to the lower end of the vertical interconnection power divider, and the middle end of the vertical interconnection power divider is connected to one end of the middle chip module; the middle chip module is located in the packaging medium; and the vertical interconnection power divider is used to perform vertical interconnection and power distribution between the upper chip module and the lower chip module.

[0005] According to the present invention, a three-dimensional packaging structure based on a miniaturized broadband power divider further includes an upper transmission line, a lower transmission line and a middle transmission line; the upper transmission line is located above the vertically interconnected power divider, the lower transmission line is located below the vertically interconnected power divider, and the middle transmission line is arranged on the same horizontal plane as the middle chip module and perpendicular to the middle of the vertically interconnected power divider; the upper transmission line is a transmission line connecting the upper chip and the vertically interconnected power divider, the lower transmission line is a transmission line connecting the lower chip and the vertically interconnected power divider, and the middle transmission line is a transmission line connecting the middle chip and the vertically interconnected power divider.

[0006] According to a three-dimensional packaging structure based on a miniaturized broadband power divider provided by the present invention, the vertically interconnected power divider is a structure integrating a quasi-coaxial and a power divider, and the vertically interconnected power divider includes an upper power divider and a lower power divider; the first end of the upper power divider serves as the upper end of the vertically interconnected power divider, the first end of the lower power divider serves as the lower end of the vertically interconnected power divider, and the common end connected to the second end of the upper power divider and the second end of the lower power divider serves as the middle end of the vertically interconnected power divider.

[0007] According to a three-dimensional packaging structure based on a miniaturized broadband power divider provided by the present invention, the upper power divider and the lower power divider are symmetrically arranged along the middle transmission line.

[0008] According to a three-dimensional packaging structure based on a miniaturized broadband power divider provided by the present invention, the structural parameters of the vertically interconnected power divider are proportional to the characteristic impedance; the structural parameters include the inner diameter and the outer diameter.

[0009] According to a three-dimensional packaging structure based on a miniaturized broadband power divider provided by the present invention, when the characteristic impedance of the upper power divider is the same as the characteristic impedance of the lower power divider, the power distribution between the upper chip module and the lower chip module is equal.

[0010] According to a three-dimensional packaging structure based on a miniaturized broadband power divider provided by the present invention, when the characteristic impedance of the upper power divider is different from the characteristic impedance of the lower power divider, the power distribution between the upper chip module and the lower chip module is unequal.

[0011] According to a three-dimensional packaging structure based on a miniaturized broadband power divider provided by the present invention, if the ratio of the outer diameter to the inner diameter decreases, the characteristic impedance decreases; if the ratio of the outer diameter to the inner diameter increases, the characteristic impedance increases; if the ratio of the outer diameter to the inner diameter remains unchanged, the characteristic impedance remains unchanged.

[0012] According to a three-dimensional packaging structure based on a miniaturized broadband power divider provided by the present invention, the upper chip module, the middle chip module and the lower chip module all operate in the millimeter wave frequency band.

[0013] According to the present invention, a three-dimensional packaging structure based on a miniaturized broadband power divider is provided. The packaging forms of the three-dimensional packaging structure include flip-chip and gold wire bonding forms.

[0014] The present invention provides a three-dimensional packaging structure based on a miniaturized broadband power divider, characterized by comprising an upper chip module, a middle chip module, and a lower chip module, arranged sequentially from top to bottom, as well as a packaging medium and a vertically interconnected power divider. One end of the upper chip module is connected to the upper end of the vertically interconnected power divider, one end of the lower chip module is connected to the lower end of the vertically interconnected power divider, and the middle end of the vertically interconnected power divider is connected to one end of the middle chip module. The middle chip module is located within the packaging medium. The present invention distributes power between the upper and lower chip modules via a vertically interconnected power divider, eliminating the need for a planar power divider structure. This significantly reduces the package size and transmission loss, facilitating package miniaturization and chip layout flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 The diagram is a schematic diagram of the principle of a three-dimensional packaging structure based on a miniaturized broadband power divider provided by the present invention.

[0017] Figure 2 This is a stereoscopic view of a three-dimensional structure integrating a quasi-coaxial device and a power divider provided by the present invention.

[0018] Figure 3 It is a side view of the three-dimensional structure integrating the quasi-coaxial device and the power divider provided by the present invention.

[0019] Figure 4 This is an S-parameter diagram of the integrated quasi-coaxial and equal power splitter provided by the present invention.

[0020] Figure 5 This is an amplitude and phase difference diagram of the integrated quasi-coaxial and equal power divider provided by the present invention.

[0021] Figure 6 This is an S-parameter diagram of the integrated quasi-coaxial and unequal power divider provided by the present invention.

[0022] Figure 7 This is a diagram of the amplitude and phase difference of the integrated quasi-coaxial and unequal power splitters provided by the present invention.

[0023] Reference numerals:

[0024] 1: Upper chip module; 2: Middle chip module; 3: Lower chip module; 4: Packaging medium; 5: Vertical interconnection power divider; 6: Upper transmission line; 7: Middle transmission line; 8: Lower transmission line. DETAILED DESCRIPTION

[0025] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0026] With the development of integrated circuits and three-dimensional packaging structures, more and more chip modules are being integrated into packaging dielectric materials. In the microwave and millimeter wave frequency bands, when two chip modules on different layers need to be connected to a chip module in an intermediate dielectric layer, the common practice is to connect the upper and lower chip modules to the intermediate metal layer through vertical interconnects, then use transmission lines to connect to a planar Wilkinson power divider, and finally to the input of the intermediate layer chip. This not only increases the package size and processing difficulty, but is also limited by the bandwidth limitations of the frequency-dependent quarter-wavelength transmission line. At the same time, most power dividers based on three-dimensional packaging have symmetrical output ports on the same horizontal plane and have long quarter-wavelength transmission lines, which are not conducive to package miniaturization and chip layout flexibility.

[0027] Please refer to Figure 1 , Figure 1 A schematic diagram of the principle of a three-dimensional packaging structure based on a miniaturized broadband power divider provided by the present invention.

[0028] The present invention provides a three-dimensional packaging structure based on a miniaturized broadband power divider, comprising an upper chip module 1, a middle chip module 2, and a lower chip module 3, which are arranged in sequence from top to bottom, as well as a packaging medium 4 and a vertical interconnection power divider 5; one end of the upper chip module 1 is connected to the upper end of the vertical interconnection power divider 5, one end of the lower chip module is connected to the lower end of the vertical interconnection power divider 5, and the middle end of the vertical interconnection power divider 5 is connected to one end of the middle chip module 2; the middle chip module 2 is located in the packaging medium 4; and the vertical interconnection power divider 5 is used to perform vertical interconnection and power distribution between the upper chip module 1 and the lower chip module 3.

[0029] In order to solve the technical problems existing in the prior art, the present invention provides a three-dimensional packaging structure based on a miniaturized broadband power divider, including an upper chip module 1, a middle chip module 2 and a lower chip module 3, which are arranged in sequence from top to bottom. In addition, it also includes a packaging medium 4 and a vertical interconnection power divider 5. The vertical interconnection power divider 5 not only realizes the physical connection between different chip modules, but also is responsible for power distribution. The vertical interconnection power divider 5 can adopt a quasi-coaxial structure. In order to achieve broadband characteristics, a low-loss dielectric material can be selected. The packaging structure can ensure that one end of the upper chip module 1 is precisely docked with the upper end of the vertical interconnection power divider 5, one end of the lower chip module 3 is precisely connected to the lower end of the vertical interconnection power divider 5, and one end of the middle chip module 2 is precisely docked with the middle end of the vertical interconnection power divider 5.

[0030] The upper chip module 1 , the middle chip module 2 , and the lower chip module 3 can all transmit RF (Radio Frequency) signals.

[0031] The power distribution ratio can be adjusted by adjusting the inner and outer diameters of the power divider. For example, if upper chip module 1 receives 70% of the total power and lower chip module 3 receives 30%, this distribution ratio can be achieved by adjusting the inner and outer diameter ratios. Assuming the total power is P, the power received by upper chip module 1 and lower chip module 3 is 0.7P and 0.3P, respectively.

[0032] The packaging medium 4 needs to have good mechanical and electrical insulation properties while providing excellent thermal stability.

[0033] When the three-dimensional packaging structure of the present invention implements a combining function, the signals of the upper chip module 1 and the lower chip module 3 are transmitted through ports 3 and 2, respectively, to the corresponding port 1 of the middle chip module 2. When the three-dimensional packaging structure implements a power splitting function, the signal corresponding to port 1 of the middle chip module 2 is transmitted to the corresponding ports 3 and 2 of the upper chip module 1 and the lower chip module 3, respectively.

[0034] The design of the present invention achieves a compact, high-performance three-dimensional packaging structure that not only meets broadband and high-speed requirements but also achieves efficient power distribution and signal transmission through vertically interconnected power dividers 5. This structure is particularly well-suited for applications requiring high performance and high-density integration, such as modern mobile communications equipment and high-speed data transmission equipment.

[0035] As a preferred embodiment, it also includes an upper transmission line 6, a lower transmission line 8 and a middle transmission line 7; the upper transmission line 6 is located above the vertical interconnection power divider 5, the lower transmission line 8 is located below the vertical interconnection power divider 5, and the middle transmission line 7 is arranged on the same horizontal plane as the middle chip module 2 and perpendicular to the middle of the vertical interconnection power divider 5; the upper transmission line 6 is a transmission line connecting the upper chip and the vertical interconnection power divider 5, the lower transmission line 8 is a transmission line connecting the lower chip and the vertical interconnection power divider 5, and the middle transmission line 7 is a transmission line connecting the middle chip and the vertical interconnection power divider 5.

[0036] In this embodiment, the transmission line is designed to ensure efficient transmission of signals between the chip module and the vertical interconnection power divider 5. The transmission line can adopt microstrip line technology. The upper transmission line 6 is located above the vertical interconnection power divider 5, and is responsible for transmitting the signal of the upper chip module 1 to the upper end of the power divider. The lower transmission line 8 is located below the vertical interconnection power divider 5, and is responsible for transmitting the signal of the lower chip module 3 to the lower end of the power divider. The lower transmission line 8 can adopt the same design parameters as the upper transmission line 6 to maintain consistent impedance matching. The middle transmission line 7 is arranged on the same horizontal plane as the middle chip module 2 and perpendicular to the middle of the vertical interconnection power divider 5. It is responsible for transmitting the output signal of the vertical interconnection power divider 5 to the middle chip module 2. The middle transmission line 7 can be designed with a shorter length to reduce signal delay.

[0037] The reliability and mechanical stability of the electrical connection should be ensured between the upper chip and the upper transmission line 6, and between the lower chip and the lower transmission line 8. The connection between the middle chip and the middle transmission line 7 can achieve a smaller package size and higher signal transmission speed.

[0038] Please refer to Figure 2 , Figure 2 A stereoscopic view of a three-dimensional structure integrating a quasi-coaxial device and a power divider provided by the present invention.

[0039] Please refer to Figure 3 , Figure 3 This is a side view of the three-dimensional structure integrating a quasi-coaxial device and a power divider provided by the present invention.

[0040] As a preferred embodiment, the vertically interconnected power divider 5 is a structure that integrates a coaxial-like structure and a power divider. The vertically interconnected power divider 5 includes an upper power divider and a lower power divider; the first end of the upper power divider serves as the upper end of the vertically interconnected power divider 5, the first end of the lower power divider serves as the lower end of the vertically interconnected power divider 5, and the common end connected to the second end of the upper power divider and the second end of the lower power divider serves as the middle end of the vertically interconnected power divider 5.

[0041] In this embodiment, the vertical interconnect power splitter 5 integrates vertical interconnects (such as quasi-coaxial) and a power splitter, significantly reducing package size and transmission loss. For power combining between chip modules on different layers, the quasi-coaxial transition alone achieves vertical interconnection and power distribution for multiple chip modules, without the need for a planar power splitter structure. The quasi-coaxial structure, comprising inner and outer conductors and a dielectric layer, exhibits low propagation loss and excellent impedance characteristics over a wide frequency range. The characteristic impedance of the quasi-coaxial structure is determined by the dimensions of the inner and outer conductors.

[0042] Specifically, the vertical interconnection power divider 5 includes an upper power divider and a lower power divider. The upper power divider is responsible for processing signals from the upper chip module 1. The first end of the upper power divider serves as the upper end of the vertical interconnection power divider 5 and is directly connected to the upper chip module 1. The lower power divider is responsible for processing signals from the lower chip module 3. The first end of the lower power divider serves as the lower end of the vertical interconnection power divider 5 and is directly connected to the lower chip module 3. The second end of the upper power divider is connected to the second end of the lower power divider to form a common end, which serves as the middle end of the vertical interconnection power divider 5 and is connected to the middle chip module 2.

[0043] Power distribution is achieved by adjusting the characteristic impedance of the upper and lower power dividers. By precisely controlling the dimensions of the inner and outer conductors, the impedance at each power divider end can be controlled, thereby adjusting the power distribution ratio. By selecting low-loss materials and optimizing structural dimensions, we can minimize signal transmission losses in the vertically interconnected power dividers.

[0044] For example, if the upper chip module 1 obtains 60% of the total power and the lower chip module 3 obtains 40%, the characteristic impedance of the upper power divider can be adjusted to be higher than the characteristic impedance of the lower power divider.

[0045] As a preferred embodiment, the upper power divider and the lower power divider are symmetrically arranged along the middle transmission line 7 .

[0046] In this embodiment, the upper power divider and the lower power divider are arranged along the middle transmission line 7 so that the central axes of the two power dividers coincide with the central axis of the middle transmission line 7. Due to the symmetric structures of the upper power divider and the lower power divider, equal power distribution can be achieved between the upper chip module 1 and the lower chip module 3.

[0047] As a preferred embodiment, the structural parameters of the vertically interconnected power divider 5 are proportional to the characteristic impedance; the structural parameters include the inner diameter and the outer diameter.

[0048] As a preferred embodiment, when the characteristic impedance of the upper power divider is the same as the characteristic impedance of the lower power divider, the power distribution between the upper chip module 1 and the lower chip module 3 is equal.

[0049] Please refer to Figure 4 , Figure 4 This is an S-parameter diagram of the integrated quasi-coaxial and equal power splitter provided by the present invention.

[0050] Please refer to Figure 5 , Figure 5 Amplitude and phase difference diagram of the integrated quasi-coaxial and equal power splitter provided by the present invention.

[0051] Figure 4 Given the equal power performance parameters, it can be found that due to the symmetry of the structure, and The parameters are almost the same, the insertion loss is about 3.1dB, and the input standing wave In the DC-40GHz frequency range, it is better than 20dB. However, due to the lack of an isolation network, the standing wave and isolation of the output port are only about -6dB. Figure 5 The amplitude and phase differences of the equal power divider are given. In the range of DC-40GHz, the amplitude difference and phase difference are less than 0.05dB and .

[0052] As a preferred embodiment, when the characteristic impedance of the upper power divider is different from the characteristic impedance of the lower power divider, the power distribution between the upper chip module 1 and the lower chip module 3 is unequal.

[0053] Please refer to Figure 6 , Figure 6 This is an S-parameter diagram of the integrated quasi-coaxial and unequal power splitter provided by the present invention.

[0054] Please refer to Figure 7 , Figure 7 Amplitude and phase difference diagram of the integrated quasi-coaxial and unequal power splitter provided by the present invention.

[0055] Figure 6 The S parameters of the unequal power divider are given. By adjusting the inner diameter r and outer diameter R of the upper and lower quasi-coaxial layers with the middle metal layer as the symmetry axis, the corresponding characteristic impedance can be changed, thereby achieving unequal power distribution. Figure 7 The amplitude and phase difference of unequal power dividers are given. In the range of 20-30GHz, the amplitude difference is about , and the corresponding phase difference is less than .

[0056] As a preferred embodiment, when the ratio of the outer diameter to the inner diameter decreases, the characteristic impedance decreases; when the ratio of the outer diameter to the inner diameter increases, the characteristic impedance increases; when the ratio of the outer diameter to the inner diameter remains unchanged, the characteristic impedance remains unchanged.

[0057] In this embodiment, the characteristic impedance can be controlled by adjusting the ratio of the inner and outer diameters of the coaxial structure. The inner and outer diameters of the upper power divider are r A and R A , the inner and outer diameters of the lower power divider are r B and R B .

[0058] When the outer diameter R decreases or the inner diameter r increases, the ratio R / r decreases, resulting in a decrease in the characteristic impedance Z0. This is suitable for circuit designs that require a lower impedance environment and can increase power distribution to chip modules with higher impedance.

[0059] When the outer diameter R increases or the inner diameter r decreases, the ratio R / r increases, resulting in an increase in the characteristic impedance Z0. This is suitable for circuit designs that require a higher impedance environment and can increase power distribution to chip modules with lower impedance.

[0060] If the dimensions of the inner and outer diameters remain constant, the characteristic impedance Z0 will remain constant, which helps maintain system performance in applications requiring stable power distribution.

[0061] The present invention achieves adjustable power splitting ratios simply by varying the inner and outer diameters of the quasi-coaxial cable, thereby varying its corresponding characteristic impedance. For example, in a multi-carrier communication system, different carriers may require different power levels. By adjusting the ratio of the inner and outer diameters of the power splitter, the appropriate characteristic impedance can be customized for each carrier, achieving precise power distribution.

[0062] A vertical inner coaxial structure is used to replace the traditional 1 / 4 wavelength converter to expand the bandwidth.

[0063] As a preferred embodiment, the upper chip module 1, the middle chip module 2 and the lower chip module 3 all operate in the millimeter wave frequency band.

[0064] In this embodiment, the upper chip module 1, middle chip module 2, and lower chip module 3 in the three-dimensional package structure all operate in the millimeter wave frequency band. The millimeter wave frequency band generally refers to the frequency range of 30 GHz to 300 GHz. This frequency range provides extremely wide bandwidth, suitable for high-speed data transmission and high-resolution radar systems. Each chip module can integrate high-performance millimeter wave circuits, such as low-noise amplifiers (LNAs), power amplifiers (PAs), mixers, and phased array antennas.

[0065] The vertically interconnected power splitter 5 operates within the millimeter wave frequency band to achieve broadband signal distribution and transmission. The characteristic impedance of the splitter needs to match the characteristic impedance of the transmission line in the millimeter wave band to reduce signal reflections and improve transmission efficiency.

[0066] As a preferred embodiment, the packaging forms of the three-dimensional packaging structure include flip-chip and wire bonding.

[0067] In this embodiment, the three-dimensional packaging structure can adopt two packaging forms: flip-chip and wire bonding. This packaging method provides mechanical stability and electrical connectivity for high-speed, high-performance electronic systems.

[0068] Flip-chip packaging is a technology that forms solder joints on the active side of a chip (the side containing the circuitry), then flips the chip over and bonds it directly to the package substrate. Flip-chip technology is used for both the upper chip module (1) and the lower chip module (3) to achieve connection to the package substrate.

[0069] Gold wire bonding creates an electrical connection by attaching gold wire (or other conductive material) from the chip's pads to the package substrate or leadframe. Gold wire bonding is used on the mid-layer chip module 2 to connect to the vertical interconnect power divider 5, providing excellent electrical performance and mechanical stability.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A three-dimensional packaging structure based on a miniaturized broadband power divider, characterized in that: It includes an upper chip module, a middle chip module and a lower chip module arranged in sequence from top to bottom, as well as a packaging medium and a vertical interconnection power divider; One end of the upper chip module is connected to the upper end of the vertical interconnection power divider, one end of the lower chip template is connected to the lower end of the vertical interconnection power divider, and the middle end of the vertical interconnection power divider is connected to one end of the middle chip module; the middle chip module is located in the packaging medium; The vertical interconnection power divider is used to perform vertical interconnection and power distribution between the upper chip module and the lower chip module.

2. The three-dimensional packaging structure based on a miniaturized broadband power divider according to claim 1, characterized in that: It also includes an upper transmission line, a lower transmission line, and a middle transmission line; The upper transmission line is located above the vertical interconnection power divider, the lower transmission line is located below the vertical interconnection power divider, and the middle transmission line is arranged on the same horizontal plane as the middle chip module and perpendicular to the middle of the vertical interconnection power divider; The upper transmission line is a transmission line connecting the upper chip and the vertical interconnection power divider, the lower transmission line is a transmission line connecting the lower chip and the vertical interconnection power divider, and the middle transmission line is a transmission line connecting the middle chip and the vertical interconnection power divider.

3. According to the three-dimensional packaging structure based on the miniaturized broadband power divider of claim 2, the vertically interconnected power divider is a structure integrating a coaxial-like structure and a power divider, and the vertically interconnected power divider includes an upper power divider and a lower power divider; the first end of the upper power divider serves as the upper end of the vertically interconnected power divider, the first end of the lower power divider serves as the lower end of the vertically interconnected power divider, and the common end connected to the second end of the upper power divider and the second end of the lower power divider serves as the middle end of the vertically interconnected power divider.

4. The three-dimensional packaging structure based on a miniaturized broadband power divider according to claim 3, wherein the upper power divider and the lower power divider are symmetrically arranged along the middle transmission line.

5. According to the three-dimensional packaging structure based on the miniaturized broadband power divider of claim 3, the structural parameters of the vertically interconnected power divider are proportional to the characteristic impedance; the structural parameters include the inner diameter and the outer diameter.

6. According to the three-dimensional packaging structure based on the miniaturized broadband power divider according to claim 5, when the characteristic impedance of the upper power divider is the same as the characteristic impedance of the lower power divider, the power distribution between the upper chip module and the lower chip module is equal.

7. According to the three-dimensional packaging structure based on the miniaturized broadband power divider according to claim 5, when the characteristic impedance of the upper power divider is different from the characteristic impedance of the lower power divider, the power distribution between the upper chip module and the lower chip module is unequal.

8. According to the three-dimensional packaging structure based on the miniaturized broadband power divider according to claim 5, if the ratio of the outer diameter to the inner diameter decreases, the characteristic impedance decreases; if the ratio of the outer diameter to the inner diameter increases, the characteristic impedance increases; if the ratio of the outer diameter to the inner diameter remains unchanged, the characteristic impedance remains unchanged.

9. According to the three-dimensional packaging structure based on the miniaturized broadband power divider according to claim 1, the upper chip module, the middle chip module and the lower chip module all operate in the millimeter wave frequency band.

10. The three-dimensional packaging structure based on the miniaturized broadband power divider according to any one of claims 1 to 9, wherein the packaging forms of the three-dimensional packaging structure include flip-chip and gold wire bonding.

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