Supporting enhanced quality levels of clock sources over BITS networks

Abstract

The embodiment of the invention relates to a communication method, equipment, a device and a computer readable medium. In some embodiments, first clock synchronization information is received via an input interface of an apparatus, where the first clock synchronization information indicates at least one enhanced quality level (QL) of a clock source; and outputting second clock synchronization information via an output interface of the apparatus, where the second clock synchronization information indicates at least one enhanced QL of the clock source, and the output interface is a Building Integrated Timing Supply (BITS) interface. In this way, end-to-end support of enhanced quality levels of clock synchronization information can be provided in a hybrid network of BITS and SyncE.

Description

Technical Field

[0001] The technology disclosed herein generally relates to the field of communications, and more particularly to methods, devices, apparatuses, and computer-readable media for supporting enhanced quality levels of clock sources on a building integrated timing supply (BITS) network. Background Art

[0002] With the rapid development and deployment of 5G services, there are more and more applications in industrial and time-sensitive fields. Typical services include global video conferencing, robot collaboration in smart factories, remote surgery in smart medical systems, etc.

[0003] In order to reduce the cost of network deployment, mobile any-haul network (MxH) based on passive optical network (PON) has become the first choice. Considering the support for time-sensitive services, the requirements for the end-to-end timing performance of PON networks are becoming higher and higher, especially the requirements for frequency stability. Therefore, in order to support high-quality, low-latency video or audio services in MxH, high-precision frequency synchronization is necessary. Summary of the invention

[0004] In general, example embodiments of the present disclosure are directed to a technical solution capable of providing end-to-end support for an enhanced quality level of clock synchronization information in a hybrid network of BITS and SyncE.

[0005] In a first aspect of the present disclosure, a device is provided. The device includes at least one processor and at least one memory. The at least one memory stores instructions, and when the instructions are executed by the at least one processor, the device at least: receives first clock synchronization information via an input interface of the device, wherein the first clock synchronization information indicates at least one enhanced quality level QL of a clock source; and outputs second clock synchronization information via an output interface of the device, wherein the second clock synchronization information indicates at least one enhanced QL of a clock source, and the output interface is a building integrated timing supply BITS interface.

[0006] In a second aspect of the present disclosure, a method is provided. The method includes: receiving first clock synchronization information via an input interface of a device, wherein the first clock synchronization information indicates at least one enhanced quality level QL of a clock source; and outputting second clock synchronization information via an output interface of the device, wherein the second clock synchronization information indicates at least one enhanced QL of the clock source, and the output interface is a building integrated timing supply BITS interface.

[0007] In a third aspect of the present disclosure, a device is provided. The device includes: a component for receiving first clock synchronization information via an input interface of the device, wherein the first clock synchronization information indicates at least one enhanced quality level QL of a clock source; and a component for outputting second clock synchronization information via an output interface of the device, wherein the second clock synchronization information indicates at least one enhanced QL of the clock source, and the output interface is a building integrated timing supply BITS interface.

[0008] In a fourth aspect of the present disclosure, a computer program is provided. The computer program includes instructions, and when the instructions are executed by a device, the device at least: receives first clock synchronization information via an input interface of the device, wherein the first clock synchronization information indicates at least one enhanced quality level QL of a clock source; and outputs second clock synchronization information via an output interface of the device, wherein the second clock synchronization information indicates at least one enhanced QL of the clock source, and the output interface is a building integrated timing supply BITS interface.

[0009] In a fifth aspect of the present disclosure, a device is provided. The device includes: a receiving circuit configured to receive first clock synchronization information via an input interface of the device, wherein the first clock synchronization information indicates at least one enhanced quality level QL of a clock source; and an output circuit configured to output second clock synchronization information via an output interface of the device, wherein the second clock synchronization information indicates at least one enhanced QL of the clock source, and the output interface is a building integrated timing supply BITS interface.

[0010] In a sixth aspect of the present disclosure, a computer-readable medium is provided, wherein instructions are stored on the computer-readable medium, and when the instructions are executed by at least one processing unit, the at least one processing unit is configured to execute the method according to the second aspect.

[0011] It should be understood that the contents described in the summary of the invention are not intended to limit the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1A An example network device is shown upon which embodiments of the present disclosure may be implemented.

[0013] Figure 1B A block diagram of an example communication system is shown in which embodiments of the present disclosure may be implemented.

[0014] Figure 2 A schematic diagram of a method for communication according to some embodiments of the present disclosure is shown.

[0015] Figure 3A functional structure diagram of a network device 300 according to some embodiments of the present disclosure is shown.

[0016] Figure 4 A functional structure diagram of a network device 400 according to some embodiments of the present disclosure is shown.

[0017] Figure 5 A simplified block diagram of an electronic device suitable for implementing embodiments of the present disclosure is shown.

[0018] Figure 6 A schematic diagram of a computer-readable medium suitable for implementing an embodiment of the present disclosure is shown.

[0019] Throughout the drawings, the same or similar reference numerals refer to the same or similar elements. DETAILED DESCRIPTION

[0020] The principles and spirit of the present disclosure will be described below with reference to several exemplary embodiments shown in the accompanying drawings. It should be understood that these specific embodiments are described only to enable those skilled in the art to better understand and implement the present disclosure, and are not intended to limit the scope of the present disclosure in any way.

[0021] As used herein, the term "including" and similar terms should be understood as open inclusion, i.e., "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0022] As used herein, the term "determine" covers a variety of actions. For example, "determine" may include operation, calculation, processing, export, investigation, search (e.g., search in a table, a database or another data structure), ascertain, etc. In addition, "determine" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. In addition, "determine" may include parsing, selecting, selecting, establishing, etc. As used herein, "at least one of the following: " and "at least one of " and similar expressions, wherein a list of two or more elements is connected by "and" or "or", means at least any one of these elements, or at least any two or more of these elements, or at least all of them.

[0023] The term "circuitry" as used herein refers to one or more of: (a) a hardware circuit implementation only (such as an implementation of analog and / or digital circuits only); and (b) a combination of hardware circuits and software, such as (if applicable): (i) a combination of analog and / or digital hardware circuits and software / firmware, and (ii) any portion of a hardware processor with software (including a digital signal processor, software and memory that work together to enable an apparatus such as an OLT or other computing device to perform various functions); and (c) a hardware circuit and / or processor, such as a microprocessor or a portion of a microprocessor, that requires software (e.g., firmware) for operation, but can be without software when software is not required for operation.

[0024] The definition of circuit applies to all uses of this term in this application (including in any claims). As another example, the term "circuit" used herein also covers an implementation of only a hardware circuit or a processor (or multiple processors), or a portion of a hardware circuit or a processor, or its accompanying software or firmware. For example, if applicable to a specific claim symbol, the term "circuit" also covers a baseband integrated circuit or a processor integrated circuit or a network device (e.g., a router, an optical network unit OUN and an optical line terminal OLT in a PON, etc.) or a similar integrated circuit in other computing devices.

[0025] As mentioned above, in order to support time-sensitive services, the requirements for the end-to-end timing performance of PON networks are becoming increasingly higher, especially the requirements for frequency stability. Frequency stability is an important indicator of frequency synchronization in communication networks, and the performance of frequency synchronization in communication networks directly determines the service level that the communication network can support.

[0026] The Building Integrated Timing Supply (BITS) interface and the Synchronous Ethernet (SyncE) interface are two popular interfaces for sending and receiving frequency signals in a clock synchronization network. In the operator's synchronization network, in addition to the above two popular interfaces, there are other types of frequency distribution interfaces. The embodiments of the present disclosure mainly relate to the two interfaces BITS and SyncE, but the embodiments of the present disclosure can also be equally or similarly applied to other types of frequency distribution interfaces. In some embodiments of the present disclosure, the BITS interface refers to the clock synchronization information transmitted thereon conforming to the BITS protocol, and the SyncE interface refers to the clock synchronization information transmitted thereon including SyncE signals.

[0027] In a BITS network, the quality level (QL) information of the clock source is transmitted in the encapsulated E1 / T1 data frame (for example, embedded in the frame header of the E1 / T1 data frame), and generally no additional upper layer protocol processing is required. In synchronous Ethernet, the QL information of the clock source is transmitted through the Ethernet slow protocol G.781 defined by ITU-T. The quality level is carried by the type-length-value (TLV) field, which is included in the Ethernet Synchronous Message Channel (ESMC) PDU. Among them, two types of ESMCPDU frames are defined and distinguished by event flags. The two types of ESMC PDU frames are ESMC information PDU and ESMC event PDU.

[0028] In order to support higher frequency accuracy, it is necessary to introduce enhanced QL of the clock source. Currently, the definition of support for enhanced QL in ITU-T standards is mainly focused on synchronous Ethernet, which is reflected in ITU-T G.781 and G.8264. Specifically, ITU-T G.781 introduces enhanced QL and defines other new quality levels. However, in the ITU-T series of standards, there is no definition of support for enhanced QL for BITS.

[0029] Figure 1A Schematically illustrates an example network device on which embodiments of the present disclosure may be implemented. Figure 1A As shown, the network device 100 in the clock synchronization network can receive clock synchronization information from other network devices located upstream through the input interface 100-1. The network device 100 performs clock calibration of the network device 100 itself based on the received clock synchronization information. Specifically, the network device 100 can synchronize its time to the time indicated in the received clock synchronization information, and synchronize the frequency of its clock to the frequency indicated in the received clock synchronization information. After the network device 100 performs clock calibration itself, it can also send the corresponding clock synchronization information to other network devices located downstream through the output interface 100-2, so that the other network devices downstream perform corresponding clock calibration. In addition, the received and sent clock synchronization information also indicates the quality level QL of the clock source corresponding to the clock synchronization information, that is, the accuracy of the clock source or the frequency accuracy of the clock source. Figure 1A The input interface 100 - 1 shown may be a BITS interface or a SyncE interface, and the output interface 100 - 2 may also be a BITS interface or a SyncE interface.

[0030] Figure 1B 1 shows a block diagram of an example communication system in which embodiments of the present disclosure may be implemented, wherein a clock synchronization network portion schematically shows a distribution topology of clock synchronization information. Figure 1BAs shown, satellite 110 is located at the most upstream (starting point) of the clock synchronization network, and a base station (not shown in the figure) can be located at the most downstream of the clock synchronization network. The device located upstream can send clock synchronization information to the device located downstream through the clock synchronization network. Specifically, satellite 110 can perform clock synchronization operation on the most advanced clock device (Grand Master) 111. Satellite 110 can be a GPS satellite, which can include an atomic clock. Satellite 110 can send a GPS signal to the most advanced clock device 111 driven by the atomic clock. The GPS signal can include time data with the same accuracy as the atomic clock. After the GPS receiver in the most advanced clock device 111 receives the GPS signal, it can synchronize the clock in the most advanced clock device 111 to the atomic clock in the GPS satellite according to the time data in the GPS signal.

[0031] Specifically, the highest-level clock device 111 can synchronize the time of the clock in the highest-level clock device 111 to the time of the atomic clock in the GPS satellite, and synchronize the frequency of the clock in the highest-level clock device 111 to the frequency of the atomic clock in the GPS satellite. After the clock of the highest-level clock device 111 is calibrated, the highest-level clock device 111 can be used as a clock source to send clock synchronization information (also called timing information) to downstream devices such as the edge router 112, thereby calibrating the clocks of other devices. After the clock of the upstream device is calibrated, it can be used as a clock source for the downstream device. In some embodiments of the present disclosure, the clock source may also be referred to as a synchronization source. Therefore, the clock synchronization information can be transmitted from upstream to downstream level by level in the clock synchronization network. For example, Figure 1B As shown, after the clock synchronization information from the satellite 110 is transmitted to the edge router 112, it can continue to be transmitted downward, for example, to the left to the IP transmission network, or to the right to the core network.

[0032] like Figure 1BAs shown, in the transmission from the highest level clock device 111 to the edge router 112 and then to the optical line terminal OLT 113, the clock synchronization information is sent and received via the SyncE interface. In the downstream transmission of OLT 113, the sending or receiving of clock synchronization information may be carried out via the SyncE interface or the BITS interface. For example, as shown in the figure, the clock synchronization information is transmitted from OLT 113 to remote OLT 114 or remote OLT 116, from remote OLT 120 to optical network unit ONU 121, and from ONU 121 to its downstream small cell 122, all via the SyncE interface. As shown by the dotted ellipse in the figure, clock synchronization information is transmitted via the BITS interface from the remote OLT 114 to the video conferencing server 115, from the remote OLT 116 to the downstream IoT factory 117, from the OLT 113 to the remote OLT 118, from the remote OLT 118 to the downstream small cell 119, from the OLT 113 to the remote OLT 120, and from the OLT 113 to the downstream network device 123.

[0033] Before a network device in a clock synchronization network is used as a clock source to calibrate the local clock of a downstream network device, it is necessary to track the quality level QL of the clock source and carry the QL information in the clock synchronization information sent to the downstream network device. As described above, in order to support higher frequency accuracy, it is necessary to introduce an enhanced quality level QL of the clock source. In the current ITU-T standard, an enhanced QL has been defined for SyncE. However, the current ITU-T standard does not define an enhanced QL for BITS. Figure 1B As shown in the figure, all BITS interface connections marked with dotted ovals will lose track of enhanced QL. Even if the SyncE interface on the same device supports enhanced QL, only QL functions (not enhanced QL functions) can be supported on its BITS interface. Even if each provider privately supports enhanced QL based on BITS, it is difficult to meet the IOP (interoperability) requirements between different providers due to the lack of a common definition.

[0034] It can be seen that since there is no ITU-T standard defining the distribution method of enhanced QL in BITS networks, it leads to the hybrid network of BITS and SyncE (for example Figure 1B End-to-end support for enhanced quality levels cannot be provided in a clock synchronous network such as the one shown.

[0035] In view of this, some embodiments of the present disclosure provide solutions for supporting enhanced QL for BITS interfaces. For example, hybrid networking supporting BITS and SyncE may be defined in ITU-T standards (e.g., ITU-T G.704 standard). Specifically, in order to achieve accurate distribution of quality levels (i.e., end-to-end tracking and delivery of enhanced QL) in a hybrid network of BITS and SyncE, the new quality level (enhanced QL) defined in ITU-T G.781 is also extended for BITS networks in ITU-T standards (e.g., ITU-T G.704 standard).

[0036] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Figure 2 , Figure 2 A schematic diagram of a method for communication according to certain embodiments of the present disclosure is shown. For the purpose of discussion, reference will be made to Figure 1A and Figure 1B The communication method 200 is described. For example, the communication method 200 may be Figure 1A For another example, the communication method 200 may be performed by the network device 100 shown in FIG. Figure 1B The control logic may be performed by various network devices shown, such as OLT 113, remote OLT 114, or remote OLT 116.

[0037] like Figure 2 As shown, in box 210, the network device 100 receives first clock synchronization information via the input interface 100-1, wherein the first clock synchronization information may indicate at least one enhanced quality level QL of the clock source. In box 220, the network device 100 outputs second clock synchronization information via the output interface 100-2, wherein the second clock synchronization information indicates at least one enhanced quality level QL of the clock source, and the output interface 100-2 may be a building integrated timing supply BITS interface. In this way, unlike the traditional technical solution that is not extended for BITS and cannot carry the enhanced quality level QL on the BITS interface, the communication method 200 provided in the embodiment of the present disclosure can output clock synchronization information carrying the enhanced quality level QL on the BITS output interface, so it will not cause the loss of the enhanced quality level QL, thereby being able to provide end-to-end support for the enhanced quality level of clock synchronization information in a hybrid network of BITS and SyncE.

[0038] In some embodiments, the input interface 100-1 of the network device 100 is a synchronous Ethernet SyncE interface, the first clock synchronization information is an enhanced synchronization status message eSSM, at least one enhanced QL is carried in the type-length-value TLV field contained in the Ethernet synchronization message channel ESMC protocol data unit PDU, and the second clock synchronization information is an E1 data frame or a T1 data frame.

[0039] As an example, the network device 100 extracts first indication information of at least one enhanced QL from the ESMC PDU. Then, the network device 100 determines second indication information of at least one enhanced QL that complies with the BITS protocol. Next, the network device generates an E1 data frame or a T1 data frame to include the second indication information.

[0040] In some other embodiments, the input interface 100 - 1 of the network device 100 is a BITS interface, the first clock synchronization information is a first E1 data frame or a first T1 data frame, and the second clock synchronization information is a second E1 data frame or a second T1 data frame.

[0041] In some cases, the network device 100 extracts at least one enhanced QL from the first E1 data frame or the first T1 data frame. Then, the network device 100 verifies the at least one enhanced QL. Next, the network device 100 generates a second E1 data frame or a second T1 data frame to indicate the verified at least one enhanced QL.

[0042] In order to support enhanced QL, the network device 100 needs to update the management model. In some embodiments, the management model adopts the Yang model. In order to support QL and enhanced QL mode in the SDN access network (clock synchronization network), a new Yang model leaf node is introduced in the network synchronization Yang model to indicate whether enhanced QL is supported.

[0043] The operator can configure the Yang model of the network device 100 according to the actual network deployment requirements. Through this configuration, the network device 100 (such as an OLT product) will support better forward compatibility and provide flexibility.

[0044] That is, the network device 100 can process the first clock synchronization information or the second clock synchronization information based on the Yang model, and the Yang model includes a model configuration for supporting at least one enhanced QL. In addition, the Yang model can include a Yang model leaf node for indicating whether the Yang model supports at least one enhanced QL.

[0045] As an example, part of the Yang model code can be updated as follows:

[0046]

[0047]

[0048]

[0049]

[0050] As shown in the above part of the code, in some embodiments of the present disclosure, a Boolean value about "enhanced QL" is added to the Yang model, and the enhanced QL mode can be enabled for the network device 100 by using the Boolean value. In addition, the above code part adds the definition of the following four quality levels: enhanced primary reference time clock ePRTC, primary reference time clock PRTC, enhanced primary reference clock ePRC, and enhanced Ethernet equipment clock eSEC. These four newly added quality levels belong to enhanced QL, which have been introduced in ITU-T G.781 for SyncE, but have not yet been defined in the ITU-T series of standards for BITS (such as ITU-T G.704 standard).

[0051] Therefore, in order to support the newly defined QL in BITS, the QL processing mechanism needs to be extended for these new types. In the ITU-T G.704 standard, section "2.3.4 SynchronizationStatus:S an The bit allocation of the synchronization status message (SSM) for 2048 kbit / s is provided as shown in Table 1 below.

[0052] Table 1 Synchronization Status Message (SSM) bit allocation for 2048 kbit / s

[0053]

[0054] For E1 data frames, the present disclosure extends the SSM bit allocation provided by G.704 as shown in Table 1, so that it also performs bit allocation for enhanced QL, such as the above four enhanced QLs: ePRTC, PRTC, ePRC, and eSEC. As an example, based on Table 1, the present disclosure extends the bit allocation for enhanced QL on E1 data frames as shown in Table 2 below.

[0055] Table 2 Extended SSM bit allocation for enhanced QL on E1

[0056]

[0057] That is, in some embodiments, the second clock synchronization information is an E1 data frame, and at least one enhanced quality level QL is indicated by a synchronization status message SSM bit allocation value in the E1 data frame.

[0058] As shown in Table 2, for the four newly added QLs, their bit allocation utilizes the reserved codes in Table 1, that is, the reserved bit allocation in Table 1 is utilized, and the reserved bit allocation is utilized in an interspersed manner. As an example, an SSM bit allocation value of 0101 can indicate ePRTC, an SSM bit allocation value of 0110 can indicate PRTC, an SSM bit allocation value of 1001 can indicate ePRC, and an SSM bit allocation value of 1100 can indicate eSEC. The advantages of setting the four newly added types of bit allocation in the above interspersed manner include, for example, facilitating balanced bit distribution and reducing crosstalk between bits.

[0059] In the ITU-T G.704 standard, chapter "2.1 Basic frame structure at 1544kbit / s" describes the detailed frame structure of 1544kbit / s. The data link provides a communication path between primary-level terminals. Functionally, data link operation messages include four types: priority messages, loopback messages, protection switching messages, and synchronization messages. In some embodiments of the present disclosure, only the synchronization message needs to be extended to support enhanced QL, and other types of messages are not affected. The data link operation message is transmitted in the form of a 16-bit sequence, as shown in Table 3.

[0060] Table 3 Data link operation message coding format

[0061]

[0062] Table 3 above shows the encoding format of the data link operation message, where the 8 bits of the first byte are all "1", the first and last bits of the second byte are all 0, and the remaining 6 bits P1-P6 are used to encode the operation message. The 6 bits can allow 64 types of messages to be encoded. The encoding of the priority message, loopback message and protection message is shown in Table 4.

[0063] Table 4 Data link operation message allocation except synchronization messages

[0064]

[0065] Table 4 above shows the encoding of the above three data link operation messages except the synchronization message. As described above, the three data link operation messages do not need to be changed.

[0066] According to some embodiments of the present disclosure, only the coding of the synchronization message is expanded to include four newly added QLs, namely enhanced QLs. According to the current G.704, the bit allocation (coding) in the data link operation information for synchronization on the T1 data frame is shown in Table 5.

[0067] Table 5 Synchronization Status Message (SSM) bit allocation for 2048 kbit / s

[0068]

[0069] Since various messages are uniformly allocated, other unallocated bit sequences (codings) shown in Table 5 can be used to represent enhanced QL, thereby transmitting enhanced QL information in the T1 data frame.

[0070] As an example, the bit sequence (coding) for extending the enhanced QL on the T1 data frame is shown in Table 6 below.

[0071] Table 6 Extensions for enhanced QL on T1

[0072]

[0073] That is, in some embodiments, the second clock synchronization information is a T1 data frame, and at least one enhanced quality level QL is indicated by a codeword of a data link operation message in the T1 data frame.

[0074] As shown in Table 6, for the four newly added QLs, according to the best effective distribution principle, their bit sequences (codings) utilize the codes or codewords that are not used in Table 5. As an example, the codeword 11111111 00110100 can indicate ePRTC, the codeword 1111111101011000 can indicate PRTC, the codeword 11111111 01101000 can indicate ePRC, and the codeword 11111111 01111000 can indicate eSEC.

[0075] The above codewords are used to indicate the four newly added types of QL, and their advantages include, for example, being conducive to balanced bit distribution and being able to reduce crosstalk between bits.

[0076] Figure 3 FIG. 3 is a schematic diagram showing the functional structure of a network device 300 according to some embodiments of the present disclosure. Figure 1A and Figure 1B Describe the network device 300. For example, the network device 300 may be Figure 1A The example structure of the network device 100 shown in FIG. Figure 1B Example structures of various network devices (such as OLT 113, remote OLT 114, or remote OLT 116, etc.) are shown.

[0077] As an example, Figure 3In the network device 300 shown, the input interface for receiving clock synchronization information adopts the SyncE interface, and the output interface for sending clock synchronization information adopts the BITS interface, that is, "SyncE in, BITS out". As shown in the figure, the network device 300 includes an Ethernet (ETH) input interface 300-1, a switch module 301, a clock hardware abstraction layer module 302, a clock application module 303, a clock latch module 304, a BITS frame encoding module 305 and an output interface 300-2. The clock application module 303 further includes an SSM message manager module 303-1 and an SSM protocol stack module 303-2. It is easy to understand that the network device 300 may also include various other functional modules not shown in the figure. The network device 300 can be remotely configured by the cloud 300-3 (e.g., a cloud server).

[0078] like Figure 3 As shown, the network device 300 receives clock synchronization information through the input interface 300-1. As shown in the figure, the clock synchronization information includes two types of information: SyncE signal and enhanced synchronization status message (eSSM) packet, wherein the SyncE signal represents the clock signal of the physical layer, and the quality level QL (i.e., the accuracy level of the corresponding clock source) information of the clock signal of the physical layer is carried in the corresponding eSSM packet.

[0079] As mentioned above, the eSSM packet is specifically an ESMC PDU, and the QL information is carried in the TLV field of the ESMC PDU. Therefore, when the SyncE interface is used, the clock synchronization information actually includes two pieces of information, one is the physical clock signal, and the other is information indicating the quality level of the physical clock signal, that is, the QL information, which is included in the eSSM packet. It can be understood that although Figure 3 The clock synchronization information shown in FIG. 1 uses two arrows to represent the SyncE signal and the eSSM packet respectively, but this does not mean that they are received via two physical interfaces respectively. In fact, the two information constituting the clock synchronization information are received via one physical interface, namely, the Ethernet interface ETH 300-1.

[0080] After the SyncE signal and the eSSM packet are received through the Ethernet interface ETH, they enter the switch module 301. The switch module 301 recovers the timing clock from the SyncE signal, and forwards the recovered timing clock together with the eSSM packet to the clock hardware abstraction layer module 302. The clock hardware abstraction layer module 302 is a hardware adapter module, which is responsible for the transmission of information between the clock application module 303 and other modules in the network device 300. For example, the clock hardware abstraction layer module 302 receives the eSSM packet from the switch module 301 and hands it over to the SSM protocol stack module 303-2 for processing. The SSM message manager module 303-1 is responsible for the management and configuration of the QL mode of the network device 300, such as the management and configuration of the QL mode based on the Yang model, including the configuration of the enhanced QL mode. After configuration of the SSM message manager module 303-1, the SSM protocol stack module 303-2 can extract the enhanced QL value from the eSSM packet (ESMC packet), convert it into an enhanced QL value in the BITS frame (for E1 format or T1 format), perform storage operations on the enhanced QL value, etc.

[0081] In addition, the network device 300 may receive multiple channels of clock synchronization information with different clock precision (i.e., different QL values). In this case, it is necessary to select the channel of clock synchronization information with the highest clock precision for clock locking and issuing operations. Then the SSM protocol stack module 303-2 will store and update the QL level based on the clock synchronization information selected by the channel. The SSM protocol stack module 303-2 forwards the selected channel of clock synchronization information to the clock latch module 304 for local clock calibration. At the same time, the SSM protocol stack module 303-2 also forwards the selected channel of clock synchronization information to the BITS frame encoding module 305. The BITS frame encoding module 305 performs BITS frame encoding operations on the clock synchronization information, including encoding the QL value into the frame header. Then, the clock synchronization information is output through the output interface 300-2 in the form of a frame (T1 frame or E1 frame), and is further transmitted to other downstream network devices.

[0082] It is easy to understand that although Figure 3 The output interface type used by the network device 300 for clock synchronization information is a BITS interface, but in some embodiments, the network device 300 may also use an output interface of the SyncE interface type, for example, the network device 300 includes one or more other output interfaces, which use SyncE signals to output clock synchronization information. In this case, the clock synchronization information selected by the clock application module 303 can be returned to the switch module 301, and the switch module 301 then outputs the clock synchronization information through the output interface, namely the SyncE interface (not shown in the figure), so as to be sent to other downstream network devices.

[0083] Figure 4 FIG. 4 is a schematic diagram showing the functional structure of a network device 400 according to some embodiments of the present disclosure. Figure 1A and Figure 1B Describe network device 400. For example, network device 400 may be Figure 1A The example structure of the network device 100 shown in FIG. 4 is another example. Figure 1B Example structures of various network devices (such as OLT 113, remote OLT 114, or remote OLT 116, etc.) are shown.

[0084] As an example, Figure 4 In the network device 400 shown, the input interface for receiving clock synchronization information and the output interface for sending clock synchronization information both adopt the BITS interface, that is, the "BITS in, BITS out" method is adopted. As shown in the figure, the network device 400 includes an input interface 400-1, a line interface unit LIU 401, a clock hardware abstraction layer module 402, a clock application module 403, a clock latch module 404, a BITS frame encoding module 405 and an output interface 400-2. The clock application module 403 further includes an SSM message manager module 403-1 and an SSM protocol stack module 403-2. It is easy to understand that the network device 400 may also include various other functional modules not shown in the figure. The network device 400 can be remotely configured by the cloud 400-3 (e.g., a cloud server).

[0085] like Figure 4 As shown, the network device 400 receives the clock synchronization information in the BITS format through the input interface 400-1. The line interface unit module LIU 401 decodes the clock synchronization information in the BITS format and passes the decoded clock synchronization information to the clock hardware abstraction layer module 402. The clock hardware abstraction layer module 402 is a hardware adapter module, which is responsible for the transmission of information between the clock application module 403 and other modules in the network device 400, for example, receiving the clock synchronization information from the LIU module and extracting the QL value, which can be an enhanced QL value, and passing it to the SSM protocol stack module 403-2 for processing. Figure 3 As discussed in , the SSM protocol stack module 403-2 is responsible for the management and configuration of the QL mode of the network device 400, such as the management and configuration of the QL mode based on the Yang model, including the configuration of the enhanced QL mode. After being configured by the SSM message manager module 403-1, the SSM protocol stack module 403-2 supports the new enhanced QL processing, which verifies the QL value in the clock synchronization information of the E1 frame or T1 frame format received by the network device 400.

[0086] As mentioned above, the network device 400 may receive multiple clock synchronization information with different clock precision (i.e., different QL values). In this case, it is necessary to select the clock synchronization information with the highest clock precision for clock locking and issuing operations. Then the SSM protocol stack module 403-2 will store and update the QL (after verification) based on the clock synchronization information selected by the channel. The SSM protocol stack module 403-2 forwards the selected clock synchronization information to the clock latch module 404 via the clock hardware abstraction layer module 402 for local clock calibration. Among them, CLOCK HWA 402 will insert the corresponding QL value into the BITS frame and forward it to the BITS frame encoding module 405. The BITS frame encoding module 405 further performs the encoding operation of the BITS frame, including encoding the QL value into the frame header. Then, the clock synchronization information is output through the output interface 400-2 in the form of a frame (T1 frame or E1 frame), and is further transmitted to other downstream network devices.

[0087] Figure 3 and Figure 4 The scenario shown can cover all situations where BITS output is used for frequency synchronization in network devices, regardless of the frequency input interface (whether BITS interface input or SyncE interface input). It is easy to understand that Figure 3 and Figure 4 The embodiment is also suitable for scenarios combined with time and phase synchronization.

[0088] According to the solution provided by the embodiments of the present disclosure, only the clock application and the clock hardware abstraction layer (ie, the clock hardware adapter HWA) need to be updated to support enhanced QL processing at the software level, without the need to update at the hardware level.

[0089] In some example embodiments, an apparatus capable of performing any of the methods 200 (e.g., network device 100, network device 300, or network device 400) may include a component for performing the corresponding operations of the method 200. The component may be implemented in any suitable form. For example, the component may be implemented in a circuit system or a software module. The apparatus may be implemented as network device 100, network device 300, or network device 400 or included in network device 100, network device 300, or network device 400.

[0090] In some example embodiments, a device includes: a component for receiving first clock synchronization information via an input interface of the device, wherein the first clock synchronization information indicates at least one enhanced quality level QL of a clock source; and a component for outputting second clock synchronization information via an output interface of the device, wherein the second clock synchronization information indicates at least one enhanced QL of the clock source, and the output interface is a Building Integrated Timing Supply BITS interface.

[0091] In some example embodiments, the input interface is a synchronous Ethernet SyncE interface, the first clock synchronization information is an enhanced synchronization status message eSSM, at least one enhanced QL is carried in a type-length-value TLV field contained in an Ethernet synchronization message channel ESMC protocol data unit PDU, and the second clock synchronization information is an E1 data frame or a T1 data frame.

[0092] In some example embodiments, the apparatus further includes: a component for extracting first indication information of at least one enhanced QL from the ESMC PDU; a component for determining second indication information of at least one enhanced QL that complies with the BITS protocol; and a component for generating an E1 data frame or a T1 data frame to include the second indication information.

[0093] In some example embodiments, the input interface is a BITS interface, the first clock synchronization information is a first E1 data frame or a first T1 data frame, and the second clock synchronization information is a second E1 data frame or a second T1 data frame.

[0094] In some example embodiments, the apparatus further comprises: means for extracting at least one enhanced QL from a first E1 data frame or a first T1 data frame; means for verifying at least one enhanced QL; and means for generating a second E1 data frame or a second T1 data frame to indicate the verified at least one enhanced QL.

[0095] In some example embodiments, the apparatus further comprises means for processing at least one of the first clock synchronization information or the second clock synchronization information based on a Yang model, and the Yang model comprises a model configuration for supporting at least one enhanced QL.

[0096] In some example embodiments, the Yang model further includes a Yang model leaf node for indicating whether the Yang model supports at least one enhanced QL.

[0097] In some example embodiments, the at least one enhanced QL includes at least one of: an enhanced primary reference time clock ePRTC, a primary reference time clock PRTC, an enhanced primary reference clock ePRC, or an enhanced Ethernet equipment clock eSEC.

[0098] In some example embodiments, the second clock synchronization information is an E1 data frame, and the at least one enhanced quality level QL is indicated by a synchronization status message SSM bit allocation value in the E1 data frame.

[0099] In some example embodiments, an SSM bit allocation value of 0101 indicates ePRTC, an SSM bit allocation value of 0110 indicates PRTC, an SSM bit allocation value of 1001 indicates ePRC, or an SSM bit allocation value of 1100 indicates eSEC.

[0100] In some example embodiments, the second clock synchronization information is a T1 data frame, and the at least one enhanced quality level QL is indicated by a codeword of a data link operation message in the T1 data frame.

[0101] In some example embodiments, the codeword is 11111111 00110100 indicating ePRTC, the codeword is 1111111101011000 indicating PRTC, the codeword is 11111111 01101000 indicating ePRC, or the codeword is 11111111 01111000 indicating eSEC.

[0102] In some example embodiments, the apparatus further comprises means for performing other steps in some embodiments of method 200. In some embodiments, the means comprises at least one processor and at least one memory storing computer program code. The at least one memory and the computer program code are configured to, together with the at least one processor, cause execution of the apparatus.

[0103] Figure 5 5 is a simplified block diagram of an electronic device 500 suitable for implementing an embodiment of the present disclosure. The device 500 may be provided to implement a communication device, such as Figure 1A The network device 100 shown in FIG. Figure 1A Various network devices (such as OLT 113, remote OLT 114, or remote OLT 116, etc.) are shown. Figure 3 The network device 300 shown and Figure 4 The network device 400 is shown. As shown, the device 500 includes one or more processors 510, one or more memories 520 coupled to the processor 510, and one or more communication modules 540 coupled to the processor 510.

[0104] The communication module 540 is used for two-way communication. For example, the communication module 540 may include a transmitter, a receiver, or a transceiver used in the embodiments of the present disclosure. The communication interface may represent any interface necessary for communicating with other network elements.

[0105] Processor 510 may be of any type suitable for the local technology network and may include, but is not limited to, one or more of a general purpose computer, a special purpose computer, a microcontroller, a digital signal controller (DSP), and a controller-based multi-core controller architecture. Device 500 may have multiple processors, such as application specific integrated circuit chips, which are time-slaved to a clock synchronized with a main processor.

[0106] The memory 520 may include one or more non-volatile memories and one or more volatile memories. Examples of non-volatile memories include, but are not limited to, read-only memory (ROM) 524, erasable programmable read-only memory (EPROM), flash memory, hard disks, compact disks (CDs), digital video disks (DVDs), and other magnetic and / or optical storage. Examples of volatile memories include, but are not limited to, random access memory (RAM) 522 and other volatile memories that do not persist over the duration of a power outage.

[0107] Computer program 530 includes computer executable instructions executed by associated processor 510. Program 530 may be stored in ROM 1420. Processor 510 may perform any suitable actions and processes by loading program 530 into RAM 520.

[0108] The embodiments of the present disclosure can be implemented with the help of program 530, so that the device 500 can execute the Figure 2 Any process of the present disclosure discussed. The embodiments of the present disclosure may also be implemented by hardware or by a combination of software and hardware.

[0109] In some embodiments, the program 530 may be tangibly embodied in a computer-readable medium that may be included in the device 500 (such as in the memory 520) or other storage device accessible by the device 500. The program 530 may be loaded from the computer-readable medium to the RAM 522 for execution. The computer-readable medium may include any type of tangible non-volatile memory, such as ROM, EPROM, flash memory, hard disk, CD, DVD, etc.

[0110] Figure 6 An example of a computer readable medium 600 in the form of a CD or DVD is shown. The computer readable medium has a program 630 stored thereon.

[0111] In general, various embodiments of the present disclosure may be implemented in hardware or dedicated circuits, software, logic, or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software, which may be performed by a controller, microprocessor, or other computing device. Although various aspects of the embodiments of the present disclosure are shown and described as block diagrams, flow charts, or using some other graphical representation, it should be understood that the blocks, devices, systems, techniques, or methods described herein may be implemented as, by way of non-limiting example, hardware, software, firmware, dedicated circuits or logic, general purpose hardware or a controller or other computing device, or some combination thereof.

[0112] The present disclosure also provides at least one computer program product tangibly stored on a non-transitory computer-readable storage medium. The computer program product includes computer executable instructions, such as instructions included in a program module, which are executed in a device on a real or virtual processor of a target to perform the above-referenced Figure 2 Method 200. Typically, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform specific tasks or implement specific abstract data types. In various embodiments, the functionality of program modules can be combined or divided between program modules as needed. Machine executable instructions for program modules can be executed in local or distributed devices. In distributed devices, program modules can be located in local and remote storage media.

[0113] The computer program code for realizing the method of the present disclosure can be written in one or more programming languages. These computer program codes can be provided to the processor of general-purpose computer, special-purpose computer or other programmable data processing device, so that the program code, when being executed by computer or other programmable data processing device, causes the function / operation specified in flow chart and / or block diagram to be implemented. The program code can be executed completely on computer, partly on computer, as independent software package, partly on computer and partly on remote computer or completely on remote computer or server.

[0114] In the context of the present disclosure, computer program codes or related data may be carried by any appropriate carrier to enable a device, apparatus or processor to perform the various processes and operations described above. Examples of carriers include signals, computer readable media, and the like. Examples of signals may include electrical, optical, radio, acoustic or other forms of propagation signals, such as carrier waves, infrared signals, and the like.

[0115] A computer-readable medium may be any tangible medium containing or storing a program for or about an instruction execution system, device or equipment. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, device or equipment, or any suitable combination thereof. A more detailed example of a computer-readable storage medium includes an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical storage device, a magnetic storage device, or any suitable combination thereof. As used herein, the term "non-transient" or "non-transient" is a limitation on the medium itself (i.e., tangible, not a signal), rather than a limitation on the persistence of data storage (e.g., RAM and ROM).

[0116] In addition, although the operation of the method of the present disclosure is described in a particular order in the accompanying drawings, this does not require or imply that these operations must be performed in this particular order, or that all the operations shown must be performed to achieve the desired result. On the contrary, the steps depicted in the flow chart can change the order of execution. Additionally or alternatively, some steps can be omitted, multiple steps can be combined into one step for execution, and / or one step can be decomposed into multiple steps for execution. It should also be noted that the features and functions of two or more devices according to the present disclosure can be embodied in one device. Conversely, the features and functions of a device described above can be further divided into being embodied by multiple devices.

[0117] Although the present disclosure has been described with reference to several specific embodiments, it should be understood that the present disclosure is not limited to the specific embodiments disclosed. The present disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0118] List of abbreviations

[0119] QL Quality Level

[0120] QL TLV quality level type length value

[0121] ESMC Ethernet Sync Message Channel

[0122] EEC Synchronous Ethernet Equipment Clock

[0123] eEEC Enhanced Synchronous Ethernet Equipment Clock

[0124] SSM synchronization status message

[0125] eSSM enhanced synchronization status message

[0126] ePRC enhanced master reference clock

[0127] ePRTC Enhanced Primary Reference Time Clock

[0128] FAS frame alignment signal

[0129] LFA frame alignment lost

[0130] SSU Synchronous Supply Unit

[0131] BITS building integrated time supply

[0132] SyncE Synchronous Ethernet

[0133] GPON Gigabit Passive Optical Network

[0134] EPON Ethernet Passive Optical Network

[0135] OLT Optical Line Terminal

[0136] ONU optical network unit

[0137] BS Base Station

[0138] DNU not used

[0139] DUS is not used for synchronization

[0140] IOP interoperability.

Claims

1. A device comprising: at least one processor; as well as at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus to at least: receiving first clock synchronization information via an input interface of the apparatus, wherein the first clock synchronization information indicates at least one enhanced quality level QL of a clock source; as well as The second clock synchronization information is output via an output interface of the device, wherein the second clock synchronization information indicates the at least one enhanced QL of the clock source, and the output interface is a Building Integrated Timing Supply (BITS) interface.

2. The device according to claim 1, wherein the input interface is a synchronous Ethernet SyncE interface, the first clock synchronization information is an enhanced synchronization status message eSSM, the at least one enhanced QL is carried in a type-length-value TLV field contained in an Ethernet synchronization message channel ESMC protocol data unit PDU, and the second clock synchronization information is an E1 data frame or a T1 data frame.

3. The apparatus according to claim 2, wherein the apparatus is further configured to: Extracting first indication information of the at least one enhanced QL from the ESMC PDU; Determine second indication information of the at least one enhanced QL that complies with the BITS protocol; as well as The E1 data frame or the T1 data frame is generated to include the second indication information. 4 . The apparatus according to claim 1 , wherein the input interface is a BITS interface, the first clock synchronization information is a first E1 data frame or a first T1 data frame, and the second clock synchronization information is a second E1 data frame or a second T1 data frame.

5. The apparatus according to claim 4, wherein the apparatus is further configured to: extracting the at least one enhanced QL from the first E1 data frame or the first T1 data frame; validating the at least one enhanced QL; and The second E1 data frame or the second T1 data frame is generated to indicate the verified at least one enhanced QL.

6. The apparatus according to any one of claims 1-5, wherein the apparatus processes at least one of the first clock synchronization information or the second clock synchronization information based on a Yang model, and the Yang model includes a model configuration for supporting the at least one enhanced QL. 7 . The apparatus according to claim 6 , wherein the Yang model further comprises a Yang model leaf node for indicating whether the Yang model supports the at least one enhanced QL.

8. The apparatus of any one of claims 1-7, wherein the at least one enhanced QL comprises at least one of: Enhanced primary reference time clock ePRTC, Primary Reference Time Clock PRTC, Enhanced Primary Reference Clock (ePRC), or Enhanced Ethernet Equipment Clock eSEC.

9. The apparatus according to any one of claims 1 to 8, wherein the second clock synchronization information is an E1 data frame, and the at least one enhanced quality level QL is indicated by a synchronization status message SSM bit allocation value in the E1 data frame.

10. The device according to claim 9, wherein at least one of the following: The SSM bit allocation value is 0101 to indicate ePRTC; The SSM bit allocation value is 0110 to indicate PRTC; The SSM bit allocation value is 1001 to indicate ePRC; or The SSM bit assignment value is 1100 indicating eSEC.

11. The apparatus according to any one of claims 1 to 8, wherein the second clock synchronization information is a T1 data frame, and the at least one enhanced quality level QL is indicated by a codeword of a data link operation message in the T1 data frame.

12. The device of claim 11, wherein at least one of the following: The codeword is 11111111 00110100 indicating ePRTC; The code word is 11111111 01011000 indicating PRTC; The codeword is 11111111 01101000 indicating ePRC; or The codeword is 11111111 01111000 indicating eSEC.

13. A method comprising: receiving, via an input interface of the device, first clock synchronization information, wherein the first clock synchronization information indicates at least one enhanced quality level QL of a clock source; as well as The second clock synchronization information is output via an output interface of the device, wherein the second clock synchronization information indicates the at least one enhanced QL of the clock source, and the output interface is a Building Integrated Timing Supply (BITS) interface.

14. The method according to claim 13, wherein the input interface is a synchronous Ethernet SyncE interface, the first clock synchronization information is an enhanced synchronization status message eSSM, the at least one enhanced QL is carried in a type-length-value TLV field contained in an Ethernet synchronization message channel ESMC protocol data unit PDU, and the second clock synchronization information is an E1 data frame or a T1 data frame.

15. The method according to claim 14, further comprising: Extracting first indication information of the at least one enhanced QL from the ESMC PDU; Determine second indication information of the at least one enhanced QL that complies with the BITS protocol; as well as The E1 data frame or the T1 data frame is generated to include the second indication information. 16 . The method according to claim 13 , wherein the input interface is a BITS interface, the first clock synchronization information is a first E1 data frame or a first T1 data frame, and the second clock synchronization information is a second E1 data frame or a second T1 data frame.

17. The method according to claim 16, further comprising: extracting the at least one enhanced QL from the first E1 data frame or the first T1 data frame; validating the at least one enhanced QL; as well as The second E1 data frame or the second T1 data frame is generated to indicate the verified at least one enhanced QL.

18. The method according to any one of claims 13 to 17, further comprising: At least one of the first clock synchronization information or the second clock synchronization information is processed based on a Yang model, and the Yang model includes a model configuration for supporting the at least one enhanced QL.

19. The method of claim 18, wherein the Yang model further comprises a Yang model leaf node for indicating whether the Yang model supports the at least one enhanced QL.

20. The method of any one of claims 13-19, wherein the at least one enhanced QL comprises at least one of: Enhanced primary reference time clock ePRTC, Primary Reference Time Clock PRTC, Enhanced Primary Reference Clock (ePRC), or Enhanced Ethernet Equipment Clock eSEC.

21. The method according to any one of claims 13 to 20, wherein the second clock synchronization information is an E1 data frame, and the at least one enhanced quality level QL is indicated by a synchronization status message SSM bit allocation value in the E1 data frame.

22. The method of claim 21, wherein at least one of the following: The SSM bit allocation value is 0101 to indicate ePRTC; The SSM bit allocation value is 0110 to indicate PRTC; The SSM bit allocation value is 1001 to indicate ePRC; or The SSM bit assignment value is 1100 indicating eSEC.

23. The method according to any one of claims 13-20, wherein the second clock synchronization information is a T1 data frame, and the at least one enhanced quality level QL is indicated by a codeword of a data link operation message in the T1 data frame.

24. The method of claim 23, wherein at least one of the following: The codeword is 11111111 00110100 indicating ePRTC; The code word is 11111111 01011000 indicating PRTC; The codeword is 11111111 01101000 indicating ePRC; or The codeword is 11111111 01111000 indicating eSEC.

25. An apparatus comprising: means for receiving, via an input interface of the apparatus, first clock synchronization information, wherein the first clock synchronization information indicates at least one enhanced quality level QL of a clock source; as well as means for outputting second clock synchronization information via an output interface of the apparatus, wherein the second clock synchronization information indicates the at least one enhanced QL of the clock source, and the output interface is a Building Integrated Timing Supply (BITS) interface.

26. A computer-readable medium having instructions stored thereon, which, when executed by at least one processing unit, causes the at least one processing unit to be configured to perform the method according to any one of claims 13-24.

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