PTP time-frequency synchronization method for distributed data synchronous acquisition

Abstract

The invention discloses a PTP (Precision Time Protocol) time-frequency synchronization method for distributed data synchronous acquisition, which comprises the following steps of: firstly building a PTP synchronization architecture of a distributed data acquisition system, and then generating a hardware timestamp based on a slave hardware clock; and finally, based on a PTP synchronization architecture of a distributed data acquisition system, realizing high-precision time and frequency synchronization between each slave and the host by adopting a three-stage synchronization mechanism, so that synchronous sampling of each slave is completed on the premise that the host and the slave perform periodic PTP synchronization.

Description

Technical Field

[0001] The present invention belongs to the technical field of distributed data acquisition, and more specifically, relates to a PTP time-frequency synchronization method for distributed data synchronous acquisition. Background Art

[0002] Distributed data acquisition system is a key part of modern measurement and control engineering. It can help avoid noise interference caused by long-distance transmission of analog signals from front-end sensors. This technology is widely used in factory automation, smart grid, large wind tunnels, large turbine shafts, long-span bridges, nuclear physics experiments and telescope arrays.

[0003] In a distributed data acquisition system, distributed data acquisition devices are required to collect multiple related signals for joint data processing and analysis. This requires time synchronization of distributed acquisition devices, giving time information to the sampling data points, and making the collected data point-to-point synchronized. At the same time, with the rapid development of science and technology, the performance of data acquisition systems is getting higher and higher, which requires not only time synchronization of distributed data acquisition systems, but also sampling synchronization of each distributed data acquisition device (i.e. frequency and phase synchronization of the sampling clock).

[0004] Precision Time Protocol (PTP) is a high-precision network time synchronization protocol based on Ethernet. This protocol has the characteristics of low cost, high synchronization accuracy and low resource consumption, and has been widely studied and applied in the field of distributed data acquisition. The PTP protocol exchanges message data on the master-slave link and records timestamps. The slave obtains four timestamps t1, t2, t3, and t4 to calculate the average delay of the master-slave link and the clock deviation of the master and slave nodes, and the synchronization algorithm completes the time synchronization of the slave to the host. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a PTP time-frequency synchronization method for distributed data synchronous acquisition to achieve high-precision time and frequency synchronization between each slave and a host in a distributed data acquisition system.

[0006] To achieve the above-mentioned object of the invention, the present invention provides a PTP time-frequency synchronization method for distributed data synchronous acquisition, characterized in that it includes the following steps:

[0007] (1) Build the PTP synchronization architecture of the distributed data acquisition system;

[0008] Select a switch that supports PTP hardware synchronization as the host of PTP synchronization, and the distributed data acquisition system as the slave of PTP synchronization, and directly connect the slave to the switch host through a network cable;

[0009] (2) Generation of hardware clock and hardware timestamp;

[0010] Set each slave to use a voltage-controlled crystal oscillator (VCXO) as the hardware clock source;

[0011] Set the initial timestamp value of each slave. The real-time clock module RTC in the slave PTP hardware clock system takes the initial timestamp value as the starting point and generates the PTP hardware timestamp T of each slave based on the hardware clock cumulative time base value. i , where i represents the slave number;

[0012] (3) The master and slave machines perform periodic PTP synchronization;

[0013] (3.1) Set the cycle number k and initialize k = 1;

[0014] (3.2) Each slave establishes a PTP protocol stack to implement PTP synchronization message exchange based on the PTP hardware timestamp T i Get the timestamp information t of the kth PTP synchronization 1,i (k)-t 4,i (k);

[0015] (3.3) Calculate the link delay d during the kth PTP synchronization between the master and slave i (k);

[0016]

[0017] (3.4) Calculate the time deviation θ of the kth PTP synchronization between the master and slave i (k);

[0018] θ i (k) = t 2,i (k)-t 1,i (k)-d i (k)

[0019] (3.5) Determine each time deviation θ i (k) Are they all less than the synchronization completion time deviation threshold θ sync , if θ i (k)<θ sync , then each slave is enabled to start synchronous sampling, and a three-level synchronization mechanism is used to achieve high-precision time and frequency synchronization between each slave and the host; otherwise, only a three-level synchronization mechanism is used to achieve high-precision time and frequency synchronization between each slave and the host;

[0020] (3.6) Let k = k + 1, and return to step (3.2) after the next synchronization cycle arrives to continue the next round of PTP synchronization.

[0021] The object of the invention of the present invention is achieved in this way:

[0022] The present invention discloses a PTP time-frequency synchronization method for distributed data synchronous acquisition. The method comprises the following steps: firstly building a PTP synchronization architecture of a distributed data acquisition system, and then generating a hardware timestamp based on a slave hardware clock; finally, based on the PTP synchronization architecture of the distributed data acquisition system, a three-level synchronization mechanism is adopted to realize high-precision time and frequency synchronization between each slave and a host, so that synchronous sampling of each slave is completed under the premise that the master and slave perform periodic PTP synchronization.

[0023] At the same time, the PTP time-frequency synchronization method for distributed data synchronous acquisition of the present invention also has the following beneficial effects:

[0024] (1) Adopt the PTP hardware synchronization solution and design the timestamp at the MII interface. Compared with PTP software synchronization, timestamp at the application layer reduces the timestamp error from microseconds to nanoseconds, greatly improving the synchronization accuracy. Compared with PTP hardware synchronization, timestamp at the PHY layer, timestamp at the MII interface does not require a PHY chip that supports PTP hardware synchronization, reducing hardware costs while maintaining the same nanosecond error level.

[0025] (2) A three-level synchronization mechanism is used to achieve fast time and frequency synchronization of the distributed data acquisition system. First, the first-level synchronization directly compensates for the time deviation of the master and slave machines, and directly reduces the time synchronization accuracy of the master and slave machines from the second level to the millisecond level. The second-level synchronization uses a PI controller combined with a corrected timestamp to generate a time base, which can quickly reduce the time synchronization accuracy of the master and slave machines from the millisecond level to hundreds of nanoseconds within dozens of cycles. The third-level synchronization uses a PI controller combined with a voltage-controlled VCXO crystal oscillator clock source, which can reduce the time synchronization accuracy of the master and slave machines within a few cycles and stabilize it within ±20ns, and complete the frequency synchronization of the master and slave clock sources.

[0026] (3) Sampling synchronization technology realizes the sampling synchronization and sampling data point synchronization of each distributed data acquisition system. Based on the ADC synchronous reset triggered by the 1PPS synchronization signal, the distributed data acquisition system can start sampling synchronously with high precision. The clock phase-locked frequency division technology is based on the 1PPS synchronization signal. Compared with the commonly used counting frequency division method, it can achieve nanosecond-level high-precision ADC sampling clock phase synchronization and complete high-precision sampling synchronization of each distributed data acquisition system. The sampling data point timestamping technology gives each sampling data point timestamp information to achieve sampling point synchronization of each distributed data acquisition system. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of a PTP time-frequency synchronization method for distributed data synchronous acquisition according to the present invention;

[0028] Figure 2This is a diagram of the PTP synchronization architecture of a distributed data acquisition system;

[0029] Figure 3 This is a schematic diagram of the RTC module generating timestamps;

[0030] Figure 4 It is a flowchart for implementing the three-level synchronization mechanism. DETAILED DESCRIPTION

[0031] The specific implementation of the present invention is described below in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0032] Example

[0033] For the convenience of description, the relevant professional terms appearing in the specific implementation methods are first explained:

[0034] PTP (Precision Time Protocol): Precision Time Protocol;

[0035] VCXO (voltage-controlled crystal oscillator): voltage-controlled crystal oscillator;

[0036] AXI GP (Advanced eXtensible Interface General Purpose): General purpose interface of advanced extensible interface;

[0037] RTC (Real Time Clock): Real-time clock;

[0038] PI (Proportional Integral Controller): Proportional Integral Controller;

[0039] DAC (Digital to Analog Converter): digital to analog converter;

[0040] ADC (Analog to Digital Converter): analog-to-digital converter;

[0041] 1PPS (One Pulse Per Second): 1 pulse per second;

[0042] TSU (Time Stamp Unit): time stamp unit;

[0043] PHC (PTP Hardware Clock): PTP hardware clock;

[0044] GMII (Gigabit Media Independent Interface): Gigabit Media Independent Interface;

[0045] ARM: ARM processor;

[0046] MII (Media Independent Interface): media independent interface;

[0047] PHY (Physical Layer): physical layer;

[0048] FPGA (Field Programmable Gate Array): Field Programmable Gate Array;

[0049] Linuxptp - an open source PTP software protocol stack.

[0050] H3C IE4320: IE4320 switch from H3C.

[0051] Xilinx ZYNQ: A fully programmable system-on-chip from Xilinx.

[0052] SoC (System on Chip): System on chip;

[0053] Figure 1 The present invention is a PTP time-frequency synchronization principle diagram for distributed data synchronous acquisition.

[0054] In this embodiment, combined with Figure 1 The PTP time-frequency synchronization principle diagram shown in the figure describes in detail a PTP time-frequency synchronization method for distributed data synchronization acquisition of the present invention, which includes the following steps:

[0055] (1) Build the PTP synchronization architecture of the distributed data acquisition system;

[0056] Select a switch that supports PTP hardware synchronization as the host of PTP synchronization, and the distributed data acquisition system as the slave of PTP synchronization, and directly connect the slave to the switch host through a network cable;

[0057] In this embodiment, the PTP synchronization architecture of the distributed data acquisition system is as follows: Figure 2As shown, H3C's IE4320 model switch is used as the host of PTP synchronization, supporting PTP hardware synchronization. Two distributed data acquisition devices are connected to the switch network cable as PTP synchronization slaves. The PC host is connected to the switch network cable, responsible for program-controlled distributed data acquisition devices and receiving and processing sampled data. In the embodiment, the two slaves complete time-frequency synchronization with the switch host through PTP time-frequency synchronization technology, and the two slaves complete sampling synchronization based on the hardware clock source of time-frequency synchronization.

[0058] In addition, the distributed data acquisition equipment (slave) uses Xilinx ZYNQ as the master SoC. ZYNQ is an FPGA+ARM architecture, with a PTP hardware clock system deployed on the FPGA side and a PTP protocol stack and clock servo system deployed on the ARM side. In addition, the hardware circuit parts including PHY, VCXO, DAC, and ADC are also designed.

[0059] (2) Generation of hardware clock and hardware timestamp;

[0060] Each slave is set to use a voltage-controlled crystal oscillator VCXO as a hardware clock source; in this embodiment, the hardware clock of each slave uses a 125MHz clock from the RGMII interface of the PHY chip, which is multiplied to 125MHz by a phase-locked loop inside the PHY chip from a 25MHz clock of the voltage-controlled crystal oscillator VCXO.

[0061] Set the initial timestamp value of each slave. The real-time clock module RTC in the slave PTP hardware clock system takes the initial timestamp value as the starting point and generates the PTP hardware timestamp T of each slave based on the hardware clock cumulative time base value. i , where i represents the slave number;

[0062] In this embodiment, the generation of timestamp is realized by the RTC module of the PTP hardware clock. The RTC module is implemented on the FPGA side, based on the accumulator principle, directly compensating the timestamp according to the time adjustment value, and accumulating the time base value under the hardware clock to generate a synchronized timestamp. Figure 3 As shown in the actual operation of FPGA, a 48-bit second register is designed to store the timestamp second information, and a 32-bit nanosecond register is designed to store the maximum 10 9 The timestamp nanosecond information of the value. The resolution of 1 in calculating the adjustment value is equal to 8×10 of the time base value. -9 Nanoseconds, so a 32-bit sub-nanosecond clock register is designed to save the sub-nanosecond information of the timestamp. When running PTP synchronization, the time adjustment value and time base value in the timestamp generation are sent by the clock servo system through the AXI_GP interface. When the system is powered on, the RTC module receives the system time and the 8ns standard time base from the ARM side, and uses this as the starting point to accumulate and generate the hardware timestamp.

[0063] (3) The master and slave machines perform periodic PTP synchronization;

[0064] (3.1) Set the cycle number k and initialize k = 1;

[0065] (3.2) Each slave establishes a PTP protocol stack to implement PTP synchronization message exchange based on the PTP hardware timestamp T i Get the timestamp information t of the kth PTP synchronization 1,i (k)-t 4,i (k);

[0066] In this embodiment, the timestamp information t of the kth PTP synchronization is 1,i (k)-t 4,i The method for obtaining (k) is:

[0067] (3.2.1) When each slave system is initialized, the PTP protocol stack configures the PHC subsystem, enables the hardware timestamp function and selects the network data packets that need to be stamped, and enables the kernel to obtain timestamps when receiving and sending data packets;

[0068] (3.2.2) In this embodiment, the host switch sends a Sync message to the slave at a period of 1s to start the PTP synchronization process;

[0069] (3.2.3) The TSU module of the PTP hardware clock system of each slave sets the timestamp of the arrival of the Sync message t 2,i (k), and then the timestamp t 2,i (k)Send to Linuxptp;

[0070] (3.2.4) The host continues to send Follow_up messages, carrying the timestamp t of the time when the Sync message was sent. 1,i (k);

[0071] (3.2.5) Each slave receives the Follow_up message, and the PHC subsystem parses the timestamp field of the message to obtain the timestamp t 1,i (k), sent to Linuxptp;

[0072] (3.2.6) The Linuxptp control of each slave sends a Delay_req message, and timestamps the time when the Delay_req message is sent in the TSU module of the PTP hardware clock system. 3,i (k), and then the timestamp t 3,i (k)Send to Linuxptp;

[0073] (3.2.7) The master timestamps the time when it receives the Delay_req message from each slave.4,i (k), carried in the Delay_Resp message and sent to each slave.

[0074] (3.2.8) Each slave receives the Delay_Resp message, and the PHC subsystem parses the timestamp field of the message to obtain the timestamp t 4,i (k), sent to Linuxptp;

[0075] (3.3) Calculate the link delay d during the kth PTP synchronization between the master and slave i (k);

[0076]

[0077] (3.4) Calculate the time deviation θ of the kth PTP synchronization between the master and slave i (k);

[0078] θ i (k) = t 2,i (k)-t 1,i (k)-d i (k)

[0079] (3.5) Determine each time deviation θ i (k) Are they all less than the synchronization completion time deviation threshold θ sync In this embodiment, θ sync is 20ns; if θ i (k)<θ sync , each slave sends a synchronization completion message to the PC host through the network, enabling each slave to start synchronous sampling, and at the same time adopts a three-level synchronization mechanism to achieve high-precision time and frequency synchronization between each slave and the host; otherwise, only a three-level synchronization mechanism is used to achieve high-precision time and frequency synchronization between each slave and the host;

[0080] Below we describe the three-level synchronization mechanism in detail. Figure 4 As shown, the details are as follows:

[0081] (3.5.1), master-slave first-level synchronization;

[0082] Record the initial time deviation θ obtained by the kernel hardware driver when each slave establishes the first PTP synchronization with the host i (1), converted to binary time adjustment value η t,i , sent to the PTP hardware clock system through the AXI_GP interface; the RTC module of the PTP hardware clock system adjusts the time value η t,i Direct compensation completes a level of synchronization in generating timestamps;

[0083] In this embodiment, the RTC module of the PTP hardware clock system obtains a 32-bit nanosecond time adjustment value and adds it to the nanosecond register to complete nanosecond compensation, and adds a 48-bit second time adjustment value to the second register to complete second compensation, thereby eliminating the initial time deviation of the master and slave machines, reducing the time deviation to the millisecond level, and completing the first-level synchronization.

[0084] (3.5.2) When the master and slave machines synchronize with each other for the kth time, k ≥ 2, and the time deviations θ are determined. i (k) Is it greater than the time deviation threshold θ? th In this embodiment, θ is set th is 100ns; if θ i (k)>θ th , then proceed to step (3.5.3) to start the master-slave secondary synchronization; otherwise, proceed to step (3.5.4) to start the master-slave tertiary synchronization;

[0085] (3.5.3), master-slave two-level synchronization;

[0086] Each slave uses the PI controller of the clock servo system according to the time deviation θ i (k) Calculate the adjustment value η i (k);

[0087]

[0088] Among them, K P and K I are the proportional parameter and integral parameter of the PI controller, where the proportional parameter is 0.7 and the integral parameter is set to 0.3; η 0,i To adjust the initial value and satisfy:

[0089]

[0090] Among them, θ i (2) t 2,i (2) The time deviation and timestamp information of the second PTP synchronization of the master and slave machines respectively;

[0091] Calculate the time base value η generated by the PTP hardware clock timestamp when the master and slave machines synchronize for the kth time p,i (k)

[0092]

[0093] Among them, T base is the period of the host hardware clock;

[0094] Finally, the time base value η is transferred to p,i(k) is sent to the PTP hardware clock system, and the RTC module of the PTP hardware clock system is based on the time base value η p,i (k) Accumulating timestamps to correct the generated timestamps and complete secondary synchronization;

[0095] In this embodiment, the hardware clock source is the 125MHz clock of the RGMII interface, and its time base value is 8ns, so the time base value has a total width of 40 bits, including a 32-bit sub-nanosecond time base and an 8-bit nanosecond time base. By correcting the time base generated by the timestamp, the influence of the master-slave clock source frequency deviation on the time synchronization deviation is eliminated, and the master-slave time synchronization deviation is reduced to hundreds of nanoseconds, completing the secondary synchronization.

[0096] (3.5.4), master-slave three-level synchronization;

[0097] The kernel hardware driver of each slave machine sets the time base value η p,i (k) is fixed to T base ,Right now:

[0098] η p,i (k) = T base

[0099] Then calculate the hardware clock frequency adjustment value η of each slave f,i (k);

[0100]

[0101] The time base value η is set through the AXI_GP interface p,i (k) and frequency adjustment value η f,i (k) is sent to the PTP hardware clock system, and the RTC module of the PTP hardware clock system is based on the new time base value η p,i (k) accumulates and generates a timestamp; and the frequency synchronization module adjusts the frequency value η f,i (k) Convert to the frequency control word of DAC, control DAC to generate corresponding control voltage, voltage-control slave hardware clock source VCXO crystal oscillator, correct slave hardware clock frequency, and complete three-level synchronization;

[0102] In this embodiment, the RTC module of the PTP hardware clock system generates a timestamp based on the 8ns time base value during the three-level synchronization. The frequency synchronization module of the PTP hardware clock system obtains the frequency adjustment value η f,i (k), frequency adjustment value η f,i (k) is the frequency deviation of the slave relative to the master, in ppb. In the embodiment, a 25MHz voltage-controlled crystal oscillator with an absolute pull range of ±50ppm and a control voltage of 0-3.3V is selected as the clock source, and a 16-bit DAC is selected to generate the voltage-controlled voltage. It can be calculated that the frequency resolution of the voltage-controlled VCXO is 1.5ppb, which is consistent with the frequency adjustment value ηf,i (k) with a 1ppb resolution, such as:

[0103]

[0104] The frequency synchronization module adjusts the value η according to the frequency f,i (k) Calculate the frequency control word code and send it to DAC to make the DAC output voltage V co Corresponding VCXO frequency correction value f fix , correct the VCXO output clock frequency, synchronize the slave clock with the master clock frequency, and complete the three-level synchronization. In the embodiment, the VCXO pulling range ±50ppm corresponds to the 0-3.3V control voltage, and also corresponds to the 16-bit bit width of the DAC, so the frequency control word code is calculated as:

[0105]

[0106] V co =1.65+3.3×10 -5 ×f fix

[0107] f fix =-η f,i (k)

[0108] code=2 15 -η f,i (k)×2 16 ×10 -5

[0109] Therefore, the frequency control word code is used to control the DAC to generate the corresponding control voltage, which controls the slave hardware clock source VCXO crystal oscillator, corrects the slave hardware clock frequency, and completes the three-level synchronization.

[0110] In addition, in this embodiment, the process of synchronous sampling of the slave is analyzed, specifically:

[0111] 1) Synchronous reset of each slave;

[0112] When the PC host receives the synchronization completion message of all distributed data acquisition systems, it sends the ADC reset program control command to each distributed data acquisition system. After each distributed data acquisition system receives the ADC reset command, the sampling synchronization module of the PTP hardware clock system uses the rising edge of the next 1PPS synchronization signal as the trigger signal, and pulls down the ADC reset pin at the same time to complete the ADC reset, so that multiple distributed data acquisition devices can start data sampling synchronously.

[0113] 2) Clock phase-locked frequency division generates ADC sampling clock;

[0114] The sampling synchronization module in the PTP hardware clock system starts with the rising edge of the 1PPS synchronization signal, triggers and counts at the rising edge of the hardware clock, compares the count value and the frequency division ratio to output an ADC sampling clock of a specific frequency, and synchronizes the ADC sampling clock phase and frequency of each slave;

[0115] In this embodiment, each slave is based on a synchronized 125MHz hardware clock, and a clock phase-locked frequency division technology is designed to generate a phase-synchronized ADC sampling clock; the ADC sampling clock has a clock edge with the same phase, and the ADC sampling clock phase deviation between each slave is affected by the rising edge phase error of the 1PPS synchronization signal and the 125MHz hardware clock phase. In the embodiment, the time synchronization deviation of each slave is within ±20ns, and the 125MHz hardware clock period is 8ns. Therefore, the clock phase-locked frequency division technology can lock the ADC sampling clock phase deviation between each slave within the range of [-28ns, 28ns], and complete the sampling synchronization of each slave.

[0116] 3) Timestamp the sampled data points;

[0117] The sampling synchronization module of the PTP hardware clock system latches the hardware timestamp of the received ADC sampling data point, and stores the timestamp and the sampling data point together, so that the data sampled by each slave at the same time has the same timestamp information, thereby completing the alignment and synchronization of the sampling data points of each slave.

[0118] The sampling synchronization module of the PTP hardware clock system implements time stamping of the sampling data points. In the embodiment, the sampling synchronization module receives the sampling data of the ADC through the SPI serial bus, takes the rising edge of the DRDY data valid signal as the trigger, latches the hardware timestamp at this time, and uses it as the timestamp of this sampling data point. Each sampling data point has corresponding timestamp information, and each distributed data acquisition system synchronizes the sampling points by comparing the same or close timestamp information, thereby realizing the synchronization of the sampling points of each distributed data acquisition system.

[0119] (3.6) Let k = k + 1, and return to step (3.2) after the next synchronization cycle arrives to continue the next round of PTP synchronization.

[0120] Although the above describes the illustrative specific embodiments of the present invention to facilitate those skilled in the art to understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations using the concept of the present invention are protected.

Claims

1. A PTP time-frequency synchronization method for distributed data synchronization acquisition, characterized in that: The following steps are involved: (1) Build the PTP synchronization architecture of the distributed data acquisition system; Select a switch that supports PTP hardware synchronization as the host of PTP synchronization, and the distributed data acquisition system as the slave of PTP synchronization, and directly connect the slave to the switch host through a network cable; (2) Generation of hardware clock and hardware timestamp; Set each slave to use a voltage-controlled crystal oscillator (VCXO) as the hardware clock source; Set the initial timestamp value of each slave. The real-time clock module RTC in the slave PTP hardware clock system takes the initial timestamp value as the starting point and generates the PTP hardware timestamp T of each slave based on the hardware clock cumulative time base value. i , where i represents the slave number; (3) The master and slave machines perform periodic PTP synchronization; (3.1) Set the cycle number k and initialize k = 1; (3.2) Each slave establishes a PTP protocol stack to implement PTP synchronization message exchange based on the PTP hardware timestamp T i Get the timestamp information t of the kth PTP synchronization 1,i (k)-t 4,i (k); (3.3) Calculate the link delay d during the kth PTP synchronization between the master and slave i (k); (3.4) Calculate the time deviation θ of the kth PTP synchronization between the master and slave i (k); θ i (k)=t 2,i (k)-t 1,i (k)-d i (k) (3.5) Determine each time deviation θ i (k) Are they all less than the synchronization completion time deviation threshold θ sync , if θ i (k)<θ sync , each slave sends a synchronization completion message to the PC host through the network, enabling each slave to start synchronous sampling, and at the same time adopts a three-level synchronization mechanism to achieve high-precision time and frequency synchronization between each slave and the host; otherwise, only a three-level synchronization mechanism is used to achieve high-precision time and frequency synchronization between each slave and the host; (3.6) After the next synchronization cycle arrives, return to step (3.2) and continue with the next round of PTP synchronization.

2. A PTP time-frequency synchronization method for distributed data synchronous acquisition according to claim 1, characterized in that: The timestamp information t of the kth PTP synchronization 1,i (k)-t 4,i The method for obtaining (k) is: (2.1) When each slave system is initialized, the PTP protocol stack configures the PHC subsystem, enables the hardware timestamp function and selects the network data packets that need to be stamped, enabling the kernel to obtain timestamps when receiving and sending data packets; (2.2) The host periodically sends a Sync message to the slave based on the PTP protocol to start the PTP synchronization process; (2.3) The TSU module of the PTP hardware clock system of each slave machine timestamps the arrival of the Sync message t 2,i (k), and then the timestamp t 2,i (k) sent to Linuxptp; (2.4) The host continues to send Follow_up messages, carrying the timestamp t of the time when the Sync message was sent. 1,i (k); (2.5) Each slave receives the Follow_up message, and the PHC subsystem parses the timestamp field of the message to obtain the timestamp t 1,i (k), sent to Linuxptp; (2.6) The Linuxptp control of each slave sends a Delay_req message and timestamps the time when the Delay_req message is sent in the TSU module of the PTP hardware clock system. 3,i (k), and then the timestamp t 3,i (k) sent to Linuxptp; (2.7) The host timestamps the time when it receives the Delay_req message from each slave. 4,i (k), carried in the Delay_Resp message and sent to each slave. (2.8) Each slave receives the Delay_Resp message, and the PHC subsystem parses the timestamp field of the message to obtain the timestamp t 4,i (k), sent to Linuxptp.

3. A PTP time-frequency synchronization method for distributed data synchronous acquisition according to claim 1, characterized in that: The method of using the three-level synchronization mechanism in step (3.5) to achieve high-precision time and frequency synchronization between each slave and the master is: (3.1) Master-slave first-level synchronization; Record the initial time deviation θ obtained by the kernel hardware driver when each slave establishes the first PTP synchronization with the host i (1), converted to binary time adjustment value η t,i , sent to the PTP hardware clock system through the AXI_GP interface; The RTC module of the PTP hardware clock system adjusts the time by the value η t,i Direct compensation completes a level of synchronization in generating timestamps; (3.2) When the master and slave machines synchronize for the kth time with PTP, k ≥ 2, the time deviations θ are determined. i (k) Is it greater than the time deviation threshold θ? th , if θ i (k)>θ th , then go to step (3.3) to start the master-slave secondary synchronization; otherwise, go to step (3.4) to start the master-slave tertiary synchronization; (3.3), master-slave two-level synchronization; Each slave uses the PI controller of the clock servo system according to the time deviation θ i (k) Calculate the adjustment value η i (k); Among them, K P and K I are the proportional and integral parameters of the PI controller, η 0,i To adjust the initial value and satisfy: Among them, θ i (2) t 2,i (2) The time deviation and timestamp information of the second PTP synchronization of the master and slave machines respectively; Calculate the time base value η generated by the PTP hardware clock timestamp when the master and slave machines synchronize for the kth time p,i (k) Among them, T base is the period of the host hardware clock; Finally, the time base value η is transferred to p,i (k) is sent to the PTP hardware clock system, and the RTC module of the PTP hardware clock system is based on the time base value η p,i (k) Accumulate timestamps to correct the generated timestamps and complete secondary synchronization. (3.4), master-slave three-level synchronization; The kernel hardware driver of each slave machine sets the time base value η p,i (k) is fixed to T base ,Right now: or p,i (k)=T base Then calculate the hardware clock frequency adjustment value η of each slave f,i (k); The time base value η is set via the AXI_GP interface p,i (k) and frequency adjustment value η f,i (k) is sent to the PTP hardware clock system, and the RTC module of the PTP hardware clock system is based on the new time base value η p,i (k) accumulates and generates a timestamp; and the frequency synchronization module adjusts the frequency value η f,i (k) is converted into the frequency control word of DAC, controls DAC to generate corresponding control voltage, controls the slave hardware clock source VCXO crystal oscillator, corrects the slave hardware clock frequency, and completes three-level synchronization.

4. A PTP time-frequency synchronization method for distributed data synchronous acquisition according to claim 1, characterized in that: The process of synchronous sampling of each slave is as follows: (4.1) Synchronous reset of each slave; The sampling synchronization module of the PTP hardware clock system uses the rising edge of the 1PPS synchronization signal as a trigger signal to synchronously reset the ADC of each slave, so that each ADC starts data sampling synchronously; (4.2) Clock phase-locked frequency division generates ADC sampling clock; The sampling synchronization module in the PTP hardware clock system starts with the rising edge of the 1PPS synchronization signal, triggers and counts at the rising edge of the hardware clock, compares the count value and the frequency division ratio to output an ADC sampling clock of a specific frequency, and synchronizes the ADC sampling clock phase and frequency of each slave; (4.3), time stamp the sampled data points; The sampling synchronization module of the PTP hardware clock system latches the hardware timestamp of the received ADC sampling data point, and stores the timestamp and the sampling data point together, so that the data sampled by each slave at the same time has the same timestamp information, thereby completing the alignment and synchronization of the sampling data points of each slave.

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