PTP synchronization method for distributed data acquisition system

Abstract

The invention discloses a PTP (Precision Time Protocol) synchronization method for a distributed data acquisition system, which comprises the following steps of: firstly building a PTP synchronization architecture of the distributed data acquisition system, then generating a hardware timestamp of each slave, and finally, synchronizing the hardware timestamp of each slave on the basis of the PTP synchronization architecture of the distributed data acquisition system. And nanosecond-level high-precision PTP time synchronization of distributed data acquisition is realized by adopting a master-slave machine periodic PTP synchronization mechanism.

Description

Technical Field

[0001] The present invention belongs to the technical field of clock synchronization of data acquisition systems, and more specifically, relates to a PTP synchronization method for distributed data acquisition systems. Background Art

[0002] In a distributed data acquisition system, distributed data acquisition devices are required to collect multiple related signals for joint data processing and analysis. This requires time synchronization between distributed acquisition devices to give the collected data time information so that the collected data can be synchronized point to point. At the same time, with the rapid development of science and technology, the performance of data acquisition systems is getting higher and higher, which puts forward higher requirements on the time synchronization accuracy of distributed data acquisition.

[0003] Precision Time Protocol (PTP) is a high-precision network time synchronization protocol based on Ethernet. This protocol has the characteristics of low cost, high synchronization accuracy and low resource consumption, and has been widely studied and applied in the field of distributed data acquisition. The PTP protocol records timestamps and exchanges message data through the master-slave link. The slave node calculates the master-slave link delay and the master-slave node time deviation based on the four timestamps t1, t2, t3, and t4 received and sent.

[0004] The PTP synchronization accuracy is mainly affected by four aspects. The first aspect is the clock source deviation of the master and slave. The master and slave devices often use crystal oscillators to provide clock signals for the system, and temperature drift and aging cause the crystal oscillator to produce clock frequency deviation, which makes the master and slave clocks asynchronous, and introduces microsecond-level time synchronization errors in PTP synchronization. The second aspect is the time stamping position. Timestamping can currently be performed at the physical layer, data link layer, and application layer. At present, the mainstream PTP timing devices are all based on the Linux system, and the Linux system is a non-real-time operating system with an interrupt response time of more than microseconds. Timestamping at the application layer will introduce time synchronization errors of more than microseconds. The data link layer and the physical layer are both implemented by hardware, and the delay error can reach the nanosecond level, but the physical layer timestamping requires a PHY chip that supports PTP, which makes the cost higher. The third aspect is the impact of link asymmetry. The PTP protocol defaults to symmetric master and slave links, but due to the transmission delay of the wired network and the processing and queuing delay of the network nodes between the master and slave, the total slave link is often asymmetric and will introduce microsecond-level time synchronization errors. Fourthly, nanosecond-level precision of PTP synchronization is also affected by the frequency of the timestamp generation clock. The clock frequency will directly determine the resolution of the timestamp, thereby introducing a nanosecond error of ±1 clock cycle. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a PTP synchronization method for a distributed data acquisition system to achieve nanosecond-level high-precision PTP time synchronization for distributed data acquisition.

[0006] To achieve the above-mentioned object of the invention, the present invention provides a PTP synchronization method for a distributed data acquisition system, characterized in that it comprises the following steps:

[0007] (1) Build a PTP synchronization architecture for distributed data acquisition systems;

[0008] Select a switch that supports PTP hardware synchronization as the host of PTP synchronization, and the distributed data acquisition system as the slave of PTP hardware synchronization, and directly connect the switch of the host through a network cable;

[0009] (2) Generate slave hardware timestamp;

[0010] Set the initial timestamp value of each slave. The real-time clock module RTC in the slave PTP hardware clock system takes the initial timestamp value as the starting point and generates the PTP hardware timestamp T of each slave based on the hardware clock cumulative time base value. i , where i represents the slave number;

[0011] (3) The master and slave machines perform periodic PTP synchronization;

[0012] (3.1) Set the cycle number k and initialize k = 1;

[0013] (3.2) Rough time synchronization of the master and slave machines during the first PTP synchronization;

[0014] (3.2.1) Let k = 1, each slave establishes a PTP protocol stack to implement PTP synchronization message exchange, and based on the PTP hardware timestamp T i Get the timestamp information t of the kth PTP synchronization 1,i (k)-t 4,i (k);

[0015] (3.2.2) Calculate the link delay d during the kth PTP synchronization between the master and slave i (k);

[0016]

[0017] Then delay the link by d i (k) After sliding median filtering, the filtered link delay is obtained

[0018] (3.2.3) Calculate the time deviation θ of the kth PTP synchronization between the master and slave i (k);

[0019]

[0020] Then the time deviation θ i (k) Establish an AR model and filter it using the SFTRLS algorithm to obtain the filtered time deviation

[0021] (3.2.4) The time deviation between the master and slave during the first PTP synchronization is θ i (1); Set θ i (1) Convert the time adjustment value η to binary i (1), and then use the AXI_GP interface to i (1) Sent to the PTP hardware clock system, the RTC module of the PTP hardware clock system adjusts the time value η i (1) Directly compensate in the generated timestamp to complete the rough synchronization of the first PTP synchronization between the master and slave machines;

[0022] (3.3) Time synchronization of the master and slave machines during the kth PTP synchronization;

[0023] (3.3.1), let k = k + 1, and calculate the timestamp information t of the kth PTP synchronization between the master and slave according to steps (3.2.1) to (3.2.3) 1,i (k)-t 4,i (k), link delay and time deviation

[0024] (3.3.2) The time deviation The adjustment value η is obtained by the PI controller i (k);

[0025]

[0026] Among them, K P and K I are the proportional and integral parameters of the PI controller, η 0,i To adjust the initial value and satisfy:

[0027]

[0028] Among them, θ i (2) t 2,i (2) The time deviation and timestamp information of the second PTP synchronization of the master and slave machines respectively;

[0029] (3.3.3) Calculate the time base value η generated by the PTP hardware clock timestamp when the master and slave machines synchronize for the kth time p,i(k)

[0030]

[0031] Among them, T base is the period of the host hardware clock;

[0032] (3.3.4) Through the AXI_GP interface, the time base value η p,i (k) is sent to the PTP hardware clock system, and the RTC module of the PTP hardware clock system is based on the time base value η p,i (k) accumulating timestamps to correct the generated timestamps;

[0033] (3.4) When the next synchronization cycle arrives, return to step (3.3) and continue with the next round of time fine synchronization.

[0034] The object of the invention of the present invention is achieved in this way:

[0035] The present invention discloses a PTP synchronization method for a distributed data acquisition system. The method first builds a PTP synchronization architecture of the distributed data acquisition system, then generates a hardware timestamp of each slave machine, and finally based on the PTP synchronization architecture of the distributed data acquisition system, adopts a master-slave periodic PTP synchronization mechanism to realize nanosecond-level high-precision PTP time synchronization of distributed data acquisition.

[0036] At the same time, the PTP synchronization method for a distributed data acquisition system of the present invention also has the following beneficial effects:

[0037] (1) Adopt the PTP hardware synchronization solution and design the timestamp at the MII interface. Compared with PTP software synchronization, timestamp at the application layer reduces the timestamp error from microseconds to nanoseconds, greatly improving the synchronization accuracy. Compared with PTP hardware synchronization, timestamp at the PHY layer, timestamp at the MII interface does not require a PHY chip that supports PTP hardware synchronization, reducing hardware costs while maintaining the same nanosecond error level.

[0038] (2) Use the sliding median filter algorithm to filter the delay of the master-slave link of PTP synchronization, establish an AR model for the master-slave time deviation and use the SFTRLS algorithm to filter it, eliminate the microsecond synchronization error introduced by the asymmetry of the master-slave link, and optimize the PTP synchronization accuracy from microseconds to nanoseconds.

[0039] (3) A two-level synchronization mechanism combining coarse time synchronization and fine time synchronization is adopted for the slave clock servo control. Coarse time synchronization directly compensates the master-slave error to the millisecond level, greatly reducing the time it takes for the master and slave to complete synchronization. Fine time synchronization is combined with a PI controller to correct the slave timestamp to generate a time base, eliminating the influence of the master-slave clock source frequency deviation, and quickly achieving nanosecond time synchronization of the master and slave.

[0040] (4) Use clock double-edge sampling technology to achieve hardware timestamping and high-precision 1PPS synchronization signal generation. Compared with the commonly used clock single-delay sampling, the timestamping error and the edge error of the 1PPS synchronization signal are reduced by half, and the master-slave synchronization accuracy is optimized by two times based on nanosecond synchronization accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a schematic diagram of a PTP synchronization method for a distributed data acquisition system of the present invention;

[0042] Figure 2 This is a schematic diagram of the RTC module generating timestamps;

[0043] Figure 3 It is the timing diagram of 1PPS generated by clock double edge sampling technology;

[0044] Figure 4 This is the PTP synchronization clock acquisition flow chart;

[0045] Figure 5 It is the block diagram of SFTRLS algorithm; DETAILED DESCRIPTION

[0046] The specific implementation of the present invention is described below in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0047] Example

[0048] For the convenience of description, the relevant professional terms appearing in the specific implementation methods are first explained:

[0049] PTP (Precision Time Protocol): Precision Time Protocol;

[0050] Linux: an operating system;

[0051] PHY (Physical Layer): physical layer;

[0052] AR (Autoregressive Model): Autoregressive model;

[0053] SFTRLS (Stable Fast Transversal Recursive Least-Squares algorithm): Stable Fast Transversal Recursive Least-Squares algorithm;

[0054] AXI GP (Advanced eXtensible Interface General Purpose): General purpose interface of advanced extensible interface;

[0055] RTC (Real Time Clock): Real-time clock;

[0056] PI (Proportional Integral Controller): Proportional Integral Controller;

[0057] Xilinx ZYNQ: A fully programmable system-on-chip from Xilinx.

[0058] SoC (System on Chip): System on chip;

[0059] MAC (Media Access Control Layer): Media Access Control Layer;

[0060] MII (Media Independent Interface): Media Independent Interface;

[0061] PHC (PTP Hardware Clock): PTP hardware clock;

[0062] Linuxptp - an open source PTP software protocol stack;

[0063] ARM: ARM processor;

[0064] IEEE 1588: Standard for precision clock synchronization protocol for networked measurement and control systems;

[0065] FPGA (Field Programmable Gate Array): Field Programmable Gate Array;

[0066] H3C IE4320: IE4320 switch from H3C.

[0067] 1PPS (One Pulse Per Second): 1 pulse per second;

[0068] TSU (Time Stamp Unit): time stamp unit;

[0069] GMII (Gigabit Media Independent Interface): Gigabit Media Independent Interface;

[0070] Figure 1The present invention is a flow chart of a PTP synchronization method for a distributed data acquisition system.

[0071] In this embodiment, combined with Figure 1 The PTP synchronization principle diagram of the distributed data acquisition system shown in the figure describes in detail a PTP synchronization method for a distributed data acquisition system of the present invention, which specifically includes the following steps:

[0072] (1) Build the PTP synchronization architecture of the distributed data acquisition system;

[0073] Select a switch that supports PTP hardware synchronization as the host of PTP synchronization, and the distributed data acquisition system as the slave of PTP hardware synchronization. Connect the host's switch directly via a network cable to build a PTP synchronization architecture for the distributed data acquisition system.

[0074] In this embodiment, the distributed data acquisition system uses Xilinx's ZYNQ as the main control SOC. According to the background technology, considering the synchronization error introduced by the timestamp position, a PTP hardware synchronization solution is adopted for timestamping at the MII interface of the MAC layer. The optimization of PTP synchronization includes the PTP protocol stack, the clock servo system and the PTP hardware clock system.

[0075] Among them, the PTP protocol stack consists of the PTP software protocol stack, the kernel PTP hardware clock subsystem PHC and the kernel hardware driver. The PTP software protocol stack is implemented by the Linuxptp program, running in the Linux user space built on the FMQL ARM side, to implement the exchange process of PTP synchronization messages. The PTP hardware clock subsystem PHC in the Linux kernel collaborates with the hardware clock that complies with the IEEE 1588 standard to capture the timestamps of PTP synchronization messages sent and received by the network, and provides an application programming interface for the Linux user space, allowing them to read and write the value of the hardware clock, as well as adjust the clock frequency. The kernel hardware driver implements the communication process between the ARM side and the FPGA side.

[0076] The clock servo system obtains the t1-t4 timestamp from the PTP protocol stack, calculates the master-slave time deviation and link delay, and designs PI control and time synchronization algorithms to achieve master-slave time synchronization. The clock servo system is implemented in the Linux system and kernel on the ARM side.

[0077] The PTP hardware clock receives the time adjustment value and time base value of the clock servo system, and implements the time synchronization between the slave PTP hardware clock and the master in the FPGA. The PTP hardware clock consists of a real-time clock RTC and a timestamp unit TSU.

[0078] In this embodiment, H3C IE4320 switch is used as the PTP synchronization host, which supports PTP hardware synchronization; two distributed data acquisition boards are used as PTP synchronization slaves and are connected to the switch respectively.

[0079] (2) Slave hardware timestamp generation;

[0080] Set the initial timestamp value of each slave. The real-time clock module RTC in the slave PTP hardware clock system takes the initial timestamp value as the starting point and generates the PTP hardware timestamp T of each slave based on the hardware clock cumulative time base value. i , where i represents the slave number;

[0081] In this embodiment, the RTC module of the PTP hardware clock realizes the generation of hardware timestamp. The RTC module is implemented on the FPGA side. Based on the accumulator principle, the timestamp is directly compensated according to the time adjustment value, and the time base value is accumulated under the hardware clock to generate a synchronized timestamp. In the embodiment, the hardware clock uses the 125MHz clock from the Gigabit Ethernet communication of the PHY chip, and the corresponding default time base value is the clock period of 8ns. Figure 2 As shown in the actual operation of FPGA, a 48-bit second register is designed to store the timestamp second information, and a 32-bit nanosecond register is designed to store the maximum 10 9 The timestamp nanosecond information of the value. The adjustment value can be calculated with a resolution of 1 equal to 8×10 of the time base value. -9 Nanoseconds, so a 32-bit sub-nanosecond clock register is designed to save the sub-nanosecond information of the timestamp. When running PTP synchronization, the time adjustment value and time base value in the timestamp generation are sent by the clock servo system through the AXI_GP interface. When the system is powered on, the RTC module receives the system time and 8ns standard time base from the ARM side, and uses this as the starting point to accumulate timestamps. When the master and slave machines are synchronized for the first time, the RTC module receives the time deviation value of the master and slave machines and adds it directly to the timestamp to achieve coarse time synchronization that eliminates the initial time deviation of the master and slave machines. In subsequent synchronizations, the RTC module accumulates timestamps based on the updated time base value.

[0082] The RTC module generates a high-precision 1PPS synchronization signal based on the clock double-edge sampling technology. Figure 3As shown. The 1PPS signal is generated using the timestamp's second carry, but the timestamp's second carry is locked to the rising edge of the hardware clock and cannot be generated exactly when the timestamp is full of 1s, resulting in an 8ns error. When the timestamp's nanosecond register is about to carry, the 1PPS_PRE signal is generated based on the rising edge of the clock. It can be seen that when the nanosecond value with more second carry is in the range of 6-8ns, the actual second carry moment is closest to the rising edge of 1PPS_PRE, and the rising edge of 1PPS_PRE is selected to output to 1PPS. When the timestamp's nanosecond register carries, the 1PPS_NEG signal is generated based on the falling edge of the clock. It can be seen that when the nanosecond value with more second carry is in the range of 2-6ns, the actual second carry moment is closest to the rising edge of 1PPS_NEG, and the rising edge of 1PPS_NEG is selected to output to 1PPS. When the nanosecond register of the timestamp carries, the 1PPS_POS signal is generated based on the rising edge of the clock. It can be seen that when the nanosecond value of the second carry is in the range of 0-2ns, the actual second carry moment is closest to the rising edge of 1PPS_POS, and the rising edge of 1PPS_POS is selected to output to 1PPS. Finally, the 8ns time synchronization error of the 1PPS signal can be reduced to within ±2ns, greatly improving the 1PPS synchronization accuracy between distributed data acquisition boards.

[0083] (3) The master and slave machines perform periodic PTP synchronization;

[0084] (3.1) Set the cycle number k and initialize k = 1;

[0085] (3.2) Rough time synchronization of the master and slave machines during the first PTP synchronization;

[0086] (3.2.1) Each slave establishes a PTP protocol stack to implement PTP synchronization message exchange and based on the PTP hardware timestamp T i Get the timestamp information t of the kth PTP synchronization 1,i (k)-t 4,i (k);

[0087] (3.2.1.1) When each slave system is initialized, the PTP protocol stack configures the PHC subsystem, enables the hardware timestamp function and selects the network data packets that need to be stamped, and enables the kernel to obtain timestamps when receiving and sending data packets;

[0088] (3.2.1.2) Based on the PTP protocol, the host periodically sends a Sync message to the slave to start the PTP synchronization process;

[0089] (3.2.1.3) The TSU module of the PTP hardware clock system of each slave sets the timestamp of the arrival of the Sync message t 2,i(k) Then TSU parses the Sync message, obtains the message type byte of the frame header to identify the Sync message, detects the rising edge of the GMII interface data valid signal, and latches the PTP hardware timestamp T at this moment based on the clock double edge sampling technology. i t 2,i (k), and timestamp t 2,i (k) Saved in the ARM memory through the AXI GP interface. The kernel hardware driver reads the timestamp t through memory mapping technology 2,i (k), sent to Linuxptp.

[0090] In this embodiment, the TSU module of the slave PTP hardware clock implements the timestamp t2 of receiving the Sync message and the timestamp t3 of sending the Delay_req message in the above process, and timestamps t2 and t3 to the PTP protocol stack. The MAC layer on the ARM side sends and receives network data packets in the form of RGMII interface, and converts RGMII into GMII form for processing in FPGA. When transmitting network data packets, the TX_EN and RX_DV signals of the GMII interface will be pulled high, and the hardware clock timestamp at this moment can be latched by detecting the rising edge of the signal. Then, it is identified whether the network data packet is a PTP message that needs to be stamped, and the latched timestamp is sent to the PTP protocol stack through the AXI_GP interface.

[0091] The clock dual-edge sampling technology is used to optimize the accuracy of latched timestamps. The TX_EN and RX_DV signals are asynchronous with the hardware clock. Directly latching the timestamp based on the rising edge of the signal will introduce an error of up to 8ns of a hardware clock cycle. With the dual-edge sampling technology, when the rising edge of the TX_EN and RX_DV signals arrives after the rising edge of the hardware clock, the timestamp error at this moment is 0-4ns, and no compensation is required. When the rising edge of the TX_EN and RX_DV signals arrives after the falling edge of the hardware clock, the timestamp error at this moment is 4-8ns, and 4ns needs to be compensated on the timestamp. Therefore, the clock dual-edge sampling technology reduces the timestamp accuracy from 0-8ns to 0-4ns.

[0092] (3.2.1.4) The host continues to send Follow_up messages, carrying the timestamp t of the time when the Sync message was sent. 1,i (k);

[0093] (3.2.1.5) Each slave receives the Follow_up message, and the PHC subsystem parses the timestamp field of the message to obtain the timestamp t 1,i (k), sent to Linuxptp;

[0094] (3.2.1.6) The Linuxptp control of each slave sends a Delay_req message, and timestamps the time when the Delay_req message is sent in the TSU module of the PTP hardware clock system. 3,i (k); TSU parses the message type byte of the network message frame header to identify the Delay_req message, detects the rising edge of the GMII interface data valid signal, and latches the PTP hardware timestamp T at this moment based on the clock double edge sampling technology. i t 3,i (k), and timestamp t 3,i (k) The timestamp is stored in the ARM memory through the AXI GP interface, and the kernel hardware driver reads the timestamp through memory mapping technology. 3,i (k) sent to Linuxptp;

[0095] (3.2.1.7) The master timestamps the time when it receives the Delay_req message from each slave. 4,i (k), carried in the Delay_Resp message and sent to each slave.

[0096] (3.2.1.8), each slave receives the Delay_Resp message, and the PHC subsystem parses the timestamp field of the message to obtain the timestamp t 4,i (k), sent to Linuxptp.

[0097] (3.2.2) Calculate the link delay d during the kth PTP synchronization between the master and slave i (k);

[0098]

[0099] Then delay the link by d i (k) After sliding median filtering, the filtered link delay is obtained

[0100] In this embodiment, the PTP protocol stack obtains the t2 and t3 timestamps of the PTP hardware clock and the t1 and t4 timestamps of the PHC subsystem, and calculates the link delay for the clock servo system, specifically: the sliding window length in the sliding median filter algorithm is set to 10, and an array is created and initialized to save the link delay value. Each time PTP synchronously calculates a new link delay value, the algorithm is started, new elements are added to the array and the oldest elements are deleted, and then the array elements are sorted by size to obtain the two values ​​in the middle of the sort; finally, the average value of these two values ​​is calculated and the filtered link delay value is output to complete the sliding median filter algorithm.

[0101] (3.2.3) Calculate the time deviation θ of the kth PTP synchronization between the master and slave i (k);

[0102]

[0103] Then the time deviation θ i (k) Establish an AR model and filter it using the SFTRLS algorithm to obtain the filtered time deviation

[0104] In this embodiment, the optimal estimation process of the time deviation value based on the AR model and the SFTRLS algorithm is as follows:

[0105] S1. Establish AR model;

[0106] Time deviation estimation based on AR model:

[0107]

[0108] Among them, w(k,N) is the weight vector at the kth synchronization, and θ(k,N) is the input vector at the kth synchronization, that is, the vector composed of sequence time deviations. Their expressions are as follows:

[0109] w(k,N)=[w(0),...,w(N-1)]

[0110] θ(k,N)=[θ(k),...,θ(k-N+1)]

[0111] The estimation process is to linearly weight the N-length time deviation vector, and estimate the optimal time deviation value by adaptively modifying the weight vector through the SFTRLS algorithm.

[0112] S2, SFTRLS algorithm filtering;

[0113] The SFTRLS algorithm is an optimization of the traditional RLS algorithm. Figure 5 As shown in FIG. 1 , it includes four parts: forward prediction filter, backward prediction filter, auxiliary filter and joint estimation filter. The SFTRLS algorithm can be regarded as a stable and fast implementation method of RLS in which these four parallel working filters exchange parameters and interact with each other.

[0114] In this embodiment, the steps of adaptive time deviation estimation based on SFTRLS algorithm are as follows:

[0115] Step 1: Initialize the SFTRLS algorithm and give the initial values ​​of each intermediate variable in the algorithm.

[0116] w f (0,N)=w b (0,N)=w(0,N)=0 N×1

[0117] γ(0,N,3)=1

[0118]

[0119] K1=1.5,K2=2.5,K3=1

[0120] Step 2: Generate the input vector X(k, N+1) of the SFTRLS algorithm according to the time deviation value θ(k);

[0121]

[0122] Step 3: Update the weight coefficient of the filter based on the SFTRLS algorithm. The update process includes forward prediction, backward prediction, auxiliary filter and joint estimation process, and calculate the optimal estimated weight vector w(k,N).

[0123] Step 4: Estimate the optimal value of time deviation using the optimal weight vector according to the established AR model

[0124]

[0125] Thus, the adaptive filtering and optimal estimation process of the time deviation value based on the AR model and the SFTRLS algorithm is completed.

[0126] (3.2.4) The time deviation between the master and slave during the first PTP synchronization is θ i (1); Set θ i (1) Convert the time adjustment value η to binary i (1), and then use the AXI_GP interface to i (1) Sent to the PTP hardware clock system, the RTC module of the PTP hardware clock system adjusts the time value η i (1) Directly compensate in the generated timestamp to complete the rough synchronization of the first PTP synchronization between the master and slave machines;

[0127] (3.3) Time synchronization of the master and slave machines during the kth PTP synchronization;

[0128] (3.3.1), let k = k + 1, and calculate the timestamp information t of the kth PTP synchronization between the master and slave according to steps (3.2.1) to (3.2.3) 1,i (k)-t 4,i (k), link delay and time deviation

[0129] (3.3.2) The time deviation The adjustment value η is obtained by the PI controller i(k);

[0130]

[0131] Among them, K P and K I are the proportional parameter and integral parameter of the PI controller. In this embodiment, the proportional parameter is 0.7 and the integral parameter is set to 0.3; η0, i To adjust the initial value and satisfy:

[0132]

[0133] Among them, θ i (2) t 2,i (2) The time deviation and timestamp information of the second PTP synchronization of the master and slave machines respectively;

[0134] (3.3.3) Calculate the time base value η generated by the PTP hardware clock timestamp when the master and slave machines synchronize for the kth time p,i (k)

[0135]

[0136] Among them, T base is the period of the host hardware clock;

[0137] In this embodiment, the PTP hardware clock uses the 125MHz clock of the Gigabit network, and the corresponding host clock time base value is 8ns, so the time base value generated by the PTP hardware clock timestamp can be used;

[0138] (3.3.4) Through the AXI_GP interface, the time base value η p,i (k) is sent to the PTP hardware clock system, and the RTC module of the PTP hardware clock system is based on the time base value η p,i (k) accumulating timestamps to correct the generated timestamps;

[0139] (3.4) When the next synchronization cycle arrives, return to step (3.3) and continue with the next round of time fine synchronization.

[0140] In this embodiment, the master-slave time synchronization error is tested, and the time synchronization error of the two distributed data acquisition boards is verified by the phase difference of the 1PPS rising edge of the two boards. After testing, the time synchronization error of the PTP synchronization optimization method for distributed data acquisition in this embodiment of the present invention is within ±15ns.

[0141] Although the above describes the illustrative specific embodiments of the present invention to facilitate those skilled in the art to understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations using the concept of the present invention are protected.

Claims

1. A PTP synchronization method for a distributed data acquisition system, characterized in that: The following steps are involved: (1) Build the PTP synchronization architecture of the distributed data acquisition system; Select a switch that supports PTP hardware synchronization as the host of PTP synchronization, and the distributed data acquisition system as the slave of PTP hardware synchronization, and directly connect the switch of the host through a network cable; (2) Generate slave hardware timestamp; Set the initial timestamp value of each slave. The real-time clock module RTC in the slave PTP hardware clock system takes the initial timestamp value as the starting point and generates the PTP hardware timestamp T of each slave based on the hardware clock accumulated time base value. i , where i represents the slave number; (3) The master and slave machines perform periodic PTP synchronization; (3.1) Set the cycle number k and initialize k = 1; (3.2) Rough time synchronization of the master and slave machines during the first PTP synchronization; (3.2.1) Let k = 1, each slave establishes a PTP protocol stack to implement PTP synchronization message exchange, and based on the PTP hardware timestamp T i Get the timestamp information t of the kth PTP synchronization 1,i (k)-t 4,i (k); (3.2.2) Calculate the link delay d during the kth PTP synchronization between the master and slave i (k); Then delay the link by d i (k) After sliding median filtering, the filtered link delay is obtained (3.2.3) Calculate the time deviation θ of the kth PTP synchronization between the master and slave i (k); Then the time deviation θ i (k) Establish an AR model and use the SFTRLS algorithm to filter and obtain the filtered time deviation (3.2.4) The time deviation between the master and slave during the first PTP synchronization is θ i (1); Set θ i (1) Convert the time adjustment value η to binary i (1), and then use the AXI_GP interface to i (1) Sent to the PTP hardware clock system, the RTC module of the PTP hardware clock system adjusts the time value η i (1) Directly compensate in the generated timestamp to complete the rough synchronization of the first PTP synchronization between the master and slave machines; (3.3) Time synchronization of the master and slave machines during the kth PTP synchronization; (3.3.1), let k = k + 1, and calculate the timestamp information t of the kth PTP synchronization between the master and slave according to steps (3.2.1) to (3.2.3) 1,i (k)-t 4,i (k), link delay and time deviation (3.3.2) The time deviation The adjustment value η is obtained by the PI controller i (k); Among them, K P and K I are the proportional and integral parameters of the PI controller, η 0,i To adjust the initial value and satisfy: Among them, θ i (2) t 2,i (2) The time deviation and timestamp information of the second PTP synchronization of the master and slave machines respectively; (3.3.3) Calculate the time base value η generated by the PTP hardware clock timestamp when the master and slave machines synchronize for the kth time p,i (k) Among them, T base is the period of the host hardware clock; (3.3.4) Through the AXI_GP interface, the time base value η p,i (k) is sent to the PTP hardware clock system, and the RTC module of the PTP hardware clock system is based on the time base value η p,i (k) accumulating timestamps to correct the generated timestamps; (3.4) When the next synchronization cycle arrives, return to step (3.3) and continue with the next round of time fine synchronization.

2. A PTP synchronization optimization method for distributed data acquisition according to claim 1, characterized in that: The timestamp information t of the kth PTP synchronization 1,i (k)-t 4,i The method for obtaining (k) is: (2.1) When each slave system is initialized, the PTP protocol stack configures the PHC subsystem, enables the hardware timestamp function and selects the network data packets that need to be stamped, enabling the kernel to obtain timestamps when receiving and sending data packets; (2.2) The host periodically sends a Sync message to the slave based on the PTP protocol to start the PTP synchronization process; (2.3) The TSU module of the PTP hardware clock system of each slave machine timestamps the arrival of the Sync message t 2,i (k), and then the timestamp t 2,i (k) sent to Linuxptp; (2.4) The host continues to send Follow_up messages, carrying the timestamp t of the time when the Sync message was sent. 1,i (k); (2.5) Each slave receives the Follow_up message, and the PHC subsystem parses the timestamp field of the message to obtain the timestamp t 1,i (k), sent to Linuxptp; (2.6) The Linuxptp control of each slave sends a Delay_req message and timestamps the time when the Delay_req message is sent in the TSU module of the PTP hardware clock system. 3,i (k), and then the timestamp t 3,i (k) sent to Linuxptp; (2.7) The host timestamps the time when it receives the Delay_req message from each slave. 4,i (k), carried in the Delay_Resp message and sent to each slave. (2.8) Each slave receives the Delay_Resp message, and the PHC subsystem parses the timestamp field of the message to obtain the timestamp t 4,i (k), sent to Linuxptp.

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