Time synchronization method and system based on Sicker bus and node equipment

Abstract

The invention discloses a time synchronization method and system based on a Sacker bus, and node equipment, which can dynamically select an optimal synchronization master clock, and determine the optimal synchronization master clock in a network automatic reconfiguration process, thereby multiplexing the network reconfiguration process and reducing communication pressure. Besides, by taking the optimal main clock as the center, the outer-layer second node equipment performs clock counting synchronization on the second outer-layer first node equipment through the optimal path port connected with the optimal main clock, so that clock synchronization is performed only between two adjacent nodes, information does not need to be directly sent to the optimal synchronization main clock, and the time delay of the clock synchronization is reduced. The whole network communication bandwidth resource consumption caused by time synchronization is reduced; and thirdly, in the interval period of two times of interactive synchronization, the second node equipment calculates the compensation proportion through the recorded periodic clock number and the clock accumulation deviation, and supplements when one clock deviation is expected to be reached, so that high-precision clock synchronization is realized.

Description

Technical Field

[0001] The present application relates to the field of communications, and in particular to a time synchronization method, system and node device based on a Shaker bus. Background Art

[0002] Accurate time synchronization is a basic requirement for many industrial communication networks. In a system without accurate time synchronization, efficient measurement, control, scheduling and collaborative work cannot be achieved between network nodes.

[0003] At present, in the network topology structure composed of various network node devices in the communication system, if a node device wants to achieve time synchronization, it needs to request data from the node device with a precise clock through other node devices. The data transmitted in this process needs to pass through at least one node device, which results in a longer data transmission process and different path lengths. The accuracy of time synchronization achieved in this way is low. Summary of the invention

[0004] In view of this, the present application provides a time synchronization method, system and node device based on Shaq bus, and its specific scheme is as follows: A time synchronization method based on Shaq bus, applied to a second node device, comprising: At intervals of a first duration, outputting parameter information of the master clock competition vector to other node devices in the network, wherein at intervals of the first duration, the network performs a reconstruction process; Obtain parameter information of a master clock competition vector output by each node device in the network, wherein the parameter information of the master clock competition vector includes at least a clock accuracy level, a clock priority, and an average distance from all node devices to the current node device of the corresponding node device; Determine the sum of the distances between each node device and other node devices based on parameter information of the master clock competition vector of each node device in the network; Determine the node device with the smallest sum of distances to other node devices in the network as the optimal node device having the optimal synchronization master clock, and determine the port in the second node device for obtaining parameter information of the master clock competition vector output by the optimal node device as the clock synchronization port; The second node device and a node device connected to the second node device through the clock synchronization port are clock synchronized to achieve clock synchronization with the optimal node device.

[0005] Further, performing clock synchronization on the second node device and a node device connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device includes: If the second node device is the optimal node device, outputting the clock count to other node devices connected to the second node device through the clock synchronization port at intervals of a second time, so that the other node devices connected to the second node device through the clock synchronization port can adjust the clock count to be synchronized with the clock count of the second node device; When the second node device performs clock synchronization with other connected node devices through the clock synchronization port of the second node device, other node devices in the network perform clock synchronization with node devices connected thereto through the clock synchronization ports of the other node devices.

[0006] Further, performing clock synchronization on the second node device and a node device connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device includes: If the second node device is a non-optimal node device, at every second time interval, based on the clock count of the first node device connected to the clock synchronization port of the second node device, the clock count of the second node device is adjusted so that the adjusted clock count of the second node device is synchronized with the clock count of the first node device.

[0007] Further, adjusting the clock count of the second node device based on the clock count of the first node device connected to the clock synchronization port of the second node device includes: Obtaining, at a second moment, a clock synchronization instruction output by the first node device, wherein the clock synchronization instruction carries a first moment at which the first node device outputs the clock synchronization instruction; outputting feedback information based on the clock synchronization instruction to the first node device at a third moment; Obtaining notification information output by the first node device, the notification information at least including: a fourth time at which the first node device obtains the feedback information; The clock count of the second node device is adjusted to be synchronized with the clock count of the first node device based on the first time, the second time, the third time and the fourth time.

[0008] Further, adjusting the clock count of the second node device to be synchronized with the clock count of the first node device based on the first moment, the second moment, the third moment, and the fourth moment includes: Determine an offset of a clock signal of the second node device relative to a clock count of the first node device based on the first time, the second time, the third time, and the fourth time; The clock count of the second node device is adjusted based on the offset so that the clock count of the second node device is synchronized with the clock count of the first node device.

[0009] Further, adjusting the clock count of the second node device to be synchronized with the clock count of the first node device based on the first moment, the second moment, the third moment, and the fourth moment includes: Based on the first moment, the second moment, the third moment and the fourth moment, the port module of the second node device adjusts the clock count of the second node device to be synchronized with the clock count of the first node device, and the port module of the second node device is different from the kernel of the second node device.

[0010] Furthermore, it also includes: Determine, based on the first moment, the second moment, the third moment, and the fourth moment, the interval time required for the clock count of the second node device and the clock count of the first node device to achieve compensation error; When it is determined that the interval duration is satisfied, the clock count of the second node device is adjusted based on the compensation error, so that the error between the adjusted clock count of the second node device and the clock count of the first node device is reduced.

[0011] Further, the determining, based on the first moment, the second moment, the third moment, and the fourth moment, the interval length required for the second node device to compensate for the error with the first node device includes: Determine a first time difference between first moments when the first node device outputs clock synchronization instructions twice in a row, the first node device outputs the clock synchronization instruction every clock cycle, and the duration of the clock cycle is equal to the first time difference; Determine a second time difference between two consecutive second moments when the second node device obtains the clock synchronization instruction output by the first node device; Determine a percentage of a difference between a clock count of the second node device and a clock count of the first node device based on the first time difference and the second time difference; The number of counts of the counter required to compensate for the cumulative error reaching more than ±1 clock is determined based on the percentage of the difference between the clock count of the second node device and the clock count of the first node device.

[0012] A second node device, comprising: A first port module includes a plurality of first ports, which can be connected to different node devices respectively, and are used to output the parameter information of the master clock competition vector to other node devices in the network through different first ports at each first time interval, wherein the network performs a reconstruction process at each first time interval; obtain the parameter information of the master clock competition vector output by each node device in the network, wherein the parameter information of the master clock competition vector at least includes the clock accuracy level, clock priority and average distance of all node devices to the current node device of the corresponding node device; determine the sum of the distances between each node device and other node devices based on the parameter information of the master clock competition vector of each node device in the network; determine the node device with the smallest sum of distances with other node devices in the network as the optimal node device with the optimal synchronous master clock, and determine the first port in the second node device for obtaining the parameter information of the master clock competition vector output by the optimal node device as the clock synchronization port; perform clock synchronization on the second node device and the node device connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device; The first kernel is used to perform other signal processing operations except the above time synchronization process.

[0013] A time synchronization system based on Shaq bus, comprising: A plurality of node devices, the plurality of node devices at least comprising: a first node device and a second node device; The second node device outputs parameter information of the master clock competition vector to other node devices in the network at intervals of a first time length, wherein the network performs a reconstruction process at intervals of a first time length; obtains parameter information of the master clock competition vector output by each node device in the network, wherein the parameter information of the master clock competition vector includes at least the clock accuracy level of the corresponding node device, the clock priority and the average distance from all node devices to the current node device; determines the sum of the distances between each node device and other node devices based on the parameter information of the master clock competition vector of each node device in the network; determines the node device with the smallest sum of distances with other node devices in the network as the optimal node device with the optimal synchronous master clock, and determines the port in the second node device for obtaining parameter information of the master clock competition vector output by the optimal node device as the clock synchronization port; performs clock synchronization on the second node device and the node device connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device; When the second node device and the node device connected to the second node device through the clock synchronization port perform clock synchronization, other node devices among the multiple node devices perform clock synchronization with the node devices connected thereto through the clock synchronization ports of the other node devices.

[0014] It can be seen from the above technical scheme that the time synchronization method, system and node device based on the Shak bus disclosed in the present application output the parameter information of the master clock competition vector to other node devices in the network at every first time interval, wherein the network performs a reconstruction process at every first time interval; obtains the parameter information of the master clock competition vector output by each node device in the network; determines the optimal node device where the optimal synchronization master clock is located based on the parameter information of the master clock competition vector of each node device in the network, and determines the port in the second node device used to obtain the parameter information of the master clock competition vector output by the optimal node device as the clock synchronization port; performs clock synchronization on the second node device and the node device connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device. In this scheme, the optimal synchronization master clock can be dynamically selected, and the optimal synchronization master clock is determined during the automatic network reconstruction process, which reuses the network reconstruction process and reduces communication pressure. In addition, with the optimal master clock as the center, the outer second node device synchronizes the clock count to the second outer first node device through the optimal path port linked to the optimal master clock, so that the clock synchronization is only performed between two adjacent nodes, and there is no need to send information directly to the optimal synchronization master clock, which reduces the consumption of communication bandwidth resources in the entire network caused by time synchronization. Thirdly, within the interval period of two interactive synchronizations, the second node device calculates the compensation ratio by recording the number of periodic clocks and the cumulative clock deviation, and supplements it when it is expected to reach 1 clock deviation, thereby achieving high-precision clock synchronization. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 A flowchart of a time synchronization method based on the Shaq bus disclosed in an embodiment of the present application; Figure 2 A schematic diagram of a clock synchronization process between a first node device and a second node device disclosed in an embodiment of the present application; Figure 3 A flowchart of another Shaq bus-based time synchronization method disclosed in an embodiment of the present application; Figure 4 A schematic diagram of a network topology structure of a Shaq bus disclosed in an embodiment of the present application; Figure 5 A flowchart of another Shaq bus-based time synchronization method disclosed in an embodiment of the present application; Figure 6 A schematic diagram of data flow when a first node device and a second node device are clock synchronized according to an embodiment of the present application; Figure 7 A flowchart of another Shaq bus-based time synchronization method disclosed in an embodiment of the present application; Figure 8 A schematic diagram of a synchronization process including at least two adjacent clock synchronization cycles disclosed in an embodiment of the present application; Fig. 9 A schematic diagram of the structure of a second node device disclosed in an embodiment of the present application; Fig.10 This is a schematic diagram of the structure of a Shaq bus-based time synchronization system disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0017] The following describes the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. The terms used in the implementation method section of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0018] The embodiments of the present application are described below in conjunction with the accompanying drawings. Those skilled in the art will appreciate that, with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0019] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, which is only to describe the distinction mode adopted by the objects of the same attributes when describing in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0020] The present application discloses a time synchronization method based on Shaq bus, which is applied to the second node device. The flow chart is as follows: Figure 1 As shown, including: Step S11: outputting parameter information of the master clock contention vector to other node devices in the network at intervals of a first duration, wherein the network performs a reconstruction process at intervals of the first duration; Step S12: Obtain parameter information of a master clock contention vector output by each node device in the network, wherein the parameter information of the master clock contention vector at least includes a clock accuracy level, a clock priority, and an average distance from all node devices to the current node device of the corresponding node device; Step S13: determining the sum of the distances between each node device and other node devices based on the parameter information of the master clock competition vector of each node device in the network; Step S14: determine the node device with the smallest sum of distances to other node devices in the network as the optimal node device having the optimal synchronization master clock, and determine the port in the second node device used to obtain parameter information of the master clock competition vector output by the optimal node device as the clock synchronization port; Step S15: Perform clock synchronization on the second node device and the node devices connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device.

[0021] The Shak bus, whose full name is free topology automatic reconstruction network, is a high-speed, strong real-time, self-constructing network field bus. The bus adopts a specially designed network structure to achieve end-to-end high-speed transmission, and supports multi-terminal parallel transmission within the network, thereby improving the total network throughput.

[0022] Time synchronization is the basis for high-precision measurement, control and scheduling in industrial networks. At present, in a network composed of multi-node devices, if a node device wants to achieve time synchronization, it needs to request data from a node device with a precise clock through other node devices. The data transmitted in this process needs to pass through at least one node device, which results in a long data transmission process and large differences in path lengths. The accuracy of time synchronization achieved in this way is low.

[0023] To avoid this problem, this scheme determines the optimal synchronization master clock once every first time interval, so that clock synchronization between two adjacent devices can be performed based on the optimal synchronization master clock. The optimal synchronization master clock is determined during the automatic network reconstruction process, which reuses the network reconstruction process and reduces communication pressure. In addition, based on the progressive method, the adjacent level synchronized clocks are synchronized to achieve clock count synchronization between adjacent node devices, so that clock synchronization is only performed between two adjacent nodes, and there is no need to send information directly to the optimal synchronization master clock, which reduces the consumption of communication bandwidth resources in the entire network caused by time synchronization.

[0024] Specifically, at each first time interval, the network performs a reconstruction process. When the network performs the reconstruction process, the optimal synchronization master clock is re-determined to achieve the purpose of multiplexing the network reconstruction process. At the same time, no communication overhead is increased in this process.

[0025] The network contains multiple nodes, and each node has no priority in status. Whenever the first time interval arrives at the time of network reconstruction, with the help of network reconstruction, each node device sends the parameter information of the master clock competition vector to other node devices in the network, that is, each node device in the network will send the parameter information of the master clock competition vector to other node devices, and at the same time, each node device can also receive the parameter information of the master clock competition vector sent by all other node devices in the network.

[0026] Among them, the parameter information of the master clock competition vector output by each node device may include at least: forced master clock setting, clock priority setting, clock accuracy level, total distance, path information, ID identification, etc., and different priority rankings are given according to the impact of each parameter on the final synchronization effect.

[0027] Each node receives parameter information of the master clock competition vector sent by other node devices in the network. Each node device can determine the optimal node device where the optimal synchronization master clock is located based on the parameter information of the master clock competition vector of other node devices received and the parameter information of the master clock competition vector of the node device itself, that is, each node device can determine the same optimal node device.

[0028] After the optimal node device is determined, each node device can determine a clock synchronization port, which is the port where the node device receives the parameter information of the master clock competition vector output by the optimal node device. Each node device has multiple ports, and different ports can communicate with different node devices. If a node device wants to communicate with the nearest node close to the optimal node device, it can only be achieved through the clock synchronization port.

[0029] After determining the clock synchronization port of each node device, clock synchronization can be performed once every second time period, wherein each clock synchronization is performed between two adjacent node devices, such as: the second node device synchronizes the clock count of the first node device, wherein the clock synchronization port of the second node device is connected to the first node device, and the clock synchronization port of the first node device is connected to other node devices closer to the optimal node device, and finally it can be indirectly connected to the optimal node device through the clock synchronization port, so that the optimal node device can perform clock synchronization with adjacent node devices, and the node devices adjacent to the optimal node device can perform clock synchronization with their own adjacent node devices until the second node device performs clock synchronization with the first node device.

[0030] For example: if the second node device is not the optimal node device, it is necessary to determine the shortest path between the second node device and the optimal node device, such as: the clock synchronization port of the second node device is connected to the first node device, the clock synchronization port of the first node device is connected to the third node device, and the clock synchronization port of the third node device is connected to the optimal node device. Then, the clock count of the optimal node device is the most accurate compared to other node devices. First, the third node device performs clock synchronization with the optimal node device through its own clock synchronization port to make the clock signal of the third node device more accurate; then, the first node device performs clock synchronization with the third node device through its own clock synchronization port, and finally, the second node device performs clock synchronization with the first node device through its own clock synchronization port.

[0031] In addition, if the second node device is the optimal node device, after determining that the second node device is the optimal node device, the node device directly connected to the second node device is synchronized with the second node device, and then time synchronization is performed layer by layer outward, such as: the second node device is the optimal node device, the clock synchronization port of the third node device is directly connected to the second node device, and the clock synchronization port of the fourth node device is directly connected to the third node device, then the third node device first performs clock synchronization with the second node device, and then the fourth node device performs clock synchronization with the third node device, so as to achieve layer-by-layer clock synchronization.

[0032] Specifically, the optimal node device where the optimal synchronous master clock is located is determined based on the parameter information of the master clock competition vector of each node device in the network, including: determining the sum of the distances between each node device and other node devices based on the parameter information of the master clock competition vector of each node device in the network; and determining the node device with the smallest sum of distances with other node devices in the network as the optimal node device with the optimal synchronous master clock.

[0033] Each node device compares the sum of the distances between each node device and other node devices in the network, thereby determining the node device with the shortest distance, and determining the node device as the optimal node device. The clock count of the optimal node device is determined as the optimal synchronous master clock.

[0034] After determining the optimal node device and the clock synchronization port of each node device, the second node device and the node devices adjacent to the second node device through the clock synchronization port are clock synchronized to achieve clock synchronization with the optimal node device.

[0035] If the second node device is the optimal node device, then at every second time interval, the clock count is output to other node devices connected to the second node device through the clock synchronization port, so that other node devices connected to the second node device through the clock synchronization port can adjust the clock count to synchronize with the clock count of the second node device.

[0036] For example, if the first node device is connected to the second node device via a clock synchronization port, the second node device outputs a clock count to the first node device at a second time interval, and the first node device synchronizes the clock count with the second node device based on the clock synchronization signal.

[0037] If the second node device is a non-optimal node device, at every second time interval, based on the clock count of the first node device connected to the clock synchronization port of the second node device, the clock count of the second node device is adjusted so that the adjusted clock count of the second node device is synchronized with the clock count of the first node device.

[0038] If the second node device is a non-optimal node device, the second node device has a clock synchronization port. At this time, the second node device can be directly connected to the optimal node device through the clock synchronization port, and the second node device can directly obtain the clock count output by the optimal node device every second time interval, thereby realizing synchronization of the second node device to the optimal node device; If the second node device is not the optimal node device, and the second node device is not directly connected to the optimal node device, the optimal node device may first send a clock count to the node device directly connected to it. After the node device directly connected to the optimal node device completes clock synchronization with the optimal node device, the node device directly connected to the optimal node device will send a clock count to the node device directly connected to it, so as to achieve layer-by-layer clock synchronization. For example, if the third node device is directly connected to the optimal node device and the second node device is directly connected to the third node device, the optimal node device sends a clock count to the third node device. After the third node device completes clock synchronization with the optimal node device based on the clock count, the third node device may output the clock count externally, such as outputting the clock count to the second node device. Then the second node device may complete clock synchronization based on the clock count output by the third node device.

[0039] It should be noted that, regardless of whether the second node device is the optimal node device, while the second node device is performing clock synchronization with a certain node device, other nodes in the network can also perform clock synchronization with the connected node device through their clock synchronization ports, thereby achieving that each node device in the network can perform clock synchronization with the adjacent node device respectively. Then, in the process of clock synchronization, the clock synchronizations between different node devices do not interfere with each other, and there is no need for a certain node device to perform clock synchronization with the optimal node device when it is not directly connected to the optimal node device, thereby avoiding occupying more bandwidth and causing the problem of increased delay uncertainty.

[0040] Further, based on the clock count of the first node device connected to the clock synchronization port of the second node device, adjusting the clock count of the second node device may be: At the second moment, a clock synchronization instruction output by the first node device is obtained, and the clock synchronization instruction carries the first moment when the first node device outputs the clock synchronization instruction; at the third moment, feedback information based on the clock synchronization instruction is output to the first node device; notification information output by the first node device is obtained, and the notification information at least includes: the fourth moment when the first node device obtains the feedback information; based on the first moment, the second moment, the third moment and the fourth moment, the clock count of the second node device is adjusted to be synchronized with the clock count of the first node device.

[0041] For any node device in the network topology structure, it can be determined as the second node device, and the node device connected to the clock synchronization port of the second node device can be determined as the first node device. In the network topology structure, a device does not always serve as the first node device or the second node device. Whether the device is the first node device or the second node device is related to the accuracy of the current clock count of the node device and the relative position relationship between the node devices. For example, when a device is synchronized in the direction of the optimal master clock, it belongs to the second node device, but when the outer device synchronizes to it, it plays the role of the first device; for example, after a certain optimal synchronization master clock determination process, the relationship between the first node device and the second node device is determined, and when the optimal synchronization master clock is updated, the relationship between the first node device and the second node device may change.

[0042] It can be: performing clock synchronization between adjacent node devices once every second time period. At this time, the first node device can initiate port detection to all valid ports and send instruction pack1 to the node device connected to the port of the first node device; the connected node device returns information pack2 to the first node device. This process enables the first node device to determine whether the port is valid.

[0043] If the clock synchronization port of the second node device is the port connected to the first node device, then the second node device will make a time synchronization request mark in the return information pack2. The first node device completes a port detection when it receives the return information pack2. However, if the time synchronization request mark in the return information pack2 is valid, the first node device will send information pack3 to the second node device. At this time, the clock synchronization instruction required for time synchronization between the second node device and the first node device can reuse instruction pack1, the feedback information can reuse the return information pack2, and the notification information can reuse pack3. The communication overhead is reduced by multiplexing; in addition, since the time synchronization process is only carried out between two adjacent nodes, there is no need to send information directly to the master clock, which greatly reduces the consumption of communication bandwidth resources in the entire network caused by time synchronization.

[0044] When a second node device obtains a clock synchronization instruction output by a first node device adjacent to it, the moment when the second node device obtains the clock synchronization instruction is recorded and determined as the second moment T2; and the first moment T1 is the moment when the first node device outputs the clock synchronization instruction, that is, when the first node device outputs the clock synchronization instruction, it will add the first moment of its output instruction to the clock synchronization instruction, or output the first moment and the clock synchronization instruction to the second node device at the same time. Then the first moment is the moment determined according to the clock count of the first node device when the first node device outputs the clock synchronization instruction, and the second moment is the moment determined according to the clock count of the second node device when the second node device receives the clock synchronization instruction.

[0045] After obtaining the clock synchronization instruction output by the first node device, the second node device will output feedback information based on the clock synchronization instruction to the first node device at the third time T3. The feedback information is only used to send a message to the first node device after determining that synchronization is required based on the clock synchronization instruction, so as to determine when the first node device receives the feedback information. The third time T3 is the time when the second node device outputs the feedback information determined according to the clock count of the second node device.

[0046] The time difference between the third moment T3 and the second moment T2 is used to store the received clock synchronization instruction in the register.

[0047] The first node device receives the feedback information. The first node device itself knows the feedback information received at the fourth moment T4 according to the clock count of the first node device. In order to enable the second node device to also know the moment when the first node device receives the feedback information, it is necessary to send the timestamp information of the fourth moment T4 to the second node device, so that the second node device can clearly know when the first node device received the feedback information. Specifically, the notification information is output at the fifth moment T5 according to the clock count of the first node device, and the notification information at least includes the fourth moment T4. The second node device receives the notification information at the sixth moment T6 according to its own clock count.

[0048] After the above process is completed, the second node device will determine at least 4 moments, namely: the first moment T1, the second moment T2, the third moment T3 and the fourth moment T4, wherein the first moment T1 and the fourth moment T4 are moments determined according to the clock count of the first node device, and the second moment T2 and the third moment T3 are moments determined according to the clock count of the second node device.

[0049] Specifically, Figure 2 As shown, it includes: the clock of the first node device and the clock of the second node device, wherein the clock synchronization instruction is output according to the first time T1 on the clock of the first node device, and the second node device receives the clock synchronization instruction according to the second time T2 on the clock of the second node device. Afterwards, when the clock of the second node device is a third time T3, the second node device outputs feedback information to the first node device, and the first node device obtains the feedback information when the clock of the first node device is a fourth time T4. Afterwards, when the clock of the first node device is a fifth time T5, the first node device sends notification information to the second node device, and the notification information at least includes the fourth time T4. When the clock of the second node device is a sixth time T6, the second node device obtains the notification information.

[0050] When the four moments of the clock counts belonging to different node devices are determined, the clock count of the second node device can be synchronized with the clock count of the first node device, so that the clock count of the second node device can be synchronized with the clock count of the first node device.

[0051] The time synchronization method based on the Shaq bus disclosed in this embodiment outputs parameter information of a master clock competition vector to other node devices in the network at intervals of a first time length, wherein the network performs a reconstruction process at intervals of a first time length; obtains parameter information of a master clock competition vector output by each node device in the network, wherein the parameter information of the master clock competition vector includes at least a clock accuracy level and a clock priority of the corresponding node device; determines the sum of distances between each node device and other node devices based on the parameter information of the master clock competition vector of each node device in the network; determines a node device in the network with the smallest sum of distances with other node devices as the optimal node device having the optimal synchronized master clock, and determines a port in a second node device for obtaining parameter information of a master clock competition vector output by the optimal node device as a clock synchronization port; performs clock synchronization on a second node device and a node device connected to the second node device via the clock synchronization port to achieve clock synchronization with the optimal node device. In this solution, the optimal synchronization master clock is dynamically adjusted, and the optimal synchronization master clock is determined during the automatic network reconstruction process, which reuses the network reconstruction process and reduces communication pressure. In addition, with the optimal master clock as the center, the outer second node device synchronizes the clock count to the second outer first node device through the optimal path port connected to the optimal master clock (the clock on the optimal node device is the optimal master clock), so that clock synchronization is only performed between two adjacent nodes, without the need to send information directly to the optimal synchronization master clock, reducing the consumption of communication bandwidth resources in the entire network caused by time synchronization.

[0052] This embodiment discloses a time synchronization method based on Shaq bus, which is applied to the second node device. The flow chart is as follows: Figure 3 As shown, including: Step S31: determining the optimal node device where the optimal synchronization master clock is located based on the parameter information of the master clock competition vector of each node device in the network, and determining the port in the second node device used to obtain the parameter information of the master clock competition vector output by the optimal node device as the clock synchronization port; Step S32: obtaining a clock synchronization instruction output by the first node device at a second time, where the clock synchronization instruction carries the first time at which the first node device outputs the clock synchronization instruction; Step S33: outputting feedback information based on the clock synchronization instruction to the first node device at a third moment; Step S34: Obtain notification information output by the first node device, where the notification information at least includes: a fourth moment when the first node device obtains feedback information; Step S35: determining an offset of a clock count of the second node device relative to a clock count of the first node device based on the first moment, the second moment, the third moment, and the fourth moment; Step S36: Adjust the clock count of the second node device based on the offset so that the clock signal of the second node device is synchronized with the clock count of the first node device.

[0053] When the second node device determines the first moment and the fourth moment based on the clock count of the first node device, and the second moment and the third moment based on the clock signal of the second node device based on the clock synchronization instruction output by the first node device, the second node device can determine the offset of the clock count of the second node device relative to the clock signal of the first node device based on the above four moments, that is, the deviation between the clock count of the second node device and the clock count of the first node device.

[0054] Specifically, according to Figure 2 The clock synchronization process between the first node device and the second node device shown can obtain: Formula (1) in, is the deviation between the clock count of the first node device and the clock count of the second node device, is the time required for data transmission between the first node device and the second node device. Based on the above formula (1), the deviation between the clock count of the first node device and the clock count of the second node device can be determined as: The deviation between the clock count of the first node and the clock count of the second node is That is, the offset of the clock count of the second node device relative to the clock count of the first node device. By adjusting the offset based on the clock count of the second node device, a clock count synchronized with the clock count of the first node device can be obtained.

[0055] In addition, since the time synchronization method disclosed in this embodiment performs time synchronization on two directly cascaded node devices, if a problem is detected in any node device in the network topology, or dynamic routing reconstruction is performed at the end of a time synchronization cycle, at this time, any routing device and its downstream node device may form a new topology structure, and each topology structure can be independently time synchronized according to the above scheme without affecting each other.

[0056] The time synchronization method based on the Shaq bus disclosed in this embodiment obtains a clock synchronization instruction output by a first node device at a second moment, the clock synchronization instruction carries the first moment when the first node device outputs the clock synchronization instruction, and the first node device is a node device directly connected to the second node device; outputs feedback information based on the clock synchronization instruction to the first node device at a third moment; obtains notification information output by the first node device, and the notification information at least includes: a fourth moment when the first node device obtains the feedback information; determines an offset of a clock count of the second node device relative to a clock count of the first node device based on the first moment, the second moment, the third moment, and the fourth moment; and adjusts the clock count of the second node device based on the offset to synchronize the clock count of the second node device with the clock count of the first node device. In this scheme, a node device whose current clock count accuracy is greater than a preset threshold sends a clock synchronization instruction to a node device directly connected to it, so that a second node device directly connected to it can adjust the clock count based on the clock count of the first node device, thereby realizing synchronization of the clock counts of the second node device and the first node device. In this scheme, a node device whose clock count accuracy is greater than a preset threshold actively requests an adjacent node device to perform time synchronization, thereby ensuring that any node device adjacent to a node device whose clock count accuracy is greater than a preset threshold can complete clock count synchronization, thereby improving synchronization accuracy. At the same time, it avoids the problem of long data transmission process and low clock synchronization accuracy caused by the need to transmit data through several node devices when performing clock count synchronization. The offset between the clock counts of the second node device and the first node device can be determined through the first moment, the second moment, the third moment and the fourth moment, thereby realizing adjustment of the clock count of the second node device, thereby ensuring the accuracy of clock synchronization.

[0057] Furthermore, in the Shaq bus-based time synchronization method disclosed in this embodiment, the first node device may be a node device that does not need clock synchronization, or may be a node device that completes clock synchronization within a time period of a first preset time interval from the first moment.

[0058] Specifically, Figure 4 As shown, it is a schematic diagram of a network topology structure of the Shak bus, which includes: a routing device and a terminal, wherein the routing device includes: a top node device 401 and an intermediate node device 402, and the terminal is represented by 403 in the network topology structure. Figure 4 The network topology structure composed of routing devices and terminals in the network shown has 7 layers in total, wherein the top node device 401 is located at the first layer from top to bottom, and so on, the terminal 403 is located at the seventh layer from top to bottom.

[0059] Among them, SharkNet can form any topology through arbitrary plug-in. Figure 4This is just one of them, and not all network topologies are limited here.

[0060] exist Figure 4 A top-down, periodic, progressive network node time synchronization scheme is provided (in a free topology structure, it is a clock synchronization scheme for progressive network nodes from the inside out with the optimal master clock as the center). In this scheme, only two network node devices directly cascaded up and down are synchronized at a time, and synchronization is performed from the top node to the bottom in each cycle, that is, a clock synchronization instruction is output from the first-layer node device to the second-layer node device to adjust the clock count of the second-layer node device so that it is synchronized with the clock count of the first-layer node device; after the clock synchronization of the second-layer node device is completed, a clock synchronization instruction is output from the second-layer node device to the third-layer node device to adjust the clock count of the third-layer node device so that it is synchronized with the clock count of the second-layer node device; and so on, until the clock count of the terminal on the seventh layer is synchronized with the clock count of the node device on the sixth layer, thus completing the clock synchronization of each node device in the network architecture.

[0061] In the entire network topology, if the clock signal of the top node device is determined to be the most accurate based on the parameter information of the master clock competition vector, then if the first node device is the optimal clock device, that is, the optimal node device, then at this time, the first node device is a node device that does not need to perform clock synchronization. Then, when performing time synchronization in the entire network topology, the first node device first outputs a clock synchronization signal to the second-layer node device directly cascaded with it, so that the second-layer node device can complete clock synchronization. After that, the second-layer node device outputs a clock synchronization signal to the third-layer node device directly cascaded with it, so that the third-layer node device can complete clock synchronization, until all node devices in the network topology complete clock synchronization; If it is determined that the clock count of a certain intermediate node device is the most accurate, then when performing time synchronization, the intermediate node device first outputs a clock synchronization signal to the node device directly cascaded with it, so that the node device directly cascaded with it can complete clock synchronization, and then expands outward to complete clock synchronization, so as to complete clock synchronization for all node devices in the network topology. It should be noted that the behavior of each layer of node devices synchronizing outward is not affected by other node devices, and they are all independently synchronized in their own periodicity and are executed in parallel.

[0062] In addition, the first node device may not be the node device with the most accurate clock count in the entire network topology structure. That is, when the entire network topology structure performs clock synchronization, the node device with the most accurate clock count in the network topology structure is first determined. Then, the node device first outputs a clock synchronization signal to the node device directly cascaded with it. If the node device directly cascaded with it completes clock synchronization, when the clock synchronization signal is output by the node device, the node device is not the node device with the most accurate clock count in the entire network topology structure, but a node device that completes clock synchronization within a time period of a first preset time interval from the first moment, that is, the node device is a node device that has just completed clock synchronization. At this time, it can also output clock synchronization instructions to the node device directly cascaded with it, so as to complete the clock synchronization between each node device in the entire network topology structure. The information used for time synchronization does not need to be transmitted between more devices, which greatly enhances the time synchronization rate and reliability of the network topology structure.

[0063] This embodiment discloses a time synchronization method based on Shaq bus, which is applied to the second node device. The flow chart is as follows: Figure 5 As shown, including: Step S51: determining the optimal node device where the optimal synchronization master clock is located based on the parameter information of the master clock competition vector of each node device in the network, and determining the port in the second node device used for obtaining the parameter information of the master clock competition vector output by the optimal node device as the clock synchronization port; Step S52: obtaining a clock synchronization instruction output by the first node device at a second time, where the clock synchronization instruction carries the first time at which the first node device outputs the clock synchronization instruction; Step S53: outputting feedback information based on the clock synchronization instruction to the first node device at the third moment; Step S54: Obtain notification information output by the first node device, where the notification information at least includes: a fourth moment when the first node device obtains feedback information; Step S55: Based on the first moment, the second moment, the third moment and the fourth moment, the port module of the second node device adjusts the clock count of the second node device to synchronize with the clock count of the first node device, and the port module of the second node device is different from the kernel of the second node device.

[0064] Any node device in the network topology structure involved in the Shaq bus-based time synchronization method disclosed in this embodiment includes a kernel and a port module. The time synchronization method disclosed in this embodiment is applied to the port module in the second node device.

[0065] Specifically, any node device may include: a kernel, a data buffer and a port module, and the port module can be directly connected to other node devices. Among them, the kernel is used to process the data inside the node device, the data buffer is used to cache data, and the port module is used to process the data that needs to be transmitted during time synchronization, so that the data that needs to be transmitted during the time synchronization process is directly output after being processed by the port module without passing through the kernel and occupying the kernel's processing time, thereby increasing the network throughput.

[0066] When the first node device and the second node device perform time synchronization, the schematic diagram is as follows: Figure 6 As shown, it includes: a first node device and a second node device, wherein the second node device includes: a first kernel 61, a first data buffer 62, and a first port module 63, and the first node device includes: a second kernel 64, a second data buffer 65 and a second port module 66.

[0067] The first core is connected to the first data buffer, the first data buffer is connected to the first port module, the second core is connected to the second data buffer, the second data buffer is connected to the second port module, and the first port module is connected to the second port module.

[0068] In the time synchronization process disclosed in this embodiment, it is all executed at the port module of the node device, that is, the information interaction and execution during the time synchronization process are performed between the second port module of the first node device and the first port module of the second node device, and the information interacted during the time synchronization process does not need to be transmitted to the first core and the second core.

[0069] That is, in the second node device, the first port module of the second node device obtains the clock synchronization instruction output by the first node device at the second moment, the first port module outputs feedback information based on the clock synchronization instruction to the first node device at the third moment, and the first port module outputs feedback information to the first node device at the third moment, and the feedback information is also generated by the first port module based on the clock synchronization instruction; the first port module obtains the notification information output by the first node device, and the clock count of the second node device adjusted by the first port module based on the first moment, the second moment, the third moment and the fourth moment is synchronized with the clock count of the first node device.

[0070] Similarly, in the first node device, the second port module of the first node outputs at the first moment a clock synchronization instruction carrying the first moment to the second node device, the second port module obtains feedback information at the fourth moment, and the second port module outputs at least notification information including the fourth moment to the second node device, and the generation of the notification information is also implemented by the second port module.

[0071] During the time synchronization process, whether it is the interaction of information or the generation of instructions or information, it is all implemented in the port module and has nothing to do with the kernel of the node device. The data does not enter the kernel of the node device, which can improve the efficiency of time synchronization. In addition, at the port layer, that is, the physical layer, the timestamp is returned to the port layer of the node device with which it is time synchronized, which can improve the accuracy of time synchronization.

[0072] The time synchronization method based on the Shaq bus disclosed in this embodiment obtains a clock synchronization instruction output by the first node device at a second moment, the clock synchronization instruction carries the first moment when the first node device outputs the clock synchronization instruction, and the first node device is a node device directly connected to the second node device; outputs feedback information based on the clock synchronization instruction to the first node device at a third moment; obtains notification information output by the first node device, the notification information at least includes: the fourth moment when the first node device obtains the feedback information; adjusts the clock count of the second node device to synchronize with the clock count of the first node device at the port module of the second node device based on the first moment, the second moment, the third moment and the fourth moment. In this scheme, the first node device sends a clock synchronization instruction to the node device directly connected to it, so that the second node device directly connected to it can adjust the clock count based on the clock count of the first node device, thereby realizing the synchronization of the clock counts of the second node device and the first node device. In this scheme, the node device whose clock count accuracy is greater than the preset threshold actively requests the adjacent node device to perform time synchronization, thereby ensuring clock count synchronization and improving the synchronization accuracy. At the same time, it avoids the problem of long data transmission process and low clock synchronization accuracy caused by the need to transmit data through several node devices when performing clock count synchronization. In addition, when performing time synchronization between node devices, any information transmitted during the time synchronization process does not pass through the kernel of the node device, and the time synchronization is completed directly at the port module of the node device that can be connected to other node devices, so as to improve the information transmission efficiency, avoid occupying the processing time of the node device kernel, and improve the throughput of the entire network architecture.

[0073] This embodiment discloses a time synchronization method based on Shaq bus, which is applied to the second node device. The flow chart is as follows: Figure 7 As shown, including: Step S71: determining the optimal node device where the optimal synchronization master clock is located based on the parameter information of the master clock competition vector of each node device in the network, and determining the port in the second node device used for obtaining the parameter information of the master clock competition vector output by the optimal node device as the clock synchronization port; Step S72: obtaining a clock synchronization instruction output by the first node device at the second moment, where the clock synchronization instruction carries the first moment when the first node device outputs the clock synchronization instruction; Step S73: outputting feedback information based on the clock synchronization instruction to the first node device at the third moment; Step S74: Obtain notification information output by the first node device, where the notification information at least includes: a fourth moment when the first node device obtains feedback information; Step S75: determining the interval time required for the clock count of the second node device and the clock count of the first node device to reach the compensation error based on the first moment, the second moment, the third moment and the fourth moment; Step S76: When it is determined that the interval duration is satisfied, adjust the clock count of the second node device based on the compensation error, so that the error between the adjusted clock count of the second node device and the clock count of the first node device is reduced.

[0074] The main body of the Shak bus is composed of a routing device and an interface board. A crystal oscillator is used to provide a reference frequency for the system. However, since the crystal oscillator itself may have errors, the clock error between the routing device and the interface board will gradually increase with the increase of working time. Moreover, this error will always exist and will continue to change.

[0075] In order to alleviate the problem of clock counting errors between adjacent node devices caused by errors in the crystal oscillator itself, this solution adds dynamic time compensation on the basis of periodic clock synchronization based on clock synchronization instructions, so as to improve the synchronization accuracy when performing clock synchronization between node devices in the network structure and realize the nanosecond synchronization requirements of bus communication. In addition, the improvement of synchronization accuracy during the interval between two interactive synchronizations depends on the compensation within the node, rather than on the first node device.

[0076] The synchronization process of a single clock synchronization cycle is as follows: Figure 2 As shown, data is exchanged between T1-T6 to realize the clock synchronization process between the two node devices within the clock synchronization cycle. For the synchronization process including at least two adjacent clock synchronization cycles, Figure 8 As shown, it includes: a first clock synchronization period 801 and a second clock synchronization period 802.

[0077] Among them, the first clock synchronization cycle 801 includes: from the first node device at the first moment T1 to the sixth moment T6, until the first node device has an interval of the second time length and the next first moment T1, the information sent by the first node device to the second node device also includes the information sent by the second node device to the first node device during this time period; the second clock synchronization cycle 802 includes: from the second moment T2 when the second node device obtains the clock synchronization instruction sent by the first node device, until the next second moment T2 when the second node device obtains the clock synchronization instruction sent by the first node device after a certain time length, and also includes the above-mentioned information interaction process. Of course, in the network architecture, interactive time synchronization is performed periodically and does not only include two clock synchronization cycles. Figure 8 Two clock synchronization cycles are used as an example for explanation. In addition, since the network architecture includes multiple node devices, different node devices in the same network architecture are synchronized with their corresponding first node devices according to this rule.

[0078] The first node device sends a clock synchronization instruction to the second node device once at intervals of a certain duration, and the duration of the interval is a duration defined relative to the clock count of the first node device.

[0079] In each clock synchronization cycle, the clock synchronization instruction of the first node device is output to the second node device during the period from the first moment T1 to the second moment T2. After the second node device obtains the clock synchronization instruction at the second moment T2, it immediately outputs feedback information at the third moment T3. Moreover, after the first node device obtains the feedback information at the fourth moment T4, it immediately sends a notification message at the fifth moment T5. After a certain period of time, it arrives at the first moment T1 for sending the clock synchronization instruction next time, and no other processing is performed in between. This shortens the time required for the interactive synchronization process in the entire clock synchronization cycle, thereby increasing the stability and reliability of the entire system.

[0080] After interactive synchronization, due to the error of the crystal oscillator itself, each clock synchronization process will produce errors. After a period of time, the errors will accumulate in large quantities, thus affecting the communication process. Therefore, the longer the interval between each adjacent clock synchronization cycle, the greater the error caused by the crystal oscillator. In order to reduce the error between the two node devices during clock synchronization in each adjacent clock synchronization cycle, dynamic time compensation is added.

[0081] The time compensation within the two interactive synchronization time intervals is implemented by the second node device itself. Based on the first moment, the second moment, the third moment and the fourth moment obtained in each clock synchronization cycle, the error between the clock count of the second node device and the clock count of the first node device can be determined. , and at the same time, the second clock synchronization period is obtained from the count between the two T2 moments, so that time compensation is performed based on these two parameters.

[0082] Specifically, determine a first time difference between the first moments when the first node device outputs clock synchronization instructions twice adjacently, the first node device outputs the clock synchronization instruction every clock synchronization cycle, and the duration of one clock cycle is equal to the first time difference; determine a second time difference △T2 between the second moments when the second node device obtains the clock synchronization instructions output by the first node device twice adjacently, and the second time difference is approximately equal to the first time difference; determine the clock count deviation of the two node devices based on the aforementioned interactive synchronization algorithm, that is, the number of interactive synchronization clock deviations N; determine the number of counts m of the counter required to compensate for the error based on the second time difference △T2 and the number of interactive synchronization clock deviations N.

[0083] m=△T2 / ABS(N) Wherein, ABS(N) represents the absolute value of the number N of interactive synchronization clock deviations.

[0084] That is, when the clock of the second node device increases by m each time, it automatically increases or decreases 1 count according to the sign of N for compensation, so that the clock count of the second node device can be approximately maintained within a deviation of ±1 clock from the clock count of the first node device.

[0085] Multiple dynamic time compensations are performed between each two adjacent clock synchronization cycles, and the time error between the first node device and the second node device is dynamically calibrated, thereby improving the accuracy and reliability of the Shaker bus communication system.

[0086] The time synchronization method based on the Shaq bus disclosed in the present application obtains a clock synchronization instruction output by a first node device at a second moment, the clock synchronization instruction carries the first moment when the first node device outputs the clock synchronization instruction, and the first node device is a node device directly connected to the second node device; outputs feedback information based on the clock synchronization instruction to the first node device at a third moment; obtains notification information output by the first node device, and the notification information at least includes: a fourth moment when the first node device obtains the feedback information; determines the interval duration required for the clock signal of the second node device and the clock count of the first node device to reach a compensation error based on the first moment, the second moment, the third moment and the fourth moment; when it is determined that the interval duration is met, adjusts the clock count of the second node device based on the compensation error, so that the error between the adjusted clock count of the second node device and the clock count of the first node device is reduced. In this solution, a node device whose current clock count accuracy is greater than a preset threshold sends a clock synchronization instruction to a node device directly connected to it, so that a second node device directly connected to it can adjust the clock count based on the clock count of the first node device, thereby realizing synchronization of the clock counts of the second node device and the first node device. In this solution, the first node device actively requests the adjacent node device to perform time synchronization, thereby ensuring clock signal synchronization and improving synchronization accuracy. At the same time, it avoids the problem of long data transmission process and low clock synchronization accuracy caused by the need to transmit data through several node devices when executing clock count synchronization. In addition, in addition to the clock synchronization instruction based on the clock synchronization instruction, the present solution also In addition to periodic time synchronization, when the interval between the clock counts of two node devices reaches the interval length, the clock count of the second node device can be adjusted by compensating the error, that is, within the interval period of two interactive synchronizations, the second node device calculates the compensation ratio by recording the number of periodic clocks and the cumulative clock deviation, and makes an addition when it is expected to reach 1 clock deviation, so as to achieve dynamic time compensation in addition to periodic time synchronization, dynamically calibrate the clock error between the two node devices, increase the accuracy and reliability of communication between node devices, reduce the accumulation of errors caused by crystal oscillators, and achieve high-precision clock synchronization.

[0087] This embodiment discloses a second node device, and its structural diagram is as follows: Fig. 9 As shown, including: A first port module 91 and a first core 92 .

[0088] The first port module 91 includes a plurality of first ports, which can be connected to different node devices respectively, and are used to output the parameter information of the master clock competition vector to other node devices in the network through different first ports at each first time interval, wherein the network performs a reconstruction process at each first time interval; obtain the parameter information of the master clock competition vector output by each node device in the network, wherein the parameter information of the master clock competition vector at least includes the clock accuracy level, clock priority and average distance of all node devices to the current node device of the corresponding node device; determine the sum of the distances between each node device and other node devices based on the parameter information of the master clock competition vector of each node device in the network; determine the node device with the smallest sum of distances with other node devices in the network as the optimal node device with the optimal synchronous master clock, and determine the first port in the second node device for obtaining the parameter information of the master clock competition vector output by the optimal node device as the clock synchronization port; perform clock synchronization on the second node device and the node device connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device; The first core 92 is used to perform other signal processing operations except the above-mentioned time synchronization process.

[0089] Furthermore, the first port module is used for: If the second node device is the optimal node device, output the clock count to other node devices connected to the second node device through the clock synchronization port at every second time interval, so that the other node devices connected to the second node device through the clock synchronization port can adjust the clock count to synchronize with the clock count of the second node device; When the second node device performs clock synchronization with other connected node devices through the clock synchronization port of the second node device, other node devices in the network perform clock synchronization with the node devices connected thereto through the clock synchronization ports of the other node devices.

[0090] Furthermore, the first port module is used for: If the second node device is a non-optimal node device, at every second time interval, based on the clock count of the first node device connected to the clock synchronization port of the second node device, the clock count of the second node device is adjusted so that the adjusted clock count of the second node device is synchronized with the clock count of the first node device.

[0091] Furthermore, the first port module is used for: The sum of the distances between each node device and other node devices is determined based on the parameter information of the master clock competition vector of each node device in the network; the node device with the smallest sum of distances between other node devices in the network is determined as the optimal node device with the optimal synchronous master clock.

[0092] Furthermore, the first port module is used for: At the second moment, a clock synchronization instruction output by the first node device is obtained, and the clock synchronization instruction carries the first moment when the first node device outputs the clock synchronization instruction; at the third moment, feedback information based on the clock synchronization instruction is output to the first node device; notification information output by the first node device is obtained, and the notification information at least includes: the fourth moment when the first node device obtains the feedback information; based on the first moment, the second moment, the third moment and the fourth moment, the clock count of the second node device is adjusted to be synchronized with the clock count of the first node device.

[0093] Furthermore, the first port module is used for: Based on the first moment, the second moment, the third moment and the fourth moment, the offset of the clock count of the second node device relative to the clock count of the first node device is determined; based on the offset, the clock count of the second node device is adjusted to synchronize the clock count of the second node device with the clock count of the first node device.

[0094] Furthermore, the first port module is used for: Based on the first moment, the second moment, the third moment and the fourth moment, the port module of the second node device adjusts the clock count of the second node device to be synchronized with the clock count of the first node device.

[0095] Furthermore, the first port module is also used for: Based on the first moment, the second moment, the third moment and the fourth moment, determine the interval duration required for the clock count of the second node device to reach the compensation error with the clock count of the first node device; when it is determined that the interval duration is met, adjust the clock count of the second node device based on the compensation error so that the error between the adjusted clock count of the second node device and the clock count of the first node device is reduced.

[0096] Furthermore, the first port module is used for: Determine a first time difference between the first moments when the first node device outputs a clock synchronization instruction twice in a row, the first node device outputs the clock synchronization instruction at intervals of one clock cycle, and the duration of one clock cycle is equal to the first time difference; determine a second time difference between the second moments when the second node device obtains the clock synchronization instruction output by the first node device twice in a row; determine the percentage of the difference between the clock count of the second node device and the clock count of the first node device based on the first time difference and the second time difference; determine the number of counts of the counter required to compensate for the error based on the percentage of the difference between the clock count of the second node device and the clock count of the first node device.

[0097] The kernel may be a processor inside the node device, such as a CPU.

[0098] The second node device disclosed in this embodiment is implemented based on the Shack bus-based time synchronization method disclosed in the above embodiment, which will not be described in detail here.

[0099] The second node device disclosed in this embodiment outputs parameter information of the master clock competition vector to other node devices in the network at intervals of a first time length, wherein the network performs a reconstruction process at intervals of the first time length; obtains parameter information of the master clock competition vector output by each node device in the network, wherein the parameter information of the master clock competition vector includes at least the clock accuracy level and the clock priority of the corresponding node device; determines the sum of the distances between each node device and other node devices based on the parameter information of the master clock competition vector of each node device in the network; determines the node device with the smallest sum of distances with other node devices in the network as the optimal node device with the optimal synchronized master clock, and determines the port in the second node device used to obtain the parameter information of the master clock competition vector output by the optimal node device as the clock synchronization port; performs clock synchronization on the second node device and the node device connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device. In this scheme, the optimal synchronization master clock is dynamically adjusted, and the optimal synchronization master clock is determined during the automatic network reconstruction process, which reuses the network reconstruction process and reduces communication pressure. In addition, with the optimal master clock as the center, the outer second node device synchronizes the clock count to the second outer first node device through the optimal path port linked to the optimal master clock, so that the clock synchronization is only performed between two adjacent nodes, and there is no need to send information directly to the optimal synchronization master clock, which reduces the consumption of communication bandwidth resources in the entire network caused by time synchronization. Thirdly, within the interval period of two interactive synchronizations, the second node device calculates the compensation ratio by recording the number of periodic clocks and the cumulative clock deviation, and supplements it when it is expected to reach 1 clock deviation, thereby achieving high-precision clock synchronization.

[0100] This embodiment discloses a time synchronization system based on the Shaker bus, and its structural diagram is shown in FIG. Fig.10 As shown, including: The multiple node devices include at least: a first node device 101 and a second node device 102 .

[0101] The second node device outputs parameter information of the master clock competition vector to other node devices in the network at intervals of a first time length, wherein the network performs a reconstruction process at intervals of a first time length; obtains parameter information of the master clock competition vector output by each node device in the network, wherein the parameter information of the master clock competition vector includes at least the clock accuracy level of the corresponding node device, the clock priority and the average distance from all node devices to the current node device; determines the sum of the distances between each node device and other node devices based on the parameter information of the master clock competition vector of each node device in the network; determines the node device with the smallest sum of distances with other node devices in the network as the optimal node device having the optimal synchronous master clock, and determines the port in the second node device for obtaining parameter information of the master clock competition vector output by the optimal node device as the clock synchronization port; performs clock synchronization on the second node device and the node device connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device; When the second node device and the node device connected to the second node device through the clock synchronization port perform clock synchronization, other node devices among the multiple node devices perform clock synchronization with the node devices connected thereto through the clock synchronization ports of the other node devices.

[0102] The specific network architecture diagram of the Shack bus-based time synchronization system disclosed in this embodiment can be as follows: Figure 4 shown.

[0103] The Shaq bus-based time synchronization system disclosed in this embodiment is implemented based on the Shaq bus-based time synchronization method disclosed in the above embodiments, which will not be described in detail here.

[0104] The time synchronization system based on the Shaq bus disclosed in this embodiment outputs parameter information of a master clock competition vector to other node devices in the network at intervals of a first time length, wherein the network performs a reconstruction process at intervals of a first time length; obtains parameter information of a master clock competition vector output by each node device in the network, wherein the parameter information of the master clock competition vector includes at least a clock accuracy level and a clock priority of the corresponding node device; determines the sum of distances between each node device and other node devices based on the parameter information of the master clock competition vector of each node device in the network; determines a node device in the network having the smallest sum of distances with other node devices as the optimal node device having the optimal synchronized master clock, and determines a port in a second node device for obtaining parameter information of a master clock competition vector output by the optimal node device as a clock synchronization port; performs clock synchronization on a second node device and a node device connected to the second node device via the clock synchronization port to achieve clock synchronization with the optimal node device. In this scheme, the optimal synchronization master clock is dynamically adjusted, and the optimal synchronization master clock is determined during the automatic network reconstruction process, which reuses the network reconstruction process and reduces communication pressure. In addition, with the optimal master clock as the center, the outer second node device synchronizes the clock count to the second outer first node device through the optimal path port linked to the optimal master clock, so that the clock synchronization is only performed between two adjacent nodes, and there is no need to send information directly to the optimal synchronization master clock, which reduces the consumption of communication bandwidth resources in the entire network caused by time synchronization. Thirdly, within the interval period of two interactive synchronizations, the second node device calculates the compensation ratio by recording the number of periodic clocks and the cumulative clock deviation, and supplements it when it is expected to reach 1 clock deviation, thereby achieving high-precision clock synchronization.

[0105] It should also be noted that the device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, in the drawings of the device embodiments provided by the present application, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines.

[0106] Through the description of the above implementation mode, the technicians in the field can clearly understand that the present application can be implemented by means of software plus necessary general hardware, and of course, it can also be implemented by special hardware including special integrated circuits, special CPUs, special memories, special components, etc. In general, all functions completed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be various, such as analog circuits, digital circuits or special circuits. However, for the present application, software program implementation is a better implementation mode in more cases. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer floppy disk, a U disk, a mobile hard disk, a ROM, a RAM, a disk or an optical disk, etc., including a number of instructions to enable a computer device (which can be a personal computer, a training device, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0107] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0108] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a training device, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, training device, or data center. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device, a data center, etc. that includes one or more available media integrations. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)), etc.

Claims

1. A time synchronization method based on Shaq bus, applied to a second node device, characterized in that: include: At intervals of a first duration, outputting parameter information of the master clock competition vector to other node devices in the network, wherein at intervals of the first duration, the network performs a reconstruction process; Obtain parameter information of a master clock competition vector output by each node device in the network, wherein the parameter information of the master clock competition vector includes at least a clock accuracy level, a clock priority, and an average distance from all node devices to the current node device of the corresponding node device; Determine the sum of the distances between each node device and other node devices based on parameter information of the master clock competition vector of each node device in the network; Determine the node device with the smallest sum of distances to other node devices in the network as the optimal node device having the optimal synchronization master clock, and determine the port in the second node device for obtaining parameter information of the master clock competition vector output by the optimal node device as the clock synchronization port; The second node device and a node device connected to the second node device through the clock synchronization port are clock synchronized to achieve clock synchronization with the optimal node device.

2. The method according to claim 1, wherein the clock synchronization of the second node device and the node device connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device comprises: If the second node device is the optimal node device, outputting the clock count to other node devices connected to the second node device through the clock synchronization port at intervals of a second time, so that the other node devices connected to the second node device through the clock synchronization port can adjust the clock count to synchronize with the clock signal of the second node device; When the second node device performs clock synchronization with other connected node devices through the clock synchronization port of the second node device, other node devices in the network perform clock synchronization with node devices connected thereto through the clock synchronization ports of the other node devices.

3. The method according to claim 1, wherein the clock synchronization of the second node device and the node device connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device comprises: If the second node device is a non-optimal node device, at every second time interval, based on the clock count of the first node device connected to the clock synchronization port of the second node device, the clock count of the second node device is adjusted so that the adjusted clock count of the second node device is synchronized with the clock count of the first node device.

4. The method according to claim 3, characterized in that The adjusting the clock count of the second node device based on the clock count of the first node device connected to the clock synchronization port of the second node device includes: Obtaining, at a second moment, a clock synchronization instruction output by the first node device, wherein the clock synchronization instruction carries a first moment at which the first node device outputs the clock synchronization instruction; outputting feedback information based on the clock synchronization instruction to the first node device at a third moment; Obtaining notification information output by the first node device, the notification information at least including: a fourth time at which the first node device obtains the feedback information; The clock count of the second node device is adjusted to be synchronized with the clock count of the first node device based on the first time, the second time, the third time and the fourth time.

5. The method according to claim 4, characterized in that The step of adjusting the clock count of the second node device to be synchronized with the clock count of the first node device based on the first moment, the second moment, the third moment, and the fourth moment includes: Determine an offset of a clock signal of the second node device relative to a clock count of the first node device based on the first time, the second time, the third time, and the fourth time; The clock count of the second node device is adjusted based on the offset so that the clock count of the second node device is synchronized with the clock count of the first node device.

6. The method according to claim 4, characterized in that The step of adjusting the clock count of the second node device to be synchronized with the clock count of the first node device based on the first moment, the second moment, the third moment, and the fourth moment includes: Based on the first moment, the second moment, the third moment and the fourth moment, the port module of the second node device adjusts the clock count of the second node device to be synchronized with the clock count of the first node device, and the port module of the second node device is different from the kernel of the second node device.

7. The method according to claim 4, characterized in that Also includes: Determine, based on the first moment, the second moment, the third moment, and the fourth moment, the interval time required for the clock count of the second node device and the clock count of the first node device to achieve compensation error; When it is determined that the interval duration is satisfied, the clock count of the second node device is adjusted based on the compensation error, so that the error between the adjusted clock count of the second node device and the clock count of the first node device is reduced.

8. The method according to claim 7, characterized in that The determining, based on the first moment, the second moment, the third moment, and the fourth moment, the interval duration required for the second node device to compensate for the error with the first node device includes: Determine a first time difference between first moments when the first node device outputs clock synchronization instructions twice in a row, the first node device outputs the clock synchronization instruction every clock cycle, and the duration of the clock cycle is equal to the first time difference; Determine a second time difference between two consecutive second moments when the second node device obtains the clock synchronization instruction output by the first node device; Determine a percentage of a difference between a clock count of the second node device and a clock count of the first node device based on the first time difference and the second time difference; The number of counts of the counter required to compensate for the cumulative error reaching more than ±1 clock is determined based on the percentage of the difference between the clock count of the second node device and the clock count of the first node device.

9. A second node device, characterized in that: include: A first port module includes a plurality of first ports, which can be connected to different node devices respectively, and are used to output the parameter information of the master clock competition vector to other node devices in the network through different first ports at each first time interval, wherein the network performs a reconstruction process at each first time interval; obtain the parameter information of the master clock competition vector output by each node device in the network, wherein the parameter information of the master clock competition vector at least includes the clock accuracy level, clock priority and average distance of all node devices to the current node device of the corresponding node device; determine the sum of the distances between each node device and other node devices based on the parameter information of the master clock competition vector of each node device in the network; determine the node device with the smallest sum of distances with other node devices in the network as the optimal node device with the optimal synchronous master clock, and determine the first port in the second node device for obtaining the parameter information of the master clock competition vector output by the optimal node device as the clock synchronization port; perform clock synchronization on the second node device and the node device connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device; The first kernel is used to perform other signal processing operations except the above time synchronization process.

10. A time synchronization system based on Shaq bus, characterized in that: include: A plurality of node devices, the plurality of node devices at least comprising: a first node device and a second node device; The second node device outputs parameter information of the master clock competition vector to other node devices in the network at intervals of a first time length, wherein the network performs a reconstruction process at intervals of a first time length; obtains parameter information of the master clock competition vector output by each node device in the network, wherein the parameter information of the master clock competition vector includes at least the clock accuracy level of the corresponding node device, the clock priority and the average distance from all node devices to the current node device; determines the sum of the distances between each node device and other node devices based on the parameter information of the master clock competition vector of each node device in the network; determines the node device with the smallest sum of distances with other node devices in the network as the optimal node device with the optimal synchronous master clock, and determines the port in the second node device for obtaining parameter information of the master clock competition vector output by the optimal node device as the clock synchronization port; performs clock synchronization on the second node device and the node device connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device; When the second node device and the node device connected to the second node device through the clock synchronization port perform clock synchronization, other node devices among the multiple node devices perform clock synchronization with the node devices connected thereto through the clock synchronization ports of the other node devices.

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