High-performance real-time bit error rate detection method and system based on GPU acceleration

Abstract

The invention provides a high-performance real-time bit error rate detection method and system based on GPU acceleration, and the method comprises the steps: receiving a plurality of test data frames, and carrying out the frame synchronization of each test data frame; triggering the CPU equipment to distribute each test data frame to each thread block in the GPU equipment; performing word comparison on each test data frame in each thread block and a template data frame, performing byte bit-by-bit comparison on each error word in the test data frame with the error word and a corresponding correct word according to bits, determining error bits in the error word, and counting the total error bit number; and triggering the GPU equipment to calculate the bit error rate according to the total bit error number, and detecting the bit error rate performance by the CPU equipment according to the bit error rate. According to the method provided by the invention, when the bit error rate comparison of a large data volume is carried out, the GPU equipment is adopted to convert an original serial operation mode into a parallel operation mode, so that the comparison efficiency is improved, and the bit error rate performance detection efficiency of system equipment is further improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a high-performance real-time detection method and system for bit error rate based on GPU acceleration. Background Art

[0002] The bit error rate (SER) refers to the ratio of the number of bit errors to the total number of bits received, and is one of the important indicators for evaluating the reliability of digital communication systems. Its basic calculation formula is: bit error rate = bit errors in transmission / total number of bits transmitted * 100%. Bit errors are caused by decay and noise in signal transmission, which changes the voltage of the signal and causes the signal to be damaged during transmission, resulting in bit errors.

[0003] In order to ensure the reliability of the communication system, the system equipment is often tested for bit error rate performance to ensure that the system equipment can accurately identify bit errors in the transmitted data. At present, in the process of bit error rate performance testing of system equipment, when performing bit error rate comparison of large amounts of data, serial operation is generally used, and the bit error comparison efficiency is low, which leads to low detection efficiency of the bit error rate performance of the system equipment. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a high-performance real-time bit error rate detection method and system based on GPU acceleration, which uses GPU devices to compare the bit error rates of large amounts of data, thereby improving the comparison efficiency and further improving the bit error rate performance detection efficiency of the system equipment.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0006] A high-performance real-time bit error rate detection method based on GPU acceleration, comprising:

[0007] Receiving a plurality of test data frames, and performing frame synchronization on each of the test data frames with a set template data frame;

[0008] Trigger the CPU device to distribute each test data frame that has passed frame synchronization to each thread block in the GPU device;

[0009] Perform word comparison on each test data frame in each thread block and the template data frame respectively to determine whether there is an error word in each test data frame, and store each error word in the test data frame with error words and the correct word corresponding to the error word in the template data frame in a storage container;

[0010] Compare each error word with the correct word corresponding to the error word in the template data frame bit by bit, determine each error bit in the error word, and count the total number of error bits in all error words;

[0011] The GPU device is triggered to calculate the bit error rate of the multiple test data frames according to the total number of bit errors, and the bit error rate is transmitted to the CPU device, and the CPU device detects the bit error rate performance according to the bit error rate.

[0012] The above-mentioned high-performance real-time bit error rate detection method based on GPU acceleration, optionally, triggering the CPU device to distribute each test data frame that has passed frame synchronization to each thread block in the GPU device, includes:

[0013] Determine the number of thread blocks in the GPU device that participate in bit error rate performance detection;

[0014] According to the number of blocks, each test data frame that has passed frame synchronization is evenly distributed to each thread block participating in the bit error rate performance detection in the GPU device.

[0015] The above-mentioned high-performance real-time bit error rate detection method based on GPU acceleration, optionally, performing word comparison on each test data frame in each thread block and the template data frame respectively, comprises:

[0016] Start multiple threads in each thread block;

[0017] Each thread is triggered to perform word comparison between the corresponding test data frame in the thread block where it is located and the template data frame.

[0018] The above-mentioned high-performance real-time detection method for bit error rate based on GPU acceleration, optionally, comparing each error word with the correct word corresponding to the error word in the template data frame bit by bit to determine each error bit in the error word, includes:

[0019] Performing an XOR operation on each byte in the error word and the byte at the corresponding position in the correct word in sequence;

[0020] If the result of the XOR operation is 1, the byte is the correct bit;

[0021] If the result of the XOR operation is 0, the byte is an error bit.

[0022] The above-mentioned high-performance real-time bit error rate detection method based on GPU acceleration, optionally, performing frame synchronization on each of the test data frames with the set template data frame, includes:

[0023] Determining a data boundary of each of the test data frames;

[0024] Based on the data boundary of each test data frame, the test data frame is synchronized with the set template data frame.

[0025] A high-performance real-time bit error rate detection system based on GPU acceleration, including:

[0026] A receiving unit, used for receiving a plurality of test data frames, and performing frame synchronization between each of the test data frames and a set template data frame;

[0027] The allocation unit is used to trigger the CPU device to allocate each test data frame that has passed the frame synchronization to each thread block in the GPU device;

[0028] A comparison unit, used for comparing each test data frame in each thread block with the template data frame, determining whether there is an error word in each test data frame, and storing each error word in the test data frame with the error word and the correct word corresponding to the error word in the template data frame in a storage container;

[0029] A statistical unit, used for comparing each error word with a correct word corresponding to the error word in the template data frame bit by bit, determining each error bit in the error word, and counting the total number of error bits in all error words;

[0030] The detection unit is used to trigger the GPU device to calculate the bit error rate of the multiple test data frames according to the total number of bit errors, and transmit the bit error rate to the CPU device, and the CPU device detects the bit error rate performance according to the bit error rate.

[0031] The above-mentioned GPU-accelerated high-performance real-time bit error rate detection system, optionally, the allocation unit includes:

[0032] A first determining subunit is used to determine the number of thread blocks participating in the bit error rate performance detection in the GPU device;

[0033] The averaging subunit is used to evenly distribute each test data frame that has passed the frame synchronization to each thread block participating in the bit error rate performance detection in the GPU device according to the number of blocks.

[0034] The above-mentioned GPU-accelerated high-performance real-time bit error rate detection system, optionally, the comparison unit includes:

[0035] A startup subunit, used to start multiple threads in each thread block;

[0036] The trigger subunit is used to trigger each thread to perform word comparison between the corresponding test data frame in the thread block where it is located and the template data frame.

[0037] The above-mentioned high-performance real-time bit error rate detection system based on GPU acceleration, optionally, the statistical unit includes:

[0038] The operation subunit is used to perform an XOR operation on each byte in the error word and the byte at the corresponding position in the correct word in sequence; if the XOR operation result is 1, the byte is a correct bit; if the XOR operation result is 0, the byte is an erroneous bit.

[0039] The above-mentioned GPU-accelerated high-performance real-time bit error rate detection system, optionally, the receiving unit includes:

[0040] A second determining subunit, configured to determine a data boundary of each of the test data frames;

[0041] The synchronization subunit is used to perform frame synchronization between the test data frame and the set template data frame based on the data boundary of each test data frame.

[0042] A storage medium includes stored instructions, wherein when the instructions are executed, the device where the storage medium is located is controlled to execute the high-performance real-time bit error rate detection method based on GPU acceleration as described above.

[0043] An electronic device includes a memory and one or more instructions, wherein the one or more instructions are stored in the memory and are configured to be executed by one or more processors to perform the high-performance real-time bit error rate detection method based on GPU acceleration as described above.

[0044] Compared with the prior art, the present invention has the following advantages:

[0045] The present invention provides a high-performance real-time detection method for bit error rate based on GPU acceleration, comprising: receiving multiple test data frames, and performing frame synchronization on each of the test data frames and a set template data frame; triggering a CPU device to distribute each test data frame that has passed the frame synchronization to each thread block in a GPU device; performing word comparison on each test data frame in each thread block with the template data frame to determine whether there is an error word in each test data frame, and storing each error word in the test data frame with the error word and the correct word corresponding to the error word in the template data frame in a storage container; comparing each error word with the correct word corresponding to the error word in the template data frame bit by bit, determining each error bit in the error word, and counting the total number of error bits in all error words; triggering the GPU device to calculate the bit error rate of the multiple test data frames according to the total number of error bits, and transmitting the bit error rate to the CPU device, and the CPU device detecting the bit error rate performance according to the bit error rate. By adopting the method provided by the present invention, when performing bit error rate comparison of large amounts of data, a GPU device is used to transform the original serial operation mode into a parallel operation mode, thereby improving the comparison efficiency and further improving the bit error rate performance detection efficiency of the system equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0047] Figure 1 A method flow chart of a high-performance real-time bit error rate detection method based on GPU acceleration provided by an embodiment of the present invention;

[0048] Figure 2 An example diagram of a high-performance real-time bit error rate detection method based on GPU acceleration provided by an embodiment of the present invention;

[0049] Figure 3 Another example diagram of a high-performance real-time bit error rate detection method based on GPU acceleration provided by an embodiment of the present invention;

[0050] Figure 4 Another example diagram of a high-performance real-time bit error rate detection method based on GPU acceleration provided by an embodiment of the present invention;

[0051] Figure 5 A schematic diagram of the structure of a high-performance real-time bit error rate detection system based on GPU acceleration provided by an embodiment of the present invention;

[0052] Figure 6 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] In this application, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0055] The present invention can be used in many general or special computing device environments or configurations, such as personal computers, server computers, handheld or portable devices, tablet devices, multi-processor devices, distributed computing environments including any of the above devices or devices, etc.

[0056] The method provided by the present invention can be applied to a processor or a server, referring to Figure 1 , which is a method flow chart of a high-performance real-time bit error rate detection method based on GPU acceleration provided by an embodiment of the present invention, is specifically described as follows, including:

[0057] S101: receiving a plurality of test data frames, and performing frame synchronization between each of the test data frames and a set template data frame;

[0058] The detection method provided in the embodiment of the present invention is applied in a system device, and the system device can detect the bit error rate of the transmitted data frame. In order to verify the bit error rate detection performance of the system device, the embodiment of the present invention is provided with a GPU device in the system device, and a detection architecture combining a CPU device with a GPU device is adopted.

[0059] According to the method provided by the embodiment of the present invention, when testing a system device, the system device receives multiple test data frames. When the system device receives multiple test data frames, a CPU arranged in the system device performs frame synchronization on each test data frame.

[0060] In the method provided by the embodiment of the present invention, each test data frame received by the system device is a sample test data frame, the bit error rate in each test data frame is known, and before detection, the correct bits at the corresponding positions in the correct data frames have been replaced with erroneous bits to obtain each test data frame.

[0061] S102: Triggering the CPU device to distribute each test data frame that has passed frame synchronization to each thread block in the GPU device;

[0062] In the method provided by an embodiment of the present invention, the executing subject of the execution method can be a processing unit set in a CPU device, which triggers the CPU device to distribute each test data frame that has passed frame synchronization to each thread block in a GPU device. Multiple thread blocks are set in the GPU device, and multiple threads can be started simultaneously in each thread block.

[0063] S103: performing word comparison on each test data frame in each thread block and the template data frame respectively, determining whether there is an error word in each test data frame, and storing each error word in the test data frame with error words and the correct word corresponding to the error word in the template data frame in a storage container;

[0064] In the method provided by the embodiment of the present invention, for each test data frame allocated to the thread block, the test data frame is compared with the template data frame to determine whether there is an erroneous word in each test data frame.

[0065] The specific comparison process can start multiple threads to compare each word in each test data frame with the word at the corresponding position in the template data frame to determine whether there is an error word in the test data frame. If there is an error word, the correct word corresponding to the determined error word is stored in a set storage container.

[0066] S104: comparing each error word with the correct word corresponding to the error word in the template data frame bit by bit, determining each error bit in the error word, and counting the total number of error bits in all error words;

[0067] The method provided by the embodiment of the present invention compares each error word with the correct word corresponding to the error word on a byte-by-byte basis in a storage container.

[0068] Each error consists of multiple bytes. The bytes are compared in order, bit by bit, to determine the error bits in each error word, and finally count the total number of error bits in all error words.

[0069] S105: Trigger the GPU device to calculate the bit error rate of the multiple test data frames according to the total number of bit errors, and transmit the bit error rate to the CPU device, and the CPU device detects the bit error rate performance according to the bit error rate.

[0070] In the method provided by the embodiment of the present invention, the GPU device calculates the bit error rate of multiple test data received by the system device based on the total bit error number, and transmits the bit error rate to the CPU device, and the processing unit in the CPU device detects the bit error rate detection performance of the system device based on the bit error rate.

[0071] By adopting the method provided by the present invention, when performing bit error rate comparison of large amounts of data, a GPU device is used to transform the original serial operation mode into a parallel operation mode, thereby improving the comparison efficiency and further improving the bit error rate performance detection efficiency of the system equipment.

[0072] In the method provided by the embodiment of the present invention, the process of triggering the CPU device to distribute each test data frame that has passed frame synchronization to each thread block in the GPU device includes:

[0073] Determine the number of thread blocks in the GPU device that participate in bit error rate performance detection;

[0074] According to the number of blocks, each test data frame that has passed frame synchronization is evenly distributed to each thread block participating in the bit error rate performance detection in the GPU device.

[0075] Specifically, in an embodiment of the present application, a plurality of thread blocks are provided in a GPU device, and a plurality of threads can be started simultaneously in each thread block. In the process of performing bit error rate performance detection on a system device, the plurality of thread blocks in the GPU device can all participate in the performance detection process, or a part of the thread blocks can be designated to participate in the performance detection process. In the actual operation process, the number of thread blocks participating in the bit error rate performance detection is determined, and each test data frame that passes frame synchronization is evenly divided according to the number of blocks, and the evenly divided test data frames are correspondingly allocated to the thread blocks participating in the bit error rate performance detection.

[0076] The method provided by the embodiment of the present invention, the process of performing word comparison between each test data frame in each thread block and the template data frame respectively, comprises:

[0077] Start multiple threads in each thread block;

[0078] Each thread is triggered to perform word comparison between the corresponding test data frame in the thread block where it is located and the template data frame.

[0079] Specifically, multiple threads may be started in each thread block, and each thread may be responsible for performing word comparison between a test data frame and a template data frame.

[0080] The method provided by the embodiment of the present invention, wherein the process of comparing each error word with the correct word corresponding to the error word in the template data frame bit by bit and determining each error bit in the error word includes:

[0081] Performing an XOR operation on each byte in the error word and the byte at the corresponding position in the correct word in sequence;

[0082] If the result of the XOR operation is 1, the byte is the correct bit;

[0083] If the result of the XOR operation is 0, the byte is an error bit.

[0084] Specifically, each byte of an error word is XOR-operated with the bytes at corresponding positions in the corresponding correct word one by one in a corresponding order, and whether the byte is an error bit is determined according to the operation result.

[0085] The method provided by the embodiment of the present invention, the process of performing frame synchronization on each of the test data frames and the set template data frame includes:

[0086] Determining a data boundary of each of the test data frames;

[0087] Based on the data boundary of each test data frame, the test data frame is synchronized with the set template data frame.

[0088] The high-performance real-time detection method for bit error rate based on GPU acceleration provided by the embodiment of the present invention is specifically used to evaluate and detect the bit error rate detection performance of system equipment. For the traditional bit error rate detection process, its process specifically includes: injecting erroneous bits into a known correct signal sequence, comparing the original correct signal sequence with the sequence after the erroneous bits are injected, and counting the number of bit errors to calculate the bit error rate. For example, if the sequence consists of 8-bit binary numbers, it is first represented as two hexadecimal numbers during the transmission process. After comparing the hexadecimal numbers, the error word is extracted, and then the correct word and the error word are compared to obtain the number of error bits, and the total number of error bits is obtained by repeating.

[0089] Finally, the bit error rate and operation time are output to test the reliability of the detection equipment and the bit error rate detection rate.

[0090] In a specific implementation, an 8-bit binary number and 1 may be bitwise ANDed and then extracted and compared to obtain the number of bit errors.

[0091] In the actual operation of the above process, when detecting a large amount of data, the bit error rate detection efficiency is low. The high-performance real-time bit error rate detection method based on GPU acceleration provided by the embodiment of the present invention can greatly improve the bit error rate detection process.

[0092] GPU, or graphics processing unit, is a hardware device specifically used for graphics processing and image computing. With the increase in computing needs, GPU, with its advantages in parallel computing architecture, has also been widely used in large-scale computing and deep learning and other fields.

[0093] In the method provided in the embodiment of the present application, the stream processing architecture of the GPU can execute a large number of threads simultaneously, and has significant advantages in performing a large number of repetitive simple calculations.

[0094] The present invention provides a high-performance real-time bit error rate detection method based on GPU acceleration, which has the characteristics of high detection efficiency and good real-time bit error rate monitoring performance. It is mainly used to solve the problem of real-time bit error rate detection in high-speed data transmission. The GPU multi-threaded bit error rate parallel comparison algorithm can produce a larger acceleration ratio than the CPU serial algorithm.

[0095] In the actual execution process, we can first generate an error template, which is the test data frame received by the system device. The bit error rate and bit error rate of each error template are also known. If the final output bit error rate is correct, it means that the designed GPU bit error rate detection algorithm is reliable. The sample data used in this experiment can be binary data with a word length of 8 and a frame length of 1024, which is represented in hexadecimal, and the corresponding frame bits are replaced to determine the bit error rate.

[0096] Furthermore, GPU threads are allocated to prepare for the next parallel operation. In GPU parallel programs, Gridsize is the grid size, Blocksize is the thread block size, and the total number of threads is Gridsize*Blocksize. In the process of parallelization improvement, initiating multiple threads for parallel operation by calling kernel functions to increase the operation rate is also the key to GPU parallel algorithms.

[0097] The error code template set at the beginning is compared bit by bit with the correct template read, and all error words are extracted.

[0098] Whenever an error word is detected, the error word is extracted and compared with the corresponding word of the correct template bit by bit. The specific method is: each bit of the error word and the correct word is extracted with "1" and then compared, the detected error bytes are accumulated, and the total number of all error words is obtained.

[0099] Compare the number of erroneous bytes with the total number of bytes to get the bit error rate and output the operation time.

[0100] The embodiment of the present invention provides a high-performance real-time bit error rate detection method based on GPU acceleration, and proposes a CPU+GPU parallel architecture. Figure 2 As shown in the figure, the CPU is no longer the main computing device, but mainly plays the logical control advantage of the CPU device. In the detection equipment, it mainly acts as the host end as an instruction control unit, and transmits the data to be compared to the GPU through the PCI bus for calculation. The GPU is a representative of a multi-core architecture with a large number of cores. Unlike the CPU, the CPU adopts a multi-core architecture. Each core of the CPU, namely the arithmetic logic unit ALU, is suitable for processing very complex control logic to optimize serial program execution; while the GPU core is lighter and is suitable for optimizing data parallel tasks with simple control logic, focusing on the data throughput of parallel programs. The heterogeneous architecture proposed in this article makes good use of the respective advantages of the CPU and GPU, thereby greatly improving the overall computing power and bit error rate comparison efficiency.

[0101] The parallel computing architecture of the GPU enables the GPU to significantly improve the computing speed of large-scale simple repetitive calculations. Compared with traditional CPUs, GPUs have thousands to tens of thousands of parallel processing units, each of which can execute multiple threads at the same time. This large-scale parallelism enables the GPU to process large amounts of data and tasks at the same time, thus performing well in handling complex computing tasks. For example, in the fields of scientific computing, deep learning, and graphics processing, the GPU can use parallel processing units to perform thousands of computing operations at the same time, quickly completing complex calculations and computationally intensive tasks. In addition, the GPU's high-speed memory bandwidth and optimized memory hierarchy further improve the speed of data transmission and access, helping to avoid performance degradation due to data bottlenecks. Therefore, the parallel computing capabilities of the GPU not only significantly improve the computing rate, but also greatly shorten the time required to process large-scale data and simple repetitive calculations.

[0102] The overall process structure of the CPU+GPU heterogeneous architecture bit error rate detection operation can be referenced Figure 3 and Figure 4 , Figure 3 and Figure 4 The process structure principle involved in is the same. In the process of understanding this solution, you can combine Figure 3 and Figure 4 Data is transmitted between the CPU and GPU via the PCI bus. In the entire program flow, the CPU mainly plays a logical control role. For the bit error rate detection part with huge computational complexity, the CPU will transfer a large amount of code data to the GPU memory, and the GPU will initiate a large number of threads for parallel calculations. In this structure, the process of extracting error words and then comparing the error words with the corresponding correct words bit by bit is run in parallel. When all bit error rate comparisons are completed, the GPU will transmit the bit error rate data back to the CPU via the PCI bus.

[0103] In the process of bit error rate comparison, the heterogeneous architecture algorithm proposed in the embodiment of the present application parallelizes the bit error rate comparison part with the largest bit error rate calculation computation amount by initiating GPU threads, which can greatly improve the rate of bit error rate comparison.

[0104] Based on the above analysis, the embodiment of the present application mainly studies how to perform a bit error rate detection method under high-speed information transmission conditions. The proposed implementation method is based on the GPU computing platform, using the parallel computing architecture of the GPU, and parallelizing and improving the traditional bit error rate detection algorithm. By writing a GPU parallel program and using the parallel architecture of the GPU to redesign the bit error rate detection program, a larger acceleration ratio is achieved relative to the CPU algorithm to achieve real-time detection of bit error rates in large data transmission. Therefore, the focus of the embodiment of the present application is on the parallel design of the bit error rate statistical algorithm. By testing the traditional CPU bit error rate algorithm and the redesigned GPU parallel algorithm, the operation rate is compared and analyzed. The experimental results show that the GPU parallel algorithm proposed in this article has a larger acceleration ratio than the traditional algorithm, can meet the real-time detection requirements of bit error rates for more high-speed transmissions in the future, and has certain application value.

[0105] In the traditional bit error rate comparison process, the receiving device usually has a predefined or theoretically expected correct data pattern template. When the receiving end receives the data from the sending end, it compares the received data with the theoretical value. Similarly, the CPU+GPU heterogeneous architecture bit error rate detection device designed in this paper will also have a theoretical received data template in advance as the correct template for comparison with the received template containing errors.

[0106] In the actual implementation process, the whole process can be divided into four modules, which are: frame synchronization of received data and local theoretical value template, word comparison of data with bit errors and correct template, taking out the error words and storing them in the container and taking out the correct words at the corresponding position for byte-by-byte extraction and comparison, and summing up to get the total bit error rate. Each step is explained in detail below.

[0107] The main purpose of frame synchronization in the first step is to ensure that the receiving end can correctly identify and locate the boundaries of the received data frame or data packet so that the subsequent bit error rate detection and decoding operations can be carried out accurately. After confirming the start and end positions of the frame, the receiving end can confirm frame synchronization. This means that the receiving end has successfully identified a complete data frame or data packet and is ready for the next step of bit error rate detection processing. Frame synchronization is essential in various communication systems, especially in high-speed, high-capacity data transmission that our bit error rate detection system is to study.

[0108] The second step is word comparison. First, the wrong word is compared with the correct word. Then, the wrong word and the correct word at the corresponding position are stored in a container before the byte is compared bit by bit. The purpose of this step is to first pick out the wrong word and then compare the bytes. Comparing the data of a single word instead of the entire byte first has significant computational advantages. By comparing the words first, the amount of data for each comparison can be effectively reduced, thereby reducing the computational complexity. In contrast, directly comparing the entire byte may result in excessive computational overhead, especially when processing large amounts of data.

[0109] The third step is to compare the selected error word and the correct word at the corresponding position bit by bit. The core of the bit-by-bit byte comparison is to use the bit-by-bit exclusive OR (XOR) operation. Suppose there is a correct word (A) and an error word (B), and their corresponding positions have been determined. For example, if (A = 10101010) (correct word) and (B = 10111011) (error word), the bit-by-bit comparison operation is as follows: perform a bit-by-bit exclusive OR operation on each bit: (A exclusive OR B). In this way, a result can be obtained, in which each bit indicates whether the corresponding bit matches (0 for match, 1 for mismatch).

[0110] In the fourth step, when the GPU device completes the bit-by-bit comparison of all data sets, it adds up all the bit errors to get the total bit error number, and then gets the bit error rate of the entire data, and finally transmits the data back to the CPU control device.

[0111] In the above-mentioned whole process, the second and third steps are the core steps of the bit error rate detection algorithm. The CPU+GPU heterogeneous architecture platform in this article also mainly accelerates the traditional algorithm in this step. The GPU can process multiple data at the same time and perform the same operation, and initiate multiple threads to process a large amount of data in parallel. Specifically, in the second step of word matching, the GPU can process multiple data at the same time and perform the same matching operation, and process a large amount of data in parallel by assigning each matching task to multiple GPU cores or thread blocks. This parallel computing method can not only speed up the matching speed of a single word, but also effectively handle the concurrent matching tasks of multiple words, further improving the overall efficiency of the algorithm. After the calculation amount has been assigned to multiple threads in the second step, the storage of the error word and the bit-by-bit byte comparison are also performed in different threads, and the overall computing efficiency is greatly improved.

[0112] and Figure 1 Corresponding to the method shown in the figure, the present invention also provides a high-performance real-time bit error rate detection system based on GPU acceleration, which is used to support Figure 1 The implementation of the method shown in the figure, the system can be set in a processor or a server, and its structural diagram is as shown in Figure 5 As shown, including:

[0113] The receiving unit 201 is used to receive a plurality of test data frames and perform frame synchronization between each of the test data frames and a set template data frame;

[0114] The allocating unit 202 is used to trigger the CPU device to allocate each test data frame that has passed the frame synchronization to each thread block in the GPU device;

[0115] The comparison unit 203 is used to compare each test data frame in each thread block with the template data frame to determine whether there is an error word in each test data frame, and store each error word in the test data frame with the error word and the correct word corresponding to the error word in the template data frame in a storage container;

[0116] A statistical unit 204 is used to compare each error word with the correct word corresponding to the error word in the template data frame bit by bit, determine each error bit in the error word, and count the total number of error bits in all error words;

[0117] The detection unit 205 is used to trigger the GPU device to calculate the bit error rate of the multiple test data frames according to the total number of bit errors, and transmit the bit error rate to the CPU device, and the CPU device detects the bit error rate performance according to the bit error rate.

[0118] In the system provided by the embodiment of the present invention, the GPU device calculates the bit error rate of multiple test data received by the system device based on the total bit error number, and transmits the bit error rate to the CPU device, and the processing unit in the CPU device detects the bit error rate detection performance of the system device based on the bit error rate.

[0119] Furthermore, the allocation unit includes:

[0120] A first determining subunit is used to determine the number of thread blocks participating in the bit error rate performance detection in the GPU device;

[0121] The averaging subunit is used to evenly distribute each test data frame that has passed the frame synchronization to each thread block participating in the bit error rate performance detection in the GPU device according to the number of blocks.

[0122] The comparison unit comprises:

[0123] A startup subunit, used to start multiple threads in each thread block;

[0124] The trigger subunit is used to trigger each thread to perform word comparison between the corresponding test data frame in the thread block where it is located and the template data frame.

[0125] The statistical unit comprises:

[0126] The operation subunit is used to perform an XOR operation on each byte in the error word and the byte at the corresponding position in the correct word in sequence; if the XOR operation result is 1, the byte is a correct bit; if the XOR operation result is 0, the byte is an erroneous bit.

[0127] The receiving unit comprises:

[0128] A second determining subunit, configured to determine a data boundary of each of the test data frames;

[0129] The synchronization subunit is used to perform frame synchronization between the test data frame and the set template data frame based on the data boundary of each test data frame.

[0130] An embodiment of the present invention further provides a storage medium, which includes stored instructions, wherein when the instructions are executed, the device where the storage medium is located is controlled to execute the above-mentioned high-performance real-time bit error rate detection method based on GPU acceleration.

[0131] The embodiment of the present invention further provides an electronic device, the structural diagram of which is shown in FIG. Figure 6 As shown, it specifically includes a memory 601, and one or more instructions 602, wherein the one or more instructions 602 are stored in the memory 601, and are configured to be executed by one or more processors 603 to execute the one or more instructions 602 to perform the above-mentioned GPU-accelerated high-performance real-time bit error rate detection method.

[0132] It should be noted that the information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions.

[0133] The specific implementation processes and derivative methods of the above-mentioned embodiments are all within the protection scope of the present invention.

[0134] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can refer to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without creative work.

[0135] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0136] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A high-performance real-time bit error rate detection method based on GPU acceleration, characterized in that: include: Receiving a plurality of test data frames, and performing frame synchronization on each of the test data frames with a set template data frame; Trigger the CPU device to distribute each test data frame that has passed frame synchronization to each thread block in the GPU device; Perform word comparison on each test data frame in each thread block and the template data frame respectively to determine whether there is an error word in each test data frame, and store each error word in the test data frame with error words and the correct word corresponding to the error word in the template data frame in a storage container; Compare each error word with the correct word corresponding to the error word in the template data frame bit by bit, determine each error bit in the error word, and count the total number of error bits in all error words; The GPU device is triggered to calculate the bit error rate of the multiple test data frames according to the total number of bit errors, and the bit error rate is transmitted to the CPU device, and the CPU device detects the bit error rate performance according to the bit error rate.

2. According to claim 1, the high-performance real-time detection method for bit error rate based on GPU acceleration is characterized in that: The triggering CPU device to distribute each test data frame that has passed frame synchronization to each thread block in the GPU device includes: Determine the number of thread blocks in the GPU device that participate in bit error rate performance detection; According to the number of blocks, each test data frame that has passed frame synchronization is evenly distributed to each thread block participating in the bit error rate performance detection in the GPU device.

3. The high-performance real-time bit error rate detection method based on GPU acceleration according to claim 1 is characterized in that: The step of comparing each test data frame in each thread block with the template data frame includes: Start multiple threads in each thread block; Each thread is triggered to perform word comparison between the corresponding test data frame in the thread block where it is located and the template data frame.

4. The high-performance real-time bit error rate detection method based on GPU acceleration according to claim 1 is characterized in that: The step of comparing each error word with a correct word corresponding to the error word in the template data frame bit by bit to determine each error bit in the error word includes: Performing an XOR operation on each byte in the error word and the byte at the corresponding position in the correct word in sequence; If the result of the XOR operation is 1, the byte is the correct bit; If the result of the XOR operation is 0, the byte is an error bit.

5. The high-performance real-time bit error rate detection method based on GPU acceleration according to claim 1 is characterized in that: The step of performing frame synchronization on each of the test data frames and the set template data frame comprises: Determining a data boundary of each of the test data frames; Based on the data boundary of each test data frame, the test data frame is synchronized with the set template data frame.

6. A high-performance real-time bit error rate detection system based on GPU acceleration, characterized in that: include: A receiving unit, used for receiving a plurality of test data frames, and performing frame synchronization between each of the test data frames and a set template data frame; The allocation unit is used to trigger the CPU device to allocate each test data frame that has passed the frame synchronization to each thread block in the GPU device; A comparison unit, used for comparing each test data frame in each thread block with the template data frame, determining whether there is an error word in each test data frame, and storing each error word in the test data frame with the error word and the correct word corresponding to the error word in the template data frame in a storage container; A statistical unit, used for comparing each error word with a correct word corresponding to the error word in the template data frame bit by bit, determining each error bit in the error word, and counting the total number of error bits in all error words; The detection unit is used to trigger the GPU device to calculate the bit error rate of the multiple test data frames according to the total number of bit errors, and transmit the bit error rate to the CPU device, and the CPU device detects the bit error rate performance according to the bit error rate.

7. The high-performance real-time bit error rate detection system based on GPU acceleration according to claim 6 is characterized in that: The distribution unit comprises: A first determining subunit is used to determine the number of thread blocks participating in the bit error rate performance detection in the GPU device; The averaging subunit is used to evenly distribute each test data frame that has passed the frame synchronization to each thread block participating in the bit error rate performance detection in the GPU device according to the number of blocks.

8. The high-performance real-time bit error rate detection system based on GPU acceleration according to claim 6 is characterized in that: The comparison unit comprises: A startup subunit, used to start multiple threads in each thread block; The trigger subunit is used to trigger each thread to perform word comparison between the corresponding test data frame in the thread block where it is located and the template data frame.

9. The high-performance real-time bit error rate detection system based on GPU acceleration according to claim 6, characterized in that: The statistical unit comprises: The operation subunit is used to perform an XOR operation on each byte in the error word and the byte at the corresponding position in the correct word in sequence; if the XOR operation result is 1, the byte is a correct bit; if the XOR operation result is 0, the byte is an erroneous bit.

10. The high-performance real-time bit error rate detection system based on GPU acceleration according to claim 6, characterized in that: The receiving unit comprises: A second determining subunit, configured to determine a data boundary of each of the test data frames; The synchronization subunit is used to perform frame synchronization between the test data frame and the set template data frame based on the data boundary of each test data frame.

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