Power amplifier chip and test method of power amplifier chip

Abstract

The embodiment of the invention provides a power amplifier chip and a test method of the power amplifier chip. The power amplifier chip comprises an internal register, a signal generation module and a signal processing module, the internal register can provide preset information for the signal generation module, the signal generation module can generate an internal sound signal according to the preset information in a test mode, and the internal sound signal is a test signal of the power amplifier chip. The signal processing module can process the internal sound signal in the test mode to obtain a target test signal. The target test signal is used for determining the test result of the power amplifier chip, so that when the power amplifier chip is tested, the power amplifier chip can generate an internal sound signal for testing, an external sound source generator is not needed, and the test scene of the power amplifier chip can be expanded.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to a power amplifier chip and a testing method for the power amplifier chip. Background Art

[0002] Amplifier chips are an indispensable part of all kinds of audio equipment. Amplifier chips are connected to the sound source device through the Inter-IC Sound (I2S) bus. Their main function is to amplify the weaker signal input from the sound source device and generate a large enough current to drive the speaker to reproduce the sound. Amplifier chips need to be tested before leaving the factory. Usually, the amplifier chip needs to be connected to an external sound source generator through the I2S bus, and the external sound source generator provides the amplifier chip with a sound signal for testing.

[0003] However, in the existing test scheme, if there is no external sound source generator, the function of the power amplifier chip cannot be tested, resulting in limited test scenarios of the power amplifier chip. Summary of the invention

[0004] The embodiments of the present disclosure provide a power amplifier chip and a test method for the power amplifier chip, which can expand the test scenarios of the power amplifier chip.

[0005] In a first aspect, the present disclosure provides a power amplifier chip, comprising: an internal register, a signal generating module and a signal processing module.

[0006] The internal register is configured to provide preset information to the signal generation module, wherein the preset information includes a preset frequency and / or a preset amplitude. The signal generation module is configured to generate an internal sound signal according to the preset information in a test mode, wherein the internal sound signal is a test signal of the power amplifier chip. The signal processing module is configured to process the internal sound signal in the test mode to obtain a target test signal.

[0007] Wherein, the target test signal is used to determine the test result of the power amplifier chip.

[0008] In some embodiments of the present disclosure, the power amplifier chip further includes an I2S interface, the input end of the I2S interface is connected to the I2S bus, the output end of the I2S interface is connected to the input end of the signal processing module and the output end of the signal generating module, and the output end of the signal processing module is connected to the output end of the power amplifier chip.

[0009] The I2S interface is configured to connect an external sound signal in the working mode. The signal processing module is also configured to process the external sound signal in the working mode.

[0010] In some embodiments of the present disclosure, an enable terminal of the signal generating module is connected to a signal output terminal of the internal register.

[0011] The internal register is further configured to generate a test mode signal in the test mode and to generate a working mode signal in the working mode. The signal generating module is further configured to generate the internal sound signal according to the preset information under the action of the test mode signal. The signal generating module is further configured not to generate the internal sound signal under the action of the working mode signal.

[0012] In some embodiments of the present disclosure, the power amplifier chip further includes a multiplexer. A first input end of the multiplexer is connected to an output end of the signal generating module, a control end of the multiplexer is connected to a signal output end of the internal register; an output end of the I2S interface is connected to a second input end of the multiplexer, and an input end of the signal processing module is connected to an output end of the multiplexer.

[0013] The internal register is further configured to generate a test mode signal in the test mode and to generate a working mode signal in the working mode. The signal generating module is further configured to generate the internal sound signal according to the preset information in the working mode. The multiplexer is configured to select and output the internal sound signal according to the test mode signal and to select and output the external sound signal according to the working mode signal.

[0014] In some embodiments of the present disclosure, the amplitude output terminal of the internal register is connected to the amplitude input terminal of the signal generating module, and the frequency output terminal of the internal register is connected to the frequency input terminal of the signal generating module.

[0015] The signal generating module is further configured to generate the internal sound signal according to the preset amplitude and the preset frequency.

[0016] In some embodiments of the present disclosure, the power amplifier chip further comprises an internal interface, wherein a first input / output terminal of the internal interface is connected to a bus, and a second input / output terminal of the internal interface is connected to an input / output terminal of the internal register.

[0017] The internal interface is configured to configure the preset information and the test mode to the internal register.

[0018] In a second aspect, the present disclosure provides a test method for a power amplifier chip, which is applied to any power amplifier chip provided in the first aspect. The test method includes:

[0019] Switch to the test mode according to the test mode instruction sent by the test device; generate an internal sound signal according to preset information, the preset information includes a preset amplitude and / or a preset frequency, and the internal sound signal is a test signal of the power amplifier chip; process the internal sound signal to obtain a target test signal; send the target test signal to the test device, so that the test device determines the test result of the power amplifier chip according to the target test signal.

[0020] In some embodiments of the present disclosure, the testing method further includes:

[0021] Switch to the working mode, in which the power amplifier chip is connected to an external sound signal; the external sound signal is processed to obtain a target interface test signal; the target interface test signal is sent to the test device, so that the test device determines the test result of the I2S interface according to the target interface test signal.

[0022] In some embodiments of the present disclosure, before the preset information generates the internal sound signal, the method further includes:

[0023] Generates test pattern signals.

[0024] The preset information generating the internal sound signal comprises:

[0025] Under the effect of the test mode signal, the internal sound signal is generated according to the preset information.

[0026] Before the external sound signal is processed to obtain the target interface test signal, the method further includes:

[0027] A working mode signal is generated; under the effect of the working mode signal, the internal sound signal is not generated.

[0028] In some embodiments of the present disclosure, before the preset information generates the internal sound signal, the method further includes:

[0029] Generates test pattern signals.

[0030] Before the internal sound signal is processed to obtain the target test signal, the method further includes:

[0031] The internal sound signal is selected to be output according to the test mode signal.

[0032] Before the external sound signal is processed to obtain the target interface test signal, the method further includes:

[0033] Generate a working mode signal; generate the internal sound signal according to the preset information; and select to output the external sound signal according to the working mode signal.

[0034] In the technical solution of the embodiment of the present disclosure, the power amplifier chip includes an internal register, a signal generation module and a signal processing module. The internal register can provide preset information to the signal generation module. The signal generation module can generate an internal sound signal according to the preset information in the test mode. The internal sound signal is a test signal of the power amplifier chip. The signal processing module can process the internal sound signal in the test mode to obtain a target test signal. The target test signal is used to determine the test result of the power amplifier chip. Therefore, when testing the power amplifier chip, the power amplifier chip itself can generate an internal sound signal for testing without an external sound source generator, thereby expanding the test scenario of the power amplifier chip.

[0035] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 A schematic diagram of the structure of a power amplifier chip provided in an embodiment of the present disclosure.

[0038] Figure 2 A waveform diagram of an internal sound signal provided in an embodiment of the present disclosure.

[0039] Figure 3 A schematic diagram of the structure of another power amplifier chip provided in an embodiment of the present disclosure.

[0040] Figure 4 A schematic diagram of the structure of another power amplifier chip provided in an embodiment of the present disclosure.

[0041] Figure 5 A schematic flow chart of a method for testing a power amplifier chip provided in an embodiment of the present disclosure.

[0042] Figure 6 A flowchart of another method for testing a power amplifier chip provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the disclosed subject matter belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0045] Reference to "embodiments" in this disclosure means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

[0046] In addition, the terms "first", "second", etc. in the specification and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0047] The term "and / or" in this disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0048] In the description of the present disclosure, unless otherwise specified, "plurality" and "at least two" mean more than two (including two), and similarly, "multiple groups" and "at least two groups" mean more than two groups (including two).

[0049] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0050] Figure 1 A schematic diagram of the structure of a power amplifier chip provided in an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the power amplifier chip includes an internal register 110, a signal generating module 120 and a signal processing module 130. The output end of the internal register 110 is connected to the input end of the signal generating module 120, the output end of the signal generating module 120 is connected to the input end of the signal processing module 130, and the output end of the signal processing module 130 is connected to the output end of the power amplifier chip.

[0051] The internal register 110 is configured to provide preset information to the signal generation module 120. The preset information includes a preset frequency and / or a preset amplitude. The signal generation module 120 is configured to generate an internal sound signal according to the preset information in the test mode, and the internal sound signal is a test signal of the power amplifier chip. The signal processing module 130 is configured to process the internal sound signal in the test mode to obtain a target test signal. The target test signal is used to determine the test result of the power amplifier chip.

[0052] Exemplarily, the internal register 110 may be an I2C register, a Serial Peripheral Interface (SPI) register, a Universal Asynchronous Receiver Transmitter (UART) register, or other types of user-accessible registers.

[0053] If the preset information stored in the internal register 110 includes a preset amplitude, the amplitude output terminal of the internal register 110 is connected to the amplitude input terminal of the signal generating module 120 to provide the preset amplitude to the signal generating module 120 .

[0054] If the preset information stored in the internal register 110 includes a preset frequency, the frequency output terminal of the internal register 110 is connected to the frequency input terminal of the signal generating module 120 to provide the preset frequency to the signal generating module 120 .

[0055] If the preset information stored in the internal register 110 includes a preset amplitude and a preset frequency, the amplitude output end of the internal register 110 is connected to the amplitude input end of the signal generating module 120, and the frequency output end of the internal register 110 is connected to the frequency input end of the signal generating module 120 to provide the preset amplitude and preset frequency to the signal generating module 120.

[0056] Exemplarily, the signal generation module 120 may be a coordinate rotation digital computer (Cordic) module, and the signal generation module 120 is a module implemented by the Cordic algorithm. In the test scenario of the power amplifier chip, the power amplifier chip may be in a test mode, and the internal sound signal generated by the signal generation module 120 is a sinusoidal signal, such as Figure 2 As shown, Figure 2 A waveform diagram of an internal sound signal provided in an embodiment of the present disclosure.

[0057] If the preset information received by the signal generation module 120 is a preset amplitude, the signal generation module 120 may generate an internal sound signal according to the preset amplitude. For example, the internal sound signal generated by the signal generation module 120 may be a sinusoidal signal with a preset amplitude and a default frequency, or a sinusoidal signal with a default frequency and an amplitude that has a specific relationship with the preset amplitude.

[0058] If the preset information received by the signal generation module 120 is a preset frequency, the signal generation module 120 may generate an internal sound signal according to the preset frequency. For example, the internal sound signal generated by the signal generation module 120 may be a sinusoidal signal with a preset frequency and a default amplitude, or a sinusoidal signal with a default amplitude and a frequency that has a specific relationship with the preset frequency.

[0059] If the preset information received by the signal generation module 120 is a preset amplitude and a preset frequency, the signal generation module 120 may generate an internal sound signal according to the preset amplitude and the preset frequency. For example, the internal sound signal generated by the signal generation module 120 may be a sinusoidal signal with a preset amplitude and a preset frequency, or may be a sinusoidal signal with an amplitude having a specific relationship with the preset amplitude and a frequency having a specific relationship with the preset frequency.

[0060] In other implementations, the signal generating module 120 may also be a module implemented based on other algorithms, and the internal sound signal may also be other types of signals such as a cosine signal, a square wave signal or a ramp signal, and the present disclosure does not impose any specific limitations on this.

[0061] Exemplarily, the signal processing module 130 includes a comb filter (CIC filter), a shaping unit, a dynamic window approach (DWA) algorithm unit, a digital-to-analog converter (DAC) and a pulse width modulation (PWM) unit, etc. In the test mode, the internal sound signal is used as a test signal of the power amplifier chip, and the signal processing module 130 can filter, shape, reduce noise, cancel echoes, perform digital-to-analog conversion and pulse width modulation on the internal sound signal to obtain a target test signal, and the target test signal is a pulse width modulation signal.

[0062] In the test scenario of the power amplifier chip, when the power amplifier chip is in the test mode, the power amplifier chip can send the target test signal to the test device. The test device includes the peripheral circuit of the power amplifier chip, and the test device can demodulate the target test signal into an audio signal, that is, demodulate it into a test feedback signal, such as Figure 2 shown.

[0063] The power amplifier chip can also send the internal sound signal to the test device, and the test device can determine whether the test feedback signal meets the first preset condition according to the frequency of the test feedback signal and the frequency of the internal sound signal. The first preset condition can be that the difference between the frequency of the test feedback signal and the frequency of the internal sound signal is less than the first preset difference.

[0064] The test device can determine whether the test feedback signal satisfies a second preset condition based on the amplitude of the test feedback signal and the amplitude of the internal sound signal. The second preset condition can be that the difference between the amplitude of the test feedback signal and N times the amplitude of the internal sound signal is less than a second preset difference, where N is any integer greater than or equal to 1.

[0065] The test device can also determine the test result of the power amplifier chip according to whether the test feedback signal meets the first preset condition and the second preset condition. For example, if the test feedback signal meets the first preset condition and the second preset condition, the test result of the power amplifier chip is determined to be qualified. If the test feedback signal meets the first preset condition but does not meet the second preset condition, the test result of the power amplifier chip is determined to be unqualified. If the test feedback signal meets the second preset condition but does not meet the first preset condition, the test result of the power amplifier chip is determined to be unqualified.

[0066] In this way, in the test scenario of the power amplifier chip, the power amplifier chip can be in the test mode, and the power amplifier chip can generate an internal sound signal according to the preset information, and the internal sound signal is used as the test signal of the power amplifier chip. The power amplifier chip can also process the internal sound signal to obtain a target test signal. The test device can demodulate the target test signal to obtain a test feedback signal, and determine the test result of the power amplifier chip according to the test feedback signal and the internal sound signal.

[0067] In the disclosed embodiment, the power amplifier chip includes an internal register, a signal generating module and a signal processing module. The internal register can provide preset information to the signal generating module. The signal generating module can generate an internal sound signal according to the preset information in the test mode. The internal sound signal is a test signal of the power amplifier chip. The signal processing module can process the internal sound signal in the test mode to obtain a target test signal. The target test signal is used to determine the test result of the power amplifier chip. Therefore, when testing the power amplifier chip, the power amplifier chip itself can generate an internal sound signal for testing without an external sound source generator, thereby expanding the test scenario of the power amplifier chip.

[0068] In some embodiments, Figure 3 A schematic diagram of the structure of another power amplifier chip provided in an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the power amplifier chip further includes an internal interface 140 , wherein a first input / output terminal of the internal interface 140 is connected to the bus, and a second input / output terminal of the internal interface 140 is connected to an input / output terminal of the internal register 110 .

[0069] The internal interface 140 is configured to configure preset information and a test mode to the internal register 110 .

[0070] Exemplarily, the internal register 110 is an I2C register, the corresponding internal interface 140 is an I2C interface, and the first input and output terminals of the internal interface 140 are connected to the I2C bus. The internal interface 140 is connected to an external device via the I2C bus, and the user can input preset information and a test mode signal to the external device. The external device sends the preset information and the test mode signal input by the user to the internal interface 140 via the I2C bus, and the internal interface 140 writes the preset information and the test mode signal into the internal register 110 to configure the preset information and the test mode to the internal register 110.

[0071] In this way, users can flexibly set preset information based on actual needs, that is, they can generate internal sound signals of any amplitude and frequency according to needs.

[0072] In other implementations, the internal register 110 is an SPI register and the internal interface 140 is an SPI, or the internal register 110 is a UART register and the internal interface 140 is a UART interface, or the internal register 110 is another type of register and the internal interface 140 is another type of matching interface.

[0073] In some embodiments, see Figure 3 The power amplifier chip further includes an I2S interface 150 . An input end of the I2S interface 150 is connected to the I2S bus, and an output end of the I2S interface 150 is connected to an input end of the signal processing module 130 and an output end of the signal generating module 120 .

[0074] The I2S interface 150 is configured to connect an external sound signal in the working mode. The signal processing module 130 is also configured to process the external sound signal in the working mode.

[0075] Exemplarily, the I2S interface 150 can be connected to an external sound source device via an I2S bus, and the external sound source device can output an external sound signal. When the power amplifier chip is in working mode, the external sound source device transmits the external sound signal to the I2S interface 150 via the I2S bus.

[0076] In the test scenario of the power amplifier chip, the external sound signal is the test signal of the power amplifier chip, and the signal processing module 130 can filter, shape, reduce noise, cancel echoes, convert digital to analog, and modulate the external sound signal to obtain a target interface test signal, and the target interface test signal is a pulse width modulated signal. In the normal use scenario of the power amplifier chip, the external sound signal is a signal to be amplified and output, and the signal processing module 130 can filter, shape, reduce noise, cancel echoes, convert digital to analog, and modulate the external sound signal to obtain a driving signal to drive the speaker to make a sound.

[0077] In the test scenario of the power amplifier chip, when the power amplifier chip is in the working mode, the power amplifier chip can send the target interface test signal to the test device, and the test device can demodulate the target interface test signal into an interface test feedback signal, and determine whether the interface test feedback signal meets the third preset condition according to the frequency of the interface test feedback signal and the frequency of the external sound signal. The third preset condition can be that the difference between the frequency of the interface test feedback signal and the frequency of the external sound signal is less than the third preset difference.

[0078] The test device may determine whether the interface test feedback signal satisfies a fourth preset condition based on the amplitude of the interface test feedback signal and the amplitude of the external sound signal. The fourth preset condition may be that the difference between the amplitude of the interface test feedback signal and M times the amplitude of the external sound signal is less than a fourth preset difference, where M is any integer greater than or equal to 1.

[0079] When the test result of the power amplifier chip is qualified, the test device can determine the test result of the I2S interface 150 according to whether the interface test feedback signal satisfies the first preset condition and the second preset condition. For example, when the test result of the power amplifier chip is qualified, if the interface test feedback signal satisfies the first preset condition and the second preset condition, the test result of the I2S interface 150 is determined to be qualified. When the test result of the power amplifier chip is qualified, if the interface test feedback signal satisfies the first preset condition but does not satisfy the second preset condition, the test result of the I2S interface 150 is determined to be unqualified. When the test result of the power amplifier chip is qualified, if the interface test feedback signal satisfies the second preset condition but does not satisfy the first preset condition, the test result of the I2S interface 150 is determined to be unqualified.

[0080] In this way, in the test scenario of the power amplifier chip, the power amplifier chip can also be in the working mode, and the external sound signal is used as the test signal of the power amplifier chip. The power amplifier chip can process the external sound signal to obtain the target interface test signal. On the basis that the test result of the power amplifier chip is qualified, the test device can demodulate the target interface test signal to obtain an interface test feedback signal, and further determine the test result of the I2S interface 150 based on the interface test feedback signal and the external sound signal.

[0081] In some embodiments, Figure 3 As shown, the power amplifier chip also includes a multiplexer 160. The first input end of the multiplexer 160 is connected to the output end of the signal generating module 120, and the control end of the multiplexer 160 is connected to the signal output end of the internal register 110. The output end of the I2S interface 150 is connected to the second input end of the multiplexer 160, and the input end of the signal processing module 130 is connected to the output end of the multiplexer 160.

[0082] The internal register 110 is further configured to generate a test mode signal in the test mode and to generate a working mode signal in the working mode. The signal generating module 120 is further configured to generate an internal sound signal according to preset information in the working mode. The multiplexer 160 is configured to select to output the internal sound signal according to the test mode signal and to select to output the external sound signal according to the working mode signal.

[0083] Exemplarily, the test mode signal may be a high level signal, and the corresponding working mode signal may be a low level signal. Alternatively, the test mode signal may be a low level signal, and the corresponding working mode signal may be a high level signal.

[0084] When the user inputs a test mode instruction to the internal register 110 through the internal interface 140, the internal register 110 generates a test mode signal and transmits the test mode signal to the control end of the multiplexer 160. When the user inputs a work mode instruction to the internal register 110 through the internal interface 140, the internal register 110 generates a work mode signal and transmits the work mode signal to the control end of the multiplexer 160.

[0085] When the test mode is not configured in the internal register, inputting the working mode instruction can be understood as not inputting the test mode instruction. When the test mode is configured in the internal register, inputting the working mode instruction can be understood as clearing the test mode configured in the internal register.

[0086] The signal generation module 120 generates an internal sound signal in both the working mode and the test mode. In the working mode, the multiplexer 160 can simultaneously receive the external sound signal output by the I2S interface 150 and the internal sound signal generated by the signal generation module 120. In the test mode, if the I2S interface 150 is connected to the external sound signal, the multiplexer 160 will also simultaneously receive the external sound signal output by the I2S interface 150 and the internal sound signal generated by the signal generation module 120.

[0087] When the multiplexer 160 receives the test mode signal, it selects to output the internal sound signal and transmits the internal sound signal to the signal processing module 130. When the multiplexer 160 receives the working mode signal, it selects to output the external sound signal and transmits the external sound signal to the signal processing module 130.

[0088] In some embodiments, Figure 4 A schematic diagram of the structure of another power amplifier chip is provided for the embodiment of the present disclosure, such as Figure 4 As shown, the enable terminal of the signal generating module 120 is connected to the signal output terminal of the internal register 110 .

[0089] The internal register 110 is further configured to generate a test mode signal in the test mode and to generate a working mode signal in the working mode. The signal generating module 120 is further configured to generate an internal sound signal according to preset information under the action of the test mode signal. The signal generating module 120 is also configured not to generate an internal sound signal under the action of the working mode signal.

[0090] Exemplarily, when the user inputs a test mode instruction to the internal register 110 through the internal interface 140, the internal register 110 transmits the generated test mode signal to the enable terminal of the signal generating module 120. When the user inputs a working mode instruction to the internal register 110 through the I20C interface 140, the internal register 110 transmits the generated working mode signal to the enable terminal of the signal generating module 120.

[0091] When the test mode is not configured in the internal register, inputting the working mode instruction can be understood as not inputting the test mode instruction. When the test mode is configured in the internal register, inputting the working mode instruction can be understood as clearing the test mode configured in the internal register.

[0092] The test mode signal is an enable signal of the signal generating module 120, and the working mode signal is a disable signal of the signal generating module 120. Therefore, when the signal generating module 120 receives the test mode signal, it is enabled, that is, it can generate an internal sound signal according to the preset information, and when the signal generating module 120 receives the test mode signal, it is disabled, that is, it will not generate an internal sound signal.

[0093] The embodiments of the present disclosure also provide a method for testing a power amplifier chip, which is applied to any power amplifier chip provided in the embodiments of the present disclosure.

[0094] Figure 5 A flow chart of a method for testing a power amplifier chip provided by an embodiment of the present disclosure is shown as follows: Figure 5 As shown, the specific steps of the test method of the power amplifier chip include:

[0095] S101, switching to a test mode according to a test mode instruction sent by a test device.

[0096] For example, in a test scenario of a power amplifier chip, a user may input a test mode instruction to a test device, which may send the test mode instruction input by the user to an internal register of the power amplifier chip, and after receiving the test mode instruction, the internal register may switch the power amplifier chip to a test mode.

[0097] S102: Generate an internal sound signal according to preset information.

[0098] Exemplarily, the preset information includes a preset amplitude and / or a preset frequency, and the internal sound signal is a test signal of the power amplifier chip. The internal sound signal can be a sine signal, a cosine signal, a square wave signal, a ramp signal, etc., and the embodiment of the present disclosure only takes a sine signal as an example for exemplary description.

[0099] If the preset information includes the preset amplitude, the signal generation module of the power amplifier chip can generate the internal sound signal according to the preset amplitude. For example, the internal sound signal can be a sinusoidal signal with a preset amplitude and a default frequency, or a sinusoidal signal with a default frequency and an amplitude that has a specific relationship with the preset amplitude.

[0100] If the preset information includes a preset frequency, the signal generation module can generate an internal sound signal according to the preset frequency. For example, the internal sound signal can be a sinusoidal signal with a preset frequency and a default amplitude, or a sinusoidal signal with a default amplitude and a frequency having a specific relationship with the preset frequency.

[0101] If the preset information includes a preset amplitude and a preset frequency, the signal generation module can generate an internal sound signal according to the preset frequency and the preset amplitude. For example, the internal sound signal can be a sinusoidal signal with a preset amplitude and a preset frequency, or a sinusoidal signal with an amplitude that has a specific relationship with the preset amplitude and a frequency that has a specific relationship with the preset frequency.

[0102] S103, processing the internal sound signal to obtain a target test signal.

[0103] Exemplarily, in the test mode, the internal sound signal is used as the test signal of the power amplifier chip. The signal processing module of the power amplifier chip can filter, shape, reduce noise, cancel echo, perform digital-to-analog conversion and pulse width modulation on the internal sound signal to obtain a target test signal, and the target test signal is a pulse width modulated signal.

[0104] S104, sending the target test signal to the test device, so that the test device determines the test result of the power amplifier chip according to the target test signal.

[0105] For example, in a test scenario of a power amplifier chip, when the power amplifier chip is in a test mode, the pin of the power amplifier chip can send a target test signal to a test device. The test device includes a peripheral circuit of the power amplifier chip, and the test device can demodulate the target test signal into Figure 2 The test feedback signal is shown.

[0106] The power amplifier chip can also send the internal sound signal to the test device, and the test device can determine whether the test feedback signal meets the first preset condition according to the frequency of the test feedback signal and the frequency of the internal sound signal. The first preset condition can be that the difference between the frequency of the test feedback signal and the frequency of the internal sound signal is less than the first preset difference.

[0107] The test device can determine whether the test feedback signal satisfies a second preset condition based on the amplitude of the test feedback signal and the amplitude of the internal sound signal. The second preset condition can be that the difference between the amplitude of the test feedback signal and N times the amplitude of the internal sound signal is less than a second preset difference, where N is any integer greater than or equal to 1.

[0108] The test device can also determine the test result of the power amplifier chip according to whether the test feedback signal meets the first preset condition and the second preset condition. For example, if the test feedback signal meets the first preset condition and the second preset condition, the test result of the power amplifier chip is determined to be qualified. If the test feedback signal meets the first preset condition but does not meet the second preset condition, the test result of the power amplifier chip is determined to be unqualified. If the test feedback signal meets the second preset condition but does not meet the first preset condition, the test result of the power amplifier chip is determined to be unqualified.

[0109] In this way, in the test scenario of the power amplifier chip, the test device can instruct the power amplifier chip to switch to the test mode. After the power amplifier chip switches to the test mode, an internal sound signal can be generated according to the preset information. The internal sound signal is used as the test signal of the power amplifier chip. The power amplifier chip can also process the internal sound signal to obtain a target test signal. The test device can demodulate the target test signal to obtain a test feedback signal, and determine the test result of the power amplifier chip based on the test feedback signal and the internal sound signal.

[0110] In the disclosed embodiment, the test mode is switched to according to the test mode instruction sent by the test device, an internal sound signal is generated according to preset information, the internal sound signal is a test signal of the power amplifier chip, the internal sound signal is processed to obtain a target test signal, and the target test signal is sent to the test device, so that the test device determines the test result of the power amplifier chip according to the target test signal. In this way, when testing the power amplifier chip, the power amplifier chip itself can generate an internal sound signal for testing, without the need for an external sound source generator, thereby expanding the test scenario of the power amplifier chip.

[0111] In some embodiments, Figure 6 A flow chart of another power amplifier chip testing method provided for the implementation of the present disclosure is provided. Figure 6 for Figure 5 Based on the embodiment shown, the test method of the power amplifier chip also includes:

[0112] S105, switching to working mode.

[0113] Exemplarily, the power amplifier chip is connected to an external sound signal in the working mode. For example, when the power amplifier chip is in the working mode, the external sound source device transmits the external sound signal to the I2S interface through the I2S bus.

[0114] In the test scenario of the power amplifier chip, the user can also input a command to clear the test mode command, that is, a working mode command, to the test device. The test device can send the working mode command input by the user to the internal register, and the internal register clears the test mode configured in the internal register after receiving the working mode command, so as to switch the power amplifier chip from the test mode to the working mode.

[0115] S106, processing the external sound signal to obtain a target interface test signal.

[0116] Exemplarily, in the test scenario of a power amplifier chip, an external sound signal is used as a test signal of the power amplifier chip, and the signal processing module can filter, shape, reduce noise, cancel echoes, perform digital-to-analog conversion, and pulse width modulation on the external sound signal to obtain a target interface test signal.

[0117] In the normal use scenario of the power amplifier chip, the external sound signal is used as the signal to be amplified and output. The signal processing module 130 can filter, shape, reduce noise, cancel echoes, perform digital-to-analog conversion and pulse width modulation on the external sound signal to obtain a driving signal to drive the speaker to make sound.

[0118] S107, sending the target interface test signal to the test device, so that the test device determines the test result of the I2S interface according to the target interface test signal.

[0119] Exemplarily, in a test scenario of a power amplifier chip, when the power amplifier chip is in working mode, the power amplifier chip can send a target interface test signal to a test device. The test device can demodulate the target interface test signal into an interface test feedback signal, and determine whether the interface test feedback signal meets a third preset condition based on the frequency of the interface test feedback signal and the frequency of the external sound signal. The third preset condition can be that the difference between the frequency of the interface test feedback signal and the frequency of the external sound signal is less than a third preset difference.

[0120] The test device may determine whether the interface test feedback signal satisfies a fourth preset condition based on the amplitude of the interface test feedback signal and the amplitude of the external sound signal. The fourth preset condition may be that the difference between the amplitude of the interface test feedback signal and M times the amplitude of the external sound signal is less than a fourth preset difference, where M is any integer greater than or equal to 1.

[0121] When the test result of the power amplifier chip is qualified, the test device can determine the test result of the I2S interface according to whether the interface test feedback signal satisfies the first preset condition and the second preset condition. For example, when the test result of the power amplifier chip is qualified, if the interface test feedback signal satisfies the first preset condition and the second preset condition, the test result of the I2S interface is determined to be qualified. When the test result of the power amplifier chip is qualified, if the interface test feedback signal satisfies the first preset condition but does not satisfy the second preset condition, the test result of the I2S interface is determined to be unqualified. When the test result of the power amplifier chip is qualified, if the interface test feedback signal satisfies the second preset condition but does not satisfy the first preset condition, the test result of the I2S interface is determined to be unqualified.

[0122] In this way, in the test scenario of the power amplifier chip, the test device can instruct the power amplifier chip to switch from the test mode to the working mode. After the power amplifier chip switches to the working mode, the external sound signal is used as the test signal of the power amplifier chip, and the power amplifier chip can process the external sound signal to obtain the target interface test signal. On the basis that the test result of the power amplifier chip is qualified, the test device can demodulate the target interface test signal to obtain the interface test feedback signal, and further determine the test result of the I2S interface based on the interface test feedback signal and the external sound signal.

[0123] In some embodiments, a test mode signal is generated before executing S102 .

[0124] Exemplarily, the test mode signal may be a high level signal, or may be a low level signal. When the user inputs a test mode instruction to the internal register 110 through the internal interface, the internal register generates a test mode signal.

[0125] In some embodiments, a specific description of a possible implementation method when performing S102 is as follows:

[0126] Under the action of the test mode signal, an internal sound signal is generated according to preset information.

[0127] Exemplarily, the test mode signal generated by the internal register is input to the enable terminal of the signal generation module. Since the test mode signal is the enable signal of the signal generation module, the signal generation module is enabled after receiving the test mode signal, that is, the internal sound signal is generated according to the preset information.

[0128] In some embodiments, before executing S103 , the internal sound signal is selected to be output according to the test mode signal.

[0129] Exemplarily, the test mode signal generated by the internal register is input to the control end of the multiplexer. The multiplexer selects to output the internal sound signal according to the received test mode signal, and outputs the internal sound signal to the signal processing module.

[0130] In some embodiments, a working mode signal is generated before executing S106 .

[0131] Exemplarily, the working mode signal may be a low level signal or a high level signal. For example, when the test mode signal is a high level signal, the working mode signal is a low level signal; when the test mode signal is a low level signal, the working mode signal is a high level signal.

[0132] When the user inputs an operating mode instruction to the internal register through the internal interface, the internal register generates an operating mode signal.

[0133] In some embodiments, no internal sound signal is generated under the action of the working mode signal before executing S106.

[0134] Exemplarily, the working mode signal generated by the internal register is input to the enable terminal of the signal generating module. Since the working mode signal is a disabling signal of the signal generating module, the signal generating module is disabled after receiving the test mode signal, that is, no internal sound signal is generated.

[0135] In some other embodiments, before executing S106 , an internal sound signal is generated according to preset information, and an external sound signal is output according to the working mode signal.

[0136] Exemplarily, in the working mode, the signal generating module also generates an internal sound signal, and the multiplexer can receive the external sound signal and the internal sound signal at the same time. The working mode signal generated by the internal register is input to the control end of the multiplexer, and the multiplexer selects to output the external sound signal according to the received working mode signal, and outputs the external sound signal to the signal processing module.

[0137] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0138] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present application.

[0139] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A power amplifier chip, characterized in that: include: Internal registers, signal generation modules and signal processing modules; The internal register is configured to provide preset information to the signal generating module, wherein the preset information includes a preset frequency and / or a preset amplitude; The signal generating module is configured to generate an internal sound signal according to the preset information in a test mode, wherein the internal sound signal is a test signal of the power amplifier chip; The signal processing module is configured to process the internal sound signal in the test mode to obtain a target test signal; wherein the target test signal is used to determine a test result of the power amplifier chip.

2. The power amplifier chip according to claim 1, characterized in that: The power amplifier chip also includes an I2S interface; The input end of the I2S interface is connected to the I2S bus, the output end of the I2S interface is connected to the input end of the signal processing module and the output end of the signal generating module, and the output end of the signal processing module is connected to the output end of the power amplifier chip; The I2S interface is configured to connect an external sound signal in working mode; The signal processing module is further configured to process the external sound signal in the working mode.

3. The power amplifier chip according to claim 2, characterized in that: The enable terminal of the signal generating module is connected to the signal output terminal of the internal register; The internal register is further configured to generate a test mode signal in the test mode and to generate an operating mode signal in the operating mode; The signal generating module is further configured to generate the internal sound signal according to the preset information under the effect of the test mode signal; The signal generating module is further configured to not generate the internal sound signal under the action of the working mode signal.

4. The power amplifier chip according to claim 2, characterized in that: The power amplifier chip also includes a multiplexer; The first input end of the multiplexer is connected to the output end of the signal generating module, and the control end of the multiplexer is connected to the signal output end of the internal register; the output end of the I2S interface is connected to the second input end of the multiplexer, and the input end of the signal processing module is connected to the output end of the multiplexer; The internal register is further configured to generate a test mode signal in the test mode and to generate an operating mode signal in the operating mode; The signal generating module is further configured to generate the internal sound signal according to the preset information in the working mode; The multiplexer is configured to select and output the internal sound signal according to the test mode signal, and to select and output the external sound signal according to the working mode signal.

5. The power amplifier chip according to any one of claims 1 to 4, characterized in that: The amplitude output terminal of the internal register is connected to the amplitude input terminal of the signal generating module, and the frequency output terminal of the internal register is connected to the frequency input terminal of the signal generating module; The signal generating module is further configured to generate the internal sound signal according to the preset amplitude and the preset frequency.

6. The power amplifier chip according to any one of claims 1 to 4, characterized in that: The power amplifier chip also includes an internal interface; The first input / output terminal of the internal interface is connected to the bus, and the second input / output terminal of the internal interface is connected to the input / output terminal of the internal register; The internal interface is configured to configure the preset information and the test mode to the internal register.

7. A method for testing a power amplifier chip, characterized in that: Applied to the power amplifier chip according to any one of claims 1 to 6, the method comprises: Switching to the test mode according to the test mode instruction sent by the test device; Generate an internal sound signal according to preset information, wherein the preset information includes a preset amplitude and / or a preset frequency, and the internal sound signal is a test signal of the power amplifier chip; Processing the internal sound signal to obtain a target test signal; The target test signal is sent to the test device, so that the test device determines the test result of the power amplifier chip according to the target test signal.

8. The method according to claim 7, characterized in that The method further comprises: Switching to a working mode, in which the power amplifier chip is connected to an external sound signal; Processing the external sound signal to obtain a target interface test signal; The target interface test signal is sent to the test device, so that the test device determines the test result of the I2S interface according to the target interface test signal.

9. The method according to claim 8, characterized in that Before the preset information generates the internal sound signal, the method further includes: generating a test mode signal; The preset information generating the internal sound signal comprises: Under the effect of the test mode signal, generating the internal sound signal according to the preset information; Before the external sound signal is processed to obtain the target interface test signal, the method further includes: generating a working mode signal; Under the effect of the working mode signal, the internal sound signal is not generated.

10. The method according to claim 8, characterized in that Before the preset information generates the internal sound signal, the method further includes: generating a test mode signal; Before the internal sound signal is processed to obtain the target test signal, the method further includes: Selecting to output the internal sound signal according to the test mode signal; Before the external sound signal is processed to obtain the target interface test signal, the method further includes: generating a working mode signal; generating the internal sound signal according to the preset information; The external sound signal is selected to be output according to the working mode signal.

Images