Semiconductor device and manufacturing method thereof, and electronic device

Abstract

The embodiments of the present application provide a semiconductor device, a method for manufacturing the same, and an electronic device. The semiconductor device includes: a substrate, a dielectric layer, a first conductive layer, a second conductive layer, a first isolation layer, and / or a second isolation layer. The material of the dielectric layer includes oxygen atoms and first metal atoms; the material of the first isolation layer includes oxygen atoms and second metal atoms, and the bond energy between the second metal atoms and the oxygen atoms is less than the bond energy between the first metal atoms and the oxygen atoms; the material of the second isolation layer includes oxygen atoms and third metal atoms, and the bond energy between the third metal atoms and the oxygen atoms is less than the bond energy between the first metal atoms and the oxygen atoms. The isolation layer of the embodiment of the present application is formed of a metal oxide material, which can not only isolate the conductive layer and the dielectric layer but also provide oxygen to the dielectric layer, which helps to reduce the amount of oxygen vacancies in the dielectric layer, thereby improving the performance of the semiconductor device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology. Specifically, the present application relates to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] Memory is a component used to store programs and various data. Capacitors are widely used in integrated circuits for memory devices, such as dynamic random access memory (DRAM) and ferroelectric random access memory (FeRAM), due to their voltage regulation and filtering capabilities.

[0003] Dynamic random access memory (DRAM) is a common memory device with high integration, fast read / write speeds, and low cost. It is widely used in various consumer electronic products such as computers and mobile phones. Ferroelectric random access memory (FeRAM) has attracted widespread attention from academia and industry due to its advantages such as fast read / write speeds, low power consumption, high integration potential, and non-volatility. It is considered one of the most promising new memory technologies in the post-Moore era.

[0004] With the miniaturization of memory devices and the improvement of market performance requirements for memory devices, new challenges have been posed to the structure, performance and process of semiconductor devices such as capacitors and transistors. Summary of the Invention

[0005] The present application proposes a semiconductor device, a manufacturing method thereof, and an electronic device, wherein the isolation layer is formed of a metal oxide material and can isolate the conductive layer and the dielectric layer. In the present application, the isolation layer can not only prevent the surface of the first conductive layer from being oxidized to form an interface layer, but also inhibit the first conductive layer and the second conductive layer from absorbing oxygen from the dielectric layer. At the same time, it can also provide oxygen to the dielectric layer, which helps to inhibit the formation of more oxygen vacancies in the dielectric layer, thereby improving the performance of the semiconductor device.

[0006] In a first aspect, an embodiment of the present application provides a semiconductor device, comprising:

[0007] substrate;

[0008] a dielectric layer, located on one side of the substrate, wherein the material of the dielectric layer includes oxygen atoms and first metal atoms;

[0009] a first conductive layer, located on a side of the dielectric layer close to the substrate;

[0010] a second conductive layer located on a side of the dielectric layer away from the substrate, wherein an orthographic projection of the second conductive layer on the substrate overlaps with an orthographic projection of the first conductive layer on the substrate; and

[0011] a first isolation layer, located between the first conductive layer and the dielectric layer and in contact with the dielectric layer, wherein the material of the first isolation layer includes oxygen atoms and second metal atoms, and the bond energy between the second metal atoms and the oxygen atoms is smaller than the bond energy between the first metal atoms and the oxygen atoms; and / or

[0012] The second isolation layer is located between the dielectric layer and the second conductive layer and contacts the dielectric layer. The material of the second isolation layer includes oxygen atoms and third metal atoms. The bond energy between the third metal atoms and the oxygen atoms is smaller than the bond energy between the first metal atoms and the oxygen atoms.

[0013] In some optional embodiments of the present application, the first isolation layer is conductive; and / or the second isolation layer is conductive.

[0014] In some optional embodiments of the present application, the metal element in the material of the first isolation layer includes at least one of indium, zinc, tin, cadmium, antimony, and gallium; and / or,

[0015] The metal element in the material of the second isolation layer includes at least one of indium, zinc, tin, cadmium, antimony, and gallium.

[0016] In some optional embodiments of the present application, the material of the first isolation layer includes InO, ZnO, ZnSnO, CdSbO, InGaO, InZnO, InSnO, In2O3, SnO2, Ga2O3, Zn2In2O5, In4Sn3O 12 、GaInO3、In4Sn3O 12 , ZnSnO3; and / or,

[0017] The material of the second isolation layer includes InO, ZnO, ZnSnO, CdSbO, InGaO, InZnO, InSnO, In2O3, SnO2, Ga2O3, Zn2In2O5, In4Sn3O 12 、GaInO3、In4Sn3O 12 , at least one of ZnSnO3.

[0018] In some optional embodiments of the present application, the material of the dielectric layer includes a ferroelectric material, the ferroelectric material includes doped hafnium oxide, and the doping element includes at least one of Zr, Si, Y, Al, La, and Gd.

[0019] In some optional embodiments of the present application, the semiconductor device is a capacitor, and the first conductive layer and the second conductive layer are two electrodes of the capacitor respectively;

[0020] The first isolation layer, the dielectric layer and the second isolation layer are sequentially formed between the first conductive layer and the second conductive layer in a direction away from the substrate. The side of the first isolation layer away from the dielectric layer contacts the first conductive layer, and the side of the second isolation layer away from the dielectric layer contacts the second conductive layer.

[0021] In some optional embodiments of the present application, the material of the dielectric layer includes a ferroelectric material or a dielectric material.

[0022] In some optional embodiments of the present application, the semiconductor device is a transistor.

[0023] The first conductive layer is a channel layer of the transistor, and the second conductive layer is a gate of the transistor;

[0024] The dielectric layer is the gate insulating layer of the transistor;

[0025] The second isolation layer is located between the gate and the gate insulating layer.

[0026] In some optional embodiments of the present application, the dielectric layer is a doped hafnium oxide layer, and the second isolation layer is an indium tin oxide layer.

[0027] In a second aspect, an embodiment of the present application provides an electronic device, including: the above-mentioned semiconductor device.

[0028] In a third aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, comprising:

[0029] providing a substrate;

[0030] forming a first conductive layer;

[0031] forming a metal oxide layer comprising oxygen atoms and first metal atoms on one side of the substrate as a dielectric layer, wherein the dielectric layer covers at least a portion of the first conductive layer;

[0032] forming a second conductive layer on a side of the dielectric layer away from the first conductive layer, wherein an orthographic projection of the second conductive layer on the substrate overlaps with an orthographic projection of the first conductive layer on the substrate;

[0033] Perform annealing treatment;

[0034] in:

[0035] After forming the first conductive layer and before forming the dielectric layer, the method for manufacturing a semiconductor device further includes: forming a metal oxide layer comprising oxygen atoms and second metal atoms on one side of the first conductive layer as a first isolation layer, wherein the first isolation layer is in contact with the dielectric layer, and the bond energy between the second metal atoms and the oxygen atoms is smaller than the bond energy between the first metal atoms and the oxygen atoms; and / or,

[0036] After forming the dielectric layer and before forming the second conductive layer, the method for manufacturing the semiconductor device further includes: forming a metal oxide layer comprising oxygen atoms and a third metal atom on a side of the dielectric layer away from the substrate to serve as a second isolation layer, the second isolation layer being in contact with the dielectric layer, and the bond energy between the third metal atom and the oxygen atom being less than the bond energy between the first metal atom and the oxygen atom.

[0037] In some optional embodiments of the present application, the semiconductor device is a capacitor.

[0038] Forming a first conductive layer includes: depositing a metal layer on one side of the substrate to serve as the first conductive layer, the first conductive layer being one of the two electrodes of the capacitor;

[0039] Forming the first isolation layer includes: depositing a first metal oxide layer having conductivity on a side of the first conductive layer away from the substrate to serve as the first isolation layer, wherein the first isolation layer contacts the first conductive layer;

[0040] Forming a dielectric layer includes: depositing a ferroelectric material or a non-ferroelectric dielectric material on a side of the first isolation layer away from the substrate to serve as the dielectric layer;

[0041] Forming the second isolation layer includes: depositing a second conductive metal oxide layer on a side of the dielectric layer away from the substrate to serve as the second isolation layer;

[0042] The second conductive layer is formed, including: depositing a metal layer on a side of the second isolation layer away from the substrate to serve as the second conductive layer, wherein the second conductive layer contacts the second isolation layer and serves as the other electrode of the capacitor.

[0043] In some optional embodiments of the present application, the semiconductor device is a transistor, the substrate is a silicon substrate,

[0044] Forming a first conductive layer includes: processing a silicon substrate through a doping process to form a first conductive layer in a partial area of ​​the silicon substrate, wherein the first conductive layer is a channel layer of the transistor;

[0045] Forming a dielectric layer includes: depositing a ferroelectric material on one side of the substrate to serve as a dielectric layer, wherein the dielectric layer contacts the channel layer and serves as a gate insulating layer of the transistor;

[0046] Forming the second isolation layer includes: depositing a second conductive metal oxide layer on a side of the dielectric layer away from the substrate to serve as the second isolation layer;

[0047] The second conductive layer is formed, including: depositing a metal layer on a side of the second isolation layer away from the substrate to form a second conductive layer, wherein the second conductive layer contacts the second isolation layer and serves as a gate of the transistor.

[0048] The isolation layer of the embodiment of the present application is formed of a metal oxide material, which can not only isolate the conductive layer and the dielectric layer to prevent the conductive layer from being oxidized by the dielectric layer, but also provide oxygen to the dielectric layer, which helps to reduce oxygen vacancies in the dielectric layer, thereby improving the performance of the semiconductor device.

[0049] Additional aspects and advantages of the present application will be given in part in the following description, which will become apparent from the following description, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0051] Figure 1 A flowchart of a specific example of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0052] Figures 2 to 6 A schematic structural diagram of different processes in a specific example of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0053] Figure 7 A flowchart of another specific example of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0054] Figure 8 A flowchart of another specific example of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0055] Figures 9 to 12 This is a structural schematic diagram of different processes in another specific example of a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0056] Reference numerals:

[0057] 100 - semiconductor device; 10 - substrate; 21 - first conductive layer; 22 - dielectric layer; 23 - second conductive layer; 24 - first isolation layer; 25 - second isolation layer; 26 - first electrode; 27 - second electrode; 28 - channel layer; 29 - gate; 30 - capacitor; 31 - first electrode; 32 - second electrode. DETAILED DESCRIPTION

[0058] The following describes the embodiments of the present application in conjunction with the accompanying drawings. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0059] Those skilled in the art will understand that, unless otherwise stated, the singular forms "a," "an," "said," and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of this application refers to the presence of the described features, integers, steps, operations, elements, and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the technical field. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may refer to the element and the other element establishing a connection relationship through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A," or as "B," or as "A and B."

[0060] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0061] The following describes the relevant technologies:

[0062] As dynamic random access memory (DRAM) shrinks, its capacitors need to meet the requirements of high capacitance and low leakage at the same time, and the selection of dielectric materials becomes particularly critical. The ideal dielectric material needs to meet the requirements of high dielectric constant (k>100), low leakage (<10e -7 A / cm 2 ), with a physical thickness of less than 10nm. However, when depositing dielectric material on the metal bottom electrode, the oxygen source introduced will cause oxidation on the metal bottom electrode surface, forming an interface layer. The interface layer of the dielectric capacitor will affect the quality of the dielectric film, thereby affecting the capacitor performance, such as leakage current and dielectric constant.

[0063] Hafnium oxide (HfO2)-based ferroelectric memory devices (such as ferroelectric field-effect transistors (FeFETs) and ferroelectric random access memories (FeRAMs)) have attracted widespread attention from academia and industry due to their fast read / write speeds, low power consumption, high integration potential, and non-volatility. They are considered one of the most promising new memory devices in the post-Moore era. However, these devices face numerous challenges. One of these challenges is that when depositing the ferroelectric layer on the metal bottom electrode, the oxygen source introduced causes oxidation on the metal bottom electrode surface, forming an interfacial layer. This interfacial layer in the ferroelectric capacitor induces lattice dislocations in the subsequently grown ferroelectric layer, increasing defects and generating a depolarization field. This intensifies charge injection into the ferroelectric layer, thereby affecting the performance of the ferroelectric memory device (such as fatigue and retention characteristics).

[0064] Therefore, for memory devices (such as the 1T1C structure, where the memory cell includes a transistor and a capacitor), both dielectric capacitors and ferroelectric capacitors have an interface layer problem. That is, when depositing the dielectric layer of the capacitor (such as the dielectric layer or the ferroelectric layer), the oxygen source introduced will cause the surface of the metal lower electrode to oxidize, forming an interface layer, which will seriously affect the performance of the device.

[0065] In addition, for memory devices, whether they are dielectric capacitors or ferroelectric capacitors, their electrode materials are usually oxygen-affinity metal materials. During the annealing process to form a high dielectric constant phase (dielectric capacitor) or a ferroelectric phase (such as FeRAM or FeFET), or during the subsequent use of the device, oxygen atoms in the dielectric layer (dielectric capacitor) or the ferroelectric layer (such as FeRAM or FeFET) will be absorbed by the metal electrode, causing the oxygen atoms to diffuse to the interface between the metal electrode and the dielectric layer (or the interface between the metal electrode and the ferroelectric layer), or even diffuse into the interior of the metal electrode, causing an increase in oxygen vacancies in the dielectric layer (or ferroelectric layer), and ultimately leading to device performance degradation.

[0066] The semiconductor device, manufacturing method thereof, and electronic device provided in this application are intended to solve at least one of the above technical problems in the prior art.

[0067] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments. It should be noted that the following embodiments can refer to, draw on, or combine with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0068] like Figures 1 to 12 As shown, the embodiment of the present application provides a semiconductor device and a method for manufacturing the same, wherein: Figure 1 、 Figure 7 and Figure 8 Flowcharts of different specific examples of a method for manufacturing a semiconductor device provided in an embodiment of the present application are respectively shown. Figures 2 to 6 Shown Figure 1 The schematic diagram of the structure of the semiconductor device in different processes in the manufacturing method shown is as follows, Figures 9 to 12 Shown Figure 8 The schematic diagram of the structure of the semiconductor device in different processes in the manufacturing method shown is as follows, Figure 6 and Figure 12 Schematic diagrams of the structure of different specific examples of a semiconductor device provided by the embodiment of the present application are shown respectively. Figure 6 and Figure 12As shown, the semiconductor device 100 includes: a substrate 10, a dielectric layer 22, a first conductive layer 21 and a second conductive layer 23. The dielectric layer 22 is located on one side of the substrate 10, and the material of the dielectric layer 22 includes oxygen atoms and first metal atoms; the first conductive layer 21 is located on the side of the dielectric layer 22 close to the substrate 10; the second conductive layer 23 is located on the side of the dielectric layer 22 away from the substrate 10, and the orthographic projection of the second conductive layer 23 on the substrate 10 overlaps with the orthographic projection of the first conductive layer 21 on the substrate 10.

[0069] The semiconductor device 100 further includes: a first isolation layer 24 and a second isolation layer 25. The first isolation layer 24 is located between the first conductive layer 21 and the dielectric layer 22 and contacts the dielectric layer 22. The material of the first isolation layer 24 includes oxygen atoms and second metal atoms. The bond energy between the second metal atoms and the oxygen atoms is smaller than the bond energy between the first metal atoms and the oxygen atoms. The second isolation layer 25 is located between the dielectric layer 22 and the second conductive layer 23 and contacts the dielectric layer 22. The material of the second isolation layer 25 includes oxygen atoms and third metal atoms. The bond energy between the third metal atoms and the oxygen atoms is smaller than the bond energy between the first metal atoms and the oxygen atoms.

[0070] Bond energy is a physical quantity that characterizes the strength of a chemical bond. It can be measured by the energy required to break the bond, and the energy unit can be kJ / mol.

[0071] In the embodiment of the present application, the substrate 10 supports the dielectric layer 22 , the first conductive layer 21 , the second conductive layer 23 , the first isolation layer 24 and the second isolation layer 25 .

[0072] In the embodiment of the present application, the material of the dielectric layer 22 includes oxygen atoms and first metal atoms, and the material of the first isolation layer 24 includes oxygen atoms and second metal atoms. By arranging a metal oxide layer (i.e., the first isolation layer 24) between the first conductive layer 21 and the dielectric layer 22, not only can the first conductive layer 21 and the dielectric layer 22 be isolated, but also the surface of the first conductive layer 21 is prevented from being oxidized to form an interface layer during the formation of the dielectric layer 22, so that no interface layer is formed on the surface of the first conductive layer 21 facing the dielectric layer 22, thereby solving the problems of the interface layer of the dielectric capacitor affecting the capacitance performance in the prior art, and solving the problem of the interface layer of the ferroelectric capacitor affecting the ferroelectric capacitor in the prior art. The performance problem of the semiconductor device (such as fatigue characteristics and retention characteristics) can be solved; the first conductive layer 21 and the dielectric layer 22 are not in direct contact, the first conductive layer 21 is inhibited from absorbing oxygen from the dielectric layer 22, and the formation of oxygen vacancies in the dielectric layer 22 is inhibited, which solves the problem in the prior art that oxygen atoms in the dielectric layer or ferroelectric layer diffuse to the metal electrode, causing an increase in oxygen vacancies in the dielectric layer or ferroelectric layer, resulting in degradation of device performance; at the same time, since the first isolation layer 24 is in contact with the dielectric layer 22, oxygen can be provided to the dielectric layer 22 and oxygen vacancies in the dielectric layer 22 can be reduced, providing space for making a thinner dielectric layer (such as a dielectric layer or ferroelectric layer) to avoid the dielectric layer being too thin and being punctured.

[0073] In the embodiment of the present application, the material of the second isolation layer 25 includes oxygen atoms and third metal atoms. By arranging a metal oxide layer (i.e., the second isolation layer 25) between the dielectric layer 22 and the second conductive layer 23, not only can the dielectric layer 22 and the second conductive layer 23 be isolated, so that the dielectric layer 22 and the second conductive layer 23 are not in direct contact, but also the second conductive layer 23 is inhibited from absorbing oxygen from the dielectric layer 22, and the formation of oxygen vacancies in the dielectric layer 22 is inhibited, thereby solving the problem in the prior art that oxygen atoms in the dielectric layer or ferroelectric layer diffuse to the metal electrode, causing an increase in oxygen vacancies in the dielectric layer or ferroelectric layer, resulting in degradation of device performance; at the same time, since the second isolation layer 25 is in contact with the dielectric layer 22, it can provide oxygen to the dielectric layer 22 and reduce oxygen vacancies in the dielectric layer 22, providing space for the production of thinner dielectric layers (such as dielectric layers or ferroelectric layers), thereby preventing the dielectric layer from being too thin and being punctured.

[0074] In the embodiment of the present application, by providing a first isolation layer 24 between the first conductive layer 21 and the dielectric layer 22 , and providing a second isolation layer 25 between the dielectric layer 22 and the second conductive layer 23 , the performance of the semiconductor device can be improved.

[0075] In the embodiment of the present application, the first isolation layer 24 is in contact with the dielectric layer 22, and the bond energy between the second metal atoms and the oxygen atoms is less than the bond energy between the first metal atoms and the oxygen atoms. The oxygen atoms in the first isolation layer 24 can easily diffuse into the dielectric layer 22 to provide oxygen for the dielectric layer 22, filling some of the oxygen vacancies in the dielectric layer 22, thereby helping to reduce the oxygen vacancies in the dielectric layer 22, providing space for making a thinner dielectric layer, avoiding the dielectric layer being too thin and being punctured, and further improving the performance and reliability of the semiconductor device.

[0076] In the embodiment of the present application, the second isolation layer 25 is in contact with the dielectric layer 22, and the bond energy between the third metal atoms and the oxygen atoms is less than the bond energy between the first metal atoms and the oxygen atoms. The oxygen atoms in the second isolation layer 25 can easily diffuse into the dielectric layer 22 to provide oxygen for the dielectric layer 22, filling some of the oxygen vacancies in the dielectric layer 22, thereby helping to reduce the oxygen vacancies in the dielectric layer 22, providing space for making a thinner dielectric layer, avoiding the dielectric layer being too thin and being punctured, and further improving the performance and reliability of the semiconductor device.

[0077] Optionally, the material of the substrate 10 includes but is not limited to Si, SiGex, etc.

[0078] In some optional embodiments of the present application, the first isolation layer 24 is conductive; the second isolation layer 25 is conductive.

[0079] In the embodiment of the present application, the first conductive layer 21, the dielectric layer 22, and the second conductive layer 23 are arranged in sequence, and the orthographic projection of the second conductive layer 23 on the substrate 10 overlaps with the orthographic projection of the first conductive layer 21 on the substrate 10. The first isolation layer 24 is located between the first conductive layer 21 and the dielectric layer 22. The first isolation layer 24 is conductive, and the first conductive layer 21 and the first isolation layer 24 form a first electrode 31. The second isolation layer 25 is located between the dielectric layer 22 and the second conductive layer 23. The second isolation layer 25 is conductive, and the second isolation layer 25 and the second conductive layer 23 form a second electrode 32. The first electrode 31, the dielectric layer 22, and the second electrode 32 form a capacitor 30.

[0080] In the embodiment of the present application, the first conductive layer 21 is configured to form the first electrode 31 together with the first isolation layer 24, the second isolation layer 25 is configured to form the second electrode 32 together with the second conductive layer 23, the dielectric layer 22 forms the insulating medium of the capacitor 30, and neither the first isolation layer 24 nor the second isolation layer 25 is configured to form the insulating medium of the capacitor together with the dielectric layer 22. In this way, the thickness between the first electrode 31 and the second electrode 32 can be characterized by the thickness of the dielectric layer 22, thereby avoiding the problem of increasing the thickness of the insulating medium and reducing the capacitance of the capacitor by configuring the first isolation layer 24 and / or the second isolation layer 25 as the insulating medium of the capacitor together with the dielectric layer 22, and the technical problem of causing the polarization strength of the ferroelectric layer to degrade. Through this configuration, the thickness of the insulating medium of the capacitor can be reduced, that is, the distance between the first electrode and the second electrode of the capacitor is reduced, which can increase the capacitance of the capacitor and prevent the polarization strength of the ferroelectric layer from degrading.

[0081] In the embodiment of the present application, the dielectric layer 22 is an insulating medium, so that there is no electrical conduction between the first electrode 31 and the second electrode 32 .

[0082] Of course, in some optional embodiments of the present application, according to actual needs, the semiconductor device 100 may also include only the first isolation layer 24. In this case, the first conductive layer 21 and the first isolation layer 24 form the first electrode 31, and the second conductive layer 23 forms the second electrode 32; or, the semiconductor device 100 may also include only the second isolation layer 25. In this case, the first conductive layer 21 forms the first electrode 31, and the second isolation layer 25 and the second conductive layer 23 form the second electrode 32.

[0083] Of course, in other optional embodiments of the present application, only the first isolation layer 24 may be made conductive, or only the second isolation layer 25 may be made conductive, according to actual needs.

[0084] In some optional embodiments of the present application, the metal element in the material of the first isolation layer 24 includes at least one of indium In, zinc Zn, tin Sn, cadmium Cd, antimony Sb, and gallium Ga.

[0085] In some optional embodiments of the present application, the metal element in the material of the second isolation layer 25 includes at least one of indium In, zinc Zn, tin Sn, cadmium Cd, antimony Sb, and gallium Ga.

[0086] In some optional embodiments of the present application, the material of the first isolation layer 24 includes InO, ZnO, ZnSnO, CdSbO, InGaO, InZnO, InSnO, In2O3, SnO2, Ga2O3, Zn2In2O5, In4Sn3O 12 、GaInO3、In4Sn3O12 , at least one of ZnSnO3.

[0087] Optionally, in the embodiment of the present application, the ratio of each component in the material of the first isolation layer 24 can be the same (for example, 1:1:1) or different, and the ratio of each component can be selectively set according to actual needs.

[0088] In some optional embodiments of the present application, the material of the second isolation layer 25 includes InO, ZnO, ZnSnO, CdSbO, InGaO, InZnO, InSnO, In2O3, SnO2, Ga2O3, Zn2In2O5, In4Sn3O 12 、GaInO3、In4Sn3O 12 , at least one of ZnSnO3.

[0089] Optionally, in the embodiment of the present application, the ratio of each component in the material of the second isolation layer 25 can be the same (for example, 1:1:1) or different, and the ratio of each component can be selectively set according to actual needs.

[0090] In a specific embodiment of the present application, Figure 6 As shown, the first conductive layer 21 is a metal electrode layer, and the first conductive layer 21 is located on one side of the substrate 10 ; the second conductive layer 23 is a metal electrode layer, and the second conductive layer 23 is located on a side of the first conductive layer 21 away from the substrate 10 .

[0091] In a specific embodiment of the present application, Figure 6 As shown, the semiconductor device 100 is a capacitor, and the first conductive layer 21 and the second conductive layer 23 are two electrodes of the capacitor respectively; the first isolation layer 24, the dielectric layer 22 and the second isolation layer 25 are sequentially formed between the first conductive layer 21 and the second conductive layer 23 in a direction away from the substrate 10, and the side of the first isolation layer 24 away from the dielectric layer 22 is in contact with the first conductive layer 21, and the side of the second isolation layer 25 away from the dielectric layer 22 is in contact with the second conductive layer 23.

[0092] In the embodiment of the present application, the semiconductor device 100 includes a first isolation layer 24 and a second isolation layer 25. In a direction away from the substrate 10, the first conductive layer 21, the first isolation layer 24, the dielectric layer 22, the second isolation layer 25, and the second conductive layer 23 are sequentially arranged in contact with each other. The first conductive layer 21 is a metal electrode layer, and the material of the first isolation layer 24 includes a conductive metal oxide. The first conductive layer 21 and the first isolation layer 24 form a first electrode 31. The dielectric layer 22 is an insulating medium, and the second conductive layer 23 is a metal electrode layer. The material of the second isolation layer 25 includes a conductive metal oxide. The second conductive layer 23 and the isolation layer 25 form a second electrode 32. The first electrode 31, the dielectric layer 22, and the second electrode 32 form a capacitor 30.

[0093] In the embodiment of the present application, the first isolation layer 24 is located between the first conductive layer 21 and the dielectric layer 22. It can not only isolate the first conductive layer 21 and the dielectric layer 22, preventing the surface of the first conductive layer 21 from being oxidized to form an interface layer; it can also inhibit the first conductive layer 21 from absorbing oxygen from the dielectric layer 22, thereby inhibiting the formation of oxygen vacancies in the dielectric layer 22; at the same time, it can also supplement oxygen atoms into the dielectric layer 22 to provide oxygen for the dielectric layer 22, so as to fill some of the oxygen vacancies in the dielectric layer 22, which helps to inhibit the formation of oxygen vacancies in the dielectric layer 22, thereby improving the performance and reliability of the semiconductor device.

[0094] In the embodiment of the present application, the second isolation layer 25 is located between the dielectric layer 22 and the second conductive layer 23, and can isolate the dielectric layer 22 and the second conductive layer 23, and can inhibit the second conductive layer 23 from absorbing oxygen from the dielectric layer 22, thereby inhibiting the formation of oxygen vacancies in the dielectric layer 22; at the same time, it can also supplement oxygen atoms into the dielectric layer 22 to provide oxygen for the dielectric layer 22, so as to fill some of the oxygen vacancies in the dielectric layer 22, which helps to inhibit the formation of oxygen vacancies in the dielectric layer 22, thereby improving the performance and reliability of the semiconductor device.

[0095] Optionally, the material of the first conductive layer 21 includes one or more of TiN, Ru, W, Pt, TaN, etc. Optionally, the material of the second conductive layer 23 includes one or more of TiN, Ru, W, Pt, TaN, etc. Optionally, the first conductive layer 21 and the second conductive layer 23 may form a symmetrical structure.

[0096] In the embodiment of the present application, first conductive layer 21 is a metal electrode layer, second conductive layer 23 is a metal electrode layer, first isolation layer 24 is made of a conductive metal oxide, and second isolation layer 25 is made of a conductive metal oxide. First conductive layer 21 and first isolation layer 24 form a first electrode 31, and second isolation layer 25 and second conductive layer 23 form a second electrode 32.

[0097] In some optional embodiments of the present application, the material of the dielectric layer 22 includes a non-ferroelectric dielectric material. The non-ferroelectric dielectric material is generally a high dielectric constant material, such as at least one of hafnium oxide (HfO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), strontium titanate (STO), etc. Among them, the high dielectric constant material generally refers to a material with a dielectric constant greater than 3.9. Strontium titanate (STO) has an ultra-high dielectric constant (k>100), which can meet the requirements of advanced nodes and enable the capacitor to meet high capacitance requirements.

[0098] Of course, in other optional embodiments of the present application, the dielectric layer 22 may be made of other materials, such as silicon dioxide, according to actual needs.

[0099] In the embodiment of the present application, dielectric layer 22 is made of a dielectric material. First electrode 31, dielectric layer 22, and second electrode 32 form capacitor 30. Capacitor 30 is a dielectric capacitor. Capacitor 30 has a structure including a metal electrode, a dielectric layer, and a metal-in-metal (MIM) electrode. Semiconductor device 100 is a memory device including a dielectric capacitor.

[0100] In some optional embodiments of the present application, the material of the dielectric layer 22 includes a ferroelectric material, the ferroelectric material includes HfO2 or doped HfO2, and the doping elements in the doped HfO2 include one or more of Zr, Si, Y, Al, La, Gd, etc.

[0101] In the embodiment of the present application, dielectric layer 22 is made of a ferroelectric material. First electrode 31, dielectric layer 22, and second electrode 32 form capacitor 30. Capacitor 30 is a ferroelectric capacitor. Capacitor 30 comprises a metal electrode, a ferroelectric layer, and a metal electrode. Semiconductor device 100 may be a ferroelectric memory.

[0102] In a specific embodiment of the present application, the semiconductor device 100 is a transistor, and the transistor includes: a first electrode 26, a second electrode 27, a channel layer 28 and a gate 29, wherein the channel layer 28 is located between the first electrode 26 and the second electrode 27; the gate 29 is located on one side of the substrate 10, and the gate 29 is insulated from the channel layer 28, and the orthographic projection of the gate 29 on the substrate 10 overlaps with the orthographic projection of the channel layer 28 on the substrate 10; wherein: the first conductive layer 21 is the channel layer 28 of the transistor, the second conductive layer 23 is the gate 29 of the transistor; the dielectric layer 22 is the gate insulating layer of the transistor. The dielectric layer 22 is formed between the channel layer 28 and the gate 29; a first isolation layer 24 is formed between the channel layer 28 and the dielectric layer 22; and / or a second isolation layer 25 (such as Figure 12 shown).

[0103] In the embodiment of the present application, the channel layer 28 , the dielectric layer 22 , the first isolation layer 24 and / or the second isolation layer 25 , and the gate 29 form a capacitor 30 .

[0104] In the embodiment of the present application, the first isolation layer 24 is located between the channel layer 28 and the dielectric layer 22. It can not only isolate the channel layer 28 and the dielectric layer 22, preventing the surface of the channel layer 28 from being oxidized to form an interface layer; it can also inhibit the channel layer 28 from absorbing oxygen from the dielectric layer 22, thereby inhibiting the formation of oxygen vacancies in the dielectric layer 22; it can also supplement oxygen atoms into the dielectric layer 22 to provide oxygen for the dielectric layer, so as to fill some of the oxygen vacancies in the dielectric layer 22, which helps to inhibit the formation of more oxygen vacancies in the dielectric layer, thereby improving the performance and reliability of the semiconductor device.

[0105] In the embodiment of the present application, the second isolation layer 25 is located between the dielectric layer 22 and the gate 29, and can isolate the dielectric layer 22 and the gate 29, thereby inhibiting the gate 29 from absorbing oxygen from the dielectric layer 22, thereby inhibiting the formation of oxygen vacancies in the dielectric layer 22; it can also supplement oxygen atoms into the dielectric layer 22 to provide oxygen for the dielectric layer, so as to fill some of the oxygen vacancies in the dielectric layer 22, which helps to inhibit the formation of more oxygen vacancies in the dielectric layer, thereby improving the performance and reliability of the semiconductor device.

[0106] It should be noted that in the embodiment of the present application, the shape of the channel layer 28 is as follows: Figure 12 The shape formed by the middle dotted line, the boundary line of the first electrode 26, the boundary line of the second electrode 27 and the upper surface of the substrate 10 is shown. This shape is a schematic diagram and is only used to schematically illustrate the shape of the channel layer 28. The actual shape of the channel layer 28 may be different from the actual shape of the channel layer 28. Figure 12 As shown in the figure, as long as the channel layer 28 is located between the first electrode 26 and the second electrode 27, it falls within the protection scope of the embodiment of the present application.

[0107] Optionally, in the embodiment of the present application, the first electrode 26 serves as one of the source and the drain, and the second electrode 27 serves as the other of the source and the drain.

[0108] In the embodiment of the present application, the first electrode 26, the second electrode 27, the channel layer 28, and the gate 29 form a transistor, and the first electrode 26, the second electrode 27, the channel layer 28, the dielectric layer 22, the first isolation layer 24 and / or the second isolation layer 25, and the gate 29 form a memory cell of the semiconductor device 100. A word line of the semiconductor device is connected to the gate, a bit line is connected to one of the first electrode and the second electrode, and the other of the first electrode and the second electrode is grounded.

[0109] In some optional embodiments of the present application, such as Figure 12As shown, the substrate 10 is a silicon substrate having a first doped region and a second doped region, the first doped region being a first electrode 26, the second doped region being a second electrode 27, and a portion of the silicon substrate located between the first doped region and the second doped region being a channel layer 28; the material of the dielectric layer 22 includes a ferroelectric material, and the dielectric layer 22 is in contact with the channel layer 28; the gate 29 is a metal electrode layer, and the second isolation layer 25 is located between the gate 29 and the dielectric layer 22, and the second isolation layer 25 is in contact with the dielectric layer 22 and the gate 29, respectively.

[0110] In the embodiment of the present application, the semiconductor device 100 includes a second isolation layer 25 but does not include a first isolation layer 24. Along a direction away from the substrate 10, a channel layer 28, a dielectric layer 22, a second isolation layer 25, and a gate 29 are sequentially arranged in contact with each other. The channel layer 28 is the first conductive layer 21 described above, the dielectric layer 22 is an insulating medium, and the gate 29 is the second conductive layer 23 described above. The material of the second isolation layer 25 includes a conductive metal oxide. The gate 29 and the second isolation layer 25 form a second electrode 32. The first electrode 31, the dielectric layer 22, and the second electrode 32 form a capacitor 30.

[0111] In the embodiment of the present application, the second isolation layer 25 is located between the dielectric layer 22 and the gate 29, and can isolate the dielectric layer 22 and the gate 29, thereby inhibiting the gate 29 from absorbing oxygen from the dielectric layer 22, thereby inhibiting the formation of oxygen vacancies in the dielectric layer 22; it can also supplement oxygen atoms into the dielectric layer 22 to provide oxygen for the dielectric layer, so as to fill some of the oxygen vacancies in the dielectric layer 22, which helps to inhibit the formation of more oxygen vacancies in the dielectric layer, thereby improving the performance and reliability of the semiconductor device.

[0112] Optionally, the material of the channel layer 28 includes semiconductor materials, including but not limited to Si, SiGe, x wait.

[0113] Optionally, the material of the gate 29 includes one or more of TiN, Ru, W, Pt, TaN, etc.

[0114] Optionally, the ferroelectric material includes HfO2, the dielectric layer 22 is a hafnium oxide layer, and the second isolation layer 25 is an indium tin oxide layer. The bond energy between O and In atoms is smaller than that between O and Hf atoms, and O is more likely to separate from In and be provided to Hf.

[0115] Optionally, the ferroelectric material includes doped HfO2, and the doping elements in the doped HfO2 include one or more of Zr, Si, Y, Al, La, Gd, etc.

[0116] In the embodiment of the present application, the channel layer 28 is the first conductive layer 21, the gate 29 is the second conductive layer 23, a second isolation layer 25 is formed between the dielectric layer 22 and the gate 29, and the second isolation layer 25 and the gate 29 form a second electrode 32. The material of the dielectric layer 22 includes a ferroelectric material. The first electrode 31, the dielectric layer 22, and the second electrode 32 form a capacitor 30. The capacitor 30 is a ferroelectric capacitor. The structure of the capacitor 30 includes a metal electrode, a ferroelectric layer, and a semiconductor electrode (MFS). The semiconductor device 100 is a memory device including a ferroelectric field effect transistor (FeFET).

[0117] The present application proposes a semiconductor device that can eliminate the interface layer and inhibit the generation of oxygen vacancies. By inserting a conductive metal oxide layer between the metal electrode and the dielectric layer (such as a dielectric layer or a ferroelectric layer), as part of the electrode, it can not only isolate the metal lower electrode and the dielectric layer, prevent the surface of the metal lower electrode from being oxidized, and form no interface layer between the dielectric layer and the metal lower electrode; it can also inhibit the metal electrode from absorbing oxygen from the dielectric layer, inhibiting the formation of more oxygen vacancies in the dielectric layer; at the same time, it can also provide oxygen to the dielectric layer, helping to inhibit the formation of more oxygen vacancies in the dielectric layer, thereby improving the performance of the semiconductor device.

[0118] In the embodiments of the present application, the bond energy of the oxygen atoms in the first isolation layer is greater than the bond energy of the oxygen atoms in the dielectric layer. Therefore, the oxygen atoms in the first isolation layer easily diffuse into the dielectric layer, filling some of the oxygen vacancies in the dielectric layer, thereby helping to reduce oxygen vacancies in the dielectric layer and further improving the performance and reliability of the semiconductor device. The bond energy of the oxygen atoms in the second isolation layer is greater than the bond energy of the oxygen atoms in the dielectric layer. Therefore, the oxygen atoms in the second isolation layer easily diffuse into the dielectric layer, filling some of the oxygen vacancies in the dielectric layer, thereby helping to reduce oxygen vacancies in the dielectric layer and further improving the performance and reliability of the semiconductor device.

[0119] The semiconductor device in the embodiment of the present application can be applied to the memory field, and can be a capacitor, a transistor, or a memory having a capacitor and / or a transistor, which can improve the capacitance performance of the memory device.

[0120] In some optional embodiments of the present application, the semiconductor device may be a random access memory, specifically a static random access memory or a dynamic random access memory, and of course, may also be a flash memory storage, etc.

[0121] Specifically, the semiconductor device in the embodiment of the present application may be a dynamic random access memory including planar or vertical transistors with vertical channels or horizontal channels.

[0122] Based on the same inventive concept, the embodiment of the present application provides a method for manufacturing a semiconductor device. The flowchart of the method for manufacturing a semiconductor device is as follows: Figure 1 、 Figure 7 and Figure 8 As shown, the method for manufacturing the semiconductor device includes:

[0123] S101. Provide a substrate 10. Optionally, the material of the substrate 10 includes but is not limited to Si, SiGex, etc.

[0124] S102, forming a first conductive layer 21;

[0125] S103 , forming a metal oxide layer including oxygen atoms and first metal atoms on one side of the substrate 10 to serve as a dielectric layer 22 , wherein the dielectric layer 22 covers at least a portion of the first conductive layer 21 ;

[0126] S104, forming a second conductive layer 23 on a side of the dielectric layer 22 away from the first conductive layer 21, wherein the orthographic projection of the second conductive layer 23 on the substrate 10 overlaps with the orthographic projection of the first conductive layer 21 on the substrate 10;

[0127] S105, performing annealing treatment; wherein:

[0128] After forming the first conductive layer 21 and before forming the dielectric layer 22, the method for manufacturing the semiconductor device further includes: S106, forming a metal oxide layer including oxygen atoms and second metal atoms on one side of the first conductive layer 21 to serve as a first isolation layer 24, wherein the first isolation layer 24 is in contact with the dielectric layer 22, and the bond energy between the second metal atoms and the oxygen atoms is smaller than the bond energy between the first metal atoms and the oxygen atoms; and / or,

[0129] After forming the dielectric layer 22 and before forming the second conductive layer 23, the method for manufacturing the semiconductor device further includes: S107, forming a metal oxide layer including oxygen atoms and third metal atoms on a side of the dielectric layer 22 away from the substrate 10 to serve as a second isolation layer 25, the second isolation layer 25 is in contact with the dielectric layer 22, and the bond energy between the third metal atoms and the oxygen atoms is less than the bond energy between the first metal atoms and the oxygen atoms.

[0130] In the embodiments of the present application, the method for manufacturing a semiconductor device can be used to manufacture the semiconductor device in any embodiment of the present application.

[0131] In a specific embodiment of the present application, Figures 1 to 6 As shown, the method for manufacturing a semiconductor device includes:

[0132] S101, providing a substrate 10;

[0133] S102, forming a first conductive layer 21;

[0134] S106, forming a first isolation layer 24 on one side of the first conductive layer 21;

[0135] S103, forming a dielectric layer 22 on a side of the first isolation layer 24 away from the first conductive layer 21;

[0136] S107, forming a second isolation layer 25 on a side of the dielectric layer 22 away from the first isolation layer 24;

[0137] S104, forming a second conductive layer 23 on a side of the second isolation layer 25 away from the dielectric layer 22;

[0138] S105: Perform annealing treatment.

[0139] At this time, in the embodiment of the present application, the first conductive layer 21, the first isolation layer 24, the dielectric layer 22, the second isolation layer 25 and the second conductive layer 23 are arranged in sequence, the first conductive layer 21 and the first isolation layer 24 form a first electrode 31, the second isolation layer 25 and the second conductive layer 23 form a second electrode 32, and the first electrode 31, the dielectric layer 22 and the second electrode 32 form a capacitor 30.

[0140] In another specific embodiment of the present application, Figure 7 As shown, the method for manufacturing a semiconductor device includes:

[0141] S101, providing a substrate 10;

[0142] S102, forming a first conductive layer 21;

[0143] S106, forming a first isolation layer 24 on one side of the first conductive layer 21;

[0144] S103, forming a dielectric layer 22 on a side of the first isolation layer 24 away from the first conductive layer 21;

[0145] S104, forming a second conductive layer 23 on a side of the dielectric layer 22 away from the first isolation layer 24;

[0146] S105: Perform annealing treatment.

[0147] At this time, in the embodiment of the present application, the first conductive layer 21, the first isolation layer 24, the dielectric layer 22 and the second conductive layer 23 are arranged in sequence, the first conductive layer 21 and the first isolation layer 24 form a first electrode 31, the second conductive layer 23 forms a second electrode 32, and the first electrode 31, the dielectric layer 22 and the second electrode 32 form a capacitor 30.

[0148] In another specific embodiment of the present application, Figures 8 to 12 As shown, the method for manufacturing a semiconductor device includes:

[0149] S101, providing a substrate 10;

[0150] S102, forming a first conductive layer 21;

[0151] S103, forming a dielectric layer 22 on one side of the first conductive layer 21;

[0152] S107, forming a second isolation layer 25 on a side of the dielectric layer 22 away from the first conductive layer 21;

[0153] S104, forming a second conductive layer 23 on a side of the second isolation layer 25 away from the dielectric layer 22;

[0154] S105: Perform annealing treatment.

[0155] At this time, in the embodiment of the present application, the first conductive layer 21, the dielectric layer 22, the second isolation layer 25 and the second conductive layer 23 are arranged in sequence, the first conductive layer 21 forms a first electrode 31, the second isolation layer 25 and the second conductive layer 23 form a second electrode 32, and the first electrode 31, the dielectric layer 22 and the second electrode 32 form a capacitor 30.

[0156] In the embodiment of the present application, the material of the dielectric layer 22 includes oxygen atoms and first metal atoms, and the material of the first isolation layer 24 includes oxygen atoms and second metal atoms. By arranging a metal oxide layer (i.e., the first isolation layer 24) between the first conductive layer 21 and the dielectric layer 22, not only can the first conductive layer 21 and the dielectric layer 22 be isolated, but also the surface of the first conductive layer 21 is prevented from being oxidized to form an interface layer during the formation of the dielectric layer 22, so that no interface layer is formed on the surface of the first conductive layer 21 facing the dielectric layer 22, thereby solving the problems of the interface layer of the dielectric capacitor affecting the capacitance performance in the prior art, and solving the problem of the interface layer of the ferroelectric capacitor affecting the ferroelectric capacitor in the prior art. The performance problem of the semiconductor device (such as fatigue characteristics and retention characteristics) can be solved; the first conductive layer 21 and the dielectric layer 22 are not in direct contact, the first conductive layer 21 is inhibited from absorbing oxygen from the dielectric layer 22, and the formation of oxygen vacancies in the dielectric layer 22 is inhibited, which solves the problem in the prior art that oxygen atoms in the dielectric layer or ferroelectric layer diffuse to the metal electrode, causing an increase in oxygen vacancies in the dielectric layer or ferroelectric layer, resulting in degradation of device performance; at the same time, since the first isolation layer 24 is in contact with the dielectric layer 22, oxygen can be provided to the dielectric layer 22 and oxygen vacancies in the dielectric layer 22 can be reduced, providing space for making a thinner dielectric layer (such as a dielectric layer or ferroelectric layer) to avoid the dielectric layer being too thin and being punctured.

[0157] In the embodiment of the present application, the material of the second isolation layer 25 includes oxygen atoms and third metal atoms. By arranging a metal oxide layer (i.e., the second isolation layer 25) between the dielectric layer 22 and the second conductive layer 23, not only can the dielectric layer 22 and the second conductive layer 23 be isolated, so that the dielectric layer 22 and the second conductive layer 23 are not in direct contact, but also the second conductive layer 23 is inhibited from absorbing oxygen from the dielectric layer 22, and the formation of oxygen vacancies in the dielectric layer 22 is inhibited, thereby solving the problem in the prior art that oxygen atoms in the dielectric layer or ferroelectric layer diffuse to the metal electrode, causing an increase in oxygen vacancies in the dielectric layer or ferroelectric layer, resulting in degradation of device performance; at the same time, since the second isolation layer 25 is in contact with the dielectric layer 22, it can provide oxygen to the dielectric layer 22 and reduce oxygen vacancies in the dielectric layer 22, providing space for the production of thinner dielectric layers (such as dielectric layers or ferroelectric layers), thereby preventing the dielectric layer from being too thin and being punctured.

[0158] In the embodiment of the present application, by forming a first isolation layer 24 between the first conductive layer 21 and the dielectric layer 22 and forming a second isolation layer 25 between the dielectric layer 22 and the second conductive layer 23 , the performance of the semiconductor device can be improved.

[0159] In the embodiment of the present application, the first isolation layer 24 is in contact with the dielectric layer 22, and the bond energy between the second metal atoms and the oxygen atoms is less than the bond energy between the first metal atoms and the oxygen atoms. The oxygen atoms in the first isolation layer 24 can easily diffuse into the dielectric layer 22 to provide oxygen for the dielectric layer 22, filling some of the oxygen vacancies in the dielectric layer 22, thereby helping to reduce the oxygen vacancies in the dielectric layer 22, providing space for making a thinner dielectric layer, avoiding the dielectric layer being too thin and being punctured, and further improving the performance and reliability of the semiconductor device.

[0160] In the embodiment of the present application, the second isolation layer 25 is in contact with the dielectric layer 22, and the bond energy between the third metal atoms and the oxygen atoms is less than the bond energy between the first metal atoms and the oxygen atoms. The oxygen atoms in the second isolation layer 25 can easily diffuse into the dielectric layer 22 to provide oxygen for the dielectric layer 22, filling some of the oxygen vacancies in the dielectric layer 22, thereby helping to reduce the oxygen vacancies in the dielectric layer 22, providing space for making a thinner dielectric layer, avoiding the dielectric layer being too thin and being punctured, and further improving the performance and reliability of the semiconductor device.

[0161] In some optional embodiments of the present application, such as Figures 1 to 6 As shown, the semiconductor device is a capacitor, and forming the first conductive layer 21 includes depositing a metal electrode layer on one side of the substrate 10 to serve as the first conductive layer 21. The first conductive layer 21 serves as one of the two electrodes of the capacitor. Optionally, the material of the first conductive layer 21 includes one or more of TiN, Ru, W, Pt, TaN, and the like.

[0162] Forming the first isolation layer 24 includes: depositing a first metal oxide layer having conductivity on a side of the first conductive layer 21 away from the substrate 10 to serve as the first isolation layer 24 , wherein the first isolation layer 24 contacts the first conductive layer 21 .

[0163] Forming the dielectric layer 22 includes depositing a ferroelectric material or a non-ferroelectric dielectric material on a side of the first isolation layer 24 away from the substrate 10 to serve as the dielectric layer 22. Optionally, the material of the dielectric layer 22 includes a ferroelectric material, which is typically HfO2 or doped HfO2, where the doping element in the doped HfO2 includes one or more of Zr, Si, Y, Al, La, Gd, and the like; or, the material of the dielectric layer 22 includes a non-ferroelectric dielectric material, which is typically a high dielectric constant material, such as at least one of hafnium oxide (HfO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), and strontium titanate (STO).

[0164] Forming the second isolation layer 25 includes depositing a conductive second metal oxide layer on a side of the dielectric layer 22 away from the substrate 10 to serve as the second isolation layer 25 .

[0165] Forming the second conductive layer 23 includes depositing a metal layer on a side of the second isolation layer 25 away from the substrate 10 to serve as the second conductive layer 23. The second conductive layer 23 contacts the second isolation layer 25 and serves as the other electrode of the capacitor. Optionally, the material of the second conductive layer 23 includes one or more of TiN, Ru, W, Pt, TaN, and the like.

[0166] In the embodiment of the present application, the first isolation layer 24 is located between the first conductive layer 21 and the dielectric layer 22. It can not only isolate the first conductive layer 21 and the dielectric layer 22, prevent the surface of the first conductive layer 21 from being oxidized, and avoid the formation of an interface layer between the dielectric layer 22 (such as a dielectric layer or a ferroelectric layer) and the first isolation layer 24; it can also inhibit the first conductive layer 21 from absorbing oxygen from the dielectric layer 22, ensuring that the oxygen atoms in the dielectric layer 22 will not be absorbed by the first conductive layer 21, thereby inhibiting the formation of oxygen vacancies in the dielectric layer 22; it can also supplement oxygen atoms into the dielectric layer 22 to provide oxygen for the dielectric layer 22, so as to fill some of the oxygen vacancies in the dielectric layer 22, which helps to inhibit the formation of oxygen vacancies in the dielectric layer 22, thereby improving the performance and reliability of semiconductor devices.

[0167] In the embodiment of the present application, the second isolation layer 25 is located between the dielectric layer 22 and the second conductive layer 23, and can isolate the dielectric layer 22 and the second conductive layer 23, and can inhibit the second conductive layer 23 from absorbing oxygen from the dielectric layer 22 (such as a dielectric layer or a ferroelectric layer), ensuring that the oxygen atoms in the dielectric layer 22 will not be absorbed by the second conductive layer 23, thereby inhibiting the formation of oxygen vacancies in the dielectric layer 22; it can also supplement oxygen atoms into the dielectric layer 22 to provide oxygen for the dielectric layer 22, so as to fill some of the oxygen vacancies in the dielectric layer 22, which helps to inhibit the formation of oxygen vacancies in the dielectric layer 22, thereby improving the performance and reliability of the semiconductor device.

[0168] In the embodiment of the present application, the first conductive layer 21 is configured to form the first electrode 31 together with the first isolation layer 24, and the second isolation layer 25 is configured to form the second electrode 32 together with the second conductive layer 23. The dielectric layer 22 forms the insulating medium of the capacitor 30. The first isolation layer 24 and the second isolation layer 25 are not configured to form the insulating medium of the capacitor together with the dielectric layer 22. In this way, the thickness between the first electrode 31 and the second electrode 32 can be represented by the thickness of the dielectric layer 22, avoiding the problem of increasing the thickness of the insulating medium and reducing the capacitance of the capacitor by configuring the first isolation layer 24 and / or the second isolation layer 25 to form the insulating medium of the capacitor together with the dielectric layer 22. Through this configuration, the thickness of the insulating medium of the capacitor can be reduced, that is, the distance between the first electrode and the second electrode of the capacitor is reduced, which can increase the capacitance of the capacitor.

[0169] Specifically, in the embodiments of the present application, as 1 to Figure 6 As shown, the method for manufacturing a semiconductor device includes:

[0170] First, a substrate 10 is provided.

[0171] Next, a metal electrode layer (ie, a metal bottom electrode) is deposited on one side of the substrate 10 to serve as the first conductive layer 21 .

[0172] Next, a first metal oxide layer having conductivity is deposited on a side of the first conductive layer 21 away from the substrate 10 to serve as a first isolation layer 24 .

[0173] Next, a ferroelectric layer or a dielectric layer is deposited on the side of the first isolation layer 24 away from the substrate 10 to serve as the dielectric layer 22 .

[0174] Next, a second conductive metal oxide layer is deposited on the side of the ferroelectric layer or the dielectric layer away from the substrate 10 to serve as a second isolation layer 25 .

[0175] Next, a metal electrode layer (ie, a metal top electrode) is deposited on a side of the second isolation layer 25 away from the substrate 10 to serve as the second conductive layer 23 .

[0176] Next, rapid thermal annealing is performed to make the ferroelectric layer ferroelectric or the dielectric layer dielectric, the first conductive layer 21 and the first isolation layer 24 form a first electrode 31, the second isolation layer 25 and the second conductive layer 23 form a second electrode 32, thereby forming a capacitor 30 including the first electrode 31, the second electrode 32 and the dielectric layer 22 with ferroelectric or dielectric properties.

[0177] In some other optional embodiments of the present application, Figures 8 to 12 As shown, the semiconductor device 100 is a transistor, and the substrate 10 is a silicon substrate; forming a first conductive layer 21 includes: processing the silicon substrate through a doping process so that the silicon substrate has a first doping region and a second doping region, the first doping region is a first electrode 26, the second doping region is a second electrode 27, and a portion of the silicon substrate located between the first doping region and the second doping region forms a channel layer 28, and the first conductive layer 21 is the channel layer 28 of the transistor. Optionally, the first doping region and the second doping region of the same doping type can be formed through the doping process, for example, the first doping region and the second doping region can both be N-type or both be P-type. Of course, in other optional embodiments of the present application, according to actual needs, the first doping region and the second doping region of different doping types can also be formed through the doping process, for example, the first doping region is N-type and the second doping region is P-type, or the first doping region is P-type and the second doping region is N-type.

[0178] The dielectric layer 22 is formed, including: depositing a ferroelectric material on one side of the substrate 10 as the dielectric layer 22, the dielectric layer 22 is in contact with the channel layer 28, and the dielectric layer 22 is the gate insulating layer of the transistor. Optionally, the ferroelectric material is usually HfO2 or doped HfO2, and the doping elements in the doped HfO2 include one or more of Zr, Si, Y, Al, La, Gd, etc. It should be noted that before depositing the ferroelectric layer on one side of the substrate 10, a substrate passivation layer is formed on the side of the channel layer 28 where the ferroelectric layer is to be formed, and the ferroelectric layer is formed on the side of the substrate passivation layer away from the channel layer 28. The substrate passivation layer is in contact with the channel layer 28 and the dielectric layer 22 respectively to avoid oxidation of the surface of the channel layer 28 due to oxygen when depositing the ferroelectric layer. Optionally, the material of the substrate passivation layer is, for example, SiO x , SiON, etc.

[0179] Forming the second isolation layer 25 includes depositing a conductive second metal oxide layer on a side of the dielectric layer 22 away from the substrate 10 to serve as the second isolation layer 25 .

[0180] Forming the second conductive layer 23 includes depositing a metal layer on a side of the second isolation layer 25 away from the substrate 10 to form a gate 29. The gate 29 contacts the second isolation layer 25. The second conductive layer 23 serves as the gate 29 of the transistor. Optionally, the material of the gate 29 includes one or more of TiN, Ru, W, Pt, TaN, and the like.

[0181] In the embodiment of the present application, the second isolation layer 25 is located between the dielectric layer 22 and the second conductive layer 23, and can isolate the dielectric layer 22 and the gate 29, and can inhibit the second conductive layer 23 from absorbing oxygen from the dielectric layer 22 (such as the ferroelectric layer), ensuring that the oxygen atoms in the dielectric layer 22 will not be absorbed by the second conductive layer 23, thereby inhibiting the formation of oxygen vacancies in the dielectric layer 22; it can also supplement oxygen atoms into the dielectric layer 22 to provide oxygen for the dielectric layer to fill some of the oxygen vacancies in the dielectric layer 22, which helps to inhibit the formation of more oxygen vacancies in the dielectric layer, thereby improving the performance and reliability of the semiconductor device.

[0182] In the embodiment of the present application, the second isolation layer 25 is configured to form the second electrode 32 together with the second conductive layer 23, and the dielectric layer 22 forms the insulating medium of the capacitor 30. The second isolation layer 25 is not configured to form the insulating medium of the capacitor together with the dielectric layer 22. In this way, the thickness between the first electrode 31 and the second electrode 32 can be represented by the thickness of the dielectric layer 22, avoiding the problem of the second isolation layer 25 being configured to form the insulating medium of the capacitor together with the dielectric layer 22, which increases the thickness of the insulating medium and reduces the capacitance of the capacitor. This configuration can reduce the thickness of the insulating medium of the capacitor, that is, reduce the distance between the first electrode and the second electrode of the capacitor, and thus increase the capacitance of the capacitor.

[0183] Specifically, in the embodiments of the present application, Figures 8 to 12 As shown, the method for manufacturing a semiconductor device includes:

[0184] First, a substrate 10 is provided.

[0185] Next, the substrate 10 is processed through a doping process so that the substrate 10 has a first doping region and a second doping region. The first doping region is the first electrode 26, and the second doping region is the second electrode 27, so as to define the source and drain regions. The portion of the substrate 10 located between the first doping region and the second doping region forms a channel layer 28, and the channel layer 28 is the first conductive layer 21.

[0186] Next, a ferroelectric layer is deposited on one side of the substrate 10 to serve as the dielectric layer 22 .

[0187] Next, a second conductive metal oxide layer is deposited on a side of the dielectric layer 22 away from the substrate 10 to serve as a second isolation layer 25 .

[0188] Next, a metal electrode layer is deposited on a side of the second isolation layer 25 away from the substrate 10 to form a gate 29 . The gate 29 is the second conductive layer 23 .

[0189] Next, a rapid thermal annealing treatment is performed to make the ferroelectric layer ferroelectric, the first conductive layer 21 (i.e., the channel layer 28) forms a first electrode 31, the second isolation layer 25 and the second conductive layer 23 (i.e., the gate 29) form a second electrode 32, thereby forming a capacitor 30 including the first electrode 31, the second electrode 32 and the dielectric layer 22 with ferroelectricity.

[0190] Optionally, in the embodiment of the present application, a gate-last process is adopted to first form the first electrode 26 and the second electrode 27 , and then form the gate 29 .

[0191] It should be noted that in the embodiments of the present application, deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, etc., and no specific limitation is made here.

[0192] In the description of the embodiments of the present application, it should be understood that a “layer” refers to a thin film of a certain material produced on a substrate by a process such as deposition or coating.

[0193] The method for manufacturing a semiconductor device according to the embodiment of the present application can be applied to the field of semiconductor device preparation and can improve the capacitance performance of the semiconductor device.

[0194] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which includes: the above-mentioned semiconductor device 100.

[0195] It should be noted that, since the electronic device of the embodiment of the present application includes the semiconductor device of the embodiment of the present application, the electronic device of the embodiment of the present application also has the above-mentioned beneficial effects of the semiconductor device of the embodiment of the present application, which will not be repeated here.

[0196] In some optional embodiments of the present application, the electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a smart mobile terminal, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0197] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0198] In the embodiment of the present application, the material of the dielectric layer includes oxygen atoms and first metal atoms, and the material of the first isolation layer includes oxygen atoms and second metal atoms. By arranging a metal oxide layer (i.e., the first isolation layer) between the first conductive layer and the dielectric layer, not only can the first conductive layer and the dielectric layer be isolated, but also the surface of the first conductive layer is prevented from being oxidized to form an interface layer during the formation of the dielectric layer, so that no interface layer is formed on the surface of the first conductive layer facing the dielectric layer, thereby solving the problems of the interface layer of the dielectric capacitor affecting the capacitance performance in the prior art, and solving the problem of the interface layer of the ferroelectric capacitor affecting the ferroelectric semiconductor in the prior art. The problem of device performance (such as fatigue characteristics and retention characteristics) can be solved; the first conductive layer and the dielectric layer are not in direct contact, which inhibits the first conductive layer from absorbing oxygen from the dielectric layer and inhibits the formation of more oxygen vacancies in the dielectric layer, thereby solving the problem in the prior art that oxygen atoms in the dielectric layer or ferroelectric layer diffuse to the metal electrode, causing an increase in oxygen vacancies in the dielectric layer or ferroelectric layer, resulting in degradation of device performance; at the same time, since the first isolation layer is in contact with the dielectric layer, oxygen can be provided to the dielectric layer and oxygen vacancies in the dielectric layer can be reduced, providing space for making a thinner dielectric layer (such as a dielectric layer or ferroelectric layer) to avoid the dielectric layer being too thin and being punctured.

[0199] In an embodiment of the present application, the material of the second isolation layer includes oxygen atoms and third metal atoms. By arranging a metal oxide layer (i.e., the second isolation layer) between the dielectric layer and the second conductive layer, not only can the dielectric layer and the second conductive layer be isolated, so that the dielectric layer and the second conductive layer are not in direct contact, but also the second conductive layer is inhibited from absorbing oxygen from the dielectric layer, and the formation of more oxygen vacancies in the dielectric layer is inhibited, thereby solving the problem in the prior art that oxygen atoms in the dielectric layer or ferroelectric layer diffuse to the metal electrode, causing an increase in oxygen vacancies in the dielectric layer or ferroelectric layer, resulting in degradation of device performance; at the same time, since the second isolation layer is in contact with the dielectric layer, it can provide oxygen to the dielectric layer and reduce oxygen vacancies in the dielectric layer, thereby providing space for making a thinner dielectric layer (such as a dielectric layer or ferroelectric layer), and preventing the dielectric layer from being too thin and being punctured.

[0200] In the embodiment of the present application, by providing a first isolation layer between the first conductive layer and the dielectric layer, and providing a second isolation layer between the dielectric layer and the second conductive layer, the performance of the semiconductor device can be improved.

[0201] In an embodiment of the present application, the first isolation layer is in contact with the dielectric layer, the bond energy between the second metal atoms and the oxygen atoms is smaller than the bond energy between the first metal atoms and the oxygen atoms, and the oxygen atoms in the first isolation layer can easily diffuse into the dielectric layer, filling some of the oxygen vacancies in the dielectric layer to provide oxygen for the dielectric layer, thereby helping to reduce the oxygen vacancies in the dielectric layer, providing space for making a thinner dielectric layer, avoiding the dielectric layer being too thin and being punctured, and further improving the performance and reliability of the semiconductor device.

[0202] In an embodiment of the present application, the second isolation layer is in contact with the dielectric layer, the bond energy between the third metal atom and the oxygen atom is less than the bond energy between the first metal atom and the oxygen atom, and the oxygen atoms in the second isolation layer easily diffuse into the dielectric layer to provide oxygen for the dielectric layer, filling some of the oxygen vacancies in the dielectric layer, thereby helping to reduce the oxygen vacancies in the dielectric layer, providing space for making a thinner dielectric layer, avoiding the dielectric layer being too thin and being punctured, and further improving the performance and reliability of the semiconductor device.

[0203] In an embodiment of the present application, the first conductive layer is configured to form a first electrode together with the first isolation layer, the second isolation layer is configured to form a second electrode together with the second conductive layer, the dielectric layer forms the insulating medium of the capacitor, and neither the first isolation layer nor the second isolation layer is configured to form the insulating medium of the capacitor together with the dielectric layer. In this way, the thickness between the first electrode and the second electrode can be characterized by the thickness of the dielectric layer, thereby avoiding the problem of increasing the thickness of the insulating medium and reducing the capacitance of the capacitor by configuring the first isolation layer and / or the second isolation layer as the insulating medium of the capacitor together with the dielectric layer, and the technical problem of causing the polarization strength of the ferroelectric layer to degrade. Through this configuration, the thickness of the insulating medium of the capacitor can be made smaller, that is, the distance between the first electrode and the second electrode of the capacitor is made smaller, which can increase the capacitance of the capacitor and prevent the polarization strength of the ferroelectric layer from degrading.

[0204] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this application may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted.

[0205] In the description of this application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", and "outside" are exemplary directions or positional relationships based on the accompanying drawings. They are intended to facilitate or simplify the description of the embodiments of this application, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0206] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0207] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0208] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0209] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless otherwise clearly stated herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be performed in other orders as required. Moreover, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time. The execution order of these sub-steps or stages may be flexibly configured as required, and the embodiments of the present application do not limit this.

[0210] The above is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of the present application, other similar implementation methods based on the technical ideas of the present application also fall within the protection scope of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: substrate; a dielectric layer, located on one side of the substrate, wherein the material of the dielectric layer includes oxygen atoms and first metal atoms; a first conductive layer, located on a side of the dielectric layer close to the substrate; a second conductive layer, located on a side of the dielectric layer away from the substrate, wherein an orthographic projection of the second conductive layer on the substrate overlaps with an orthographic projection of the first conductive layer on the substrate; as well as: a first isolation layer, located between the first conductive layer and the dielectric layer and in contact with the dielectric layer, wherein a material of the first isolation layer includes oxygen atoms and second metal atoms, and a bond energy between the second metal atoms and the oxygen atoms is smaller than a bond energy between the first metal atoms and the oxygen atoms; and / or, The second isolation layer is located between the dielectric layer and the second conductive layer and contacts the dielectric layer. The material of the second isolation layer includes oxygen atoms and third metal atoms. The bond energy between the third metal atoms and the oxygen atoms is smaller than the bond energy between the first metal atoms and the oxygen atoms.

2. The semiconductor device according to claim 1, wherein The first isolation layer is conductive; and / or the second isolation layer is conductive.

3. The semiconductor device according to claim 1, wherein The metal element in the material of the first isolation layer includes at least one of indium, zinc, tin, cadmium, antimony, and gallium; and / or, The metal element in the material of the second isolation layer includes at least one of indium, zinc, tin, cadmium, antimony, and gallium.

4. The semiconductor device according to claim 1, wherein The material of the first isolation layer includes InO, ZnO, ZnSnO, CdSbO, InGaO, InZnO, InSnO, In2O3, SnO2, Ga2O3, Zn2In2O5, In4Sn3O 12 、GaInO3、In4Sn3O 12 , ZnSnO3; and / or, The material of the second isolation layer includes InO, ZnO, ZnSnO, CdSbO, InGaO, InZnO, InSnO, In2O3, SnO2, Ga2O3, Zn2In2O5, In4Sn3O 12 、GaInO3、In4Sn3O 12 , at least one of ZnSnO3.

5. The semiconductor device according to claim 3, wherein The material of the dielectric layer includes a ferroelectric material, the ferroelectric material includes doped hafnium oxide, and the doping element includes at least one of Zr, Si, Y, Al, La, and Gd.

6. The semiconductor device according to any one of claims 1 to 5, wherein: The semiconductor device is a capacitor, and the first conductive layer and the second conductive layer are two electrodes of the capacitor respectively; The first isolation layer, the dielectric layer and the second isolation layer are formed in sequence between the first conductive layer and the second conductive layer in a direction away from the substrate, the side of the first isolation layer away from the dielectric layer is in contact with the first conductive layer, and the side of the second isolation layer away from the dielectric layer is in contact with the second conductive layer.

7. The semiconductor device according to claim 6, wherein: The material of the dielectric layer includes ferroelectric material or dielectric material.

8. The semiconductor device according to any one of claims 1 to 5, wherein: The semiconductor device is a transistor, The first conductive layer is a channel layer of the transistor, and the second conductive layer is a gate of the transistor; The dielectric layer is a gate insulating layer of the transistor; The second isolation layer is located between the gate and the gate insulating layer.

9. The semiconductor device according to claim 8, wherein The dielectric layer is a doped hafnium oxide layer, and the second isolation layer is an indium tin oxide layer.

10. An electronic device, characterized in that: include: The semiconductor device according to any one of claims 1 to 9.

11. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; forming a first conductive layer; forming a metal oxide layer comprising oxygen atoms and first metal atoms on one side of the substrate as a dielectric layer, wherein the dielectric layer covers at least a portion of the first conductive layer; forming a second conductive layer on a side of the dielectric layer away from the first conductive layer, wherein an orthographic projection of the second conductive layer on the substrate overlaps with an orthographic projection of the first conductive layer on the substrate; Perform annealing treatment; in: After forming the first conductive layer and before forming the dielectric layer, the method for manufacturing a semiconductor device further includes: forming a metal oxide layer comprising oxygen atoms and second metal atoms on one side of the first conductive layer as a first isolation layer, wherein the first isolation layer is in contact with the dielectric layer, and the bond energy between the second metal atoms and the oxygen atoms is smaller than the bond energy between the first metal atoms and the oxygen atoms; and / or, After forming the dielectric layer and before forming the second conductive layer, the method for manufacturing the semiconductor device further includes: forming a metal oxide layer comprising oxygen atoms and a third metal atom on a side of the dielectric layer away from the substrate to serve as a second isolation layer, wherein the second isolation layer is in contact with the dielectric layer, and the bond energy between the third metal atom and the oxygen atom is less than the bond energy between the first metal atom and the oxygen atom.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: The semiconductor device is a capacitor, Forming a first conductive layer includes: depositing a metal layer on one side of the substrate to serve as the first conductive layer, wherein the first conductive layer is one of two electrodes of the capacitor; Forming the first isolation layer includes: depositing a first conductive metal oxide layer on a side of the first conductive layer away from the substrate to serve as the first isolation layer, wherein the first isolation layer is in contact with the first conductive layer; Forming a dielectric layer, comprising: depositing a ferroelectric material or a non-ferroelectric dielectric material on a side of the first isolation layer away from the substrate to serve as the dielectric layer; Forming the second isolation layer includes: depositing a second conductive metal oxide layer on a side of the dielectric layer away from the substrate to serve as the second isolation layer; Forming a second conductive layer includes: depositing a metal layer on a side of the second isolation layer away from the substrate to serve as the second conductive layer, wherein the second conductive layer contacts the second isolation layer and is the other electrode of the capacitor.

13. The method for manufacturing a semiconductor device according to claim 11, wherein: The semiconductor device is a transistor, and the substrate is a silicon substrate. Forming a first conductive layer includes: processing a silicon substrate through a doping process to form a first conductive layer in a partial area of ​​the silicon substrate, wherein the first conductive layer is a channel layer of the transistor; Forming a dielectric layer, comprising: depositing a ferroelectric material on one side of the substrate to serve as a dielectric layer, wherein the dielectric layer contacts the channel layer and serves as a gate insulating layer of the transistor; Forming the second isolation layer includes: depositing a second conductive metal oxide layer on a side of the dielectric layer away from the substrate to serve as the second isolation layer; The second conductive layer is formed, comprising: depositing a metal layer on a side of the second isolation layer away from the substrate to form a second conductive layer, wherein the second conductive layer contacts the second isolation layer and serves as a gate of the transistor.

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