Multilayer n-buffer structure for accelerating electron extraction in sj-ligbt devices

Abstract

The application provides a multi-layer N-buffer structure SJ-LIGBT device accelerating electron extraction, introduces N-pillar drift region and P-pillar drift region to form a super junction structure on the basis of a traditional LIGBT device, improves the breakdown voltage of the device and reduces the on-state voltage drop; introduces a collector N-buffer region, a collector P region, a collector metal electrode and a collector gate oxide layer to form an electron extraction structure, when the device is turned off, the positive voltage of the collector makes a conductive channel appear in the collector P region, and electrons can flow through the conductive channel and directly flow into the collector metal electrode without passing through the p region barrier, thereby accelerating the extraction of electrons, effectively reducing the turn-off time and turn-off loss of the device, and introducing N-bufferlayer1 region, N-bufferlayer2 region and N-bufferlayer3 region to form an auxiliary depletion region, improve the breakdown voltage of the device, and provide a path for the extraction of electrons when the device is turned off.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductors, and particularly relates to a multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction. BACKGROUND

[0002] LIGBT (Lateral Insulated Gate Bipolar Transistor) is a kind of bipolar power semiconductor device, which has the characteristics of large breakdown voltage, small on-state voltage drop, high working frequency, and is widely used in various electronic fields such as transportation and communication. IGBT can be approximately regarded as a combination of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and BJT (Bipolar junction transistor), so it has the characteristics of gate voltage control of MOSFET and double-carrier conduction of BJT.

[0003] SJ (Super-Junction) is a new structure that can be applied to MOS, IGBT and other devices, which was first proposed by Academician Chen Xingbi. SJ changes the n-type drift region in MOS and IGBT into an alternating structure of n-pillar and p-pillar, which introduces a lateral electric field in the device without affecting the longitudinal electric field of the device, thereby increasing the breakdown voltage of the device without affecting the on-state voltage drop: when the device is turned off, the n-pillar and p-pillar are mutually depleted, and the device drift region can be approximately regarded as an intrinsic semiconductor, thereby improving the breakdown voltage of the device, optimizing the ratio of breakdown voltage to on-state voltage drop from 2.52 to 1.3, and successfully breaking through the traditional "silicon limit".

[0004] In order to completely deplete the drift region and achieve the maximum breakdown voltage, the n-pillar and the p-pillar often have the same doping concentration. However, in LIGBT, due to the low-doped p-type substrate, there is a parasitic pn junction between the n-pillar and the substrate, and the p-type substrate makes the n-pillar deplete first compared with the p-pillar, and at the same time makes the p-pillar unable to completely deplete, so how to control the synchronous depletion of the p-pillar and the n-pillar becomes a problem to be solved.

[0005] In addition, the IGBT is a gate voltage control power device, so the IGBT has a large breakdown voltage and a high working frequency; and because the IGBT is a double-carrier conduction, the IGBT has a small conduction voltage drop. However, the bipolar conduction also has defects. When the device is turned off, the residual carriers in the drift region will cause a certain tail current, increasing the turn-off loss of the device. This is because the collector electrode has a p region, which will play a role in barrier to hinder the extraction of electrons when the device is turned off, so the excess carriers in the drift region of the device need to disappear through recombination, resulting in a long turn-off time and a tail current, greatly increasing the turn-off loss of the device. Therefore, how to reduce the turn-off loss of the IGBT has become a problem that needs to be solved urgently. SUMMARY

[0006] In order to solve the above problems existing in the prior art, the application provides a multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction. The technical problem to be solved by the application is solved by the following technical scheme:

[0007] The application provides a multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction, comprising: an emitter P+ region 1, an emitter N+ region 2, an emitter P-well region 3, a P-type substrate region 4, an emitter metal electrode 5, a gate oxide layer 6, a gate metal electrode 7, an N-pillar drift region 8, a P-pillar drift region 9, a collector N-buffer region 10, a collector P region 11, an N-buffer layer 1 region 12, an N-buffer layer 2 region 13, an N-buffer layer 3 region 14, a collector metal electrode 15, and a collector gate oxide layer 16.

[0008] The P-type substrate region 4 is located at the bottom of the multi-layer N-buffer structure SJ-LIGBT device, and one end has a trapezoidal structure; the emitter P-well region 3, the emitter P+ region 1, the emitter N+ region 2, and the emitter metal electrode 5 together form an emitter region located at one end of the top of the device; the gate oxide layer 6 and the gate metal electrode 7 form a gate metal region, which is arranged next to the emitter region; the N-pillar drift region 8 and the P-pillar drift region 9 are arranged horizontally and staggered in the middle of the top of the device to form a drift region; the collector N-buffer region 10, the collector P region 11, the N-buffer layer 1 region 12, the N-buffer layer 2 region 13, the N-buffer layer 3 region 14, the collector metal electrode 15, and the collector gate oxide layer 16 together form a collector region, which is arranged at the other end of the top of the multi-layer N-buffer structure SJ-LIGBT device opposite to the emitter region.

[0009] Advantages:

[0010] The application provides a multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction. The N-pillar drift region 8 and the P-pillar drift region 9 are introduced into a conventional LIGBT device to form a super junction structure, so that the breakdown voltage of the device is improved and the on-state voltage drop is reduced. The collector N-buffer region 10, the collector P region 11, the collector metal electrode 15 and the collector gate oxide layer 16 are introduced to form an electron extraction structure. When the device is turned off, the positive voltage of the collector causes a conductive channel to appear in the collector P region 11, so that the electrons can flow through the conductive channel and directly flow into the collector metal electrode 15 without passing through the collector P region as in the conventional LIGBT, and thus the electrons are extracted without passing through the P region barrier, so that the extraction of the electrons is accelerated, and the turn-off time and turn-off loss of the device are effectively reduced. The N-buffer layer 1 region 12, the N-buffer layer 2 region 13 and the N-buffer layer 3 region 14 are introduced to form an auxiliary depletion region, so that the breakdown voltage of the device is improved, and a path is provided for the extraction of the electrons when the device is turned off.

[0011] The application will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 Fig. 1 is a schematic diagram of a three-dimensional structure of a multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction provided by the application;

[0013] Figure 2 Fig. 2 is a sectional view of the multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction provided by the application. DETAILED DESCRIPTION

[0014] The application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0015] The application aims to provide a multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction. The device can assist the P-type substrate to be depleted by using the multi-layer N-buffer structure, so that the breakdown voltage of the device is improved. In addition, the multi-layer N-buffer structure combined with the collector gate oxide structure can assist the extraction of electrons to accelerate the turn-off speed of the device and reduce the turn-off loss when the device is turned off.

[0016] Combination Figure 1 and Figure 2The application provides a multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction, which comprises an emitter P+ region 1, an emitter N+ region 2, an emitter P-well region 3, a P-type substrate region 4, an emitter metal electrode 5, a gate oxide layer 6, a gate metal electrode 7, an N-pillar drift region 8, a P-pillar drift region 9, a collector N-buffer region 10, a collector P region 11, an N-buffer layer 1 region 12, an N-buffer layer 2 region 13, an N-buffer layer 3 region 14, a collector metal electrode 15 and a collector gate oxide layer 16.

[0017] The P-type substrate region 4 is located at the lowermost part of the multi-layer N-buffer structure SJ-LIGBT device and has a stepped structure at one end; the emitter P-well region 3, the emitter P+ region 1, the emitter N+ region 2 and the emitter metal electrode 5 jointly form an emitter region at one end of the top of the device; the gate oxide layer 6 and the gate metal electrode 7 jointly form a gate metal region, which is arranged next to the emitter region; the N-pillar drift region 8 and the P-pillar drift region 9 are arranged in a staggered manner at the middle of the top of the device and jointly form a drift region; the collector N-buffer region 10, the collector P region 11, the N-buffer layer 1 region 12, the N-buffer layer 2 region 13, the N-buffer layer 3 region 14, the collector metal electrode 15 and the collector gate oxide layer 16 jointly form a collector region, which is arranged at the other end of the top of the multi-layer N-buffer structure SJ-LIGBT device.

[0018] The N-pillar drift region 8 and the P-pillar drift region 9 have the same shape and size, and have the same thickness as the emitter P-well region 3.

[0019] It is worth noting that the N-buffer layer 1 region 12, the N-buffer layer 2 region 13 and the N-buffer layer 3 region 14 form an auxiliary depletion region. The auxiliary depletion region formed by the multi-layer n-buffer structure can assist the P-type substrate to be depleted, thereby improving the breakdown voltage of the device. The collector N-buffer region 10, the collector P region 11, the collector metal electrode 15 and the collector gate oxide layer 16 form an electron extraction structure, and the multi-layer n-buffer structure combined with the collector electron extraction structure can assist in extracting electrons to accelerate the turn-off speed of the device and reduce the turn-off loss when the device is turned off.

[0020] Reference Figure 1 and Figure 2In the emitter region, the emitter P-well region 3 is located at the other end of the P-type substrate region 4, and surrounds the emitter P+ region 1 and the emitter N+ region 2 in an inverted L shape; the emitter P+ region 1 and the emitter N+ region 2 are adjacent to each other and are both located on the emitter P-well region 3; the emitter metal electrode 5 is located on the emitter P+ region 1 and the emitter N+ region 2.

[0021] Reference Figure 1 and Figure 2 In the gate metal region, the gate oxide layer 6 is located on the one end of the emitter P-well region 3 which protrudes in an inverted L shape, and the gate metal electrode 7 is located on the gate oxide layer 6.

[0022] Reference Figure 1 and Figure 2 In the collector region, the N-bufferlayer3 region 14 is located at the bottommost step of the emitter P+ region 1; the N-bufferlayer2 region 13 is located on the N-bufferlayer3 region 14; the N-bufferlayer1 region 12 is located on the N-bufferlayer2 region 13; the collector gate oxide layer 16 is located on the outside of the device, and the collector metal electrode 15 is located above the collector P region 11 and the collector gate oxide layer 16 and on the right side of the collector gate oxide layer 16, and surrounds the collector P region 11 and the collector gate oxide layer 16 in an inverted L shape.

[0023] In the embodiment of the present application, the directions are as follows: "up", "down", "thickness", "height" are from top to bottom along the direction of the emitter P+ region 1 to the P-type substrate region 4; "length", "left", "right" are from left to right along the direction of the emitter P+ region 1 to the collector P region 11; "width", "front", "back" are from front to back along the direction of the N-pillar drift region 8 to the P-pillar drift region 9.

[0024] In a specific embodiment of the present application, the length of the emitter P+ region 1 is 2 μm, the length of the emitter N+ region 2 is 2 μm, the length of the emitter P-well region 3 is 6 μm, the length of the P-type substrate region 4 is 74 μm, the length of the emitter metal electrode 5 is 4 μm, the length of the gate oxide layer 6 and the gate metal electrode 7 is 2 μm, the length of the N-pillar drift region 8 and the P-pillar drift region 9 is 60 μm, the length of the collector N-buffer region 10 is 5 μm, the length of the collector P region 11 is 4.5 μm, the length of the N-bufferlayer1 region 12 is 8 μm, the length of the N-bufferlayer2 region 13 is 6 μm, the length of the N-bufferlayer3 region 14 is 4 μm, the length of the collector metal electrode 15 is 4.6 μm, and the length of the collector gate oxide layer 16 is 0.1 μm.

[0025] In a specific embodiment of the present application, the thickness of the whole SJ-LIGBT device with multi-layer N-buffer structure is 100 μm, the thickness of the emitter P+ region 1 is 0.2 μm, the thickness of the emitter N+ region 2 is 0.2 μm, the thickness of the emitter P-well region 3 is 0.6 μm, the thickness of the P-type substrate region 4 is 99.4 μm, the thickness of the emitter metal electrode 5, the collector metal electrode 15, the gate oxide layer 6 and the gate metal electrode 7 is 0.1 μm, the thickness of the N-pillar drift region 8 and the P-pillar drift region 9 is 0.2 μm, the thickness of the collector N-buffer region 10 is 0.6 μm, the thickness of the collector P region 11 is 0.3 μm, the thickness of the N-bufferlayer1 region 12, the N-bufferlayer2 region 13 and the N-bufferlayer3 region 14 is 0.5 μm, and the thickness of the collector gate oxide layer 16 is 0.3 μm;

[0026] In the above embodiment, the width of the other regions of the SJ-LIGBT device with multi-layer N-buffer structure is 2 μm, and the width of the N-pillar drift region 8 and the P-pillar drift region 9 is 1 μm.

[0027] In a specific embodiment of the present application, the emitter P+ region 1 is P-type doped with a doping concentration of 1e19 cm-3, the emitter N+ region 2 is N-type doped with a doping concentration of 1e19 cm-3, the emitter P-well region 3 is P-type doped with a doping concentration of 1e16 cm-3, the P-type substrate region 4 is P-type doped with a doping concentration of 1e14 cm-3, the N-pillar drift region 8 and the P-pillar drift region 9 are N-type doped and P-type doped respectively with a doping concentration of 1e16 cm-3, the collector N-buffer region 10 is N-type doped with a doping concentration of 5e16 cm-3, the collector P region 11 is P-type doped with a doping concentration of 1e17 cm-3, the N-bufferlayer1 region 12 has a length of 8 μm, the N-bufferlayer2 region 13 has a length of 6 μm, the N-bufferlayer3 region 14 is N-type doped with a doping concentration of 1e16 cm-3. -3 -3 -3 -3 -3 -3 -3 -3 .

[0028] The working principle of the device of the present application is as follows:

[0029] ​​​​​​​When the device is forward conducting, the gate metal electrode 7 is connected to positive voltage, the emitter metal electrode 5 is connected to negative voltage, the collector metal electrode 15 is connected to positive voltage, and there is an electron extraction structure, i.e. the collector gate oxide layer 16 and the collector metal electrode 15, on the right side of the collector P region 11. Because the positive voltage is applied to the collector contact metal electrode 13, the holes in the part of the collector P region 11 contacting the collector gate oxide layer 16 are repelled, thus generating a conductive channel. The electrons flow from the conductive channel generated in the collector P region 11 and flow into the collector metal electrode 15 without passing through the PN junction barrier generated between the collector N-buffer region 10 and the collector P region 11, thus reducing the on-state voltage drop.

[0030] When the device is in voltage resistance, the gate metal electrode 7 is connected to negative voltage, the emitter metal electrode 5 is connected to negative voltage, and the collector metal electrode 15 is connected to positive voltage. Because there is a multi-layer N-buffer structure in the P-type substrate region 4, the multi-layer N-buffer structure and the P-type substrate region 4 are mutually depleted, which can effectively prevent the device from being vertically broken down, improve the vertical voltage resistance capability of the device, and realize full utilization of the substrate. In addition, the mutual depletion between the multi-layer N-buffer structure and the P-type substrate region 4 can also prevent the P-type substrate region 4 from affecting the mutual depletion between the N-pillar drift region 8 and the P-pillar drift region 9, thus improving the lateral voltage resistance capability of the device.

[0031] When the device is off, the gate metal electrode 7 changes from positive voltage to negative voltage, the emitter metal electrode 5 is connected to negative voltage, and the collector metal electrode 15 is connected to positive voltage. On the right side of the collector P region 11, there is an electron extraction structure, i.e. the collector gate oxide layer 16 and the collector metal electrode 15. Because the positive voltage is applied to the collector contact metal electrode 13, the holes in the part of the collector P region 11 contacting the collector gate oxide layer 16 are repelled, thus generating a conductive channel. When the device is off, the residual electrons remaining in the drift region can flow through the collector n-buffer region and the conductive channel and flow into the collector metal electrode 15 without passing through the PN junction barrier generated between the collector N-buffer region 10 and the collector P region 11. Compared with the traditional SJ-LIGBT structure, this structure provides an electron extraction conductive channel when the device is off, reduces the off-time, and reduces the off-loss when the device is off.

[0032] Although the present application is described herein in conjunction with various embodiments, those skilled in the art will understand and appreciate that other changes in the disclosed embodiments can be understood and implemented by referring to the attached drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality.

[0033] The above is further detailed description of the present application in combination with specific preferred embodiments, and cannot be deemed as limitation of the specific implementation of the present application to these descriptions. For those skilled in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, and all should be deemed as falling within the protection scope of the present application.

Claims

1. A multi-layer N-buffer structure SJ-LIGBT device accelerating electron extraction, characterized in that, Comprise: emitter P+ region (1), emitter N+ region (2), emitter P-well region (3), P-type substrate region (4), emitter metal electrode (5), gate oxide layer (6), gate metal electrode (7), N-pillar drift region (8), P-pillar drift region (9), collector N-buffer region (10), collector P region (11), N-buffer layer 1 region (12), N-buffer layer 2 region (13), N-buffer layer 3 region (14), collector metal electrode (15) and collector gate oxide layer (16); Wherein, the P-type substrate region (4) is located at the bottom of the multi-layer N-buffer structure SJ-LIGBT device, and one end is in trapezoidal structure; the emitter P-well region (3), emitter P+ region (1), emitter N+ region (2), emitter metal electrode (5) together constitute the emitter region located at one end of the top of the device; the gate oxide layer (6) and the gate metal electrode (7) constitute the gate metal region, which is arranged next to the emitter region; the N-pillar drift region (8) and the P-pillar drift region (9) are arranged horizontally staggered in the middle position of the top of the device to form a drift region; the collector N-buffer region (10), collector P region (11), N-buffer layer 1 region (12), N-buffer layer 2 region (13), N-buffer layer 3 region (14), collector metal electrode (15), collector gate oxide layer (16) together constitute the collector region, and are arranged at the other end of the top of the multi-layer N-buffer structure SJ-LIGBT device opposite to the emitter region.

2. The multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction according to claim 1, wherein, In the emitter region, the emitter P-well region (3) is located at the other end of the P-type substrate region (4), and is in inverse L shape to surround the emitter P+ region (1) and the emitter N+ region (2); the emitter P+ region (1) and the emitter N+ region (2) are next to each other and are located above the emitter P-well region (3); the emitter metal electrode (5) is located above the emitter P+ region (1) and the emitter N+ region (2).

3. The multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction according to claim 1, wherein, In the gate metal region, the gate oxide layer (6) is covered on the one end of the emitter P-well region (3) which is inverse L protruding, and the gate metal electrode (7) is covered on the gate oxide layer (6).

4. The multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction according to claim 1, wherein, In the collector region, the N-bufferlayer3 region (14) is arranged at the bottommost step of the emitter P+ region (1); the N-bufferlayer2 region (13) is arranged above the N-bufferlayer3 region (14); the N-bufferlayer1 region (12) is arranged above the N-bufferlayer2 region (13); the collector gate oxide layer (16) is arranged outside the device, and the collector metal electrode (15) is arranged above and right of the collector P region (11) and the collector gate oxide layer (16) in an inverse L shape to surround the collector P region (11) and the collector gate oxide layer (16).

5. The multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction according to claim 1, wherein, The length of the emitter P+ region (1) is 2 μm, the length of the emitter N+ region (2) is 2 μm, the length of the emitter P-well region (3) is 6 μm, the length of the P-type substrate region (4) is 74 μm, the length of the emitter metal electrode (5) is 4 μm, the length of the gate oxide layer (6) and the gate metal electrode (7) is 2 μm, the length of the N-pillar drift region (8) and the P-pillar drift region (9) is 60 μm, the length of the collector N-buffer region (10) is 5 μm, the length of the collector P region (11) is 4.5 μm, the length of the N-bufferlayer1 region (12) is 8 μm, the length of the N-bufferlayer2 region (13) is 6 μm, the length of the N-bufferlayer3 region (14) is 4 μm, the length of the collector metal electrode (15) is 4.6 μm, and the length of the collector gate oxide layer (16) is 0.1 μm.

6. The multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction according to claim 1, wherein, The thickness of the SJ-LIGBT device as a whole without considering the metal electrode is 100 μm, the thickness of the emitter P+ region (1) is 0.2 μm, the thickness of the emitter N+ region (2) is 0.2 μm, the thickness of the emitter P-well region (3) is 0.6 μm, and the thickness of the P-type substrate region (4) is 99.4 μm; the thickness of the emitter metal electrode (5), the collector metal electrode (15), the gate oxide layer (6) and the gate metal electrode (7) is 0.1 μm; the thickness of the N-pillar drift region (8) and the P-pillar drift region (9) is 0.2 μm, the thickness of the collector N-buffer region (10) is 0.6 μm, the thickness of the collector P region (11) is 0.3 μm, the thickness of the N-bufferlayer1 region (12), the N-bufferlayer2 region (13) and the N-bufferlayer3 region (14) is 0.5 μm, and the thickness of the collector gate oxide layer (16) is 0.3 μm. The width of other regions of the multi-layer N-buffer structure SJ-LIGBT device is 2 μm, except the N-pillar drift region (8) and the P-pillar drift region (9), and the width of the N-pillar drift region (8) and the P-pillar drift region (9) is 1 μm.

7. The multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction according to claim 1, wherein, The emitter P+ region (1) is P-type doped with a doping concentration of 1e19 cm -3 The emitter N+ region (2) is N-type doped with a doping concentration of 1e19 cm -3 The emitter P-well region (3) is P-type doped with a doping concentration of 1e16 cm -3 The P-type substrate region (4) is P-type doped with a doping concentration of 1e14 cm -3 The N-pillar drift region (8) and the P-pillar drift region (9) are N-type doped and P-type doped respectively with a doping concentration of 1e16 cm -3 The collector N-buffer region (10) is N-type doped with a doping concentration of 5e16 cm -3 The collector P region (11) is P-type doped with a doping concentration of 1e17 cm -3 The N-bufferlayer1 region (12) has a length of 8 μm, the N-bufferlayer2 region (13) has a length of 6 μm, and the N-bufferlayer3 region (14) is N-type doped with a doping concentration of 1e16 cm -3 .

8. The multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction according to claim 1, wherein, The N-bufferlayer1 region (12), the N-bufferlayer2 region (13), and the N-bufferlayer3 region (14) constitute an auxiliary depletion region.

9. The multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction according to claim 1, wherein, The collector N-buffer region (10), the collector P region (11), the collector metal electrode (15), and the collector gate oxide layer (16) constitute an electron extraction structure.

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