Trench structure and method of manufacturing the same, semiconductor device and method of manufacturing the same

Abstract

The embodiment of the present disclosure provides a trench structure and a preparation method thereof, and a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. The trench structure comprises: a trench located in a substrate; an oxide layer pattern located on the surface of the trench; a nitride layer pattern located on the oxide layer pattern and away from the surface of the trench; and a semiconductor film pattern located on the nitride layer pattern and away from the oxide layer pattern. The embodiment of the present disclosure is at least beneficial to improving hot electron induced punchthrough.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of semiconductor technology, and particularly relates to a trench structure and a preparation method thereof, and a semiconductor device and a preparation method thereof. BACKGROUND

[0002] With the increasing integration of semiconductor devices, the design rules of components of the semiconductor devices are constantly reduced. In particular, the gate length is constantly reduced, which can cause an additional hot electron induced punch through (HEIP) phenomenon, resulting in unexpected electrical performance of the semiconductor device. SUMMARY

[0003] The embodiments of the present disclosure provide a trench structure and a preparation method thereof, and a semiconductor device and a preparation method thereof, which can at least improve HEIP.

[0004] The embodiments of the present disclosure provide a trench structure, comprising: a trench located in a substrate; an oxide layer pattern located on a surface of the trench; a nitride layer pattern located on the oxide layer pattern and away from the surface of the trench; and a semiconductor film pattern located on the nitride layer pattern and away from the oxide layer pattern.

[0005] The embodiments of the present disclosure provide a preparation method of a trench structure, comprising: forming a trench in a substrate; forming an oxide layer on the substrate and a surface of the trench; forming a nitride layer on the oxide layer and away from the surface of the trench; and forming a semiconductor film on the nitride layer and away from the oxide layer.

[0006] The embodiments of the present disclosure provide a semiconductor device, comprising: a substrate; and a trench structure according to any one of the embodiments of the present disclosure.

[0007] The embodiments of the present disclosure provide a preparation method of a semiconductor device, comprising: providing a substrate; forming a trench in the substrate; forming an oxide layer on the substrate and a surface of the trench; forming a nitride layer on the oxide layer and away from the surface of the trench; and forming a semiconductor film on the nitride layer and away from the oxide layer. BRIEF DESCRIPTION OF DRAWINGS

[0008] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of the present disclosure. It is to be understood that the drawings are only schematic, and that they do not purport to be to scale with respect to one another. The embodiments will be described with reference to the drawings in conjunction with a detailed description.

[0009] Figure 1 (a) and Figure 1 (b) shows a plan view and a cross-sectional view in the B-B' direction (front view) of a semiconductor device.

[0010] Figure 2 shows a plan view of a semiconductor device.

[0011] Figure 3 shows Figure 2 a cross-sectional view in the A-A' direction.

[0012] Figure 4 shows Figure 2 a cross-sectional view in the B-B' direction.

[0013] Figure 5 shows a structural schematic diagram of a semiconductor device.

[0014] Figure 6 shows a schematic diagram of the relationship between electrostatic potential and action distance.

[0015] Figure 7 shows a schematic diagram of a trench structure provided by an embodiment of the present disclosure.

[0016] Figure 8 shows Figure 7 a schematic diagram of the principle of a trench structure provided.

[0017] Figure 9 shows Figure 7 a schematic diagram of the electrostatic field distribution of a trench structure provided.

[0018] Figure 10 shows Figure 7 another schematic diagram of the electrostatic field distribution of a trench structure provided.

[0019] Figure 11 shows a schematic diagram of a structure corresponding to one step in a preparation method of a trench structure provided by an embodiment of the present disclosure.

[0020] Figure 12 shows a schematic diagram of a structure corresponding to another step in a preparation method of a trench structure provided by an embodiment of the present disclosure.

[0021] Figure 13A structure corresponding to another step in the method of manufacturing the trench structure provided by the embodiment of the present disclosure is shown.

[0022] Figure 14 A structure corresponding to another step in the method of manufacturing the trench structure provided by the embodiment of the present disclosure is shown.

[0023] Figure 15 A structure corresponding to another step in the method of manufacturing the trench structure provided by the embodiment of the present disclosure is shown.

[0024] Figure 16 A structure corresponding to another step in the method of manufacturing the trench structure provided by the embodiment of the present disclosure is shown. Figure 7 A schematic diagram of the relationship between the electrostatic potential and the distance of the trench structure provided by the embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0025] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the present disclosure is not limited to the following description, and it can be modified in various ways without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the contents described in the following embodiments.

[0026] Further, in order to facilitate understanding, the position, size, and range, etc. of each structure shown in the drawings, etc. are not necessarily indicative of the actual position, size, and range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, and range, etc. disclosed in the drawings, etc.

[0027] Further, in the present specification, etc., first, second, etc. ordinal numbers are added for convenience, and they are not necessarily used to describe the order or the stacking order of the steps. Therefore, for example, "first" can be appropriately replaced with "second" or "third" or the like to be described. Further, the ordinal numbers described in the present specification, etc. and the ordinal numbers used to specify one embodiment of the present disclosure are not necessarily consistent.

[0028] In the present specification, for convenience, words such as "upper", "lower", etc. are used to describe the positional relationship of the components to explain the positional relationship of the components with reference to the drawings. In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the present specification, and can be appropriately changed according to the situation.

[0029] Note that in the present specification, etc., when the structure of the invention is described with reference to the drawings, the same symbol is sometimes used in common in different drawings to indicate the same part.

[0030] In this embodiment, a transistor refers to an element including at least a gate (gate electrode), a drain (drain electrode), and a source (source electrode). A transistor has a channel region between a drain and a source, and current can flow through the drain, the channel region, and the source. The channel region refers to a region where current flows mainly. In this embodiment, a thin film transistor is a kind of field effect transistor.

[0031] In addition, the functions of the source and the drain are sometimes interchanged with each other in the case of using transistors of different polarities or in the case where the direction of current flow in a circuit is changed, for example. Therefore, in this embodiment, the source and the drain can be interchanged with each other.

[0032] Note that the channel length refers to, for example, the distance between the source and the drain in a region where the semiconductor layer (or a portion of the semiconductor layer through which current flows when the transistor is in an on state) and the gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed.

[0033] In this embodiment, "electrically connected" includes the case where "an element having a certain function" is connected. Here, "an element having a certain function" is not particularly limited as long as it can transmit and receive an electrical signal between objects to be connected. For example, "an element having a certain function" includes not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and an element having another function.

[0034] Reference Figures 1 to 4 is a model diagram of a trench structure (e.g., STI (shallow trench isolation) 4) inducing HEIP. Here, a semiconductor device is exemplified as a PMOS (Positive Channel Metal Oxide Semiconductor, a MOS transistor in which an n-type substrate and a p-channel are used, which means that holes are used for current transport). 2 represents a drain of the PMOS, 1 represents a gate of the PMOS, 3 represents a source of the PMOS, 4 represents an STI, 41 represents a sidewall oxide in the STI, and 42 represents a Si3N4 liner in the STI, which is an electron trap.

[0035] STI is mostly ONO (i.e. oxide layer-nitride layer-oxide layer) structure, where the oxide layer can be, for example, silicon dioxide, and the nitride layer can be, for example, silicon nitride, but not limited thereto. Due to the electron trapping at the ON interface within the STI, holes are concentrated in the active area (AA) near the STI, causing HEIP. The electrons trapped at the top region of the ON interface of the STI cause the Vth of the active edge of the transistor to decrease, thus causing the off-state current (Ioff) of the active edge transistor to increase. off ) increase.

[0036] Figure 3 and Figure 4 The circled "+" represents hole (h+ hereinafter), and the circled "-" represents electron (e- hereinafter).

[0037] Figure 5 A structure diagram of a semiconductor device is shown.

[0038] As shown in Figure 5 , 500 represents PMOS, 501 represents the gate of PMOS, 502 represents the drain of PMOS, 503 represents the source of PMOS, and 504 represents STI.

[0039] It can be known from Figure 5 that the ON interface within the STI 504 traps electrons, so that the boundary of the STI 504 and the gate 501 accumulates electrons, causing the electrostatic potential of the boundary of the drain 502 and the gate 501 to decrease, and holes to accumulate.

[0040] The trapping of electrons decreases the electrostatic potential of the PMOS channel near the side of the trap electron one, and the Boltzmann factor can be used to know that the channel accumulates holes near the side of the trap electron one.

[0041] In physics, the Boltzmann factor is a weighting factor that determines the relative probability of states i in a multi-state system at thermal equilibrium at temperature T where k B is Boltzmann's constant, and E i is the energy of state i. The ratio of the probabilities of two states is given by the ratio of their Boltzmann factors.

[0042] Figure 6From the Fermi level perspective, the Fermi level is expressed as follows:

[0043]

[0044] where, is the standard state, only related to the material (assuming all carriers are electrons). Therefore, N-type, P-type and intrinsic semiconductors have the same standard chemical potential. is called the concentration term, sometimes can be replaced by a more accurate activity term (activity term), a represents the activity of electrons in the alpha phase. -φ α is the electrostatic energy of a single electron in the alpha phase. k is the Boltzmann constant. is the electron concentration in the alpha phase.

[0045] Capturing electrons reduces the electrostatic potential of the PMOS channel near the side of the captured electrons, in order to meet the equal Fermi level at any position, it is necessary to have less electron concentration near the side of the captured electrons to reduce the electrostatic potential at any position X e X h is a constant, X e and X h respectively represent the electron concentration and hole concentration, resulting in the accumulation of holes in the channel near the side of the captured electrons.

[0046] Figure 6 The relationship between the electrostatic potential and the action distance is shown in the schematic diagram. E p represents the electrostatic potential of the PMOS channel near the side of the captured electrons, r represents the distance between the top region of the captured electrons in the ON interface in the STI and the active region. From Figure 6 it can be seen that according to Coulomb's law, the electrostatic potential E p is inversely proportional to the square of the distance r, and the electrostatic potential E p rapidly decays with the increase of the action distance r.

[0047] The trench structure and the preparation method thereof provided by the embodiments of the present disclosure can reduce the influence of the captured electrons on the electrostatic potential of the channel near the side of the captured electrons, thereby reducing the accumulation of holes in the channel near the side of the captured electrons, and achieving the purpose of improving HEIP.

[0048] Figure 7A schematic diagram of a trench structure provided by an embodiment of the present disclosure is shown.

[0049] As shown in Figure 7 , the trench structure provided by an embodiment of the present disclosure includes a trench 100, an oxide layer pattern 310, a nitride layer pattern 320, and a semiconductor film pattern 330.

[0050] The trench 100 can be located in a substrate 200. The oxide layer pattern 310 can be located on the surface of the trench 100. Specifically, the surface of the trench 100 can include a bottom surface 100B and two side surfaces 100S, and the oxide layer pattern 310 can be located on the bottom surface 100B and the two side surfaces 100S of the trench 100.

[0051] The trench structure formed in an embodiment of the present disclosure can be located in a substrate and used to define an active region.

[0052] In an embodiment of the present disclosure, the oxide layer pattern 310 can conformally cover the bottom surface 100B and the two side surfaces 100S of the trench 100, and the upper surface of the substrate 100. The nitride layer pattern 320 can conformally cover the surface of the oxide layer pattern 310 away from the trench 100.

[0053] The nitride layer pattern 320 can be located on the oxide layer pattern 310 and away from the surface of the trench 100. The semiconductor film pattern 330 can be located on the nitride layer pattern 320 and away from the oxide layer pattern 310.

[0054] In some embodiments, the upper surface of the semiconductor film pattern 330 can be flush with the upper surface of the nitride layer pattern 320. However, the present disclosure is not limited thereto.

[0055] The trench structure provided by an embodiment of the present disclosure can, on the one hand, reduce the accumulation of positive charges near the side capturing electrons by adding a semiconductor film pattern on the side of the nitride layer pattern of the trench structure away from the substrate, thereby improving the heat electron induced punch through (HEIP) phenomenon. On the other hand, since the semiconductor film pattern is added on the side of the nitride layer pattern of the trench structure away from the substrate, the distance between the semiconductor film pattern and the active region in the substrate can be increased, in particular, the distance between the semiconductor film pattern and the drain region (corresponding to the drain electrode of the semiconductor device) in the active region, thereby preventing the semiconductor film pattern and the drain region of the active region from forming a parasitic capacitance, reducing the delay, and reducing the loss.

[0056] Continuing to refer to Figure 7 , the trench structure can further include an insulating layer pattern 340. The insulating layer pattern 340 can be located on the semiconductor film pattern 330 and away from the nitride layer pattern 320.

[0057] In an exemplary embodiment, the insulating layer pattern 340 includes an oxide, i.e., the STI is an ONO structure. In embodiments of this disclosure, the insulating layer pattern 340 and the oxide layer pattern 310 may include the same oxide, for example, both including silicon dioxide, but this disclosure is not limited thereto.

[0058] In an exemplary embodiment, the insulating layer pattern 340 fills the trench 100.

[0059] In an exemplary embodiment, the semiconductor film pattern 330 includes a P-type doped or N-type doped semiconductor material.

[0060] In an exemplary embodiment, the semiconductor film pattern 330 includes polysilicon.

[0061] The semiconductor film pattern 330 in this embodiment may include any semiconductor material, including polycrystalline silicon.

[0062] For example, N-type doped semiconductor materials can be polycrystalline silicon doped with pentavalent impurity elements (such as phosphorus, arsenic, etc.). In N-type doped semiconductor materials, free electrons are the majority carriers and holes are the minority carriers. P-type doped semiconductor materials can be polycrystalline silicon doped with trivalent impurity elements (such as boron, gallium, etc.). In P-type doped semiconductor materials, holes are the majority carriers and free electrons are the minority carriers.

[0063] In an exemplary embodiment, the trench structure is a shallow trench isolation structure. In the following embodiments, the trench structure is exemplified as an STI (Shallow Trench Isolation Structure), but this disclosure is not limited thereto.

[0064] The trench structure provided in this disclosure, on the one hand, reduces the impact of trapped electrons on the electrostatic potential of the PMOS channel, thereby reducing the accumulation of holes on the side of the PMOS channel near the trapped electrons and thus improving the hot electron-induced punch-through (HEIP) phenomenon. On the other hand, the semiconductor film pattern added in this disclosure is farther away from the active region in the substrate, thereby preventing the semiconductor film pattern from forming parasitic capacitance with the drain region of the active region, thus reducing delay and loss.

[0065] Figure 8 It shows Figure 7 A schematic diagram of the provided trench structure. (For example...) Figure 8 As shown, on the side of the Oxide-Nitride interface (i.e., the ON interface, where the ON interface refers to the interface between the nitride layer pattern 320 and the insulating layer pattern 340, where the insulating layer pattern 340 contains oxide), an introduction is made... Figure 8The dipoles with the indicated orientation (i.e., semiconductor film pattern 330) increase the potential barrier for electron trapping in the interface region, that is, trapping electrons at the Oxide-Nitride interface, causing the semiconductor film pattern 330 to be closer to the end where the trapped electrons are located (e.g., ...). Figure 8 As shown, terminal A is located in the top region of the ON interface, which is the location where electrons are captured, and holes are accumulated.

[0066] Figure 8 E shown c E represents the conduction band edge, also known as the bottom of the conduction band. It is the energy space formed by free electrons, that is, the energy range possessed by freely moving electrons within a fixed structure. v This refers to the valence band edge (valence band apex). Electrons in atomic orbitals that are bonded are called valence electrons. The many energy levels occupied by these valence electrons can be grouped together as a single, continuous energy range. This low-energy band formed by the energy levels of filled atomic orbitals is called the valence band (filled band). Any energy change usually occurs within the valence band.

[0067] Assume that the insulating layer pattern 340 contains silicon dioxide (SiO2). When hot electrons cross the potential barriers and are trapped at the interface between the silicon dioxide and nitride layer patterns 320, the electric potential (denoted by φ) at terminal A decreases. To ensure that the Fermi level is equal at any location, a positive charge (provided by a location farther from the trapped electron) accumulates at terminal A. The positive charge at terminal A counteracts the effect of electron trapping on the PMOS channel potential. In embodiments of this disclosure, the positive charge accumulated at terminal A can be positively charged holes or fixed positive charges, depending on the doping type of the semiconductor film pattern.

[0068] Figure 9 It shows Figure 7 A schematic diagram of the electrostatic field distribution of the provided trench structure. Figure 9 In this diagram, X represents the channel from the drain, and Y represents the electric potential (electrostatic potential E). p ).from Figure 9 It can be seen that as the electrostatic potential decreases, holes accumulate at the interface near the drain in the channel. However, the electrostatic potential at the interface between the source and the gate remains unchanged.

[0069] Figure 10 It shows Figure 7 Another schematic diagram of the electrostatic field distribution of the provided trench structure. Figure 10 In the diagram, X' represents the distance from point A, combined with the above...Figure 8 , assuming A is the origin of the X' axis and B is the B point of the X' axis, Y represents electric potential.

[0070] The HEIP is due to the STI capturing a negative charged electron, which in turn affects the channel electrostatic potential distribution, resulting in the accumulation of holes on the side close to the captured electron, equivalent to the channel length being reduced. The trench structure provided by the embodiments of the present disclosure introduces a semiconductor film pattern between the nitride layer pattern and the insulating layer pattern in the STI. When the STI captures an electron, the semiconductor film pattern close to the region where the electron is captured will accumulate positive charges, thereby weakening the influence of the captured electron on the active region electrostatic potential and improving the HEIP effect. At the same time, since the semiconductor film pattern is separated from the active region by the Oxide-Nitride insulating film, the semiconductor film will not be in contact with the conductive structure on the substrate, thereby ensuring the reliability of the semiconductor device.

[0071] The embodiments of the present disclosure also provide a preparation method of a trench structure, comprising: forming a trench in a substrate; forming an oxide layer on the surface of the substrate and the trench; forming a nitride layer on the oxide layer, and the nitride layer being away from the surface of the trench; forming a semiconductor film on the nitride layer, and the semiconductor film being away from the oxide layer.

[0072] In exemplary embodiments, the preparation method of the trench structure provided by the embodiments of the present disclosure can further comprise: forming an insulating layer on the semiconductor film, and the insulating layer being away from the nitride layer.

[0073] In exemplary embodiments, the preparation method of the trench structure provided by the embodiments of the present disclosure can further comprise: performing a planarization treatment on the trench structure to form an oxide layer pattern, a nitride layer pattern, a semiconductor film pattern and an insulating layer pattern of the trench structure from the oxide layer, the nitride layer, the semiconductor film and the insulating layer respectively, and the surface height of the trench structure being flush with the surface height of the substrate.

[0074] The preparation method of the trench structure provided by the embodiments of the present disclosure, on the one hand, by adding a semiconductor film pattern on the side of the nitride layer pattern of the trench structure away from the substrate, the accumulation of positive charges on the side close to the captured electron can be reduced, thereby improving the HEIP phenomenon; on the other hand, since the semiconductor film pattern is added on the side of the nitride layer pattern of the trench structure away from the substrate, the distance between the semiconductor film pattern and the active region in the substrate can be increased, in particular, the distance between the semiconductor film pattern and the drain region (corresponding to the drain of the semiconductor device) in the active region, thereby preventing the semiconductor film pattern and the drain region of the active region from forming a parasitic capacitance, reducing the delay and loss.

[0075] The following is combined with Figures 11 to 15 The method for preparing the trench structure provided in the embodiments of this disclosure is illustrated by example, but this disclosure is not limited thereto.

[0076] like Figure 11 As shown, the fabrication of STI is illustrated here. First, a substrate 200 is provided, such as a silicon substrate, but this disclosure is not limited to this. Then, the substrate 200 is etched to form trenches 100 in the substrate. Dry etching or wet etching can be used, and this disclosure does not limit the etching method. The etched trenches 100 may include a bottom surface 100B and two side surfaces 100S. In the embodiments of this disclosure, the etched trenches 100 may be an inverted trapezoid, i.e., the width of the upper surface is greater than the width of the lower surface, but this disclosure is not limited to this. The width refers to the direction parallel to the upper surface of the substrate 100.

[0077] like Figure 12 As shown above, in the above Figure 11 Based on the formed trench 100, an oxide layer 310a is deposited on the bottom surface 100B and the two side surfaces 100S of the trench 100, as well as the upper surface of the substrate 200. The oxide layer 310a conformally covers the bottom surface 100B and the two side surfaces 100S of the trench 100, as well as the upper surface of the substrate 200, without completely filling the trench 100.

[0078] like Figure 13 As shown above, in the above Figure 12 Based on the formed trench 100 containing oxide layer 310a, a nitride layer 320a is further deposited on the bottom surface, two side surfaces, and top surface of oxide layer 310a. The nitride layer 320a can conformally cover the bottom surface, two side surfaces, and top surface of oxide layer 310a, without completely filling trench 100.

[0079] like Figure 14 As shown above, in the above Figure 13 Based on this, a semiconductor film 330a is deposited on the bottom surface and two side surfaces of the nitride layer 320a. The semiconductor film 330a does not completely fill the trench 100. The upper surface of the semiconductor film 330a can be flush with the upper surface of the nitride layer 320a, that is, the upper surface of the nitride layer 320a is not covered by the semiconductor film 330a.

[0080] like Figure 15 As shown above, in the above Figure 14 Based on this, an insulating layer is then filled into the remaining gaps in trench 100, i.e., an insulating layer is applied to the bottom and side surfaces of the semiconductor film 330a, with the insulating layer located away from the nitride layer 320a. (Continue to refer to...) Figure 15After that, the trench structure can be planarized, for example, a CMP (Chemical Mechanical Polishing) operation is performed to remove part of the oxide layer 310a, the nitride layer 320a, the semiconductor film 330a and the insulating layer, expose the upper surface of the substrate 200, so that the upper surfaces of the oxide layer 310a, the nitride layer 320a, the semiconductor film 330a and the insulating layer are flush with the exposed upper surface of the substrate 200, and the oxide layer pattern 310, the nitride layer pattern 320, the semiconductor film pattern 330 and the insulating layer pattern 340 of the trench structure are formed, and the surface height of the trench structure is flush with the surface height of the substrate 200.

[0081] In the embodiments of the present disclosure, any one or more deposition processes can be used to deposit the oxide layer 310a, the nitride layer 320a, the semiconductor film 330a and the insulating layer, such as PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), ALD (atomic layer deposition) and the like. PVD is a technology that uses physical methods to vaporize the surface of a material source (solid or liquid) into gaseous atoms, molecules or partially ionized ions, and then deposits a thin film with certain special functions on the surface of the substrate through a low-pressure gas (or plasma) process. CVD is a method of generating a thin film on the surface of a substrate by chemical reaction of one or more gas-phase compounds or elements containing thin film elements. With the increasing integration and decreasing size of integrated circuits, high-k gate dielectrics gradually replace traditional silicon oxide gates, and the aspect ratio is getting larger and larger, so the step coverage capability of the deposition technology is also higher and higher. Therefore, ALD, as a new deposition process that can meet the above requirements, has been increasingly adopted. ALD is a method of alternately passing gas-phase precursors into a reactor and chemically adsorbing and reacting on the deposition substrate to form a deposition film. Unlike CVD, the reaction precursors are alternately deposited during the deposition process, and the chemical reaction of a new atomic film is directly associated with the previous layer. This way only one atomic layer is deposited each time.

[0082] The preparation method of the trench structure provided by the embodiments of the present disclosure can weaken the influence of the captured electrons on the electrostatic potential of the PMOS channel, thereby reducing the accumulation of holes on the side of the PMOS channel close to the captured electrons, and thus improving the HEIP phenomenon of hot electron-induced punchthrough. On the other hand, the semiconductor film pattern added by the embodiments of the present disclosure is farther away from the active region in the substrate, thereby preventing the semiconductor film pattern and the drain region of the active region from forming a parasitic capacitance, and thus reducing the delay and loss.

[0083] Further, the semiconductor device provided by the embodiment of the present disclosure comprises: a substrate; and the trench structure according to any one of the embodiments of the present disclosure.

[0084] In an example embodiment, the substrate further comprises an active region between adjacent trench structures. The distance between the semiconductor film pattern and the active region is greater than a preset threshold.

[0085] In an example embodiment, the preset threshold is 2 μm.

[0086] Figure 16 The relationship between the electrostatic potential of the trench structure and the distance is shown. Figure 7 The relationship between the electrostatic potential of the trench structure and the distance is shown.

[0087] From Figure 16 It can be seen that if the distance between the semiconductor film pattern and the active region is less than the preset threshold, the semiconductor film pattern in the STI will induce charges (response charges to the active region AA potential) even if the STI does not capture electrons, at this time the semiconductor film pattern and the drain region (drain) in the active region AA form a parasitic capacitance, which increases the delay (delay) and increases the power consumption. The semiconductor film in the STI and the active region, especially the drain region in the active region, can be avoided to form a parasitic capacitance by setting the distance between the semiconductor film pattern added in the STI and the active region to be greater than the preset threshold, so as to reduce the time delay, reduce the power consumption, and improve the performance of the semiconductor device.

[0088] In an example embodiment, the semiconductor device comprises a P-type metal-oxide-semiconductor field-effect transistor.

[0089] The semiconductor device in the embodiment of the present disclosure can be a semiconductor storage device, that is, a semiconductor device having a storage function or capable of being used to assist in forming a storage function, for example, a PMOS in an array region, a core region or a peripheral region of a DRAM (Dynamic Random Access Memory).

[0090] Further, the embodiment of the present disclosure further provides a preparation method of a semiconductor device, comprising: providing a substrate; forming a trench in the substrate; forming an oxide layer on the surface of the substrate and the trench; forming a nitride layer on the oxide layer, and the nitride layer is away from the surface of the trench; forming a semiconductor film on the nitride layer, and the semiconductor film is away from the oxide layer.

[0091] In an example embodiment, the preparation method of the semiconductor device provided by the embodiment of the present disclosure can further comprise: forming an insulating layer on the semiconductor film, and the insulating layer is away from the nitride layer.

[0092] In the example embodiment, the method for manufacturing a semiconductor device further comprises: performing a planarization process to form an oxide layer pattern, a nitride layer pattern, a semiconductor film pattern and an insulating layer pattern of the trench structure respectively from the oxide layer, the nitride layer, the semiconductor film and the insulating layer, and the surface height of the trench structure is flush with the surface height of the substrate.

[0093] The method for manufacturing a semiconductor device provided by the example embodiment can reduce the accumulation of positive charges near the side of capturing electrons, thereby improving the HEIP phenomenon, by adding the semiconductor film pattern on the side of the nitride layer pattern of the trench structure away from the substrate. In addition, the distance between the semiconductor film pattern and the active region in the substrate, especially the distance between the semiconductor film pattern and the drain region (corresponding to the drain of the semiconductor device) in the active region, can be increased by adding the semiconductor film pattern on the side of the nitride layer pattern of the trench structure away from the substrate, thereby preventing the semiconductor film pattern and the drain region of the active region from forming a parasitic capacitance, reducing the time delay and power loss.

[0094] The switching characteristics of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) are derived from the "Vg regulated surface potential" to achieve the purpose of controlling the channel carrier concentration. Vg represents the gate voltage of MOSFET. Therefore, in addition to the gate to bulk (strictly speaking, Cox (oxide capacitance per unit area)) capacitance, the remaining capacitances are redundant and harmful, which are called parasitic capacitances (para.cap. for short). The trench structure and the method for manufacturing the same, the semiconductor device and the method for manufacturing the same provided by the example embodiment can reduce the time delay and power loss by avoiding the parasitic capacitance formed by the semiconductor film pattern in the STI and the active region.

[0095] In the description of the present specification, the description referring to the terms "some embodiments", "exemplarily", and the like means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples without contradiction.

[0096] Although the embodiments of the present disclosure have been shown and described above, it is understood that the above-described embodiments are exemplary, and are not to be construed as limiting the present disclosure, and those skilled in the art can make changes, modifications, replacements and variations to the above-described embodiments within the scope of the present disclosure, and any changes or modifications made in accordance with the claims and the specification of the present disclosure shall be within the scope of the present disclosure.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate; a shallow trench isolation structure in the substrate, and defining an active region in the substrate, the active region being between adjacent shallow trench isolation structures, the active region comprising a drain, a source, and a channel between the drain and the source, the shallow trench isolation structure reducing the electrostatic potential of the channel near the side capturing electrons; a gate over the channel of the active region and over the shallow trench isolation structure; wherein the shallow trench isolation structure comprises: an oxide layer pattern on the surface of the trench of the shallow trench isolation structure, and in contact with the active region; a nitride layer pattern on the oxide layer pattern, and away from the surface of the trench; a semiconductor film pattern comprising polysilicon on the nitride layer pattern, and away from the oxide layer pattern, the semiconductor film pattern being more than 2 μm away from the active region; an insulating layer pattern comprising oxide, the insulating layer pattern filling the remaining space of the trench, the insulating layer pattern being on the semiconductor film pattern, and away from the nitride layer pattern; a surface height of the shallow trench isolation structure comprising the oxide layer pattern, the nitride layer pattern, the semiconductor film pattern, and the insulating layer pattern being flush with a surface height of the substrate.

2. The semiconductor device according to claim 1, wherein: the semiconductor device comprises a P-type metal-oxide-semiconductor field-effect transistor.

3. The semiconductor device according to claim 1, wherein: the semiconductor film pattern comprises a P-type doped or N-type doped semiconductor material.

4. A method of manufacturing a semiconductor device, characterized by The semiconductor device comprises: providing a substrate, and forming a shallow trench isolation structure in the substrate, the shallow trench isolation structure defining an active region, the active region comprising a drain, a source, and a channel between the drain and the source, the shallow trench isolation structure reducing the electrostatic potential of the channel near the side capturing electrons; forming a gate over the channel and over the shallow trench isolation structure; forming the shallow trench isolation structure comprises: forming trenches in the substrate, the substrate portions between adjacent trenches being the active region; forming an oxide layer on the substrate and on the surfaces of the trenches; forming a nitride layer on the oxide layer, and the nitride layer being away from the surfaces of the trenches; forming a semiconductor film comprising polysilicon on the nitride layer, and the semiconductor film being away from the oxide layer, the semiconductor film being more than 2 μm away from the active region; filling an insulating layer comprising oxide in the remaining space of the trenches, the insulating layer being on the semiconductor film, and away from the nitride layer; planarizing the shallow trench isolation structure to form an oxide layer pattern, a nitride layer pattern, a semiconductor film pattern, and an insulating layer pattern of the shallow trench isolation structure from the oxide layer, the nitride layer, the semiconductor film, and the insulating layer respectively, and a surface height of the shallow trench isolation structure being flush with a surface height of the substrate.

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