An enhanced GaN longitudinal field effect transistor with reverse freewheeling capability

Abstract

The present application belongs to the technical field of power semiconductor, and relates to an enhanced GaN longitudinal field effect transistor with reverse freewheeling capability. The main feature of the present application is that when etching a P-GaN layer, the P-GaN layer under a gate is reserved, so that the enhanced GaN longitudinal field effect transistor is realized, and meanwhile, part of the unetched P-GaN layer at the other end of the device is reserved to form contact with a source metal, so as to integrate a freewheeling diode with an anode and a source short-circuit and a cathode and a drain short-circuit. The freewheeling diode is only turned on in a reverse conduction mode, and is turned off in a forward conduction mode and a blocking mode, and does not affect the forward characteristics of the device. Compared with a freewheeling diode connected in reverse parallel outside the device, the present application reduces parasitic parameters, improves power density, and is simple in process and easy to implement.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductor, and relates to an enhanced GaN longitudinal field effect transistor with reverse freewheeling capability. BACKGROUND

[0002] Compared with GaN HEMT transverse devices, GaN longitudinal field effect transistors have smaller chip area and can realize higher power density at the same voltage level. However, the weak reverse freewheeling capability is one of the main problems restricting the practical application of the GaN longitudinal field effect transistors. To solve this problem, a freewheeling diode is usually connected in parallel outside the device, or a Schottky contact is formed between the source and the semiconductor, however, these methods will introduce additional parasitic parameters such as capacitance and inductance, or increase the leakage current of the device in the off state, thereby reducing the reliability of the device. SUMMARY

[0003] The application is based on the need of application of the GaN longitudinal field effect transistor, and provides an enhanced GaN longitudinal field effect transistor with reverse freewheeling capability. The P-GaN layer is etched, the P-GaN layer under the gate is reserved, the enhanced type is realized, and part of the unetched P-GaN layer at the other end of the device is reserved to form a contact with the source metal, so as to integrate a freewheeling diode with anode and source short circuit and cathode and drain short circuit.

[0004] To realize the above-mentioned application purposes, the technical scheme of the application is as follows:

[0005] An enhanced GaN longitudinal field effect transistor with reverse freewheeling capability, comprising a first conductive material 1, a substrate 2, a drift region 3, a barrier layer 5 and a dielectric passivation layer 6 arranged in sequence along the vertical direction of the device; the upper end of the device is respectively provided with a second conductive material 71 and a fourth conductive material 72, and the lower end of the second conductive material 71 and the fourth conductive material 72 extends downward, and extends into the drift region 3 after sequentially penetrating the dielectric passivation layer 6 and the barrier layer 5; the upper surface of the barrier layer 5 between the second conductive material 71 and the fourth conductive material 72 is provided with a first P-GaN layer 91 and a second P-GaN layer 92, and the first P-GaN layer 91 and the second P-GaN layer 92 are wrapped by the dielectric passivation layer 6, wherein the first P-GaN layer 91 is located on the side close to the second conductive material 71, and has a spacing between each other; the drift region 3 is also respectively provided with a first P-GaN buried layer 41 and a second P-GaN buried layer 42, the upper end of the first P-GaN buried layer 41 and the second P-GaN buried layer 42 has a spacing with the upper end of the drift region 3, and the upper end of the first P-GaN buried layer 41 on one side is in contact with the lower end of the second conductive material 71, and the upper end of the first P-GaN buried layer 41 on the other side extends to be located directly below part of the first P-GaN layer 91, the upper end of the second P-GaN buried layer 42 on one side is in contact with the lower end of the fourth conductive material 72, and the upper end of the second P-GaN buried layer 42 on the other side extends to be located directly above part of the second P-GaN layer 92; the upper surface of the first P-GaN layer 91 is provided with a third conductive material 8, and the part of the third conductive material 8 beyond the upper surface of the dielectric passivation layer 6 extends on both sides; the side of the fourth conductive material 72 close to the second P-GaN layer 92 extends to the upper surface of the second P-GaN layer 92, and the terminal end extends downward to contact the upper surface of the second P-GaN layer 92.

[0006] The first conductive material 1 forms an ohmic contact with the GaN substrate 2 to lead out the drain; the second conductive material 71 forms an ohmic contact with the drift region 3 to lead out the source; the third conductive material 8 leads out the gate; the fourth conductive material 72 forms an ohmic contact with the drift region 3 to lead out the source.

[0007] Further, the lower end of the second conductive material 71 is embedded into the upper end of the first P-GaN buried layer 41; the lower end of the fourth conductive material 72 is embedded into the upper end of the second P-GaN buried layer 42.

[0008] Further, the lateral width of the part of the third conductive material 8 on the upper surface of the dielectric passivation layer 6 is less than the lateral width of the first P-GaN layer 91.

[0009] Further, the extended part of the fourth conductive material 72 is in contact with the middle part of the upper surface of the second P-GaN layer 92.

[0010] Further, the material of the substrate 2 is one of sapphire, Si, SiC, AlN, GaN, AlGaN, ZnO and GaAs.

[0011] Further, the material of the barrier layer 5 is one or a combination of several of AlN, AlGaN, InGaN and InAlN.

[0012] Further, the material of the dielectric passivation layer 6 is one of SiNx, SiO2, Al2O3 and AlN.

[0013] The integrated freewheeling diode overcomes the problems of large leakage current and introduction of additional parasitic capacitance and inductance in the off state of the device, and only opens in the reverse conduction, and is in the off state in the forward conduction and blocking mode, and does not affect the forward characteristics of the device, and realizes the integration of the freewheeling diode while enhancing the device, and has low process difficulty and is easy to realize. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a structural schematic diagram of Example 1. DETAILED DESCRIPTION

[0015] The technical solutions of the present application will be described in detail below in combination with the drawings and examples:

[0016] Example 1

[0017] As Figure 1As shown, an enhanced GaN longitudinal field effect transistor with reverse freewheeling capability includes a first conductive material 1, a substrate 2, a drift region 3, a potential barrier layer 5 and a dielectric passivation layer 6 arranged in sequence in the vertical direction of the device; the upper end of the device has a second conductive material 71 and a fourth conductive material 72 respectively, and the lower end of the second conductive material 71 and the fourth conductive material 72 extends downward, and extends into the drift region 3 after penetrating the dielectric passivation layer 6 and the potential barrier layer 5 in sequence; the upper surface of the potential barrier layer 5 between the second conductive material 71 and the fourth conductive material 72 has a first P-GaN layer 91 and a second P-GaN layer 92, and the first P-GaN layer 91 and the second P-GaN layer 92 are wrapped by the dielectric passivation layer 6, wherein the first P-GaN layer 91 is located on the side close to the second conductive material 71, and has a spacing between each other; the drift region 3 also has a first P-GaN buried layer 41 and a second P-GaN buried layer 42 respectively, the upper end of the first P-GaN buried layer 41 and the second P-GaN buried layer 42 has a spacing with the upper end of the drift region 3, and the upper end of the first P-GaN buried layer 41 on one side contacts the lower end of the second conductive material 71, and the upper end of the first P-GaN buried layer 41 on the other side extends to be located directly below part of the first P-GaN layer 91, the upper end of the second P-GaN buried layer 42 on one side contacts the lower end of the fourth conductive material 72, and the upper end of the second P-GaN buried layer 42 on the other side extends to be located directly below part of the second P-GaN layer 92; the upper surface of the first P-GaN layer 91 has a third conductive material 8, and the part of the third conductive material 8 beyond the upper surface of the dielectric passivation layer 6 extends on both sides; the side of the fourth conductive material 72 close to the second P-GaN layer 92 extends to the upper side of the second P-GaN layer 92, and the terminal end extends downward to contact the upper surface of the second P-GaN layer 92;

[0018] The first conductive material 1 forms an ohmic contact with the GaN substrate 2 to lead out the drain; the second conductive material 71 forms an ohmic contact with the drift region 3 to lead out the source; the third conductive material 8 leads out the gate; and the fourth conductive material 72 forms an ohmic contact with the drift region 3 to lead out the source.

[0019] The working principle of the present application is that during reverse freewheeling, the source is at a high potential relative to the drain, a 2DEG channel is formed below the second P-GaN layer, and the PN junction formed by the second P-GaN buried layer and the drift region is in a positive bias state, and the depletion region formed between the two is contracted, so that a conductive path is formed between the source and the drain, and the current flows from the source to the drain through the 2DEG channel and the drift region.

[0020] When the device is forward biased, the 2DEG channel under the gate is turned on, and the current flows from the drain through the drift region and then through the channel to the source. At this time, the 2DEG in the channel under the second P-GaN layer is depleted, and the PN junction formed by the second P-GaN buried layer and the drift region is in a reverse-biased state. The depletion regions formed by the two overlap, blocking the conduction path, and do not affect the forward characteristics of the device.

[0021] When the device is forward biased, the 2DEG in the channel under the first P-GaN layer is depleted, and the PN junction formed by the first P-GaN buried layer and the drift region is in a reverse-biased state. The depletion regions formed by the two overlap, blocking the conduction path. Similarly, the 2DEG in the channel under the second P-GaN layer is depleted, and the PN junction formed by the second P-GaN buried layer and the drift region is in a reverse-biased state. The depletion regions formed by the two overlap, blocking the conduction path.

Claims

1. An enhanced GaN longitudinal field effect transistor with reverse freewheeling capability, characterized in that, The device comprises a first conductive material (1), a substrate (2), a drift region (3), a barrier layer (5) and a dielectric passivation layer (6) which are sequentially stacked in the vertical direction of the device; the upper ends of the device are respectively provided with a second conductive material (71) and a fourth conductive material (72), and the lower ends of the second conductive material (71) and the fourth conductive material (72) extend downward, sequentially penetrating the dielectric passivation layer (6) and the barrier layer (5) and then extending into the drift region (3); the upper surface of the barrier layer (5) between the second conductive material (71) and the fourth conductive material (72) is provided with a first P-GaN layer (91) and a second P-GaN layer (92), and the first P-GaN layer (91) and the second P-GaN layer (92) are wrapped by the dielectric passivation layer (6), wherein the first P-GaN layer (91) is located on the side close to the second conductive material (71) and has a spacing therebetween; the drift region (3) is further provided with a first P-GaN buried layer (41) and a second P-GaN buried layer (42), respectively, and the upper ends of the first P-GaN buried layer (41) and the second P-GaN buried layer (42) have a spacing with the upper end of the drift region (3), and the upper end of the first P-GaN buried layer (41) on one side is in contact with the lower end of the second conductive material (71), and the upper end of the first P-GaN buried layer (41) on the other side extends to be located directly below part of the first P-GaN layer (91), the upper end of the second P-GaN buried layer (42) on one side is in contact with the lower end of the fourth conductive material (72), and the upper end of the second P-GaN buried layer (42) on the other side extends to be located directly above part of the second P-GaN layer (92); the upper surface of the first P-GaN layer (91) is provided with a third conductive material (8), and the part of the third conductive material (8) which exceeds the upper surface of the dielectric passivation layer (6) extends to both sides; the side of the fourth conductive material (72) close to the second P-GaN layer (92) extends to the upper surface of the second P-GaN layer (92) and the terminal end thereof extends downward to be in contact with the upper surface of the second P-GaN layer (92). The first conductive material (1) forms an ohmic contact with the GaN substrate (2) to lead out the drain; the second conductive material (71) forms an ohmic contact with the drift region (3) to lead out the source; the third conductive material (8) leads out the gate; and the fourth conductive material (72) forms an ohmic contact with the drift region (3) to lead out the source.

2. The enhancement-mode GaN longitudinal field effect transistor with reverse freewheeling capability according to claim 1, wherein, The lower end of the second conductive material (71) is embedded into the upper end of the first P-GaN buried layer (41); and the lower end of the fourth conductive material (72) is embedded into the upper end of the second P-GaN buried layer (42).

3. The enhancement-mode GaN vertical field-effect transistor with reverse freewheeling capability according to claim 1, wherein, The lateral width of the part of the third conductive material (8) on the upper surface of the dielectric passivation layer (6) is less than the lateral width of the first P-GaN layer (91).

4. The enhancement-mode GaN longitudinal field effect transistor with reverse freewheeling capability of claim 1, wherein, The extension part of the fourth conductive material (72) is in contact with the middle part of the upper surface of the second P-GaN layer (92).

5. The enhancement-mode GaN longitudinal field effect transistor with reverse freewheeling capability of claim 1, wherein, The material used for the substrate (2) is one of sapphire, Si, SiC, AlN, GaN, AlGaN, ZnO, GaAs.

6. The enhancement-mode GaN longitudinal field effect transistor with reverse freewheeling capability of claim 1, wherein, The material used for the barrier layer (5) is one or a combination of several of AlN, AlGaN, InGaN, InAlN.

7. The enhancement-mode GaN longitudinal field effect transistor with reverse freewheeling capability of claim 1, wherein, The material used for the dielectric passivation layer (6) is one of SiN x , SiO2, Al2O3, AlN.

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