CMOS device and method for forming the same

Abstract

A CMOS device and a method for forming the same. The CMOS device includes: a semiconductor substrate having a P-well and an N-well in the P-well; separate first and second trenches in the P-well and N-well; a drain region of a first NMOS transistor in the P-well and a drain region of a first PMOS transistor in the N-well located at the bottom of the first trench; a drain region of a second NMOS transistor in the P-well and a drain region of a second PMOS transistor in the N-well located at the bottom of the second trench; a first gate dielectric layer and a second gate dielectric layer located on the sidewalls and bottom surfaces of the first and second trenches, respectively; a first gate electrode that completely fills the first trench and a second gate electrode that completely fills the second trench; and a common source located on the surface of the N-well between the first and second gate electrodes. The CMOS device occupies a small area, thereby improving the device's integration.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a CMOS device and a method for forming the same. Background Art

[0002] CMOS inverters are the core of almost all digital integrated circuit designs. They have the advantages of large noise margin, extremely high input resistance, extremely low static power consumption, and insensitivity to noise and interference. Therefore, they are widely used in digital integrated circuits.

[0003] Existing CMOS inverters are generally complementary push-pull structures consisting of NMOS transistors (or NMOS field-effect transistors) and PMOS transistors (PMOS field-effect transistors), with the NMOS transistor acting as a driver transistor (pull-down transistor) and the PMOS transistor acting as a load transistor (pull-up transistor).

[0004] However, in the existing CMOS inverter manufacturing process, the NMOS transistors and PMOS transistors in the CMOS inverter are usually manufactured as a planar structure, which occupies a large substrate area and is not conducive to improving the device integration. Summary of the Invention

[0005] Some embodiments of the present disclosure provide a CMOS device, including:

[0006] A semiconductor substrate, wherein the semiconductor substrate has a P-well, the P-well has an N-well, and the depth of the N-well is smaller than the depth of the P-well;

[0007] A first trench and a second trench are located in the P-well and the N-well, each of the first trench and the second trench spans a portion of the P-well and the N-well, and the depth of the first trench and the second trench is less than the depth of the N-well;

[0008] a drain region of a first NMOS transistor located in the P-well at the bottom of the first trench, a drain region of a first PMOS transistor located in the N-well at the bottom of the first trench, a drain region of a second NMOS transistor located in the P-well at the bottom of the second trench, and a drain region of a second PMOS transistor located in the N-well at the bottom of the second trench, the drain region of the first NMOS transistor being in contact with the drain region of the first PMOS transistor, and the drain region of the second NMOS transistor being in contact with the drain region of the second PMOS transistor;

[0009] a first gate dielectric layer located on the sidewalls and bottom surface of the first trench, and a second gate dielectric layer located on the sidewalls and bottom surface of the second trench;

[0010] a first gate electrode located on the surface of the first gate dielectric layer and completely filling the first trench, and a second gate electrode located on the surface of the second gate dielectric layer and completely filling the second trench;

[0011] a common source of the first PMOS transistor and the second PMOS transistor located in the surface of the N-well between the first gate electrode and the second gate electrode;

[0012] The source region of the first NMOS transistor is located in the P-well surface of the first gate electrode away from the common source, and the source region of the second NMOS transistor is located in the P-well surface of the second gate electrode away from the common source.

[0013] In some embodiments, a size of the first trench is equal to a size of the second trench, and a depth of the first trench is equal to a depth of the second trench.

[0014] In some embodiments, the present invention further includes: a first plug located in the semiconductor substrate and connected to the drain region of the first NMOS transistor and the drain region of the first PMOS transistor; and a second plug located in the semiconductor substrate and connected to the drain region of the second NMOS transistor and the drain region of the second PMOS transistor.

[0015] In some embodiments, the present invention further includes: a dielectric layer located on the semiconductor substrate; a third plug located in the dielectric layer and connected to a common source; a fourth plug located in the dielectric layer and connected to a source region of the first NMOS transistor; a fifth plug located in the dielectric layer and connected to a source region of the second NMOS transistor; a sixth plug located in the dielectric layer and connected to the first gate electrode; and a seventh plug located in the dielectric layer and connected to the second gate electrode.

[0016] In some embodiments, the CMOS device is used in an inverter or a charge pump.

[0017] The present disclosure also provides a method for forming a CMOS device, comprising:

[0018] Providing a semiconductor substrate, wherein a P-well is formed in the semiconductor substrate, an N-well is formed in the P-well, and a depth of the N-well is smaller than a depth of the P-well;

[0019] Etching and removing a portion of the P-well and the N-well to form a first trench and a second trench separately in the P-well and the N-well, wherein the first trench and the second trench both span a portion of the P-well and the N-well, and the depths of the first trench and the second trench are less than the depth of the N-well;

[0020] forming a drain region of a first NMOS transistor in the P-well at the bottom of the first trench, forming a drain region of a first PMOS transistor in the N-well at the bottom of the first trench, forming a drain region of a second NMOS transistor in the P-well at the bottom of the second trench, and forming a drain region of a second PMOS transistor in the N-well at the bottom of the second trench, wherein the drain region of the first NMOS transistor contacts the drain region of the first PMOS transistor, and the drain region of the second NMOS transistor contacts the drain region of the second PMOS transistor;

[0021] forming a common source of the first PMOS transistor and the second PMOS transistor in the surface of the N-well between the first trench and the second trench;

[0022] forming a source region of a first NMOS transistor in a P-well surface of the first trench away from the common source, and forming a source region of a second NMOS transistor in a P-well surface of the second trench away from the common source;

[0023] forming a first gate dielectric layer on the sidewalls and bottom surface of the first trench, and forming a second gate dielectric layer on the sidewalls and bottom surface of the second trench;

[0024] A first gate electrode is formed on the surface of the first gate dielectric layer to fill the first trench, and a second gate electrode is formed on the surface of the second gate dielectric layer to fill the second trench.

[0025] In some embodiments, the drain region of the first PMOS transistor, the drain region of the second PMOS transistor, and the common source region of the first PMOS transistor and the second PMOS transistor are formed by a first ion implantation process; the impurity ions implanted by the first ion implantation process are P-type ions.

[0026] In some embodiments, the source region and the drain region of the first NMOS transistor and the source region and the drain region of the second NMOS transistor are formed by a second ion implantation process; the impurity ions implanted by the second ion implantation process are N-type ions.

[0027] In some embodiments, the method further includes forming a first plug in the semiconductor substrate to connect the drain region of the first NMOS transistor and the drain region of the first PMOS transistor, and forming a second plug to connect the drain region of the second NMOS transistor and the drain region of the second PMOS transistor.

[0028] In some embodiments, the method further includes: forming a dielectric layer on the semiconductor substrate; forming a third plug connected to a common source in the dielectric layer, forming a fourth plug connected to a source region of the first NMOS transistor, forming a fifth plug connected to a source region of the second NMOS transistor, forming a sixth plug connected to the first gate electrode, and forming a seventh plug connected to the second gate electrode.

[0029] The CMOS device and its formation method in some of the aforementioned embodiments of the present disclosure include a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, and a second PMOS transistor. The drain region of the first NMOS transistor contacts the drain region of the first PMOS transistor, the drain region of the second NMOS transistor contacts the drain region of the second PMOS transistor, the source of the first PMOS transistor and the source of the second PMOS transistor are a common source, the first gate electrode can simultaneously control the conduction or shutoff of the first NMOS transistor and the first PMOS transistor, and the second gate electrode can simultaneously control the conduction or shutoff of the second NMOS transistor and the second PMOS transistor. That is, the CMOS device of the present disclosure includes a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, and a second PMOS transistor. In the device, the four transistors share two gates buried in the semiconductor substrate (a first gate electrode located in the first trench and a second gate electrode located in the second trench, respectively), and some drain regions between different transistors in the four transistors (the drain region of the first NMOS transistor contacts the drain region of the first PMOS transistor, and the drain region of the second NMOS transistor contacts the drain region of the second PMOS transistor) and source regions between different transistors (the common source of the first PMOS transistor and the second PMOS transistor located in the N-well surface between the first gate electrode and the second gate electrode) are directly electrically connected, without the need for additional metal wires or plugs, thereby greatly reducing the area occupied by the CMOS device of the present disclosure and improving the integration of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1-Figure 7 A schematic structural diagram of a formation process of a CMOS device in some embodiments of the present disclosure;

[0031] Figure 8 Schematic diagram of the structure of a CMOS inverter in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0032] The following detailed description of the specific embodiments of the present disclosure is provided in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure, the schematic diagrams may be partially enlarged to a different scale for ease of explanation. Furthermore, the schematic diagrams are merely illustrative and should not limit the scope of protection of the present disclosure. Furthermore, in actual production, the three-dimensional dimensions of length, width, and depth should be included.

[0033] Some embodiments of the present disclosure first provide a method for forming a semiconductor structure, which is described in detail below with reference to the accompanying drawings.

[0034] refer to Figure 1 A semiconductor substrate is provided, in which a P-well 201 is formed. An N-well 202 is formed in the P-well 201 , and a depth of the N-well 202 is less than a depth of the P-well 201 .

[0035] The semiconductor substrate serves as the carrier for the subsequent formation of CMOS devices. In some embodiments, the semiconductor substrate can be made of silicon (Si), germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC); it can also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI); or other materials, such as III-V compounds such as gallium arsenide.

[0036] A P-well 201 is formed in the semiconductor substrate. In some embodiments, the P-well 201 is formed by a (third) ion implantation process. In a specific embodiment, the process of forming the P-well 201 includes: forming a patterned first mask layer (not shown) on the semiconductor substrate, the patterned first mask layer having a first opening exposing a portion of the surface of the semiconductor substrate; using the patterned first mask layer as a mask, using the (third) ion implantation process to implant P-type impurity ions into the exposed semiconductor substrate to form the P-well 201, wherein the P-type impurity ions are one or more of boron ions, gallium ions, or indium ions; and removing the patterned first mask layer.

[0037] An N-well 202 is formed in the P-well 201. The depth of the N-well 202 is less than the depth of the P-well 201, and the width of the N-well 202 is also less than the width of the P-well 201. In some embodiments, the N-well 202 is formed by a (fourth) ion implantation process. In a specific embodiment, the process of forming the N-well 202 includes: forming a patterned second mask layer (not shown) on a semiconductor substrate, the patterned second mask layer having a second opening exposing a portion of the surface of the semiconductor substrate; using the patterned second mask layer as a mask, using the (fourth) ion implantation process to implant N-type impurity ions into the exposed semiconductor substrate to form the N-well 202, wherein the N-type impurity ions include one or more of phosphorus ions, arsenic ions, or antimony ions; and removing the patterned second mask layer.

[0038] In some embodiments, the N-well 202 is formed after the P-well 201 is formed.

[0039] In this embodiment, the number of the P-well 201 is one, and the number of the N-well 202 in the P-well 201 is also one. Subsequently, a CMOS device can be formed in the P-well 201 and the corresponding N-well 202 .

[0040] In other embodiments, there is one P-well 201 , and there are multiple N-wells 202 in the P-well 201 . The multiple N-wells 202 are discrete, and multiple CMOS devices can be formed subsequently in one P-well 201 and the corresponding multiple N-wells 202 .

[0041] In other embodiments, there are multiple P-wells 201 , and the multiple P-wells 201 are discrete. Each P-well 201 has an N-well 202 . Subsequently, multiple CMOS devices can be formed in the multiple P-wells 201 and the corresponding N-wells 202 .

[0042] refer to Figure 2 , part of the P-well 201 and the N-well 202 are etched away, and separate first trenches 203 and second trenches 204 are formed in the P-well 201 and the N-well 202. The first trench 203 and the second trench 204 both span part of the P-well 201 and the N-well 202, and the depth of the first trench 203 and the second trench 204 is less than the depth of the N-well 202.

[0043] The formed first trench 203 and the second trench 204 are separate, and both the first trench 203 and the second trench 204 span part of the P-well 201 and the N-well 202, that is, the first trench 203 may include a first part and a second part connected to the left and right, the first part is located in the P-well 201, and the second part is located in the N-well 202, and the second trench 204 may include a third part and a fourth part connected to the left and right, the third part is located in the P-well 201, and the fourth part is located in the N-well 202. Subsequently, a drain region of a first NMOS transistor can be formed in the P-well 201 at the bottom of the first trench 203, and the portion of the P-well 201 exposed by the sidewall of the first trench 203 serves as the channel region of the first NMOS transistor. A drain region of a first PMOS transistor can be formed in the N-well 202 at the bottom of the first trench 203, and the portion of the N-well 202 exposed by the sidewall of the first trench 203 serves as the channel region of the first PMOS transistor. A drain region of a second NMOS transistor is formed in the P-well 201 at the bottom of the second trench 204, and the portion of the P-well 201 exposed by the sidewall of the second trench 204 serves as the channel region of the second NMOS transistor. A drain region of a second PMOS transistor is formed in the N-well 202 at the bottom of the second trench 204, and the portion of the N-well 202 exposed by the sidewall of the second trench 204 serves as the channel region of the second PMOS transistor.

[0044] The first trench 203 and the second trench 204 have the same size and shape. Specifically, the size of the first trench 203 is equal to the size of the second trench 204, and the depth of the first trench 203 is equal to the depth of the second trench 204. This ensures that the electrical performance of the first NMOS transistor and the first PMOS transistor subsequently formed at the first trench 203 and the second NMOS transistor and the second PMOS transistor subsequently formed at the second trench 204 are consistent. When the CMOS device formed by the present disclosure is subsequently used in an inverter or a charge pump, the electrical performance of the inverter or charge pump is improved.

[0045] In some embodiments, the sidewall areas of the first portion and the second portion of the first trench 203 may be the same or different. To avoid inconsistent response rates between the first NMOS transistor and the first PMOS transistor, in a specific embodiment, the sidewall area of ​​the first portion is smaller than the sidewall area of ​​the second portion, so that the channel area of ​​the subsequently formed first NMOS transistor is smaller than the channel area of ​​the subsequently formed first PMOS transistor. This ensures that the response rates of the subsequently formed first NMOS transistor and the first PMOS transistor are consistent or have a small difference. When the CMOS device formed according to the present disclosure is subsequently used in an inverter or a charge pump, the electrical performance of the inverter or charge pump is further improved.

[0046] In some embodiments, the sidewall areas of the third portion and the fourth portion of the second trench 204 may be the same or different. To avoid inconsistent response rates between the second NMOS transistor and the second PMOS transistor, in a specific embodiment, the sidewall area of ​​the third portion is smaller than the sidewall area of ​​the fourth portion, so that the channel area of ​​the subsequently formed second NMOS transistor is smaller than the channel area of ​​the subsequently formed second PMOS transistor. This ensures that the response rates of the subsequently formed second NMOS transistor and the second PMOS transistor are consistent or have a small difference. When the CMOS device formed according to the present disclosure is subsequently used in an inverter or a charge pump, the electrical performance of the inverter or charge pump is further improved.

[0047] refer to Figure 3A drain region 206 of a first NMOS transistor is formed in the P-well 201 at the bottom of the first trench 203, a drain region 207 of a first PMOS transistor is formed in the N-well 202 at the bottom of the first trench 203, a drain region 210 of a second NMOS transistor is formed in the P-well 201 at the bottom of the second trench 204, and a drain region 209 of a second PMOS transistor is formed in the N-well 202 at the bottom of the second trench 204. The drain region 206 of the first NMOS transistor contacts the drain region 207 of the first PMOS transistor, and the drain region 210 of the second NMOS transistor is formed in the P-well 201 at the bottom of the second trench 204. The drain region 210 of the MOS transistor contacts the drain region 209 of the second PMOS transistor; a common source 208 of the first PMOS transistor and the second PMOS transistor is formed in the surface of the N-well 202 between the first trench 203 and the second trench 204; a source region 205 of the first NMOS transistor is formed in the surface of the P-well 201 on the side of the first trench 203 away from the common source 208, and a source region 211 of the second NMOS transistor is formed in the surface of the P-well 201 on the side of the second trench 204 away from the common source 208.

[0048] The drain region 207 of the first PMOS transistor, the drain region 209 of the second PMOS transistor, and the common source 208 of the first PMOS transistor and the second PMOS transistor are formed by the same ion implantation process. In a specific embodiment, the formation process of the drain region 207 of the first PMOS transistor, the drain region 209 of the second PMOS transistor, and the common source 208 of the first PMOS transistor and the second PMOS transistor includes: forming a patterned third mask layer (not shown in the figure) on the semiconductor substrate, the patterned third mask layer having a plurality of third openings exposing the to-be-implanted regions; using the patterned third mask layer as a mask, performing a first ion implantation; The process injects P-type impurity ions into the area to be implanted, forms a drain region 207 of the first PMOS transistor in the N-well 202 at the bottom of the first trench 203, forms a drain region 209 of the second PMOS transistor in the N-well 202 at the bottom of the second trench 204, and forms a common source 208 of the first PMOS transistor and the second PMOS transistor in the surface of the N-well 202 between the first trench 203 and the second trench 204. The P-type impurity ions are one or more of boron ions, gallium ions or indium ions. The concentration of the P-type impurity ions implanted by the first ion implantation process is greater than the concentration of the N-type impurity ions implanted by the fourth ion implantation process; and removes the patterned third mask layer.

[0049] The drain region 206 of the first NMOS transistor, the source region 205 of the first NMOS transistor, the drain region 210 of the second NMOS transistor, and the source region 211 of the second NMOS transistor are formed by the same ion implantation process. In a specific embodiment, the formation process of the drain region 206 of the first NMOS transistor, the source region 205 of the first NMOS transistor, the drain region 210 of the second NMOS transistor, and the source region 211 of the second NMOS transistor includes: forming a patterned fourth mask layer (not shown) on the semiconductor substrate, the patterned fourth mask layer having a plurality of third openings exposing the regions to be implanted; using the patterned fourth mask layer as a mask, using a second ion implantation process to implant N-type impurity ions into the regions to be implanted, thereby forming the drain region 206 of the first NMOS transistor in the P-well 201 at the bottom of the first trench 203. , a drain region 210 of the second NMOS transistor is formed in the P-well 201 at the bottom of the second trench 204, a source region 205 of the first NMOS transistor is formed in the surface of the P-well 201 on the side of the first trench 203 away from the common source 208, and a source region 211 of the second NMOS transistor is formed in the surface of the P-well 201 on the side of the second trench 204 away from the common source 208, the N-type impurity ions include one or more of phosphorus ions, arsenic ions or antimony ions, and the concentration of the N-type impurity ions implanted by the second ion implantation process is greater than the concentration of the P-type impurity ions implanted by the third ion implantation process; and the patterned fourth mask layer is removed.

[0050] In some embodiments, the step of performing the second ion implantation process may be performed after or before the step of performing the first ion implantation process.

[0051] In the present disclosure, the drain region 206 of the first NMOS transistor contacts the drain region 207 of the first PMOS transistor, that is, the drain region 206 of the first NMOS transistor is directly electrically connected to the drain region 207 of the first PMOS transistor (without passing through a metal wire or plug), and the drain region 210 of the second NMOS transistor contacts the drain region 209 of the second PMOS transistor, that is, the drain region 210 of the second NMOS transistor is directly electrically connected to the drain region 209 of the second PMOS transistor (without passing through a metal wire or plug), and a common source 208 of the first PMOS transistor and the second PMOS transistor is formed in the surface of the N-well 202 between the first trench 203 and the second trench 204, that is, the source region of the first PMOS transistor and the source region of the second PMOS transistor are directly electrically connected (without passing through a metal wire or plug), thereby facilitating further reducing the area occupied by the subsequently formed CMOS device.

[0052] refer to Figure 4 A first gate dielectric layer (212) is formed on the sidewalls and bottom surface of the first trench 203, and a second gate dielectric layer (212) is formed on the sidewalls and bottom surface of the second trench 204.

[0053] The first gate dielectric layer (212) and the second gate dielectric layer (212) are formed simultaneously. In some embodiments, the surface of the semiconductor substrate may also be covered with a gate dielectric layer material.

[0054] In some embodiments, the material of the first gate dielectric layer (212) and the second gate dielectric layer (212) is silicon oxide, and the formation process of the first gate dielectric layer (212) and the second gate dielectric layer (212) includes an in-situ oxidation process or a chemical vapor deposition process.

[0055] In another embodiment, the material of the first gate dielectric layer (212) and the second gate dielectric layer (212) is a high-K dielectric material, and the high-K dielectric material is one or more of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3 or BaSrTiO, and the formation process of the first gate dielectric layer (212) and the second gate dielectric layer (212) includes a chemical vapor deposition process or a sputtering process.

[0056] refer to Figure 5 A first gate electrode 213 is formed on the surface of the first gate dielectric layer (212) to fill the first trench 203, and a second gate electrode 214 is formed on the surface of the second gate dielectric layer (212) to fill the second trench 204.

[0057] The first gate electrode 213 and the second gate electrode 214 may be made of a metal. The metal may be one or more of W, Al, Cu, Ti, Ta, Co, TaN, NiSi, CoSi, TiN, TiAl, and TaSiN. In other embodiments, the first gate electrode 213 and the second gate electrode 214 may be made of doped polysilicon.

[0058] After forming the first gate electrode 213 and the second gate electrode 214, the CMOS device of the present disclosure includes four transistors, specifically including a first NMOS transistor NM1, a first PMOS transistor PM1, a second NMOS transistor NM2, and a second PMOS transistor PM2. The drain region 206 of the first NMOS transistor NM1 contacts the drain region 207 of the first PMOS transistor PM1, the drain region 210 of the second NMOS transistor NM2 contacts the drain region 209 of the second PMOS transistor PM2, the source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are a common source 208, and the first gate electrode 213 is used to simultaneously control the first NMOS transistor NM1 and the second PMOS transistor PM2. The MOS transistor NM1 and the first PMOS transistor PM1 are turned on or off, and the second gate electrode 214 is used to simultaneously control the conduction or shutoff of the second NMOS transistor NM2 and the second PMOS transistor PM2. That is, in the CMOS device disclosed in the present invention, the four transistors share two gates buried in the semiconductor substrate (a first gate electrode located in the first trench and a second gate electrode located in the second trench, respectively), and some drain regions and source regions of different transistors in the four transistors are directly electrically connected to each other, without the need for additional metal wires or plugs, thereby greatly reducing the area occupied by the CMOS device disclosed in the present invention and improving the integration of the device.

[0059] In some embodiments, the present invention further includes: forming a first plug (not shown in the figure) in the semiconductor substrate to connect the drain region 206 of the first NMOS transistor NM1 and the drain region 207 of the first PMOS transistor PM1, and forming a second plug (not shown in the figure) to connect the drain region 210 of the second NMOS transistor NM2 and the drain region 209 of the second PMOS transistor PM2. The corresponding electrical connection points can be brought out through the first plug and the second plug to facilitate subsequent wiring and electrical connection.

[0060] In some embodiments, reference Figure 6 (and combined with reference Figure 5 ), further comprising: forming a dielectric layer 214 on the semiconductor substrate; referring to Figure 7 A third plug 216 connected to the common source 208 is formed in the dielectric layer 214, a fourth plug 215 connected to the source region 205 of the first NMOS transistor NM1 is formed, a fifth plug 217 connected to the source region of the second NMOS transistor NM2 is formed, a sixth plug (not shown in the figure) connected to the first gate electrode 213 is formed, and a seventh plug (not shown in the figure) connected to the second gate electrode 214 is formed.

[0061] The dielectric layer 214 may be made of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-k material, other suitable materials, and / or combinations thereof.

[0062] The materials of the first plug, the second plug, the third plug 216 , the fourth plug 215 , the fifth plug 217 , the sixth plug and the seventh plug are metal or doped polysilicon.

[0063] In some embodiments, a capping layer 220 is formed on surfaces of the first gate electrode 213 and the second gate electrode 214 .

[0064] The CMOS device formed by the above method can be applied to an inverter or a charge pump. The inverter or charge pump is an inverter or charge pump including four transistors (two NMOS transistors and two PMOS transistors). The CMOS device formed by the above method can be applied to an inverter or a charge pump. Corresponding metal lines can also be formed to connect one or more of the first plug, second plug, third plug 216, fourth plug 215, fifth plug 217, sixth plug and seventh plug formed above to form a corresponding inverter circuit or charge pump circuit.

[0065] In a specific embodiment, the CMOS device formed by the above method is applied to Figure 8 The CMOS inverter circuit shown, reference Figure 8The CMOS inverter circuit includes: a first NMOS transistor NM1, a first PMOS transistor PM1, a second NMOS transistor NM2, and a second PMOS transistor PM2. The drain of the first PMOS transistor PM1 is electrically connected to the drain of the first NMOS transistor NM1, the gate of the first PMOS transistor PM1 is electrically connected to the gate of the first NMOS transistor NM1, the source of the first PMOS transistor PM1 is electrically connected to the source of the second PMOS transistor PM2 and to the power supply terminal VDD, the source of the first NMOS transistor NM1 is electrically connected to the source of the second NMOS transistor NM2 and to the ground terminal GND, the drain of the second PMOS transistor PM2 is electrically connected to the drain of the second NMOS transistor NM2 and to the gate of the first PMOS transistor PM1 and the gate of the first NMOS transistor NM1, and the gate of the second PMOS transistor PM2 is electrically connected to the gate of the second NMOS transistor NM2 and to the drain of the first PMOS transistor PM1 and the drain of the first NMOS transistor NM1. The first NMOS transistor NM1, the first PMOS transistor PM1, the second NMOS transistor NM2, and the second PMOS transistor PM2 in the CMOS inverter circuit are the same as the first NMOS transistor NM1, the first PMOS transistor PM1, the second NMOS transistor NM2, and the second PMOS transistor PM2 in the CMOS device formed by the above method (refer to Figure 5 , Figure 6 or Figure 7 )correspond.

[0066] Some embodiments of the present disclosure further provide a CMOS device, referring to Figure 5 ,include:

[0067] A semiconductor substrate having a P-well 201 therein, an N-well 202 in the P-well 201, and a depth of the N-well 202 being less than a depth of the P-well 201;

[0068] A first trench 203 and a second trench 204 are located in the P-well 201 and the N-well 202 , wherein the first trench 203 and the second trench 204 both span a portion of the P-well 201 and the N-well 202 , and the depth of the first trench 203 and the second trench 204 is less than the depth of the N-well 202 ;

[0069] a drain region 206 of the first NMOS transistor NM1 in the P-well 201 at the bottom of the first trench 203, a drain region 207 of the first PMOS transistor PM1 in the N-well 202 at the bottom of the first trench 203, a drain region 210 of the second NMOS transistor NM2 in the P-well 201 at the bottom of the second trench 204, and a drain region 209 of the second PMOS transistor PM2 in the N-well 202 at the bottom of the second trench 204; the drain region 206 of the first NMOS transistor NM1 contacts the drain region 207 of the first PMOS transistor PM1, and the drain region 210 of the second NMOS transistor NM2 contacts the drain region 209 of the second PMOS transistor PM2;

[0070] A first gate dielectric layer (212) is located on the sidewalls and bottom surface of the first trench 203, and a second gate dielectric layer (212) is located on the sidewalls and bottom surface of the second trench 207;

[0071] A first gate electrode 213 located on the surface of the first gate dielectric layer (212) and filling the first trench 203, and a second gate electrode 214 located on the surface of the second gate dielectric layer (212) and filling the second trench 204;

[0072] a common source 208 of the first PMOS transistor PM1 and the second PMOS transistor PM2 located in the surface of the N-well 202 between the first gate electrode 213 and the second gate electrode 214 ;

[0073] The source region 205 of the first NMOS transistor NM1 is located in the surface of the P-well 201 on the side of the first gate electrode 213 away from the common source 208 , and the source region 211 of the second NMOS transistor NM2 is located in the surface of the P-well 201 on the side of the second gate electrode 214 away from the common source 208 .

[0074] In some embodiments, the size of the first trench 203 is equal to the size of the second trench 204 , and the depth of the first trench 203 is equal to the depth of the second trench 204 .

[0075] In some embodiments, the source region 205 and the drain region 206 of the first NMOS transistor NM1 and the source region 211 and the drain region 210 of the second NMOS transistor NM2 are doped with N-type ions.

[0076] In some embodiments, the drain region 207 of the first PMOS transistor PM1 , the drain region 209 of the second PMOS transistor PM2 , and the common source region 208 of the first PMOS transistor PM1 and the second PMOS transistor PM2 are doped with P-type ions.

[0077] In some embodiments, the present invention further includes: a first plug (not shown in the figure) located in the semiconductor substrate and connected to the drain region 206 of the first NMOS transistor NM1 and the drain region 207 of the first PMOS transistor PM1, and a second plug (not shown in the figure) located in the semiconductor substrate and connected to the drain region 210 of the second NMOS transistor NM2 and the drain region 209 of the second PMOS transistor PM2.

[0078] In some embodiments, reference Figure 7 , further comprising: a dielectric layer 214 located on the semiconductor substrate; a third plug 216 located in the dielectric layer 214 and connected to the common source 208, a fourth plug 215 located in the dielectric layer 214 and connected to the source region 205 of the first NMOS transistor, a fifth plug 217 located in the dielectric layer 214 and connected to the source region 211 of the second NMOS transistor, a sixth plug located in the dielectric layer 214 and connected to the first gate electrode 213 (not shown in the figure), and a seventh plug located in the dielectric layer 214 and connected to the second gate electrode 214 (not shown in the figure).

[0079] In some embodiments, the CMOS device is used in an inverter or a charge pump.

[0080] It should be noted that the terms "including" and "having" and their variations involved in this disclosure are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates otherwise. It should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments in this disclosure and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies has been omitted to avoid unnecessary confusion of the concepts of this disclosure. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to (or referenced) with each other.

[0081] Although the present disclosure has been disclosed as above in terms of preferred embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make possible changes and modifications to the technical solutions of the present disclosure by using the methods and technical contents disclosed above without departing from the spirit and scope of the present disclosure. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solutions of the present disclosure shall fall within the scope of protection of the technical solutions of the present disclosure.

Claims

1. A CMOS device, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate has a P-well, the P-well has an N-well, and the depth of the N-well is smaller than the depth of the P-well; A first trench and a second trench are located in the P-well and the N-well, each of the first trench and the second trench spans a portion of the P-well and the N-well, and the depth of the first trench and the second trench is less than the depth of the N-well; a drain region of a first NMOS transistor located in the P-well at the bottom of the first trench, a drain region of a first PMOS transistor located in the N-well at the bottom of the first trench, a drain region of a second NMOS transistor located in the P-well at the bottom of the second trench, and a drain region of a second PMOS transistor located in the N-well at the bottom of the second trench, the drain region of the first NMOS transistor being in contact with the drain region of the first PMOS transistor, and the drain region of the second NMOS transistor being in contact with the drain region of the second PMOS transistor; a first gate dielectric layer located on the sidewalls and bottom surface of the first trench, and a second gate dielectric layer located on the sidewalls and bottom surface of the second trench; a first gate electrode located on the surface of the first gate dielectric layer and completely filling the first trench, and a second gate electrode located on the surface of the second gate dielectric layer and completely filling the second trench; a common source of the first PMOS transistor and the second PMOS transistor located in the surface of the N-well between the first gate electrode and the second gate electrode; The source region of the first NMOS transistor is located in the P-well surface of the first gate electrode away from the common source, and the source region of the second NMOS transistor is located in the P-well surface of the second gate electrode away from the common source.

2. The CMOS device according to claim 1, wherein The size of the first trench is equal to the size of the second trench, and the depth of the first trench is equal to the depth of the second trench.

3. The CMOS device according to claim 1, wherein Also includes: A first plug located in the semiconductor substrate is connected to the drain region of the first NMOS transistor and the drain region of the first PMOS transistor, and a second plug located in the semiconductor substrate is connected to the drain region of the second NMOS transistor and the drain region of the second PMOS transistor.

4. The CMOS device according to claim 3, wherein: Also includes: a dielectric layer located on the semiconductor substrate; a third plug located in the dielectric layer and connected to the common source, a fourth plug located in the dielectric layer and connected to the source region of the first NMOS transistor, a fifth plug located in the dielectric layer and connected to the source region of the second NMOS transistor, a sixth plug located in the dielectric layer and connected to the first gate electrode, and a seventh plug located in the dielectric layer and connected to the second gate electrode.

5. The CMOS device according to claim 4, wherein: The CMOS device is used in an inverter or a charge pump.

6. A method for forming a CMOS device, characterized in that: include: Providing a semiconductor substrate, wherein a P-well is formed in the semiconductor substrate, an N-well is formed in the P-well, and a depth of the N-well is smaller than a depth of the P-well; Etching and removing a portion of the P-well and the N-well to form a first trench and a second trench separately in the P-well and the N-well, wherein the first trench and the second trench both span a portion of the P-well and the N-well, and the depths of the first trench and the second trench are less than the depth of the N-well; forming a drain region of a first NMOS transistor in the P-well at the bottom of the first trench, forming a drain region of a first PMOS transistor in the N-well at the bottom of the first trench, forming a drain region of a second NMOS transistor in the P-well at the bottom of the second trench, and forming a drain region of a second PMOS transistor in the N-well at the bottom of the second trench, wherein the drain region of the first NMOS transistor contacts the drain region of the first PMOS transistor, and the drain region of the second NMOS transistor contacts the drain region of the second PMOS transistor; forming a common source of the first PMOS transistor and the second PMOS transistor in the surface of the N-well between the first trench and the second trench; forming a source region of a first NMOS transistor in a P-well surface of the first trench away from the common source, and forming a source region of a second NMOS transistor in a P-well surface of the second trench away from the common source; forming a first gate dielectric layer on the sidewalls and bottom surface of the first trench, and forming a second gate dielectric layer on the sidewalls and bottom surface of the second trench; A first gate electrode is formed on the surface of the first gate dielectric layer to fill the first trench, and a second gate electrode is formed on the surface of the second gate dielectric layer to fill the second trench.

7. The method for forming a CMOS device according to claim 6, wherein: The drain region of the first PMOS transistor, the drain region of the second PMOS transistor, and the common source region of the first PMOS transistor and the second PMOS transistor are formed by a first ion implantation process; the impurity ions implanted by the first ion implantation process are P-type ions.

8. The method for forming a CMOS device according to claim 7, wherein: The source region and the drain region of the first NMOS transistor and the source region and the drain region of the second NMOS transistor are formed by a second ion implantation process; the impurity ions implanted by the second ion implantation process are N-type ions.

9. The method for forming a CMOS device according to claim 6, wherein: Also includes: A first plug connected to the drain region of the first NMOS transistor and the drain region of the first PMOS transistor is formed in the semiconductor substrate, and a second plug connected to the drain region of the second NMOS transistor and the drain region of the second PMOS transistor is formed.

10. The method for forming a CMOS device according to claim 9, wherein: Also includes: A dielectric layer is formed on the semiconductor substrate; a third plug connected to a common source is formed in the dielectric layer, a fourth plug connected to a source region of the first NMOS transistor is formed, a fifth plug connected to a source region of the second NMOS transistor is formed, a sixth plug connected to the first gate electrode is formed, and a seventh plug connected to the second gate electrode is formed.

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