Light-emitting display device

Abstract

A light emitting display device includes: a substrate; a buffer layer; a first semiconductor layer; a first insulating layer; a first conductive layer; a second insulating layer disposed on the first semiconductor layer; a second semiconductor layer; a third insulating layer; a second conductive layer; a fourth insulating layer; and a third conductive layer. The first semiconductor layer comprises low-temperature polycrystalline silicon. The second semiconductor layer includes an oxide semiconductor. The third insulating layer overlaps an upper surface of the second semiconductor layer. The third conductive layer includes: a first electrode directly connected to the first semiconductor layer; a second electrode directly connected to the first semiconductor layer and spaced apart from the first electrode; a third electrode directly connected to the second semiconductor layer; and a fourth electrode directly connected to the second semiconductor layer and spaced apart from the third electrode.

Description

[0001] This application is a divisional application of an invention patent application with an application date of June 12, 2019, application number 201910506492.4, and invention name “Organic light-emitting diode display device and method for forming a semiconductor layer of a display device”. Technical Field

[0002] Embodiments of the present disclosure are directed to an organic light emitting diode display device. Background Art

[0003] Various types of electronic devices including mobile phones, tablet computers, laptop computers, etc. employ flat panel displays (FPDs). Flat panel display devices, hereinafter referred to as display devices, include liquid crystal display (LCD) devices, plasma display panel (PDP) devices, organic light emitting display (OLED) devices, etc. Recently, electrophoretic display (EPD) devices have also become widely used.

[0004] An organic light emitting display device displays an image by using an organic light emitting element that emits light due to recombination of electrons and holes. The organic light emitting display device includes a plurality of transistors that supply a driving current to the organic light emitting element.

[0005] Generally, a PMOS transistor is used as a transistor of an organic light emitting display device. However, there has been research on using an NMOS transistor alone or in combination with a PMOS transistor. Summary of the invention

[0006] The embodiments of the present disclosure can provide an organic light emitting display device that can dope a semiconductor layer of an NMOS transistor with n-type impurity ions only through a heat treatment without pre-treatment.

[0007] According to an embodiment of the present disclosure, an organic light-emitting display device is provided. The organic light-emitting display device includes: a first thin film transistor, which is disposed on a substrate; and a second thin film transistor, which is disposed on the substrate and spaced apart from the first thin film transistor. The first thin film transistor includes a first semiconductor layer, a first conductive layer disposed on the first semiconductor layer and overlapping with the first semiconductor layer, and a first insulating layer disposed between the first semiconductor layer and the first conductive layer. The second thin film transistor includes a second semiconductor layer and a second conductive layer, the second conductive layer being disposed on the second semiconductor layer and overlapping with the second semiconductor layer. The first semiconductor layer is disposed on a layer higher than the second semiconductor layer, the first semiconductor layer includes an oxide semiconductor, the second semiconductor layer includes low temperature polycrystalline silicon (LTPS), and the first insulating layer covers the entire first semiconductor layer.

[0008] According to an embodiment of the present disclosure, an organic light-emitting display device is provided. The organic light-emitting display device includes: a buffer layer, the buffer layer is arranged on a substrate; a first semiconductor layer, the first semiconductor layer is arranged on the buffer layer; a first insulating layer, the first insulating layer is arranged on the first semiconductor layer; a first conductive layer, the first conductive layer is arranged on the first insulating layer and overlaps with the first semiconductor layer; a second insulating layer, the second insulating layer is arranged on the first conductive layer; a second conductive layer, the second conductive layer is arranged on the second insulating layer and overlaps with the first semiconductor layer; a third insulating layer, the third insulating layer is arranged on the second conductive layer; a second semiconductor layer, the second semiconductor layer is arranged on the third insulating layer and does not overlap with the first semiconductor layer; a fourth insulating layer, the fourth insulating layer is arranged on the second semiconductor layer; a third conductive layer, the third conductive layer is arranged on the fourth insulating layer and overlaps with the second semiconductor layer; and a fifth insulating layer, the fifth insulating layer is arranged on the third conductive layer. The first semiconductor layer includes low temperature polycrystalline silicon (LTPS), the second semiconductor layer includes an oxide semiconductor, and the fourth insulating layer covers the entire second semiconductor layer.

[0009] According to another embodiment of the present disclosure, a method for forming a semiconductor layer of a display device is provided. The method comprises the steps of stacking an oxide semiconductor, a first insulating layer, a conductive layer, and a second insulating layer on a third insulating layer in sequence, wherein the oxide semiconductor is a metal oxide semiconductor, and the second insulating layer comprises silicon oxide (SiO x ) and silicon nitride (SiN x ) multiple layers; and without etching the first insulating layer, subjecting the first end and the opposite second end of the oxide semiconductor to reduction treatment by heat treatment. Hydrogen ions (H+) present in the second insulating layer diffuse into the first end and the second end of the oxide semiconductor, wherein a conductive source region and a conductive drain region are formed at the first end and the second end, respectively, and a low conductive region is formed in a central region of the oxide semiconductor overlapping the conductive layer. The heat treatment is performed in a temperature range of 90°C to 110°C, and the surface resistance of the conductive source region and the conductive drain region is less than 1,000Ω / □.

[0010] According to the embodiments of the present disclosure, the semiconductor layer of the NMOS transistor may be doped with n-type impurity ions only through thermal treatment, and the dehydrogenation effect of the PMOS transistor may be improved to increase the driving range. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An organic light emitting display device according to an exemplary embodiment of the present disclosure is shown.

[0012] Figure 2 is a block diagram of an organic light emitting display device according to an exemplary embodiment of the present disclosure.

[0013] Figure 3 is an equivalent circuit diagram of a pixel of an organic light emitting display device according to an exemplary embodiment of the present disclosure.

[0014] Figure 4 is a cross-sectional view of an organic light emitting display device according to an exemplary embodiment of the present disclosure.

[0015] Figures 5 to 7 is a cross-sectional view illustrating a process of forming a source region and a drain region of an upper semiconductor layer according to an exemplary embodiment of the present disclosure.

[0016] Figure 8 is a cross-sectional view of an organic light emitting display device according to an exemplary embodiment of the present disclosure.

[0017] Fig. 9 is a cross-sectional view of an organic light emitting display device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The features of the embodiments of the inventive concept and the methods of implementing the embodiments may be more easily understood by referring to the following detailed description of the embodiments and the accompanying drawings. However, the inventive concept may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0019] It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected to or coupled to the other element or layer, or intervening elements or layers may be present.

[0020] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. Throughout the specification, the same reference numerals may be used for the same or similar components.

[0021] The display device according to various exemplary embodiments of the present disclosure can be used as a display screen for various devices or stereoscopic display devices for presenting videos or still images, and the various devices or stereoscopic display devices include portable electronic devices such as mobile communication terminals, smart phones, tablet computers, smart watches or navigation devices, and devices such as televisions, laptop computers, monitors, electronic billboards or devices for the Internet of Things.

[0022] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, an organic light-emitting display device is described as an example of a display device. However, it will be understood that the embodiments of the present disclosure are not limited thereto. Without departing from the spirit of the embodiments of the present disclosure, the display device according to the embodiment may be included in other display devices, such as a liquid crystal display device, a field emission display (FED) panel, or an electrophoretic display device. Throughout the accompanying drawings, the same reference numerals may indicate the same elements.

[0023] Figure 1 An organic light emitting display device according to an exemplary embodiment of the present disclosure is shown.

[0024] Reference Figure 1 , the organic light emitting display device 60 according to an exemplary embodiment of the present disclosure includes a display area DA and a non-display area NDA.

[0025] According to an embodiment, the display area DA is an area in which an image is displayed. The display area DA may also be used to detect an external environment. That is, the display area DA may be used as an area for displaying an image or recognizing a touch or fingerprint of a user. According to an exemplary embodiment of the present disclosure, the display area DA has a generally flat area FA and an at least partially curved area BA. However, it will be understood that the embodiments of the present disclosure are not limited thereto. The display area DA may have a completely flat shape.

[0026] According to an embodiment, an organic light emitting display device 60 includes a plurality of pixels 1 in a display area DA. Each of the pixels 1 includes an organic light emitting diode. The organic light emitting display device 60 displays an image using the pixels 1.

[0027] According to an embodiment, the non-display area NDA is an area in which an image is not displayed and is disposed on at least one side of the display area DA. In an exemplary embodiment, a speaker module, a camera module M1, a sensor module M2, etc. are disposed in the non-display area NDA. In an exemplary embodiment, the sensor module M2 includes at least one of an illumination sensor, a proximity sensor, an infrared sensor, or an ultrasonic sensor.

[0028] Figure 2 is a block diagram of an organic light emitting display device according to an exemplary embodiment of the present disclosure.

[0029] Reference Figure 2 According to an embodiment, an organic light emitting display device 60 includes a plurality of pixels 1 in a display area DA, a scan driver 20 , a data driver 30 , an emission control driver 40 , and a controller 50 .

[0030] According to an embodiment, the display area DA includes a plurality of pixels 1 arranged in a matrix form, wherein each of the pixels 1 is located at an intersection of a plurality of scan lines SL11 to SL1n, SL21 to SL2n and SL31 to SL3n, a plurality of data lines DL1 to DLm and a plurality of emission control lines EL1 to ELn.

[0031] According to an embodiment, a plurality of scan lines SL11 to SL1n, SL21 to SL2n and SL31 to SL3n and a plurality of emission control lines EL1 to ELn extend in a row direction, and a plurality of data lines DL1 to DLm extend in a column direction. The row direction and the column direction are interchangeable. The initialization voltage (VINT) supply line branches into a plurality of lines extending in the row direction. The first power supply voltage (ELVDD) supply line branches into a plurality of lines extending in the column direction. However, it will be understood that the embodiments of the present disclosure are not limited thereto. The initialization voltage (VINT) supply line and the first power supply voltage (ELVDD) supply line may be modified in various ways.

[0032] According to an embodiment, in the pixel 1 in the first row and the first column, three scan lines SL11, SL21 and SL31, one data line DL1, one emission control line EL1, one initialization voltage (VINT) supply line and one first power supply voltage (ELVDD) supply line pass through. Other pixels have similar lines to the pixels in the first row and the first column.

[0033] According to an embodiment, the controller 50 receives a plurality of externally supplied signals, including a red image signal R, a green image signal G, and a blue image signal B, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a clock signal MCLK. Based on these signals, the controller 50 generates an emission control signal ESC and transmits the emission control signal ESC to the emission control driver 40, generates a red data signal DR, a green data signal DG, and a blue data signal DB and a data control signal DCS and transmits the red data signal DR, the green data signal DG, and the blue data signal DB and the data control signal DCS to the data driver 30, and generates a scan control signal SCS and transmits the scan control signal SCS to the scan driver 20.

[0034] According to an embodiment, the scan driver 20 generates three scan signals based on the received scan control signal SCS and transmits the three scan signals to each pixel 1 through the plurality of scan lines SL11 to SL1n, SL21 to SL2n, and SL31 to SL3n. That is, the scan driver 20 sequentially transmits the scan signals to the first scan lines SL11 to SL1n, the second scan lines SL21 to SL2n, and the third scan lines SL31 to SL3n.

[0035] According to an embodiment, the data driver 30 transmits a data signal to each pixel 1 through the plurality of data lines DL1 to DLm based on the received red, green and blue data signals DR, DG and DB and the data control signal DCS. Whenever a first scan signal is transmitted to the first scan lines SL11 to SL1n, the data signal is transmitted to the pixel 1 selected by the first scan signal.

[0036] According to an embodiment, the emission control driver 40 generates an emission control signal based on the emission control signal ECS received from the controller 50 and transmits the emission control signal to each pixel 1 through the respective emission control lines EL1 to ELn. The emission control signal controls the emission time of the pixel 1. The emission control driver 40 may be removed according to the internal structure of the pixel 1 or when the scan driver 20 generates the emission control signal as well as the scan signal.

[0037] According to an embodiment, each of the plurality of pixels 1 receives a first power voltage ELVDD and a second power voltage ELVSS. The first power voltage ELVDD has a predetermined high voltage level, and the second power voltage ELVSS has a voltage level lower than that of the first power voltage ELVDD.

[0038] According to an embodiment, each of the plurality of pixels 1 emits light of predetermined brightness by receiving a driving current transmitted to a light emitting element according to a data signal transmitted through the respective data lines DL1 to DLm.

[0039] According to an embodiment, the first power voltage ELVDD, the second power voltage ELVSS, the initialization voltage VINT, etc. may be received from an external voltage source.

[0040] Figure 3 is an equivalent circuit diagram of a pixel of an organic light emitting display device according to an exemplary embodiment of the present disclosure.

[0041] Reference Figure 3 According to an embodiment, a circuit of a pixel 1 of an organic light emitting display device 60 includes an organic light emitting diode OLED, a plurality of transistors T1 to T7, and a storage capacitor Cst. The circuit of the pixel 1 receives a data signal DATA, a first scan signal GW, a second scan signal GI, a third scan signal GB, an emission control signal EM, a first power supply voltage ELVDD, a second power supply voltage ELVSS, and an initialization voltage VINT.

[0042] According to an embodiment, the organic light emitting diode OLED includes an anode electrode and a cathode electrode. The storage capacitor Cst includes a first electrode and a second electrode.

[0043] According to an embodiment, the plurality of transistors include first to seventh transistors T1 to T7. Each of the transistors T1 to T7 includes a gate electrode, a first electrode, and a second electrode. One of the first and second electrodes of each of the transistors T1 to T7 is a source electrode and the other is a drain electrode.

[0044] According to an embodiment, each of the transistors T1 to T7 is a thin film transistor. Each of the transistors T1 to T7 may be a PMOS transistor or an NMOS transistor. In an exemplary embodiment, the first transistor T1 is a driving transistor, the second transistor T2 is a data transfer transistor, the fifth transistor T5 is a first emission control transistor, the sixth transistor T6 is a second emission control transistor, and the seventh transistor T7 is a bypass transistor, and each of the aforementioned transistors is a PMOS transistor. On the other hand, the third transistor T3 is a compensation transistor, and the fourth transistor T4 is an initialization transistor, and the third transistor T3 and the fourth transistor T4 are NMOS transistors. PMOS transistors and NMOS transistors have different characteristics. The NMOS transistor used to implement the third transistor T3 and the fourth transistor T4 has a relatively good cut-off characteristic that reduces the leakage of the driving current Id during the emission period of the organic light emitting diode OLED.

[0045] Hereinafter, each of the elements will be described in detail.

[0046] According to an embodiment, a gate electrode of the first transistor T1 is connected to a first electrode of a storage capacitor Cst. A first electrode of the first transistor T1 is connected to a first power supply voltage ELVDD via a fifth transistor T5. A second electrode of the first transistor T1 is connected to an anode electrode of an organic light emitting diode OLED via a sixth transistor T6. The first transistor T1 receives a data signal DATA through a switching operation of the second transistor T2 to transmit a driving current Id to the organic light emitting diode OLED.

[0047] According to an embodiment, a gate electrode of the second transistor T2 is connected to a first scan signal (GW) terminal. A first electrode of the second transistor T2 is connected to a data signal (DATA) terminal. A second electrode of the second transistor T2 is connected to a first electrode of the first transistor T1 and is connected to a first power supply voltage (ELVDD) terminal through a fifth transistor T5. The second transistor T2 is turned on according to the first scan signal GW and performs a switching operation to transmit the data signal DATA to the first electrode of the first transistor T1.

[0048] According to an embodiment, the gate electrode of the third transistor T3 is connected to the first scan signal GW terminal. The first electrode of the third transistor T3 is connected to the second electrode of the first transistor T1 and is connected to the anode electrode of the organic light emitting diode OLED via the sixth transistor T6. The second electrode of the third transistor T3 is connected to the first electrode of the storage capacitor Cst, the first electrode of the fourth transistor T4, and the gate electrode of the first transistor T1. The third transistor T3 is turned on by the first scan signal GW to connect the gate electrode of the first transistor T1 with the second electrode so as to connect the first transistor T1 in a diode manner. Therefore, a voltage difference equal to the threshold voltage of the first transistor T1 is generated between the first electrode and the gate electrode of the first transistor T1. The deviation of the threshold voltage of the first transistor T1 can be compensated by supplying the data signal DATA compensating the threshold voltage to the gate electrode of the first transistor T1.

[0049] According to an embodiment, a gate electrode of the fourth transistor T4 is connected to a second scan signal (GI) terminal. A second electrode of the fourth transistor T4 is connected to an initialization voltage (VINT) terminal. A first electrode of the fourth transistor T4 is connected to a first electrode of a storage capacitor Cst, a second electrode of the third transistor T3, and a gate electrode of the first transistor T1. The fourth transistor T4 is turned on by the second scan signal GI to transmit the initialization voltage VINT to the gate electrode of the first transistor T1 so as to initialize the voltage at the gate electrode of the first transistor T1.

[0050] According to an embodiment, a gate electrode of the fifth transistor T5 is connected to an emission control signal EM terminal. A first electrode of the fifth transistor T5 is connected to a first power supply voltage ELVDD terminal. A second electrode of the fifth transistor T5 is connected to a first electrode of the first transistor T1 and a second electrode of the second transistor T2.

[0051] According to an embodiment, a gate electrode of the sixth transistor T6 is connected to the emission control signal EM terminal. A first electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1 and the first electrode of the third transistor T3. A second electrode of the sixth transistor T6 is connected to the anode electrode of the organic light emitting diode OLED.

[0052] According to an embodiment, the fifth transistor T5 and the sixth transistor T6 are simultaneously turned on in response to the emission control signal EM so that the driving current Id flows through the organic light emitting diode OLED.

[0053] According to an embodiment, a gate electrode of the seventh transistor T7 is connected to a third scan signal GB terminal. A first electrode of the seventh transistor T7 is connected to an anode electrode of the organic light emitting diode OLED. A second electrode of the seventh transistor T7 is connected to an initialization voltage VINT terminal. The seventh transistor T7 is turned on by the third scan signal GB to initialize the anode electrode of the organic light emitting diode OLED. In order to display a black image, the emission current of the organic light emitting diode OLED has a minimum current amount required for reliably presenting a black image, and the emission current of the organic light emitting diode OLED is reduced by the amount of the bypass current Ibp flowing from the anode electrode of the organic light emitting diode OLED through the seventh transistor T7. Therefore, it is possible to realize an image with accurate black brightness by using the seventh transistor T7, thereby improving contrast.

[0054] According to an embodiment, although the third scan signal GB is transmitted to the gate electrode of the seventh transistor T7, in other embodiments, the pixel circuit may be configured such that the emission control signal EM is transmitted to the gate electrode of the seventh transistor T7.

[0055] Furthermore, according to an embodiment, although the second scan signal GI and the third scan signal GB are independent of each other, in other embodiments, the circuit may be configured such that the second scan signal GI and the third scan signal GB are the same signal electrically connected to each other.

[0056] According to an embodiment, a second electrode of the storage capacitor Cst is connected to a first power supply voltage ELVDD terminal. A first electrode of the storage capacitor Cst is connected to a gate electrode of the first transistor T1, a second electrode of the third transistor T3, and a first electrode of the fourth transistor T4. A cathode electrode of the organic light emitting diode OLED is connected to a second power supply voltage ELVSS terminal. The organic light emitting diode OLED receives a driving current Id from the first transistor T1 and emits light to display an image.

[0057] According to an embodiment, each of the transistors T1 to T7 includes a conductive layer forming an electrode, a semiconductor layer forming a channel, and an insulating layer. The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 as PMOS transistors are thin film transistors using low temperature polycrystalline silicon (LTPS). The third transistor T3 and the fourth transistor T4 as NMOS transistors are thin film transistors using an oxide semiconductor layer.

[0058] In the exemplary embodiment, a thin film transistor having a top gate structure in which the gate electrode of each of the transistors T1 to T7 is disposed above the semiconductor layer will be described as an example. However, it will be understood that the embodiments of the present disclosure are not limited thereto. At least some of the transistors T1 to T7 may be a thin film transistor having a bottom gate structure in which the gate electrode is disposed below the semiconductor layer.

[0059] Hereinafter, the pixel will be described in more detail with reference to the cross-sectional structure of the pixel.

[0060] Figure 4 is a cross-sectional view of an organic light emitting display device according to an exemplary embodiment of the present disclosure.

[0061] Reference Figure 4 According to the embodiment, the layers of the pixel 1 include: a substrate 110, a buffer layer 121, a lower semiconductor layer, a first insulating layer 122, a first conductive layer G1, a second insulating layer 123, a second conductive layer G2, a third insulating layer 124, an upper semiconductor layer, a fourth insulating layer 125, a third conductive layer G3, and a fifth insulating layer 126. Each of the layers disclosed above may be composed of a single layer or a plurality of layers, and another layer may be further provided between the layers.

[0062] According to an embodiment, the substrate 110 supports various layers disposed on the substrate 110. When the organic light emitting display device 60 is a bottom emission organic light emitting display device or a double-sided emission organic light emitting display device, a transparent substrate 110 is used. When the organic light emitting display device 60 is a top emission organic light emitting display device, a semi-transparent or opaque substrate 110 as well as a transparent substrate 110 may be used.

[0063] According to an embodiment, the substrate 110 is made of an insulating material such as glass, quartz or a polymer resin. Examples of polymer materials include polyethersulfone (PES), polyacrylate (PA), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP) or a combination thereof. The substrate 110 may include a metal.

[0064] According to an embodiment, the substrate 110 may be a rigid substrate 110 or a flexible substrate 110 that may be bent, folded, rolled, etc. Examples of a flexible material for the flexible substrate 110 include polyimide (PI), but are not limited to polyimide (PI).

[0065] According to an embodiment, a buffer layer 121 is provided on the entire surface of the substrate 110. The buffer layer 121 prevents diffusion of impurity ions, penetration of moisture or external air, and provides a flat surface. The buffer layer 121 includes silicon nitride, silicon oxide, silicon oxynitride, etc. The buffer layer 121 may be removed according to the type of the substrate 110, process conditions, etc.

[0066] According to an embodiment, the lower semiconductor layer is an active layer forming channels of the first transistor T1 , the second transistor T2 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 .

[0067] According to an embodiment, the lower semiconductor layer includes low temperature polysilicon (LTPS). However, it will be understood that the embodiments of the present disclosure are not limited thereto. The lower semiconductor layer may include single crystal silicon, amorphous silicon, etc.

[0068] According to an embodiment, a thin film transistor (LTPS TFT) including low temperature polysilicon generally exhibits excellent carrier mobility even with a small profile, and is therefore suitable for implementing an integrated drive circuit. Because the low temperature polysilicon thin film transistor (LTPS TFT) has excellent carrier mobility, the low temperature polysilicon thin film transistor (LTPS TFT) is used for a component with a high operating speed. Despite the above-mentioned features, the low temperature polysilicon thin film transistor (LTPS TFT) still has a different initial threshold voltage due to the grain boundary of the polysilicon semiconductor layer.

[0069] According to an embodiment, the lower semiconductor layer includes a source region S1 disposed on one side, a drain region D1 disposed on the other side, and a channel region A1 disposed between the source region S1 and the drain region D1. Portions of the lower semiconductor layer connected to the source electrode SE1 and the drain electrode DE1 of each of the transistors T1, T2, T5, T6, and T7, that is, the source region S1 and the drain region D1, are doped with impurity ions, specifically, p-type impurity ions in the case of a PMOS transistor. A trivalent dopant such as boron (B) may be used as the p-type impurity ions.

[0070] According to an embodiment, the first insulating layer 122 is disposed on the lower semiconductor layer, and is generally disposed on the entire surface of the substrate 110. The first insulating layer 122 is a gate insulating layer having a gate insulating function.

[0071] According to an embodiment, the first insulating layer 122 includes a silicon compound, a metal oxide, etc. For example, the first insulating layer 122 includes silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. They may be used alone or in combination. The first insulating layer 122 may have a single layer or a plurality of layers of different materials stacked on each other.

[0072] According to an embodiment, the first conductive layer G1 is disposed on the first insulating layer 122. At least a portion of the first conductive layer G1 overlaps with the lower semiconductor layer. As used herein, unless otherwise explicitly stated to the contrary, the phrase "one element overlaps with another element" means that one element is above the other element in the thickness direction of the organic light emitting display device, that is, in a direction perpendicular to the surface of the substrate 110 in the figure.

[0073] According to an embodiment, the first conductive layer G1 includes: a first conductive layer for transmitting a first scanning signal ( Figure 3 GW in the scanning line, used to transmit the third scanning signal ( Figure 3 GB in the scanning line, the gate electrode of the first transistor T1, and the gate electrode for transmitting the emission control signal ( Figure 3 The emission control line of EM) or used to transmit the initialization voltage ( Figure 3 The initialization voltage line of VINT in .

[0074] According to an embodiment, the first conductive layer G1 includes at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer G1 may have a single layer or a plurality of layers.

[0075] According to an embodiment, the second insulating layer 123 covers the first conductive layer G1. The second insulating layer 123 is generally disposed on the entire surface of the substrate 110. The second insulating layer 123 is a gate insulating layer having a gate insulating function. The second insulating layer 123 may include the same material as the first insulating layer 122, or may include one or more other materials selected from the materials listed above for the first insulating layer 122. The second insulating layer 123 may have a single layer or a plurality of layers of different materials stacked on each other.

[0076] According to an embodiment, the second conductive layer G2 is disposed on the second insulating layer 123. The second conductive layer G2 overlaps at least a portion of the lower semiconductor layer and the first conductive layer G1. The second conductive layer G2 may include the same material as the first conductive layer G1, or may include at least one other material selected from the materials listed above for the first conductive layer G1. The second conductive layer G2 may have a single layer or a plurality of layers of different materials stacked on each other.

[0077] According to an embodiment, the second conductive layer G2 includes a storage capacitor ( Figure 3 Cst) electrode line in and another emission control line for transmitting an emission control signal EM.

[0078] According to an embodiment, third insulating layer 124 insulates second conductive layer G2 from an upper semiconductor layer to be described below. Third insulating layer 124 is disposed on first conductive layer G1 and is generally formed on the entire surface of substrate 110. Third insulating layer 124 is an interlayer dielectric layer.

[0079] According to an embodiment, the third insulating layer 124 includes silicon oxide (SiO x ), silicon nitride (SiN x ), an inorganic insulating material such as silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide, or an organic insulating material such as a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene oxide resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB). The third insulating layer 124 may have a single layer or a plurality of layers of different materials stacked on each other.

[0080] According to an embodiment, the upper semiconductor layer is disposed on the third insulating layer 124. Specifically, the upper semiconductor layer is disposed on the third insulating layer 124, but does not overlap with the lower semiconductor layer. The upper semiconductor layer may include one of amorphous silicon (a-Si), polycrystalline silicon (p-Si), an oxide semiconductor, and an organic semiconductor. The oxide semiconductor includes at least one of Zn, In, Ga, Sn, or a mixture thereof. The oxide semiconductor is a metal oxide semiconductor and is made of the following materials: a metal oxide such as a metal oxide formed of zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti), or a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) or an oxide thereof. For example, the oxide semiconductor material may be one of zinc oxide (ZnO), zinc tin oxide (ZTO), indium zinc oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), and indium zinc tin oxide (IZTO).

[0081] According to an embodiment, the upper semiconductor layer includes a source region S2 disposed on one side, a drain region D2 disposed on the opposite side, and a channel region A2 disposed between the source region S2 and the drain region D2. Portions of the upper semiconductor layer connected to the source electrode SE2 and the drain electrode DE2 of each of the transistors T3 and T4, namely the source region S2 and the drain region D2, are doped with impurity ions, specifically, in the case of an NMOS transistor, n-type impurity ions. The n-type impurity ions may be alkali metals, alkaline earth metals, or n-type organic dopants. Examples of n-type organic dopants include: Cr2hpp4 (hpp: anions of 1,3,4,6,7,8-hexahydro-2H-pyrimido[1,2-a]pyrimidine), Fe2hpp4, Mn2hpp4, Co2hpp4, Mo2hpp4, W2hpp4, Ni2hpp4, Cu2hpp4, Zn2hpp4, W(hpp)4, etc. In addition, examples include other organic dopant compounds such as 4,4',5,5'-tetracyclohexyl-1,1',2,2',3,3'-hexamethyl-2,2',3,3-tetrahydro-1H,1'H2,2'-biimidazole; 2,2'-diisopropyl-1,1',3,3'-tetramethyl-2,2',3,3',4,4',5,5',6,6',7,7'-dodecahydro-1H,1'H-2,2'-bisbenzo[d]imidazole; 2,2'-diisopropyl-4,4',5,5'-tetrakis(4-methoxyphenyl)-1,1',3,3'-tetramethyl -2,2',3,3'-tetrahydro-1H,1'H-2,2'-biimidazole); or 2,2'-diisopropyl-4,5-bis(2-methoxyphenyl)-4',5'-bis(4-methoxyphenyl)-1,1',3,3'-tetramethyl-2,2',3,3'-tetrahydro-1H,1'H-2,2'-biimidazole.

[0082] According to an embodiment, when the upper semiconductor layer includes an oxide semiconductor, a light blocking layer that blocks light from the upper semiconductor layer is formed on and below the upper semiconductor layer.

[0083] According to an embodiment, the fourth insulating layer 125 is disposed on the upper semiconductor layer. The fourth insulating layer 125 covers the entire upper semiconductor layer. For example, the fourth insulating layer 125 is disposed on the upper semiconductor layer and is formed on the entire surface of the substrate 110.

[0084] According to an embodiment, the fourth insulating layer 125 is a gate insulating layer having a gate insulating function. The fourth insulating layer 125 may include the same material as the first insulating layer 122, or may include one or more other materials selected from the materials listed above for the first insulating layer 122. The second insulating layer 123 may have a single layer or a plurality of layers of different materials stacked on each other.

[0085] According to an embodiment, the third conductive layer G3 is disposed on the fourth insulating layer 125. The third conductive layer G3 overlaps at least a portion of the upper semiconductor layer. The third conductive layer G3 may include the same material as the first conductive layer G1 or may include at least one other material selected from the materials listed above for the first conductive layer G1. The third conductive layer G3 may have a single layer or a plurality of layers of different materials stacked on each other.

[0086] According to an embodiment, the third conductive layer G3 includes a conductive layer for transmitting a first scanning signal ( Figure 3 GW in the scanning line, the gate electrode of the third transistor T3 and the gate electrode of the fourth transistor T7.

[0087] According to an embodiment, the fifth insulating layer 126 covers the fourth conductive layer. The fifth insulating layer 126 is disposed on the first conductive layer G1 and generally on the entire surface of the substrate 110. The fifth insulating layer 126 is an interlayer dielectric layer. The fifth insulating layer 126 includes silicon oxide (SiO x ) and silicon nitride (SiN x ) multiple layers. However, it will be understood that the embodiments of the present disclosure are not limited thereto. The fifth insulating layer 126 may have a silicon oxide (SiO x ), silicon nitride (SiN x ), a single layer of silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc., or multiple layers of different materials stacked on each other.

[0088] According to an embodiment, the fifth insulating layer 126 is used to supply hydrogen ions (H+) so that n-type impurity ions can be doped into the upper semiconductor layer through heat treatment. This will be referred to below. Figures 5 to 7 In addition, the fifth insulating layer 126 provides a flat surface.

[0089] According to an embodiment, a plurality of source electrodes SE1 and SE2 and a plurality of drain electrodes DE1 and DE2 are disposed on the fifth insulating layer 126. Each of the source electrodes SE1 and SE2 and the drain electrodes DE1 and DE2 is formed of a conductive metal. For example, the source electrodes SE1 and SE2 and the drain electrodes DE1 and DE2 may include aluminum (Al), copper (Cu), titanium (Ti), or molybdenum (Mo).

[0090] According to an embodiment, the first source electrode SE1 is electrically connected to the source region S1 of the lower semiconductor layer, and the first drain electrode DE1 is electrically connected to the drain region D1 of the lower semiconductor layer. More specifically, the first source electrode SE1 and the first drain electrode DE1 are electrically connected to the source region S1 and the drain region D1 of the lower semiconductor layer through contact holes that penetrate the first insulating layer 122 to the fifth insulating layer 126, respectively.

[0091] According to an embodiment, the second source electrode SE2 is electrically connected to the source region S2 of the upper semiconductor layer, and the second drain electrode DE2 is electrically connected to the drain region D2 of the upper semiconductor layer. More specifically, the second source electrode SE2 and the second drain electrode DE2 are electrically connected to the source region S2 and the drain region D2 of the upper semiconductor layer, respectively, through contact holes penetrating the fourth insulating layer 125 and the fifth insulating layer 126.

[0092] According to an embodiment, a first via layer 127 is disposed on the fifth insulating layer 126 and is formed on the entire surface of the substrate 110 to cover the plurality of source electrodes SE1 and SE2 and the plurality of drain electrodes DE1 and DE2. The first via layer 127 is made of an insulating material. For example, the first via layer 127 may include a single layer or multiple layers of an inorganic material, an organic material, or an organic / inorganic composite material, and may be formed by various deposition methods. In some exemplary embodiments, the first via layer 127 is made of one or more of a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or a benzocyclobutene (BCB).

[0093] According to an embodiment, the second through-layer 128 is disposed on the first through-layer 127. The second through-layer 128 is formed on the entire surface of the substrate 110. The second through-layer 128 may include the same material as the first through-layer 127, or may include one or more other materials listed above for the first through-layer 127.

[0094] According to an embodiment, a contact metal CM is disposed between the first through layer 127 and the second through layer 128. The pixel electrode 140 is electrically connected to the contact metal CM through a contact hole in the second through layer 128. The contact metal CM is electrically connected to the first drain electrode DE1 through a contact hole in the first through layer 127. The contact metal CM electrically connects the pixel electrode 140 to the first drain electrode DE1. Note that the first through layer 127 and the contact metal CM may be removed. Then, the pixel electrode 140 may be directly connected to the first drain electrode DE1 through the contact hole in the second through layer 128.

[0095] According to an embodiment, the pixel electrode 140 is disposed on the second through layer 128. The pixel electrode 140 is an anode electrode of the organic light emitting diode.

[0096] According to an embodiment, the pixel electrode 140 includes a material having a high work function. The pixel electrode 140 includes indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and the like. The conductive materials listed above have a relatively high work function and are transparent. When the organic light-emitting display device is a top-emitting organic light-emitting display device, in addition to the conductive materials listed above, the pixel electrode 140 may also include a reflective material such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a combination thereof. Therefore, the pixel electrode 140 may have a single-layer structure of the conductive material and the reflective material listed above, or may have a multilayer structure in which a single layer is stacked on each other.

[0097] According to an embodiment, the pixel defining layer 130 is disposed on the pixel electrode 140. The pixel defining layer 130 includes an opening through which at least a portion of the pixel electrode 140 is exposed. The pixel defining layer 130 may include an organic material or an inorganic material. In an exemplary embodiment, the pixel defining layer 130 includes a material such as a photoresist, a polyimide resin, an acrylic resin, a silicon compound, or a polyacrylic resin.

[0098] According to an embodiment, an organic emission layer is disposed on a portion of the pixel electrode 140 exposed by the pixel defining layer 130, and a common electrode is disposed on the organic emission layer. The common electrode is a cathode electrode of the organic light emitting diode.

[0099] According to an embodiment, the common electrode includes a material with a low work function. The common electrode includes one of Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba or a compound or mixture thereof, for example, a mixture of Ag and Mg. The common electrode also includes an auxiliary electrode. The auxiliary electrode includes a layer formed by depositing a low work function material and a transparent metal oxide on the layer, the transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium tin zinc oxide (ITZO).

[0100] According to an embodiment, when the organic light emitting display device 60 is a top emission organic light emitting diode display device, a thin conductive layer having a low work function is formed as a common electrode, and a conductive layer such as an indium tin oxide (ITO) layer, an indium zinc oxide (IZO) layer, a zinc oxide (ZnO) layer, or an indium oxide (In 2 O 3) layer is formed on the thin conductive layer.

[0101] According to an embodiment, the pixel electrode 140 , the organic emission layer, and the common electrode form an organic light emitting diode.

[0102] Hereinafter, a method of manufacturing the source region S2 and the drain region D2 of the upper semiconductor layer will be described.

[0103] Figures 5 to 7 is a cross-sectional view showing a process of forming a source region and a drain region of an upper semiconductor layer.

[0104] Now refer to Figures 5 to 7 According to an embodiment, an oxide semiconductor A2_a, a fourth insulating layer 125, a third conductive layer G3, and a fifth insulating layer 126 are sequentially stacked on the third insulating layer 124. The oxide semiconductor A2_a is a metal oxide semiconductor such as indium gallium zinc oxide (IGZO) as described above. The fifth insulating layer 126 includes silicon oxide (SiO x ) and silicon nitride (SiN x ). For example, the fifth insulating layer 126 has a plurality of layers in which a silicon oxide layer 126b is stacked on a silicon nitride layer 126a. The stacking structure of the fifth insulating layer 126 is not limited thereto. In another exemplary embodiment, the fifth insulating layer 126 includes a plurality of layers formed by stacking a silicon nitride layer on a silicon oxide layer, or may be a single layer including silicon oxide or silicon nitride.

[0105] Next, according to an embodiment, the first end and the opposite second end of the oxide semiconductor A2_a are subjected to reduction treatment by heat treatment without a separate etching process such as a process of etching the fourth insulating layer 125. When heat is applied from above the substrate, hydrogen ions (H+) present in the fifth insulating layer 126 diffuse into the oxide semiconductor A2_a. In an exemplary embodiment, as Figure 6 As shown in FIG. 1 , during the heat treatment, hydrogen ions (H + ) are mainly generated in the silicon nitride layer 126 a of the fifth insulating layer 126 and diffused into the oxide semiconductor A2 — a .

[0106] According to the embodiment, by performing heat treatment, hydrogen ions (H+) diffuse into the first and second ends of the oxide semiconductor A2_a so that reduction starts to form a conductive source region S2 and a conductive drain region D2. Because the oxide semiconductor includes a region overlapping with the third conductive layer G3, the reduction becomes weaker toward the center of the oxide semiconductor A2_a so as to form a low conductive region. After the reduction by heat treatment, the source region S2 and the drain region D2 are formed at the first and second ends of the oxide semiconductor A2_a, respectively, and as shown in FIG. Figure 7 As shown in FIG. 1 , a channel region A2 as a low conductive region is formed between a source region S2 and a drain region D2 .

[0107] According to an embodiment, the heat treatment is performed at about 90° C. to about 110° C. However, the temperature is not limited thereto, and the heat treatment may be performed at a temperature higher than 110° C. It will be understood that hydrogen ions (H+) are not necessarily generated in the fifth insulating layer 126. Hydrogen ions (H+) present in the third insulating layer 124 and the fourth insulating layer 125 may diffuse into the oxide semiconductor A2_a.

[0108] According to an embodiment, the fourth insulating layer 125 has a minimum thickness so that hydrogen ions (H+) generated in the fifth insulating layer 126 do not substantially reach the lower semiconductor layer. In an exemplary embodiment, if the heat treatment temperature is about 95° C., the thickness of the fourth insulating layer 125 is equal to or greater than The hydrogen concentration in the fourth insulating layer 125 is less than or equal to about 9×10 20 Atom / cm 3 .

[0109] According to an embodiment, the third insulating layer 124 has a thickness greater than or equal to about The hydrogen concentration in the third insulating layer 124 is less than or equal to about 9×10 20 Atom / cm 3 The thickness of the fifth insulating layer 126 is about In an exemplary embodiment, the fifth insulating layer 126 includes silicon oxide (SiO x ) layer and disposed on a silicon oxide (SiO x ) layer on the silicon nitride (SiN x ) layer, the silicon oxide (SiO x ) layer has a value greater than or equal to about The thickness of the silicon nitride (SiN x ) layer has about 1500 to about Thickness.

[0110] According to the embodiment, the surface resistance of the upper semiconductor layer doped with n-type impurity ions through the thermal treatment is less than 1000Ω / □. Specifically, the surface resistance of the source region S2 and the drain region D2 is less than or equal to about 1000Ω / □.

[0111] In this way, according to an embodiment, by doping an oxide semiconductor with n-type impurity ions only through heat treatment without an additional etching process, it is possible to prevent side effects that may be generated during the etching process, such as an increase in a tapered angle, a short circuit in the third conductive layer G3 and the upper semiconductor, etc. In addition, according to the above-mentioned doping scheme according to the embodiment, it is possible to reduce the wiring resistance of the upper semiconductor layer by increasing the temperature during the heat treatment. Because the heat treatment temperature can be increased, the dehydrogenation in the lower semiconductor layer can be improved so that the driving range of the transistors T1, T2, T5, T6 and T7 including the lower semiconductor layer can be increased. Even if the heat treatment temperature is increased, it is still possible to prevent hydrogen ions (H+) from diffusing into the transistors T1, T2, T5, T6 and T7 by adjusting the thickness of the fourth insulating layer 125. In an exemplary embodiment, the driving range of the transistors T1, T2, T5, T6 and T7 is greater than or equal to about 2.9V.

[0112] Next, an organic light emitting display device according to an exemplary embodiment of the present disclosure will be described. Figures 1 to 7 In addition, the same reference numerals may refer to the same elements as those in the above reference. Figures 1 to 7 Features described are similar to features.

[0113] Figure 8 is a cross-sectional view of an organic light emitting display device 61 according to an exemplary embodiment of the present disclosure.

[0114] According to an embodiment, Figure 8 The organic light emitting display device 61 shown in FIG. Figures 1 to 7 The organic light emitting display device 60 shown in FIG. 1 is different in that the fourth insulating layer 125_1 is formed only in a portion of the substrate 110 to cover the upper semiconductor layer, rather than on the entire surface of the substrate 110 .

[0115] According to an embodiment, the fourth insulating layer 125_1 includes Figure 4 The first insulating layer 122 may be the same material as that of the first insulating layer 122 shown in , or may include one or more other materials selected from the materials listed above for the first insulating layer 122 .

[0116] According to an embodiment, the fourth insulating layer 125_1 covers the upper portion and the side of the upper semiconductor layer. Since the fourth insulating layer 125_1 covers the upper semiconductor layer, as in Figures 1 to 7 As in the exemplary embodiment shown in FIG. 1 , the fourth insulating layer 125_1 performs the same function of supplying hydrogen ions (H+) so that the upper semiconductor layer can be doped with n-type impurity ions through heat treatment.

[0117] Fig. 9 is a cross-sectional view of an organic light emitting display device according to an exemplary embodiment of the present disclosure.

[0118] According to an embodiment, Fig. 9 The organic light emitting display device 62 shown in FIG. Figures 1 to 7 The organic light emitting display device 60 shown in FIG. 1 is different in that the fourth insulating layer 125_2 is formed in a portion of the substrate 110 to cover the upper semiconductor layer, rather than on the entire surface of the substrate 110. In addition, Fig. 9 The organic light emitting display device 62 shown in FIG. Figure 8 The organic light emitting display device 61 shown in FIG. 6 is different in that the fourth insulating layer 125_2 includes a portion overlapping with and covering the lower semiconductor layer.

[0119] According to an embodiment, the fourth insulating layer 125_2 may include Figure 4 The first insulating layer 122 may be the same material as that of the first insulating layer 122 shown in , or may include one or more other materials selected from the materials listed above for the first insulating layer 122 .

[0120] According to an embodiment, the fourth insulating layer 125_2 covers the upper portion and the side of the upper semiconductor layer. In addition, the fourth insulating layer 125_2 extends to a region overlapping the lower semiconductor layer.

[0121] According to the embodiment, since the fourth insulating layer 125_2 covers the upper semiconductor layer, Figures 1 to 7 As in the exemplary embodiment shown in , the fourth insulating layer 125_2 performs the same function of supplying hydrogen ions (H+) so that the upper semiconductor layer can be doped with n-type impurity ions by heat treatment. In addition, since the fourth insulating layer 125_2 extends to the region overlapping the lower semiconductor layer, it is possible to prevent hydrogen ions (H+) from diffusing into the lower semiconductor layer, thereby increasing the driving range of the transistors T1, T2, T5, T6, and T7 including the lower semiconductor layer.

[0122] The effects of the embodiments of the present disclosure are not limited to the foregoing, and other various effects can be expected herein.

[0123] Although exemplary embodiments of the present disclosure have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the embodiments of the present disclosure as recited in the accompanying claims.

Claims

1. A light-emitting display device, wherein: The light emitting display device comprises: A substrate having a display area and a non-display area; A buffer layer is disposed on the substrate; A first semiconductor layer, disposed on the buffer layer in the display region; A first insulating layer, disposed on the first semiconductor layer; A first conductive layer, disposed on the first insulating layer and overlapping the first semiconductor layer; a second insulating layer, disposed on the first semiconductor layer; a second semiconductor layer, disposed on the second insulating layer in the display region and not overlapping the first semiconductor layer; a third insulating layer, disposed on the second semiconductor layer in the display area; a second conductive layer, disposed on the third insulating layer and overlapping the second semiconductor layer; a fourth insulating layer, disposed on the second semiconductor layer; and A third conductive layer is disposed on the fourth insulating layer, Wherein, the first semiconductor layer comprises low temperature polysilicon, Wherein, the second semiconductor layer comprises an oxide semiconductor, The third insulating layer overlaps with the upper surface of the second semiconductor layer. Wherein, the third conductive layer comprises: a first electrode directly connected to the first semiconductor layer; a second electrode directly connected to the first semiconductor layer and spaced apart from the first electrode; a third electrode directly connected to the second semiconductor layer; and A fourth electrode is directly connected to the second semiconductor layer and is spaced apart from the third electrode.

2. The light-emitting display device according to claim 1, wherein: The first electrode, the second electrode, the third electrode, and the fourth electrode are made of the same material.

3. The light-emitting display device according to claim 1, wherein: The oxide semiconductor is indium-gallium-zinc oxide.

4. The light-emitting display device according to claim 1, in, The third insulating layer has a thickness greater than or equal to The thickness of Wherein, the surface resistance of the second semiconductor layer is equal to or less than 1000Ω / □.

5. The light-emitting display device according to claim 1, wherein: The thickness of the second insulating layer is greater than or equal to 6. The light-emitting display device according to claim 5, wherein: The second insulating layer includes silicon oxide.

7. The light-emitting display device according to claim 6, wherein: The second insulating layer or the third insulating layer contains less than or equal to 9×10 20 Atom / cm 3 of hydrogen concentration.

8. The light-emitting display device according to claim 1, wherein: The thickness of the fourth insulating layer is greater than or equal to 9. The light-emitting display device according to claim 1, wherein: The fourth insulating layer includes a plurality of layers of a silicon oxide layer and a silicon nitride layer.

10. The light emitting display device according to claim 9, wherein: The thickness of the silicon oxide layer is greater than or equal to The thickness of the silicon nitride layer is to within the range.

11. The light-emitting display device according to claim 1, wherein: The first semiconductor layer includes a first region and a second region at a first end and an opposite second end of the first semiconductor layer, respectively, and includes a channel region between the first region and the second region, and The first region and the second region are doped with n-type impurity ions.

12. The light-emitting display device according to claim 1, wherein: The first insulating layer overlaps the second semiconductor layer.

13. The light-emitting display device according to claim 1, wherein: Each of the first electrode, the second electrode, the third electrode, and the fourth electrode is disposed in the display area.

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