Semiconductor device and electrical device having the same
By setting the electrode extension in the second electrode graphics of the semiconductor device, the problem of uneven distribution of the electric field is solved, and the higher voltage isolation capacity is achieved, and the cost and process have not increased.
Patent Information
- Application Number
- CN202310916672.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-24
- Publication Date
- 2025-01-24
AI Technical Summary
In existing semiconductor devices, the electric field distribution at the edge region of the electrode and the line connection positions is uneven, resulting in dielectric breakdown and reducing high-voltage isolation capabilities.
By setting the electrode extension in the second electrode graphics, the outer edge of the second electrode structure is expanded and the average edge electric field is reduced, thereby reducing the strength of the electric field and improving the voltage isolation ability.
A more uniform electric field distribution is achieved, which significantly suppress the concentration of the electric field and improves the ability of high -voltage isolation without increasing special process steps or costs.
Smart Images
Figure CN119365068A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a semiconductor device having the semiconductor device. Background Art
[0002] In the related art, the structures of some semiconductor devices such as on-chip transformers and on-chip capacitors have uneven electric field distribution between the electrode main body distribution area and the outer edge area of the electrode main body distribution area, and the electric field lines in the outer edge area of the electrode main body distribution area converge significantly, causing this location to be more prone to dielectric breakdown than other electrode main body distribution areas, thereby reducing the high-voltage isolation capability of the device. Summary of the invention
[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a semiconductor device that can suppress the electric field concentration in the electrode edge area and the line connection position, making the electric field distribution more uniform and improving the high voltage isolation capability.
[0004] A second aspect of the present invention provides an electrical device.
[0005] In order to achieve the above-mentioned purpose, a semiconductor device according to an embodiment of the first aspect of the present invention comprises: a substrate layer, a first electrode pattern, an isolation dielectric layer and a second electrode pattern; in the longitudinal direction of the device, the first electrode pattern is located on the substrate layer, the isolation dielectric layer is located on the first electrode pattern, and the second electrode pattern is located on the isolation dielectric layer; the first electrode pattern comprises a first electrode main body, the second electrode pattern comprises a second electrode main body and an electrode extension portion connected to each other, and in the device plane where the electrode extension portion is located, the electrode extension portion is located at the outer edge of the second electrode main body; wherein, in the longitudinal direction of the device, the second electrode main body is arranged corresponding to the first electrode main body, and the electrode extension portion extends toward the edge position corresponding to the substrate layer along the lateral direction of the device.
[0006] The semiconductor device of the present application, by providing an electrode extension portion on the second electrode pattern, is equivalent to extending the outer edge of the second electrode structure, so that the area of the second electrode structure is expanded, and the edge electric field is averaged by the electrode extension portion, thereby reducing the electrode edge electric field strength, thereby achieving the purpose of improving voltage isolation capability.
[0007] In some embodiments, the electrode extension portion surrounds the second electrode body portion.
[0008] In some embodiments, the electrode extension portion extends to an edge of the corresponding substrate layer.
[0009] In some embodiments, a projection of the electrode extension on the substrate layer at least covers the first electrode pattern.
[0010] In some embodiments, the first electrode pattern further includes: a first electrode pad, the first electrode pad is connected to the first end of the first electrode body and is used for binding connection of the first electrode body.
[0011] In some embodiments, a first window is provided on the isolation dielectric layer corresponding to the first electrode pad, and a second window is provided on the electrode extension portion corresponding to the first window, and an area of the second window is larger than an area of the first window.
[0012] In some embodiments, the semiconductor device further includes: a dielectric layer, the dielectric layer is located on the substrate layer, and the first electrode pattern is located in the dielectric layer.
[0013] In some embodiments, the first electrode pattern further includes: a second electrode pad, which is disposed on the dielectric layer; an electrode connecting line, which is disposed on the substrate layer and is located between the substrate layer and the dielectric layer; a first connecting hole is disposed in the dielectric layer corresponding to the second electrode pad, and a second connecting hole is disposed in the dielectric layer corresponding to the second end of the first electrode body, the electrode connecting line is connected to the second electrode pad through the first connecting hole, and the electrode connecting line is connected to the second end of the first electrode body through the second connecting hole.
[0014] In some embodiments, the isolation dielectric layer is provided with a third window corresponding to the second electrode pad, the electrode extension portion is provided with a fourth window corresponding to the third window, and an area of the fourth window is greater than an area of the third window.
[0015] In some embodiments, the first electrode body is a first electrode coil, the first electrode coil is located on the dielectric layer, and the first electrode coil is configured as a spiral structure that spreads from the inside to the outside.
[0016] In some embodiments, the second electrode body is a second electrode coil, the second electrode coil is disposed on the isolation medium layer, the second electrode coil is configured as a spiral structure that spreads from the inside to the outside, and the second electrode coil is disposed opposite to the first electrode coil.
[0017] In some embodiments, the second electrode pattern further includes: a third electrode pad, the third electrode pad is disposed on the isolation dielectric layer, the third electrode pad is connected to the inner end of the second electrode coil, and is used to bind the second electrode coil.
[0018] In some embodiments, both the first electrode pattern and the second electrode body are one or more, wherein a plurality of the second electrode bodies are respectively arranged corresponding to a plurality of the first electrode bodies of the first electrode patterns.
[0019] In some embodiments, there are two first electrode patterns and two second electrode main bodies, the two first electrode patterns are arranged in the transverse direction of the device, and the two second electrode main bodies are arranged corresponding to the first electrode main bodies of the two first electrode patterns.
[0020] In some embodiments, the second electrode pattern further includes an extension pad, and the extension pad is disposed on the isolation dielectric layer and corresponds to a central position of the electrode extension portion, and is used to bind the electrode extension portion.
[0021] In order to achieve the above-mentioned object, an electrical device according to an embodiment of the second aspect of the present invention includes the semiconductor device.
[0022] The electrical device according to the embodiment of the present invention can improve the isolation withstand voltage level by adopting the semiconductor device of the above embodiment without adding additional special process steps and without increasing the cost.
[0023] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:
[0025] Figure 1 is a perspective view of a semiconductor device according to an embodiment of the present invention;
[0026] Figure 2 It corresponds to Figure 1 Schematic diagram of the anatomy of a semiconductor device;
[0027] Figure 3 is a perspective view of a semiconductor device according to another embodiment of the present invention;
[0028] Figure 4 is a top view of a semiconductor device according to an embodiment of the present invention;
[0029] Figure 5 is a top view of a semiconductor device according to an embodiment of the present invention;
[0030] Figure 6 It corresponds to Figure 5 Schematic diagram of the anatomy of a semiconductor device;
[0031] Figure 7 is a schematic diagram of a dielectric layer and a first electrode pattern thereon according to an embodiment of the present invention;
[0032] Figure 8 is a schematic diagram of an isolation dielectric layer and a window thereon according to an embodiment of the present invention;
[0033] Fig. 9 is a top view of a semiconductor device according to an embodiment of the present invention;
[0034] Fig.10 is a schematic diagram of a substrate layer and electrode connection lines thereon according to an embodiment of the present invention;
[0035] Fig.11 is a schematic diagram of a dielectric layer and a connecting hole thereon according to an embodiment of the present invention;
[0036] Fig.12 is a block diagram of an electrical device according to an embodiment of the present invention.
[0037] Reference numerals:
[0038] Electrical equipment 1000;
[0039] Semiconductor device 100;
[0040] Substrate layer 1, first electrode pattern 2, isolation dielectric layer 3, second electrode pattern 4;
[0041] First electrode main body 21, second electrode main body 41, electrode extension portion 42, first electrode pad 22, first window 31, second window 421, dielectric layer 5, second electrode pad 23, electrode connecting line 24, first connecting hole 51, second connecting hole 52, third window 32, fourth window 422, extension pad 43, third electrode pad 44, pad 25. DETAILED DESCRIPTION
[0042] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.
[0043] Reference below Figure 1-Figure 11 A semiconductor device according to an embodiment of the present invention is described.
[0044] The semiconductor device of the embodiment of the present invention can be a high-voltage isolation device, including but not limited to a high-voltage isolation switch device, a high-voltage capacitor isolator, a high-voltage magnetic isolator, etc., which can improve the electric field distribution between the high-voltage difference electrodes of such devices, thereby improving the voltage resistance characteristics of high-voltage dielectric materials and high and low voltage difference electrodes.
[0045] Figure 1is a perspective view of a semiconductor device according to an embodiment of the present invention, Figure 2 For the corresponding Figure 1 Schematic diagram of the anatomy of a semiconductor device, such as Figure 1 As shown in FIG. 2 , the semiconductor device 100 includes a substrate layer 1 , a first electrode pattern 2 , an isolation dielectric layer 3 and a second electrode pattern 4 .
[0046] In the longitudinal direction of the device, the first electrode pattern 2 is located on the substrate layer 1 , the dielectric layer 3 is located on the first electrode pattern 2 , and the second electrode pattern 4 is located on the isolation dielectric layer 3 .
[0047] In the embodiment, the longitudinal direction of the device may be a direction perpendicular to the plane of the substrate layer 1 , and the lateral direction of the device may be a direction parallel to the plane of the substrate layer 1 , that is, orthogonal to the vertical direction.
[0048] The isolation dielectric layer 3 plays an isolation role, and the first electrode pattern 2 and the second electrode pattern 4 located on both sides of the isolation dielectric layer 3 induce each other to generate an electric field to achieve signal isolation transmission.
[0049] The first electrode pattern 2 includes a first electrode body 21. For example, for an on-chip transformer, the first electrode body may be an electrode coil, and for an on-chip capacitor, the first electrode body may be a capacitor electrode plate, etc. The first electrode pattern 2 may also include some connecting parts and binding parts, etc.
[0050] The second electrode pattern 4 includes a second electrode main body 41 and an electrode extension 42 connected to each other. Similarly, the second electrode main body 41 can be an electrode coil or a capacitor electrode plate, etc. In the device plane where the electrode extension 42 is located, the electrode extension 42 is located at the outer edge of the second electrode main body 41. The electrode extension 42 can surround the second electrode main body 41 or can be located only on one side or both sides of the second electrode main body 41 or half surround or surround three quarters of the area. It can play the role of extending the electrode main body 41, so as to average the electric field distribution at the outer edge of the second electrode main body 41, and avoid the concentration of the electric field here and cause dielectric breakdown.
[0051] The second electrode main body 41 is arranged corresponding to the first electrode main body 21 in the longitudinal direction of the device, and the electrode extension 42 extends toward the edge position of the corresponding substrate layer 1 in the transverse direction of the device. Figure 1 The middle electrode extension portion 42 may extend to a position corresponding to the edge of the substrate layer 1 , or may extend to a position close to the edge of the substrate layer 1 , or may extend to a position at a distance from the edge of the substrate layer 1 .
[0052] Specifically, when working, an induced electric field is generated between the first electrode main body 21 and the second electrode main body 41, and the electric field lines are more concentrated at the edge position, which is more likely to cause dielectric breakdown and affect the voltage isolation capability. However, the semiconductor device 100 of the present application, by setting the electrode extension 42 on the second electrode pattern 4, is equivalent to expanding the outer edge area of the second electrode structure, so that the area of the second electrode structure is expanded, and the edge electric field is averaged by the electrode extension 42, thereby reducing the edge electric field strength, thereby achieving the purpose of improving the voltage isolation capability. In addition, the preparation of the electrode extension 42 can adopt a standard semiconductor preparation process, for example, the same process as the second electrode main body 41 can be adopted, and it can be prepared in the same steps as the second electrode main body 41, without adding additional special process steps, and will not increase the cost significantly.
[0053] In the embodiment of the present invention, the first electrode pattern 2 and the second electrode body 41 are both one or more, for example Figure 1 For two examples, Figure 3 As shown, the first electrode pattern 2 and the second electrode main body 41 are both one. Of course, the first electrode pattern 2 and the second main body 41 can also be set in multiple groups as needed. Among them, the multiple second electrode main bodies 41 are respectively set corresponding to the first electrode main bodies 21 of the multiple first electrode patterns 2 to achieve signal isolation transmission.
[0054] In the embodiment, the second electrode body 41 is extended to reduce the edge electric field strength. Figure 1 As shown, the electrode extension portion 42 surrounds the second electrode main body 41, extends to the four sides of the second electrode main body 41, and extends toward the edge of the corresponding substrate layer 1, so as to achieve the goal of extending the second electrode pattern 4, thereby averaging the electric field strength at the edge of the second electrode main body 41, reducing the electric field strength at the edge, avoiding dielectric breakdown there, and improving the voltage isolation capability.
[0055] In some embodiments, Figure 4 As shown, the electrode extension portion 42 extends to the edge of the corresponding substrate layer 1, that is, the first electrode pattern 4 is extended to a degree close to the substrate edge or the substrate layer area, thereby achieving the effect of averaging the electric field strength at the edge of the second electrode body 41.
[0056] Alternatively, in some embodiments, the electrode extension portion 42 does not necessarily extend to the edge position of the corresponding substrate layer 1. For example, the projection of the electrode extension portion 42 on the substrate layer 1 at least covers the first electrode pattern 2, that is, it can cover the first electrode main body 21 and other connecting parts, etc., so as to average the electric field distribution of the first electrode main body 21 and the second electrode main body 41, reduce the electric field strength at the edge of the second electrode main body 41, and reduce the concentration of the electric field there.
[0057] For example, Figure 5 is a top view of a semiconductor device according to an embodiment of the present invention, Figure 6 For the corresponding Figure 4 Schematic diagram of the anatomy of a semiconductor device. Figure 4 and 5 As shown, the electrode extension portion 42 extends to the vicinity of the edge of the corresponding substrate layer 1, and is projected on the plane where the first electrode pattern 2 is located to at least cover the first electrode image 2, and is arranged in a manner surrounding the electrode. In this embodiment, although the electrode extension portion 42 does not extend to the edge position of the corresponding substrate layer 1, only a limited area is retained, for example, the area of the electrode extension portion 42 does not exceed 25% of the top view area of the substrate layer 1, it also falls within the protection scope of the present invention.
[0058] In an embodiment, Figure 7 As shown, the first electrode pattern 2 further includes a first electrode pad 22 , which is connected to a first end of the first electrode body 21 and is used for binding the first electrode body 21 .
[0059] Furthermore, if Figure 8 As shown, a first window 31 is provided on the isolation dielectric layer 3 corresponding to the first electrode pad 22. Fig. 9 As shown, the electrode extension portion 42 is provided with a second window 421 corresponding to the first window, and the first electrode pad 22 can be wire-bonded through the first window 31 and the second window 421. In addition, the area of the second window 421 is larger than the area of the first window 31 to avoid a short circuit between the first electrode main body 21 and the second electrode main body 41.
[0060] In the embodiment, the first window 31 and the second window 421 may be circular, semicircular or other shapes, which are not specifically limited herein.
[0061] In order to achieve a better high-voltage isolation effect, the isolation dielectric layer 3 will be relatively thick, for example, the thickness is greater than 10um. Based on the current preparation process, it is not easy to prepare the connecting holes. However, in this application, a window is set on the isolation dielectric layer 3 corresponding to the pad position, which can be achieved through the existing preparation process, so it can be compatible with the standard preparation process.
[0062] like Figure 1 As shown in FIG. 2 , the semiconductor device 100 further includes a dielectric layer 5 . The dielectric layer 5 is located on the substrate layer 1 , and the first electrode pattern 2 is located on the dielectric layer 5 .
[0063] In an embodiment, for some semiconductor devices such as capacitive isolation devices, the electrode pattern may be provided with a pad to achieve a single-ended electrical connection of the capacitive device, while for other isolation devices such as an on-chip transformer, the electrode pattern has a double-ended electrical connection.
[0064] In some embodiments of the present invention, Figure 7 As shown, the first electrode pattern 2 further includes a second electrode pad 23, and the second electrode pad 23 is disposed on the dielectric layer 5. Fig.10 As shown, the first electrode pattern 2 further includes an electrode connection line 24 . The electrode connection line 24 is disposed on the substrate layer 1 and located between the substrate layer 1 and the dielectric layer 5 .
[0065] like Fig.11 As shown, the dielectric layer 5 is provided with a first connecting hole 51 corresponding to the second electrode pad 23, and the dielectric layer 5 is provided with a second connecting hole 52 corresponding to the second end of the first electrode main body 21. The electrode connecting line 24 is connected to the second end of the first electrode main body 21, that is, the pad 25 at one end of the first electrode pattern, through the first connecting hole 51, and the electrode connecting line 24 is connected to the second electrode pad 23 through the second connecting hole 52, so that the connection between the first electrode main body 21 and the second electrode pad 23 can be realized.
[0066] Furthermore, if Figure 8 As shown, the isolation dielectric layer 3 is provided with a third opening 32 corresponding to the second electrode pad 23, as shown in FIG. Figure 8 As shown, the electrode extension portion 42 is provided with a fourth window 422 corresponding to the third window 32. The wire bonding of the second electrode pad 23 can be achieved through the third window 32 and the fourth window 422. In addition, the area of the fourth window 422 is larger than the area of the third window 32 to avoid a short circuit between the first electrode main body 21 and the second electrode main body 41.
[0067] In the above embodiment, two first electrode patterns 2 and two second electrode main bodies 41 are used as an example, and the two first electrode patterns 2 are arranged horizontally along the device, and the two second electrode main bodies 41 are arranged corresponding to the two first electrode patterns 2 to achieve signal isolation transmission. In the embodiment, the number of groups of electrode patterns can also be set according to the specific structure. For example, for an on-chip transformer, one or more groups of electrode patterns can be arranged correspondingly to achieve high-voltage signal isolation transmission.
[0068] like Fig. 9 As shown, the second electrode pattern 4 further includes an extension pad 43 , which is disposed on the isolation dielectric layer 3 and corresponds to the central position of the electrode extension 42 , and is used to bind the electrode extension 43 .
[0069] Take the on-chip transformer as an example, Figure 1As shown in Figure 2, the first electrode body 21 is a first electrode coil, which can be used as a primary coil or a secondary coil of a transformer. The first electrode coil is located on the dielectric layer 5, and the first electrode coil is arranged in a spiral structure that spreads from the inside to the outside. The second electrode body 41 is a second electrode coil, which is arranged on the isolation dielectric layer 3, and the second electrode coil is arranged in a spiral structure that spreads from the inside to the outside, and the second electrode coil is arranged opposite to the first electrode coil. When the first electrode coil is a primary coil, the second electrode coil can be used as a secondary coil of a transformer, or when the first electrode coil is a secondary coil of a transformer, the second electrode coil can be used as a primary coil of a transformer.
[0070] The first end of the first electrode coil is connected to the first electrode pad 22, and the central pad of the first electrode coil is connected to the second electrode pad 23 through the electrode connection line 24 on the substrate layer 1, and the first electrode pad 22 and the second electrode pad 23 can be exposed through the openings on the isolation medium 3 and the electrode extension 42, so that wire bonding can be performed. The second electrode pattern 4 also includes a third electrode pad 44, which is arranged on the isolation medium layer 3, and the third electrode pad 44 is connected to the inner end of the second electrode coil for binding the second electrode coil.
[0071] During operation, an electric field is induced between the first electrode coil and the second electrode coil, thereby achieving isolated transmission of high-voltage signals.
[0072] In general, the semiconductor device 100 of the embodiment of the present invention, by providing the electrode extension portion 42 through the first electrode pattern 4, is equivalent to extending the first electrode, which can change the edge electric field distribution, especially extending to the edge position corresponding to the substrate layer 1, that is, the entire second electrode pattern covers the entire first electrode pattern, which can achieve better isolation and withstand voltage performance, significantly suppress the electric field concentration of the connection line and the connection pad part of the first electrode main body 41 and the second electrode main body 21, thereby improving the isolation withstand voltage level of the two electrodes. And no special process technology is required, so it is compatible with standard semiconductor manufacturing processes.
[0073] Based on the semiconductor device 100 of the above embodiment, a second embodiment of the present invention provides an electrical device.
[0074] Fig.12 1 is a schematic diagram of an electrical device according to an embodiment of the present invention. The electrical device 1000 of the embodiment of the present invention includes the semiconductor device 100 of the above embodiment. The specific structure of the semiconductor device 100 can refer to the description of the above embodiment, wherein the semiconductor device 100 includes but is not limited to on-chip capacitors, on-chip transformers, etc.
[0075] The electrical device 1000 according to the embodiment of the present invention can improve the isolation withstand voltage level by adopting the semiconductor device 100 of the above embodiment without adding additional special process steps and increasing the cost.
[0076] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.
[0077] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.
Claims
1. A semiconductor device, characterized in that: include: A substrate layer, a first electrode pattern, an isolation dielectric layer, and a second electrode pattern; In the longitudinal direction of the device, the first electrode pattern is located above the substrate layer, the isolation dielectric layer is located on the first electrode pattern, and the second electrode pattern is located on the isolation dielectric layer; The first electrode pattern includes a first electrode main body, the second electrode pattern includes a second electrode main body and an electrode extension portion connected to each other, and the electrode extension portion is located at the outer edge of the second electrode main body on the device plane where the electrode extension portion is located; The second electrode main body is arranged corresponding to the first electrode main body in the longitudinal direction of the device, and the electrode extension portion extends toward an edge position corresponding to the substrate layer in the transverse direction of the device.
2. The semiconductor device according to claim 1, wherein: The electrode extension portion surrounds the second electrode body portion.
3. The semiconductor device according to claim 1 or 2, characterized in that: The electrode extension portion extends to an edge corresponding to the substrate layer.
4. The semiconductor device according to claim 1 or 2, characterized in that: The projection of the electrode extension on the substrate layer at least covers the first electrode pattern.
5. The semiconductor device according to claim 1, wherein: The first electrode pattern further includes: A first electrode pad is connected to a first end of the first electrode body and is used for binding connection of the first electrode body.
6. The semiconductor device according to claim 5, characterized in that A first window is provided on the isolation dielectric layer corresponding to the first electrode pad, and a second window is provided on the electrode extension portion corresponding to the first window, and an area of the second window is larger than an area of the first window.
7. The semiconductor device according to claim 6, characterized in that The semiconductor device further comprises: A dielectric layer is located on the substrate layer, and the first electrode pattern is located on the dielectric layer.
8. The semiconductor device according to claim 7, characterized in that The first electrode pattern further includes: A second electrode pad, the second electrode pad being arranged on the dielectric layer (5); An electrode connection line, the electrode connection line is arranged on the substrate layer and located between the substrate layer and the dielectric layer; The dielectric layer is provided with a first connecting hole corresponding to the second electrode pad, the dielectric layer is provided with a second connecting hole corresponding to the second end of the first electrode body, the electrode connecting line is connected to the second electrode pad through the first connecting hole, and the electrode connecting line is connected to the second end of the first electrode body through the second connecting hole.
9. The semiconductor device according to claim 8, characterized in that The isolation dielectric layer is provided with a third window corresponding to the second electrode pad, and the electrode extension portion is provided with a fourth window corresponding to the third window, and an area of the fourth window is greater than an area of the third window.
10. The semiconductor device according to claim 8, characterized in that The first electrode body is a first electrode coil, the first electrode coil is located on the dielectric layer, and the first electrode coil is configured as a spiral structure that spreads from the inside to the outside.
11. The semiconductor device according to claim 10, characterized in that The second electrode body is a second electrode coil, which is disposed on the isolation medium layer. The second electrode coil is configured as a spiral structure that spreads from the inside to the outside, and the second electrode coil is disposed opposite to the first electrode coil.
12. The semiconductor device according to claim 11, characterized in that The second electrode pattern further includes: A third electrode pad is disposed on the isolation dielectric layer and is connected to an inner end of the second electrode coil for binding the second electrode coil.
13. The semiconductor device according to claim 1, wherein: The first electrode pattern and the second electrode main body are both one or more, wherein a plurality of the second electrode main bodies are respectively arranged corresponding to the first electrode main bodies of a plurality of the first electrode patterns.
14. The semiconductor device according to claim 13, characterized in that There are two first electrode patterns and two second electrode main bodies, the two first electrode patterns are arranged in the transverse direction of the device, and the two second electrode main bodies are arranged corresponding to the first electrode main bodies of the two first electrode patterns.
15. The semiconductor device according to claim 14, characterized in that The second electrode pattern further includes an extension pad, which is disposed on the isolation dielectric layer and corresponds to a central position of the electrode extension portion, and is used to bind the electrode extension portion.
16. An electrical device, characterized in that: A semiconductor device comprising any one of claims 1 to 15.