Apparatus, system and method for efficiently picking microaccumulations for

Abstract

A disclosed method for efficiently picking micro-operations for execution includes selecting a first set of micro-operations to be executed during a certain clock cycle. The method also includes selecting a second set of micro-operations to be performed during the certain clock cycle. The method additionally includes replacing one or more complex microcalculations included in the first set of microcalculations with one or more simple microcalculations included in the second set of microcalculations at least in part due to the number of complex microcalculations included in the first set of microcalculations exceeding a set of complex resources capable of performing the complex microcalculations. Various other apparatuses, systems, and methods are also disclosed.

Description

[0001] Priority declaration

[0002] This application claims priority to U.S. application No. 17 / 855,528, filed on June 30, 2022, the disclosure of which is incorporated herein by reference in its entirety. Background Art

[0003] Processors often include a picker responsible for selecting a micro-operation group (commonly referred to as micro-operation), which is fed to implementation resources, such as an arithmetic logic unit (ALU), a binary multiplier and / or a floating point unit (FPU) for implementation. In some examples, the ALU cannot perform and / or implement some complex micro-operations (e.g., multiplication and / or division operations). In these examples, a binary multiplier and / or FPU can perform and / or implement such complex micro-operations. However, these binary multipliers and / or FPUs may need and / or consume more space and / or real estate than the ALU on such processors. For this reason, manufacturers often select and / or preferably include a processor architecture that includes more ALUs than binary multipliers and / or FPUs.

[0004] Accordingly, the present disclosure identifies and addresses the need for additional and improved apparatus, systems, and methods for efficiently picking micro-operations in view of the number of execution resources (eg, ALUs, binary multipliers, and / or FPUs) included in certain processor architectures. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The accompanying drawings illustrate several exemplary implementations and are a part of the specification. Together with the following description, these drawings demonstrate and explain the various principles of the present disclosure.

[0006] Figure 1 is a block diagram of an exemplary processor for efficiently picking micro-operations for execution according to one or more implementations of the present disclosure.

[0007] Figure 2 is a block diagram of an exemplary implementation of certain features that facilitate efficient picking of micro-operations for execution in accordance with one or more implementations of the present disclosure.

[0008] Figure 3 is a block diagram of an exemplary pipeline included in a processor that facilitates efficient selection of micro-operations for execution in accordance with one or more implementations of the present disclosure.

[0009] Figure 4 is a block diagram of an exemplary implementation of certain features that facilitate efficient picking of micro-operations for execution in accordance with one or more implementations of the present disclosure.

[0010] Figure 5is a block diagram of an exemplary pipeline included in a processor that facilitates efficient selection of micro-operations for execution in accordance with one or more implementations of the present disclosure.

[0011] Figure 6 is a block diagram of an exemplary implementation of a processor that efficiently picks micro-operations for execution in accordance with one or more implementations of the present disclosure.

[0012] Figure 7 is a block diagram of an exemplary implementation of a processor that efficiently picks micro-operations for execution in accordance with one or more implementations of the present disclosure.

[0013] Figure 8 is a flow chart of an exemplary method for efficiently picking micro-operations for execution according to one or more implementations of the present disclosure.

[0014] In all drawings, the same reference numerals and descriptions indicate similar but not necessarily identical elements. Although the exemplary implementations described herein are susceptible to various modifications and alternative forms, specific implementations have been shown by way of example in the drawings and will be described in detail herein. However, the exemplary implementations described herein are not intended to be limited to the specific forms disclosed. On the contrary, the present disclosure covers all modifications, equivalents, and alternatives that fall within the scope of the appended claims. DETAILED DESCRIPTION

[0015] The present disclosure describes various devices, systems and methods for efficiently picking micro-operations for execution. As will be explained in more detail below, the various devices, systems and / or methods described herein can provide various benefits and / or advantages over certain traditional implementations of processors, pipelines and / or pickers.

[0016] In some cases, binary multipliers and / or FPUs perform and / or implement complex micro-operations (e.g., multiplication and / or division operations) that the ALUs cannot perform and / or implement. However, because these binary multipliers and / or FPUs may require and / or consume more space and / or real estate than the ALUs on such processors, manufacturers often select and / or prefer processor architectures that include more ALUs than binary multipliers and / or FPUs. Unfortunately, if the number of complex micro-operations selected by the picker in a given clock cycle exceeds the number of binary multipliers and / or FPUs in the processor, the excessive complex micro-operations are discarded and / or removed from the picker.

[0017] For example, if a processor includes 5 ALUs and 1 binary multiplier, a picker in the processor may select 6 micro-operations per clock cycle. However, in this example, if the picker selects more than 1 complex micro-operation in a given clock cycle, the picker is forced to discard all complex micro-operations exceeding 1 due, at least in part, to the fact that the processor includes only 1 binary multiplier. Such discarding may result in incomplete and / or underutilized picking, thereby potentially harming the performance and / or efficiency of the processor.

[0018] The various devices, systems, and / or methods described herein address and / or resolve such incomplete and / or underutilized picks, and may thereby improve the performance and / or efficiency of a processor. For example, the various devices, systems, and / or methods described herein may ensure that complex micro-operations (e.g., multiplication and / or division operations) that are discarded by a picker due to insufficient complex resources in a given clock cycle are replaced with simple micro-operations (e.g., addition, subtraction, and / or comparison operations). By doing so, these devices, systems, and / or methods may avoid issuing incomplete and / or underutilized picks that have empty slots, thereby potentially improving the performance and / or efficiency of the processor on which the picker is implemented.

[0019] In one example, a method for completing such a task includes selecting a first set of micro-operations to be executed during a certain clock cycle. The method also includes selecting a second set of micro-operations to be executed during a certain clock cycle. The method additionally includes replacing one or more complex micro-operations included in the first set of micro-operations with one or more simple micro-operations included in the second set of micro-operations, at least in part because the number of complex micro-operations included in the first set of micro-operations exceeds a set of complex resources capable of executing the complex micro-operations.

[0020] In one example, the method further includes feeding the first set of micro-operations to the set of complex resources and the set of simple resources via a set of issue ports when replacing one or more complex micro-operations with one or more simple micro-operations in the first set of micro-operations. In one example, the set of complex resources may include one or more binary multipliers and / or one or more FPUs. Additionally or alternatively, the set of simple resources may include one or more ALUs.

[0021] In one example, the method further includes selecting the first set of micro-operations from the scheduler queue at least in part due to the first set of micro-operations being older than all other micro-operations in the scheduler queue during a certain clock cycle. Additionally or alternatively, the method may include selecting one or more simple micro-operations from the scheduler queue to include in the second set of micro-operations at least in part due to the second set of micro-operations being older than all other simple micro-operations in the scheduler queue during a certain clock cycle.

[0022] In one example, the method further includes identifying the number of complex micro-operations by counting the number of complex micro-operations included in the first group of micro-operations during a subsequent clock cycle. In this example, the method further includes replacing one or more complex micro-operations included in the first group of micro-operations by calculating the difference between the number of complex micro-operations included in the first group of micro-operations and the number of complex resources capable of executing the complex micro-operations in the processor, and then determining that the one or more complex micro-operations included in the first group of micro-operations are sufficient to satisfy the difference between the number of complex micro-operations included in the first group of micro-operations and the number of complex resources and that the one or more complex micro-operations included in the first group of micro-operations are younger than all other complex micro-operations included in the first group of micro-operations.

[0023] In one example, the first set of micro-operations may include a combination of complex micro-operations and simple micro-operations. In this example, the second set of micro-operations consists only of simple micro-operations.

[0024] In one example, the first set of micro-operations includes a number of micro-operations that is consistent with the total number of complex resources and simple resources in the processor. In this example, the second set of micro-operations includes a number of simple micro-operations that does not exceed the difference between the number of micro-operations in the processor and the total number of complex resources.

[0025] In one example, complex micro-operations may each require multiple clock cycles for the processor to execute. In this example, simple micro-operations may each require a single clock cycle for the processor to execute.

[0026] In one example, the complex micro-operations may each include at least one of a multiplication operation and / or a division operation. In this example, the simple micro-operations may each include at least one of an addition operation, a subtraction operation, and / or a comparison operation.

[0027] In one example, the method may further include identifying the set of emit ports leading to a complex resource and a set of simple resources. In this example, the method further includes identifying one or more emit ports leading to the set of complex resources within the set of emit ports. Additionally or alternatively, the method may include rearranging the order of the first set of micro-operations so that all complex micro-operations included in the first set of micro-operations are fed to one or more emit ports leading to the set of complex resources.

[0028] In one example, a processor that efficiently picks micro-operations for execution includes a first picker that is configured to select a first set of micro-operations that are ready to be executed during a certain clock cycle. The processor also includes a second picker that is configured to select a second set of micro-operations that are ready to be executed during a certain clock cycle. In this example, the first picker or the second picker is configured to replace one or more complex micro-operations included in the first set of micro-operations with one or more simple micro-operations included in the second set of micro-operations, at least in part because the number of complex micro-operations included in the first set of micro-operations exceeds a set of complex resources capable of executing the complex micro-operations.

[0029] In one example, the first picker is further configured to feed the first set of micro-operations to the set of complex resources and the set of simple resources via a set of issue ports when replacing one or more complex micro-operations with one or more simple micro-operations in the first set of micro-operations. In one example, the set of complex resources may include one or more binary multipliers and / or one or more FPUs. Additionally or alternatively, the set of simple resources may include one or more ALUs.

[0030] In one example, the first picker is further configured to select the first group of micro-operations from the scheduler queue at least in part due to the first group of micro-operations being older than all other micro-operations in the scheduler queue during a certain clock cycle. Additionally or alternatively, the second picker is further configured to select one or more simple micro-operations from the scheduler queue to include in the second group of micro-operations at least in part due to the second group of micro-operations being older than all other simple micro-operations in the scheduler queue during a certain clock cycle.

[0031] In one example, the first picker or the second picker is also configured to identify the number of complex micro-operations by counting the number of complex micro-operations included in the first group of micro-operations during a subsequent clock cycle. In this example, the first picker or the second picker is further configured to replace one or more complex micro-operations included in the first group of micro-operations by calculating the difference between the number of complex micro-operations included in the first group of micro-operations and the number of complex resources capable of executing the complex micro-operations in the processor, and then determining that the one or more complex micro-operations included in the first group of micro-operations are sufficient to satisfy the difference between the number of complex micro-operations included in the first group of micro-operations and the number of complex resources and that the one or more complex micro-operations included in the first group of micro-operations are younger than all other complex micro-operations included in the first group of micro-operations.

[0032] In one example, the first set of micro-operations may include a combination of complex micro-operations and simple micro-operations. In this example, the second set of micro-operations consists only of simple micro-operations.

[0033] In one example, the first set of micro-operations includes a number of micro-operations that is consistent with the total number of complex resources and simple resources in the processor. In this example, the second set of micro-operations includes a number of simple micro-operations that does not exceed the difference between the number of micro-operations in the processor and the total number of complex resources.

[0034] In some examples, a computing device that efficiently selects micro-operations for implementation includes a processor and a memory device communicatively coupled to the processor. In one example, the processor is configured to select a first group of micro-operations to be implemented during a certain clock cycle. In this example, the processor is configured to select a second group of micro-operations to be implemented during a certain clock cycle. The processor is also configured to replace one or more complex micro-operations included in the first group of micro-operations with one or more simple micro-operations included in the second group of micro-operations, at least in part because the number of complex micro-operations included in the first group of micro-operations exceeds a group of complex resources that can implement complex micro-operations. In one example, the memory device is configured to store one or more computer-readable instructions, and the processor can derive the first group of micro-operations and the second group of micro-operations from the instruction.

[0035] The following will refer to Figures 1 to 7 A detailed description of exemplary devices, systems and / or corresponding implementations for efficiently picking micro-operations for execution is provided. Figure 8 A detailed description of an exemplary method for efficiently picking micro-operations for execution is provided.

[0036] Figure 1 An exemplary processor 100 is shown that facilitates efficient selection of micro-operations for execution. Figure 1 As illustrated, processor 100 includes and / or represents a scheduler queue 102 that maintains, stores, and / or buffers micro-operations 108(1)-(N). In some examples, scheduler queue 102 maintains, stores, and / or buffers micro-operations 108(1)-(N) in an age-based order and / or a first-in, first-out (FIFO) order. Additionally or alternatively, processor 100 includes and / or represents a picker 104 and / or a picker 106 that is responsible for picking and / or selecting groups of micro-operations 108(1)-(N) from scheduler queue 102.

[0037] In some examples, processor 100 includes and / or represents a set of one or more complex resources 114(1)-(N) and / or a set of one or more simple resources 116(1)-(N). In one example, complex resources 114(1)-(N) are capable of executing, computing, and / or performing complex micro-operations picked and / or selected by picker 104. In this example, simple resources 116(1)-(N) are capable of executing, computing, and / or performing simple micro-operations picked and / or selected by picker 104 and / or picker 106.

[0038] In some examples, processor 100 may include and / or represent any type or form of hardware-implemented device capable of interpreting and / or executing computer-readable instructions. In one example, processor 100 includes and / or represents one or more semiconductor devices implemented and / or deployed as part of a computing system. Examples of processor 100 include, but are not limited to, a central processing unit (CPU), a microprocessor, a microcontroller, a field programmable gate array (FPGA) implementing a softcore processor, an application specific integrated circuit (ASIC), a system on a chip (SoC), portions of one or more of them, variations or combinations of one or more of them, and / or any other suitable processor.

[0039] Processor 100 can be implemented and / or configured with any one of a variety of different architectures and / or micro-architectures. For example, processor 100 can be implemented and / or configured as a reduced instruction set computer (RISC) architecture. In another example, processor 100 can be implemented and / or configured as a complex instruction set computer (CISC) architecture. Additional examples of such architectures and / or micro-architectures include, but are not limited to, 16-bit computer architectures, 32-bit computer architectures, 64-bit computer architectures, x86 computer architectures, advanced RISC machine (ARM) architectures, microprocessors without interlocked pipeline stages (MIPS) architectures, scalable processor architectures (SPARC), load-store architectures, parts of one or more of them, combinations or variations of one or more of them, and / or any other suitable architecture or micro-architecture.

[0040] In some examples, the scheduler queue 102 may include and / or represent any type or form of queue and / or buffer implemented and / or configured in the processor 100. In one example, the scheduler queue 102 may include and / or represent a data structure and / or abstract data type. In another example, the scheduler queue 102 may include and / or represent a feature of the CPU that maintains, presents, and / or provides micro-operations 108(1)-(N) to be picked for issuance to complex resources 116(1)-(N) and / or simple resources 114(1)-(N). Additionally or alternatively, the scheduler queue 102 may include and / or represent hardware, software, and / or firmware implemented as part of the processor 100.

[0041] In some examples, picker 104 and / or picker 106 may include and / or represent any type or form of processes, modules, and / or units that pick and / or select groups of micro-operations 108(1)-(N) for execution by complex resources 114(1)-(N) and / or simple resources 116(1)-(N). In one example, picker 104 is configured to pick and / or select a certain number of micro-operations 108(1)-(N) as pick 110, and picker 106 is configured to pick and / or select a certain number of micro-operations 108(1)-(N) as pick 112. For example, picker 104 is configured to pick and / or select simple and / or complex operations, while picker 106 is configured to pick and / or select only simple micro-operations. In some implementations, picker 104 and / or picker 106 may include and / or represent hardware, software, and / or firmware implemented as part of processor 100.

[0042] In some examples, pick 110 includes and / or represents a higher or lower number of micro-operations than pick 112. Additionally or alternatively, pick 110 may include and / or represent any combination of complex and simple micro-operations, while pick 112 includes and / or represents only simple micro-operations. In some cases, picks 110 and 112 may share certain overlapping micro-operations in common with each other.

[0043] In some examples, pick 110 includes a number of micro-operations that is consistent with the total number of complex resources and simple resources in processor 100. In such examples, pick 112 includes a number of simple micro-operations that does not exceed the difference between the number of micro-operations included in pick 110 and the number of complex resources in processor 100. For example, in some pick cycles, pick 110 may include the maximum number of complex micro-operations allowed by processor 100, with the remainder being simple micro-operations. However, in other pick cycles, pick 110 may include all simple micro-operations and no complex micro-operations.

[0044] In some examples, complex resources 114(1)-(N) and / or simple resources 116(1)-(N) may include and / or represent any type or form of digital circuitry that performs micro-operations on quantities, data, and / or values. In one example, complex resources 114(1)-(N) may include and / or represent a binary multiplier and / or FPU capable of performing complex micro-operations (such as multiplication and / or division operations). Additionally or alternatively, complex resources 114(1)-(N) may each include and / or represent any other type of resource (e.g., a complex ALU) capable of performing such complex micro-operations. In this example, simple resources 116(1)-(N) may include and / or represent an ALU capable of performing simple micro-operations (e.g., addition, subtraction, and / or comparison operations).

[0045] In some examples, micro-operations 108(1)-(N) may include and / or represent any type or form of code and / or instructions that are executed and / or performed by complex resources 114(1)-(N) and / or simple resources 116(1)-(N) of processor 100. In one example, micro-operations 108(1)-(N) may include and / or represent one or more complex and / or special micro-operations (such as multiplication and / or division operations) that require multiple clock cycles to be performed by complex resources 114(1)-(N). Additionally or alternatively, micro-operations 108(1)-(N) may include and / or represent one or more simple and / or general micro-operations (such as addition, subtraction, and / or comparable operations) that require only a single clock cycle to be performed by simple resources 116(1)-(N). Micro-operations 108 ( 1 )-(N) may also involve and / or represent updates to registers, data transfers to or between registers, and / or data transfers from an interface (eg, a bus) to registers or vice versa.

[0046] In some examples, processor 100 may include and / or incorporate Figure 1 One or more additional components not explicitly represented and / or illustrated in the processor 100. Examples of such additional components include, but are not limited to, registers, memory devices, circuits, transistors, resistors, capacitors, diodes, connections, traces, buses, semiconductor (e.g., silicon) devices and / or structures, combinations or variations of one or more of them, and / or any other suitable components that enable the processor 100 to efficiently select micro-operations for execution. Additionally or alternatively, the processor 100 may exclude and / or omit Figure 1 For example, in a pipeline implementation featuring only a single complex resource, processor 100 may exclude and / or omit complex resource 114 (N).

[0047] In some examples, picker 104 selects and / or picks a certain number of micro-operations 108(1)-(N) from scheduler queue 102 to include in pick 110. In such examples, the micro-operations selected and / or picked by picker 104 prepare one or more of complex resources 114(1)-(N) and / or simple resources 116(1)-(N) for execution. In one example, picker 104 may select and / or pick the oldest N micro-operations of any type and / or kind.

[0048] In some examples, the picker 106 selects and / or picks a certain number of micro-operations 108(1)-(N) from the scheduler queue 102 to include in the pick 112. In such examples, the micro-operations selected and / or picked by the picker 106 are ready for execution by one or more simple resources 116(1)-(N). In one example, the picker 106 may select and / or pick the oldest number M of micro-operations 108(1)-(N) that can be executed and / or performed by the simple resources 116(1)-(N).

[0049] In some examples, the phrase "ready to execute" as used in this context can indicate and / or imply that those micro-operations do not have the dependence and / or accident that may potentially change the state of one or more variables of such micro-operations. In one example, if the state of (multiple) variables of a micro-operation is not due to the change before the execution of the micro-operation, the micro-operation can be considered and / or regarded as ready to execute. For example, the multiplication operation ready to execute includes and / or represents one or more variables in the appropriate and / or correct state for execution. In other words, before executing the multiplication operation, the variables included and / or represented in the multiplication operation do not undergo changes (by, for example, another operation). In other words, if a specific micro-operation is ready to execute, the variables included and / or represented in this specific micro-operation do not act on any other micro-operation and / or are not changed by it until after executing this specific micro-operation.

[0050] In some examples, picker 104 and / or another component of processor 100 may count and / or identify the number of complex micro-operations included in pick 110. In such examples, picker 104 and / or another component of processor 100 may determine that the number of complex micro-operations included in pick 110 exceeds the number of complex resources 114(1)-(N) capable of performing the complex micro-operations in processor 100. In response to this determination, picker 104 and / or another component of processor 100 may replace one or more complex micro-operations included in pick 110 with one or more simple micro-operations included in pick 112. In other words, picker 104 and / or another component of processor 100 may replace one or more complex micro-operations included in pick 110 with one or more simple micro-operations included in pick 112. In one example, when replacing one or more complex micro-operations in pick 110 with one or more simple micro-operations, picker 104 can feed, push and / or issue pick 110 down the pipeline of processor 100 for execution by complex resources 114(1)-(N) and / or simple resources 116(1)-(N).

[0051] Figure 2 An exemplary embodiment 200 of a processor that facilitates efficient selection of micro-operations for execution is shown. Figure 2 As illustrated, the scheduler queue 102 maintains, stores, and / or loads various simple and complex micro-operations in an age-ordered arrangement. In some examples, Figure 2 The left side of the scheduler queue 102 corresponds to and / or represents the oldest queued micro-operation, while Figure 2 The right side of the scheduler queue 102 corresponds to and / or represents the youngest queued micro-operation. Figure 2 As shown, the scheduler queue 102 includes and / or represents complex micro-operations 208(1) and 208(2) and simple micro-operations 210(1), 210(2), 210(3), 210(4), and 210(5). In this example, the complex micro-operation 208(1) is the oldest in the scheduler queue 102, and the simple micro-operation 210(5) is the youngest in the scheduler queue 102.

[0052] In some examples, Figure 2 The scheduler queue 102 in FIG. 1 may include and / or represent a scheduler queue 102 that is younger than the simple micro-operation 210 (5) but is removed for simplicity and / or clarity. Figure 2 Various other micro-operations omitted and / or excluded in Figure 2 The scheduler queue 102 in may include and / or represent is not yet ready to be implemented and therefore for simplicity and / or clarity from Figure 2 Various other micro-operations omitted and / or excluded in .

[0053] In some examples, the exemplary implementation 200 of the processor includes and / or represents 1 complex resource and 5 simple resources (not necessarily in Figure 2 exemplified or labeled in ). In one example, picker 104 initially selects complex micro-operations 208(1)-(2) and simple micro-operations 210(1)-(4) as picks 110 because these are the oldest micro-operations ready to be executed in scheduler queue 102. In this example, picker 106 initially selects simple micro-operations 210(1)-(5) as picks 112 because these are the oldest simple micro-operations ready to be executed in scheduler queue 102. However, because the exemplary implementation 200 of the processor includes only 1 complex resource, picker 104 and / or another component of processor 100 may discard and / or remove complex micro-operation 208(2) from picks 110. As a result, complex micro-operation 208(2) remains in scheduler queue 102 and / or is returned to scheduler queue 102 when and / or after picks 110 are issued for execution by complex resources and simple resources. Therefore, the complex micro-operation 208(2) remains available for selection by the picker 104 in a subsequent pick.

[0054] In some examples, the picker 104 and / or another component of the processor 100 fills the slot vacated by the complex micro-operation 208(2) in the pick 110 with the simple micro-operation 210(5). By doing so, the picker 104 and / or another component of the processor 100 effectively replaces the complex micro-operation 208(2) with the simple micro-operation 210(5) in the pick 110. The picker 104 then issues the pick 110 to the complex resources and the simple resources for execution. When the pick 110 is issued and / or executed, the complex micro-operation 208(1) and / or the simple micro-operation 210(1)-(5) may be broadcast to their slaves and / or associated registers to update corresponding data and / or values ​​within the processor 100.

[0055] As a specific example, an exemplary embodiment 200 of a processor may involve and / or represent a picking scheme that lasts and / or spans 2 clock cycles. In this example, a simple micro-operation may have a latency of 1 clock cycle for execution, and a complex micro-operation may have a latency of N clock cycles for execution. During a first clock cycle of the 2-cycle picking scheme, the picker 104 may initially select the complex micro-operation 208(1)-(2) and the simple micro-operation 210(1)-(4) as picks 110, and the picker 106 may initially select the simple micro-operation 210(1)-(5) as picks 112. In the next clock cycle of the 2-cycle picking scheme, the picker 104 may discard the complex micro-operation 208(2) from picks 112 and / or replace it with a simple micro-operation 210(5) from picks 110. The picker 104 may then issue picks 110 to the complex and simple resources for execution. When the pick 110 is issued and / or executed, the simple micro-operations 210(1)-(4) may be broadcast immediately to their slaves and / or associated registers to update the corresponding data and / or values ​​within the processor 100. However, when the simple micro-operation 210(5) replaces the complex micro-operation 208(2) in the pick 110, the simple micro-operation 210(5) may be broadcast to its slaves and / or associated registers to update the corresponding data and / or values ​​within the processor 100 during the next clock cycle. In addition, since the complex micro-operation 208(1) has a latency of N cycles, the complex micro-operation 208(1) may be broadcast to its slaves and / or associated registers to update the corresponding data and / or values ​​within the processor 100 after N cycles.

[0056] Figure 3 A specific implementation thereof is shown in Figure 2 An exemplary pipeline 300 of a processor in FIG. Figure 3 As illustrated, the pipeline 300 of the processor may include and / or involve modifying pick 110 based at least in part on pick 112 via a replacement operation 312. In some examples, after completing this modification, pick 110 may be issued to the complex resources 114(1) and simple resources 116(1)-(5) of the processor via ports 302(1), 302(2), 302(3), 302(4), 302(5), and 302(6), respectively. Therefore, in this specific implementation, pipeline 300 may include and / or represent 6 issue slots. In these examples, upon receiving the micro-operations issued in pick 110, complex resources 114(1) and simple resources 116(1)-(5) may execute, compute, and / or perform the micro-operations.

[0057] In one example, replacement operation 312 may involve and / or represent picker 104 replacing complex micro-operation 208(2) with simple micro-operation 210(5) in pick 110. Thus, prior to replacement operation 312, pick 110 includes and / or represents an initial version and / or composition of pick 110. Conversely, after replacement operation 312, pick 110 includes and / or represents an updated and / or modified version of pick 110. In this example, upon completion of the replacement operation 312, the picker 104 may direct, dispatch and / or issue a pick 110 by feeding the complex micro-operation 208(1) to the complex resource 114(1) via port 302(1), feeding the simple micro-operation 210(1) to the simple resource 116(1) via port 302(2), feeding the simple micro-operation 210(2) to the simple resource 116(2) via port 302(3), feeding the simple micro-operation 210(3) to the simple resource 116(3) via port 302(4), feeding the simple micro-operation 210(4) to the simple resource 116(4) via port 302(5) and / or feeding the simple micro-operation 210(5) to the simple resource 116(5) via port 302(6).

[0058] Figure 4 An exemplary embodiment 400 of a processor that facilitates efficient selection of micro-operations for execution is shown. Figure 4 As illustrated, the scheduler queue 102 maintains, stores, and / or loads various simple and complex micro-operations in an age-ordered arrangement. In some examples, such as Figure 4 , the scheduler queue 102 includes and / or represents addition operations 410(1) and 410(2), multiplication operations 402(1) and 402(2), subtraction operations 412(1) and 412(2), division operation 404(1), and / or comparison operation 408(1). In one example, the scheduler queue 102 is sorted by age such that addition operation 410(1) is the oldest micro-operation within the scheduler queue 102 and subtraction operation 412(2) is the youngest micro-operation within the scheduler queue 102. Additionally, Figure 4 The scheduler queue 102 in includes and / or represents a scheduler queue 102 that is younger than the simple micro-operation 210 (5) but is removed from the scheduler queue 102 for simplicity and / or clarity. Figure 4 Various other micro-operations omitted and / or excluded in .

[0059] In some examples, the exemplary implementation 400 of the processor includes and / or represents 2 complex resources and 4 simple resources (not necessarily in Figure 4404(1)). In one example, picker 104 initially selects addition operation 410(1)-(2), multiplication operation 402(1)-(2), subtraction operation 412(1) and / or division operation 404(1) as pick 430. In this example, picker 106 initially selects addition operation 410(1)-(2), subtraction operation 412(1)-(2) and comparison operation 408(1) as pick 432. However, because the exemplary embodiment 400 of the processor includes only 2 complex resources, picker 104 and / or another component of processor 100 may discard and / or remove division operation 404(1) from pick 430. As a result, division operation 404(1) remains in scheduler queue 102 and / or is returned to scheduler queue 102 when and / or after pick 430 is issued for execution by complex resources and simple resources. Therefore, the division operation 404 ( 1 ) is still available for selection by the picker 104 in a subsequent pick.

[0060] In some examples, picker 104 and / or another component of processor 100 fills the slot vacated by division operation 404(1) in pick 430 with comparison operation 408(1). By doing so, picker 104 and / or another component of processor 100 may effectively replace division operation 404(1) with comparison operation 408(1) in pick 430. Picker 104 then issues pick 430 to complex and simple resources for execution. When pick 430 is issued and / or executed, addition operation 410(1)-(2), multiplication operation 402(1)-(2), subtraction operation 412(1), and / or comparison operation 408(1) are broadcast to their slaves and / or associated registers to update corresponding data and / or values ​​within processor 100.

[0061] As a specific example, an exemplary embodiment 400 of a processor may involve and / or represent a picking scheme that lasts and / or spans 2 clock cycles. In this example, addition operations 410(1)-(2), subtraction operations 412(1), and comparison operations 408(1) may each have a latency of 1 clock cycle, and multiplication operations 402(1)-(2) may each have a latency of N clock cycles. During a first clock cycle of the 2-cycle picking scheme, picker 104 initially selects addition operations 410(1)-(2), multiplication operations 402(1)-(2), subtraction operations 412(1), and / or division operations 404(1) as picks 430, and picker 106 initially selects addition operations 410(1)-(2), subtraction operations 412(1)-(2), and comparison operations 408(1) as picks 432. In the next clock cycle of the 2-cycle picking scheme, the picker 104 discards the division operation 404(1) from the pick 430 and / or replaces it with the comparison operation 408(1) from the pick 432. The picker 104 then issues the pick 430 to the complex and simple resources for execution. When the pick 430 is issued and / or executed, the addition operation 410(1)-(2) and / or the subtraction operation 412(1) may be immediately broadcast to its slaves and / or associated registers to update the corresponding data and / or values ​​within the processor 100. However, when the comparison operation 408(1) replaces the division operation 404(1) in the pick 430, the comparison operation 408(1) is broadcast to its slaves and / or associated registers to update the corresponding data and / or values ​​within the processor 100 during the next cycle. Additionally, since multiplication operations 402(1)-(2) each have a latency of N clock cycles, multiplication operations 402(1)-(2) are broadcast to their slaves and / or associated registers to update corresponding data and / or values ​​within processor 100 N clock cycles later.

[0062] Figure 5 An embodiment thereof is shown in Figure 4 An exemplary pipeline 500 of a processor in FIG. Figure 5As illustrated, the pipeline 500 of the processor may include and / or involve modifying the pick 430 via the reconciliation operation 502. In some examples, upon completing this modification, the pick 430 is issued to the processor's multipliers 514(1) and 514(2) and / or ALUs 516(1), 516(2), 516(3), and 516(4) via ports 504(1), 504(2), 504(3), 504(4), 504(5), and 504(6), respectively. Thus, in this specific implementation, the pipeline 500 includes and / or represents six issue slots. In these examples, upon receiving the micro-operations issued in the pick 430, the multipliers 514(1)-(2) and / or the ALUs 516(1)-(4) execute, calculate, and / or perform these micro-operations.

[0063] In one example, reconciliation operation 502 involves and / or represents picker 104 rearranging and / or reordering addition operations 410(1)-(2), multiplication operations 402(1)-(2), subtraction operation 412(1), and / or comparison operation 408(1) in pick 110. For example, each micro-operation included in pick 430 corresponds to and / or is assigned to one of six issue slots. In this example, as part of reconciliation operation 502, picker 104 rearranges and / or reorders pick 430 relative to the six issue slots such that multiplication operations 402(1)-(2) are aligned with and / or directed to multipliers 514(1)-(2), respectively. Additionally or alternatively, the picker 104 rearranges and / or reorders the picks 430 relative to the six issue slots so that the addition operation 410(1), the subtraction operation 412(1), the addition operation 410(2), and / or the comparison operation 408(1) are aligned with and / or directed to the ALUs 516(1)-(4), respectively. After completing the reconciliation operation 502, the picker 104 issues and / or feeds the multiplication operation 402(1)-(2) to the multiplier 514(1)-(2) via ports 504(1)-(2), and / or the picker 104 issues and / or feeds the addition operation 410(1), the subtraction operation 412(1), the addition operation 410(2), and / or the comparison operation 408(1) to the ALU 516(1)-(4) via ports 504(3)-(6).

[0064] Figure 6 An exemplary embodiment 600 of a processor that facilitates efficient selection of micro-operations for execution is shown. Figure 6As illustrated, exemplary implementation 600 includes and / or represents various micro-operations maintained, stored, and / or loaded into a scheduler queue in an age-ordered arrangement. For example, such micro-operations include and / or represent Mul1, Op1, Mul2, Op2, Op3, Op4, Op5, Mul3, Op6, Op7, Op8, and / or Op9 within the scheduler queue. In this example, Mul1 is the oldest micro-operation within the scheduler queue, and Op9 is the youngest micro-operation within the scheduler queue.

[0065] In some examples, various micro-operations (e.g., Mul1, Op1, Op2, Mul3, Op6, and / or Op9) loaded into the scheduler queue are ready to execute, while various other micro-operations (e.g., Mul2, Op3, Op4, Op5, Op7, and / or Op8) are not yet ready to execute. Because they are not yet ready to execute, those other micro-operations are not available for selection by the picker 104 and / or the picker 106 until the next clock cycle. In one example, the picker 104 selects Mul1, Op1, Op2, and / or Mul3 as the pick 610. In this example, the picker 106 selects Op1, Op2, Op6, and / or Op9 as the pick 612.

[0066] In implementation 600, the pipeline of the processor includes and / or represents an execution unit having 1 complex resource (e.g., multiplier) and / or 3 simple resources (e.g., ALU). In pick 610, Mul1 and / or Mul3 constitute and / or represent multiplication operations, and Op1 and Op2 constitute and / or represent simple micro-operations (e.g., addition, subtraction, and / or comparison operations). In contrast, all micro-operations included in pick 612 constitute and / or represent simple micro-operations.

[0067] In some examples, because the pipeline of the processor only includes 1 complex resource, the picker 104 and / or another component of the processor counts the number of multiplication operations in the pick 610 and then determines that the pick 610 includes 1 multiplication operation that exceeds the number of complex resources. As a result, the picker 104 and / or other component of the processor can perform a replacement operation 622 by discarding and / or removing Mul3 from the pick 610 and then adding Op6 from the pick 612 to the pick 610. By doing so, the picker 104 and / or other component of the processor can ensure that all issue slots available for execution within the pipeline of the processor are utilized, thereby improving the efficiency and / or performance of the processor. Upon completion of the replacement operation 622, the final pick consisting of Mul1, Op1, Op2 and / or Op6 is fed to the complex and / or simple resources for execution as an issue 628.

[0068] In some examples, the picking scheme depicted in embodiment 600 relates to and / or represents 4 micro-operations picked per clock cycle and / or 4 micro-operations issued per clock cycle. In one example, the picking scheme depicted in embodiment 600 allows and / or facilitates the selection of 1 multiplication operation per clock cycle. In this example, the selection of picking 610 and 612 and the execution of replacement operation 622 jointly last and / or consume 2 clock cycles. Continuing with this example, the introduction of replacement operation 622 uses and / or exploits the 1 / 2 cycle that exists and / or is available in the 2 clock cycles of the picking scheme.

[0069] Figure 7 An exemplary implementation 700 involving a computing device 702 is illustrated. Figure 7 As illustrated, computing device 702 includes and / or represents a processor 100 communicatively coupled to a memory device 704. In some examples, memory device 704 maintains and / or stores one or more computer-readable instructions 710. In such examples, processor 100 of computing device 702 derives certain micro-operations (including the above combined operations) from the computer-readable instructions 710 in memory device 704. Figures 1 to 6 For example, the processor 100 of the computing device 702 may decode the computer-readable instructions 710 to generate and / or produce certain micro-operations that are subsequently executed, calculated, and / or performed by the complex resources 114(1)-(N) and / or the simple resources 116(1)-(N).

[0070] In some examples, computing device 702 may include and / or represent any type or form of computer capable of performing computing tasks and / or communicating with other computers. Examples of computing device 702 include, but are not limited to, client devices, laptop computers, tablet computers, desktop computers, servers, cellular phones, personal digital assistants (PDAs), multimedia players, embedded systems, wearable devices, game consoles, routers, switches, hubs, modems, bridges, repeaters, gateways (such as broadband network gateways (BNGs)), multiplexers, network adapters, network interfaces, line cards, portions of one or more of them, variations or combinations of one or more of them, and / or any other suitable computing devices.

[0071] In some examples, memory device 704 includes and / or represents any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. Examples of memory device 704 include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), optical drive, cache, variations or combinations of one or more thereof, and / or any other suitable memory device.

[0072] Figure 8 8 is a flow chart of an exemplary method 800 for efficiently selecting micro-operations for execution. In one example, Figure 8 The steps shown in may be performed by one or more components of a processor incorporated into a computing device. Additionally or alternatively, Figure 8 The steps shown in may also be incorporated and / or referred to in combination with the above Figures 1 to 7 The description provided is consistent with each sub-step and / or variation.

[0073] like Figure 8 As illustrated, method 800 includes and / or involves the step of selecting a first set of micro-operations to be executed during a certain clock cycle (810). Step 810 can be implemented in various ways, including in combination with the above. Figures 1 to 7 Any of those described. For example, a master picker included in the processor selects a first group of micro-operations from a scheduler queue included in the processor, the first group of micro-operations being ready to be executed by a group of complex resources or a group of simple resources during a certain clock cycle.

[0074] Method 800 also includes a step (820) of selecting a second set of micro-operations to be executed during a certain clock cycle. Step 820 can be performed in various ways, including the above combination Figures 1 to 7 Any of those described. For example, a replacement picker included in the processor selects a second set of micro-operations from a scheduler queue, the second set of micro-operations being ready to be executed by the set of simple resources during a certain clock cycle. In one example, the second set of micro-operations is smaller than the first set of micro-operations (e.g., includes fewer micro-operations).

[0075] Method 800 also includes a step (830) of replacing one or more complex micro-operations included in the first set of micro-operations with one or more simple micro-operations included in the second set of micro-operations, at least in part because the number of complex micro-operations included in the first set of micro-operations exceeds a set of complex resources capable of executing the complex micro-operations. Step 830 can be performed in various ways, including in combination with the above. Figures 1 to 7Any of the ways described. For example, at least in part because the number of complex micro-operations included in the first set of micro-operations exceeds a set of complex resources capable of performing complex micro-operations, the primary picker replaces one or more complex micro-operations included in the first set of micro-operations with one or more simple micro-operations included in the second set of micro-operations.

[0076] As described above in connection with Figures 1 to 8 the above, an exemplary processor includes a primary picker and / or an alternative picker. The primary picker is capable of selecting any type of ready micro-operations (including both single-cycle and multi-cycle operations) queued by a scheduler, and the alternative picker is capable of selecting only ready single-cycle operations queued in the scheduler. In some examples, the execution units of the processor include M special resources (e.g., multipliers and / or FPUs) capable of performing special micro-operations (e.g., multiplication, division, etc.) that require multiple clock cycles and general resources (e.g., a general ALU) capable of performing general micro-operations (e.g., addition, subtraction, comparison, etc.) that require only a single clock cycle. In such examples, the primary picker has the ability to select N micro-operations per clock cycle (where M < N), and the alternative picker has the ability to select N to M micro-operations per clock cycle. In one example, the primary picker selects the N oldest ready micro-operations of any type during a certain clock cycle, and the alternative picker selects N to M of the oldest ready general single-cycle micro-operations during this clock cycle. In the next clock cycle, the primary picker discards all special operations greater than M from its selection and replaces them with one or more general micro-operations selected by the alternative picker. The primary picker and / or another component of the processor then feeds, pushes, and / or issues the resulting mix of special and general micro-operations found in its final selection down the pipeline via certain issue ports to the special and general resources. The special and general resources then perform those operations at the appropriate time (e.g., after two or three clock cycles) to perform one or more computational tasks.

[0077] Although the foregoing disclosure has illustrated various embodiments using specific block diagrams, flowcharts, and examples, each block diagram component, flowchart step, operation, and / or component described and / or illustrated herein can be implemented individually and / or jointly using a wide range of hardware, software, or firmware (or any combination thereof) configurations. Additionally, any disclosure of components contained within other components should be considered exemplary in nature, as many other architectures can be implemented to achieve the same functionality.

[0078] The devices, systems, and methods described herein may employ any number of software, firmware, and / or hardware configurations. For example, one or more exemplary embodiments and / or specific implementations disclosed herein may be encoded as a computer program (also referred to as computer software, software applications, computer-readable instructions, and / or computer control logic) on a computer-readable medium. The term "computer-readable medium" generally refers to any form of device, carrier, or medium capable of storing or carrying computer-readable instructions. Examples of computer-readable media include, but are not limited to, transmission-type media such as carrier waves and non-transient media such as magnetic storage media (e.g., hard drives and floppy disks), optical storage media (e.g., compact disks (CDs) and digital video disks (DVDs)), electronic storage media (e.g., solid-state drives and flash memory media), and / or other distribution systems.

[0079] In addition, one or more of the modules, instructions, and / or micro-operations described herein may transform data, physical devices, and / or representations of physical devices from one form to another. Additionally or alternatively, one or more of the modules, instructions, and / or micro-operations described herein may transform a processor, volatile memory, non-volatile memory, and / or any other portion of a physical computing device from one form to another by executing on a computing device, storing data on a computing device, and / or otherwise interacting with a computing device.

[0080] The order of process parameters and steps described and / or illustrated herein is given by way of example only and may be varied as desired. For example, although the steps illustrated and / or described herein are shown or discussed in a particular order, these steps do not necessarily need to be performed in the order illustrated or discussed. The various exemplary methods described and / or illustrated herein may also omit one or more steps described or illustrated herein, or include additional steps in addition to those disclosed.

[0081] The previous description has been provided to enable others skilled in the art to best utilize the various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the present disclosure. It should be considered that the embodiments disclosed herein are illustrative and non-restrictive in all aspects. In determining the scope of the present disclosure, reference should be made to the attached claims and their equivalents.

[0082] Unless otherwise indicated, the terms "connected to" and "coupled to" (and their derivatives) as used in the specification and claims will be deemed to allow both direct and indirect (i.e., via other elements or components) connections. In addition, the terms "a" or "an" as used in the specification and claims will be deemed to mean "at least one". Finally, for ease of use, the terms "including" and "having" (and their derivatives) as used in the specification and claims are interchangeable with the word "comprising" and have the same meaning.

Claims

1. A method, comprising: Selecting a first set of micro-operations to be executed during a clock cycle; selecting a second set of micro-operations to be executed during the certain clock cycle; as well as At least in part because the number of complex micro-operations included in the first set of micro-operations exceeds a set of complex resources capable of executing the complex micro-operations, one or more complex micro-operations included in the first set of micro-operations are replaced with one or more simple micro-operations included in the second set of micro-operations.

2. The method of claim 1 , further comprising, when replacing the one or more complex micro-operations with the one or more simple micro-operations in the first group of micro-operations, feeding the first group of micro-operations to the group of complex resources and the group of simple resources via a group of issue ports.

3. The method according to claim 2, wherein: The set of complex resources includes at least one of the following: one or more binary multipliers; or One or more floating point units; and The set of simple resources includes one or more arithmetic logic units.

4. The method of claim 1 , wherein selecting the first set of micro-operations comprises selecting the first set of micro-operations from the scheduler queue due at least in part to the first set of micro-operations being older than all other micro-operations in the scheduler queue during the certain clock cycle.

5. The method of claim 1 , wherein selecting the second set of micro-operations comprises selecting the one or more simple micro-operations from the scheduler queue for inclusion in the second set of micro-operations at least in part because the second set of micro-operations are older than all other simple micro-operations in the scheduler queue during the certain clock cycle.

6. The method of claim 1 , further comprising identifying the number of complex micro-operations by counting the number of complex micro-operations included in the first set of micro-operations during a subsequent clock cycle; and Wherein replacing the one or more complex micro-operations included in the first group of micro-operations with the one or more simple micro-operations comprises: calculating a difference between the number of complex micro-operations included in the first set of micro-operations and the number of complex resources capable of executing the complex micro-operations in a processor; as well as Determining the one or more complex micro-operations included in the first set of micro-operations: sufficient to satisfy a difference between the number of complex micro-operations included in the first set of micro-operations and the number of complex resources; and Younger than all other complex micro-operations included in the first set of micro-operations.

7. The method according to claim 1, wherein: The first set of micro-operations includes a combination of complex micro-operations and simple micro-operations; and The second group of micro-operations consists of only simple micro-operations.

8. The method according to claim 1, wherein: The first set of micro-operations includes a number of micro-operations consistent with the total number of complex resources and simple resources in the processor; and The second set of micro-operations includes a number of simple micro-operations that does not exceed a difference between the number of micro-operations in the processor and a total number of complex resources.

9. The method according to claim 1, wherein: The complex micro-operations each require multiple clock cycles for the processor to execute; and The simple micro-operations each require a single clock cycle for the processor to execute.

10. The method of claim 1, wherein: Each of the complex micro-operations includes at least one of the following: multiplication; or division operation; and Each of the simple micro-operations includes at least one of the following: Addition operation; Subtraction; or Comparison operation.

11. The method according to claim 1, further comprising: identifying a set of outgoing ports leading to the set of complex resources and the set of simple resources; identifying one or more egress ports within the set of egress ports that lead to the set of complex resources; as well as The order of the first set of micro-operations is rearranged so that all complex micro-operations included in the first set of micro-operations are fed to the one or more issue ports leading to the set of complex resources.

12. A processor, the processor comprising: a first picker configured to select a first set of micro-operations to be executed during a certain clock cycle; and a second picker configured to select a second set of micro-operations to be executed during the certain clock cycle; and Wherein the first picker or the second picker is also configured to replace one or more complex micro-operations included in the first group of micro-operations with one or more simple micro-operations included in the second group of micro-operations, at least in part because the number of complex micro-operations included in the first group of micro-operations exceeds a set of complex resources capable of executing the complex micro-operations.

13. The processor of claim 12, wherein the first picker is further configured to feed the first set of micro-operations to the set of complex resources and the set of simple resources via a set of issue ports when replacing the one or more complex micro-operations with the one or more simple micro-operations.

14. The processor of claim 13, wherein: The set of complex resources includes at least one of the following: one or more binary multipliers; or One or more floating point units; and The set of simple resources includes one or more arithmetic logic units.

15. The processor of claim 12, wherein the first picker is further configured to select the first group of micro-operations from the scheduler queue at least in part because the first group of micro-operations is older than all other micro-operations in the scheduler queue during the certain clock cycle.

16. The processor of claim 12, wherein the second picker is further configured to select the one or more simple micro-operations from the scheduler queue to be included in the second group of micro-operations at least in part because the second group of micro-operations is older than all other simple micro-operations in the scheduler queue during the certain clock cycle.

17. The processor of claim 12, wherein the first picker or the second picker is further configured to: identifying the number of complex micro-operations by counting the number of complex micro-operations included in the first set of micro-operations during a subsequent clock cycle; and The one or more complex micro-operations included in the first group of micro-operations are replaced with the one or more simple micro-operations by the following steps: calculating a difference between the number of complex micro-operations included in the first set of micro-operations and the number of complex resources capable of executing the complex micro-operations in the processor; and Determining the one or more complex micro-operations included in the first set of micro-operations: sufficient to satisfy a difference between the number of complex micro-operations included in the first set of micro-operations and the number of complex resources; and Younger than all other complex micro-operations included in the first set of micro-operations.

18. The processor of claim 12, wherein: The first set of micro-operations includes a combination of complex micro-operations and simple micro-operations; and The second group of micro-operations consists of only simple micro-operations.

19. The processor of claim 12, wherein: The first set of micro-operations includes a number of micro-operations consistent with the total number of complex resources and simple resources in the processor; and The second set of micro-operations includes a number of simple micro-operations that does not exceed a difference between the number of micro-operations in the processor and a total number of complex resources.

20. A computing device, the computing device comprising: A processor, the processor being configured to: Selecting a first set of micro-operations to be executed during a clock cycle; selecting a second set of micro-operations to be executed during the certain clock cycle; as well as replacing one or more complex micro-operations included in the first set of micro-operations with one or more simple micro-operations included in the second set of micro-operations due, at least in part, to a number of complex micro-operations included in the first set of micro-operations exceeding a set of complex resources capable of executing the complex micro-operations; and A memory device is communicatively coupled to the processor and configured to store one or more computer-readable instructions from which the processor can derive the first set of micro-operations and the second set of micro-operations.

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