Stairless three-dimensional memory device and method of manufacturing same by forming replacement word lines through memory openings

Abstract

A semiconductor structure includes an alternating stack of insulating layers and conductive layers, a memory opening extending vertically through the alternating stack, and a memory opening filling structure in the memory opening and including a respective vertical stack of respective vertical semiconductor channels and memory cells. An integrated wire and via structure is provided that is a unitary structure including a metal plate portion that is part of a conductive layer or laterally contacts the conductive layer, and a metal via portion that extends vertically through a plate of dielectric material overlying the metal plate portion.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 385,328 filed on November 29, 2022 and U.S. Provisional Patent Application No. 63 / 385,338 filed on November 29, 2022, the entire contents of which are hereby incorporated by reference for all purposes. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and in particular to staircase-free three-dimensional memory devices and methods of forming the same. Background Art

[0004] A three-dimensional memory device including a three-dimensional vertical NAND string with one bit per cell is disclosed in an article by T. Endoh et al. entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36. Support circuitry for performing write, read, and erase operations of the memory cells in the vertical NAND string is typically provided by a complementary metal oxide semiconductor (CMOS) device formed on the same substrate as the three-dimensional memory device. Summary of the invention

[0005] According to one aspect of the present disclosure, a semiconductor structure is provided, which includes: an alternating stack of insulating layers and composite layers, wherein each of the composite layers includes a corresponding set of conductive layers, and the corresponding set of conductive layers is laterally spaced apart by a corresponding set of dielectric material portions; a memory opening, which vertically extends through the alternating stack of portions and is laterally spaced apart from each of the dielectric material portions; a memory opening filling structure, which is located in the memory opening, wherein a vertically extending interface between the conductive layer and the dielectric material portion is laterally offset from a sidewall of a nearest one of the memory opening filling structures, and wherein each of the memory opening filling structures includes a corresponding vertical semiconductor channel and a corresponding vertical stack of memory cells; and an integrated line and via structure, which includes a metal plate portion that laterally contacts a first conductive layer of the conductive layer, and also includes a metal via portion that vertically extends through a subset of the dielectric material portions overlying the metal plate portion.

[0006] According to another aspect of the present disclosure, a semiconductor structure is provided, the semiconductor structure comprising: an alternating stack of insulating layers and conductive layers; a memory opening, the memory opening extending vertically through the alternating stack; a memory opening filling structure, the memory opening filling structure being located in the memory opening and comprising a corresponding vertical stack of corresponding vertical semiconductor channels and memory cells; a pair of backside trench filling structures, the pair of backside trench filling structures laterally contacting the alternating stack and laterally spaced apart from each other by the alternating stack; a pair of dielectric barrier structures, the pair of dielectric barrier structures extending vertically through the alternating stack; a vertical stack of dielectric material plates, the vertical stack being located at the level of a subset of the conductive layers and contacting each of the pair of dielectric barrier structures; and an integrated line and via structure, the integrated line and via structure being an integral structure, comprising a first conductive layer of the conductive layers and also comprising a metal via portion, the metal via portion extending vertically through each of the dielectric material plates overlying the first conductive layer.

[0007] According to another aspect of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising: forming an alternating stack of insulating layers and sacrificial material layers including dielectric material; forming memory openings through the alternating stack; replacing a proximal portion of the sacrificial material layer surrounding each of the memory openings with a conductive layer, wherein each of the conductive layers includes a corresponding set of conductive material portions and contacts a remaining portion of the corresponding sacrificial material layer constituting the dielectric material portion; forming a through-hole opening extending vertically through a subset of the dielectric material portions; forming a laterally extending cavity below the through-hole opening so that the sidewalls of a first conductive layer in the conductive layer are physically exposed; and forming an integrated line and through-hole structure in a continuous volume including the laterally extending cavity and the volume within the through-hole opening, wherein the integrated line and through-hole structure includes a metal plate portion that laterally contacts the first conductive layer and also includes a metal through-hole portion formed in the through-hole opening.

[0008] According to another aspect of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising: forming an alternating stack of insulating layers and sacrificial material layers including dielectric materials; forming a memory opening filling structure through the alternating stack; forming a through-hole opening through an upper portion of the alternating stack; forming a laterally extending cavity below the through-hole opening by isotropically recessing a first sacrificial material layer in the sacrificial material layers; forming a back-side groove through the alternating stack before or after forming the laterally extending cavity; isotropically recessing the sacrificial material layer from around the back-side groove to form a back-side recess in the volume of the portion from which the sacrificial material layer is removed, wherein one of the back-side recesses is connected to the laterally extending cavity to form a continuous void; and depositing a conductive material in the back-side recess and the through-hole opening, wherein the portions of the conductive material deposited in the back-side recess and the laterally extending cavity constitute a conductive layer, and the portion of the conductive material filling the through-hole opening constitutes a metal through-hole portion.

[0009] According to another aspect of the present disclosure, a semiconductor structure is provided, which includes: an alternating stack of insulating layers and conductive layers; a memory opening, which extends vertically through the alternating stack; a memory opening filling structure, which is located in the memory opening and includes a corresponding vertical stack of corresponding vertical semiconductor channels and memory cells; a vertical stack of dielectric material plates, which is located at the level of a subset of the conductive layers; and an integrated line and via structure, which is an integral structure, including a first conductive layer and a second conductive layer in the conductive layer, a metal plate portion vertically connecting the first conductive layer and the second conductive layer, and a metal through-hole portion extending vertically through each dielectric material plate in the dielectric material plates overlying the first conductive layer.

[0010] According to even another aspect of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising: forming an alternating stack of insulating layers and sacrificial material layers including dielectric materials; forming a memory stack structure through the alternating stack; forming a through-hole opening through an upper portion of the alternating stack so that a top surface of a first sacrificial material layer in the sacrificial material layers is physically exposed; extending the through-hole opening vertically through the first sacrificial material layer so that a top surface of a first insulating layer in the insulating layer is physically exposed; forming an insulating layer level laterally extending cavity by isotropically recessing the first insulating layer to expose a top surface of a second sacrificial material layer in the sacrificial material layer; and etching the first sacrificial material layer isotropically. and the second sacrificial material layer to form a multi-level laterally extending cavity; forming a back side groove passing through the alternating stack before or after forming the multi-level laterally extending cavity; isotropically recessing the sacrificial material layer from around the back side groove to form a back side recess in the volume of the portion from which the sacrificial material layer is removed, wherein two of the back side recesses are connected to the multi-level laterally extending cavity to form a continuous gap; and depositing a conductive material in the back side recess, the multi-level laterally extending cavity and the through hole opening, wherein the portion of the conductive material deposited in the back side recess and the laterally extending cavity constitutes a conductive layer, and the portion of the conductive material filling the through hole opening constitutes a metal through hole portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic vertical cross-sectional view of a first exemplary structure after forming alternating stacks of insulating layers and sacrificial material layers over a substrate according to the first embodiment of the present disclosure.

[0012] Figure 2A is a vertical cross-sectional view of a first exemplary structure after forming a memory opening according to the first embodiment of the present disclosure.

[0013] Figure 2B It is along Figure 2A A horizontal cross-sectional view of the first exemplary structure taken along the vertical plane BB'. The vertical plane AA' is Figure 2A A plane of a vertical section.

[0014] Figure 2C It is along Figure 2B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0015] Figure 3A is a vertical cross-sectional view of the first exemplary structure after replacing a portion of the sacrificial material layer proximate to the memory opening with a conductive layer according to the first embodiment of the present disclosure.

[0016] Figure 3B It is along Figure 3A A horizontal cross-sectional view of the first exemplary structure taken along the vertical plane BB'. The vertical plane AA' is Figure 3A A plane of a vertical section.

[0017] Figure 3C It is along Figure 3B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0018] 4A to 4F are sequential schematic vertical cross-sectional views of a memory opening within a first exemplary structure during formation of a memory opening filling structure therein according to a first embodiment of the present disclosure.

[0019] Figure 5A is a vertical cross-sectional view of the first exemplary structure after forming a memory opening filling structure in the memory opening according to the first embodiment of the present disclosure.

[0020] Figure 5B It is along Figure 5A A horizontal cross-sectional view of the first exemplary structure taken along the vertical plane BB'. The vertical plane AA' is Figure 5A A plane of a vertical section.

[0021] Figure 5C It is along Figure 5B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0022] Fig. 6A is a vertical cross-sectional view of the first exemplary structure after forming a contact via opening according to the first embodiment of the present disclosure.

[0023] Figure 6B It is along Fig. 6A A horizontal cross-sectional view of the first exemplary structure taken along the vertical plane BB'. The vertical plane AA' is Fig. 6A A plane of a vertical section.

[0024] Figure 6C It is along Figure 6B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0025] Fig. 7A is a vertical cross-sectional view of the first exemplary structure after forming a dielectric contact via liner according to the first embodiment of the present disclosure.

[0026] Figure 7B It is along Fig. 7A A horizontal cross-sectional view of the first exemplary structure taken along the vertical plane BB'. The vertical plane AA' is Fig. 7A A plane of a vertical section.

[0027] Figure 7C It is along Figure 7B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0028] Fig. 8A is a vertical cross-sectional view of the first exemplary structure after forming a laterally-extending cavity according to the first embodiment of the present disclosure.

[0029] Figure 8B It is along Fig. 8A A horizontal cross-sectional view of the first exemplary structure taken along the vertical plane BB'. The vertical plane AA' is Fig. 8A A plane of a vertical section.

[0030] Figure 8C It is along Figure 8B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0031] Fig.9A is a vertical cross-sectional view of the first exemplary structure after forming an integrated connection and contact structure according to the first embodiment of the present disclosure.

[0032] Fig. 9B It is along Fig.9A A horizontal cross-sectional view of the first exemplary structure taken along the vertical plane BB'. The vertical plane AA' is Fig.9A A plane of a vertical section.

[0033] Fig. 9C It is along Fig. 9B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0034] Fig. 10A is a vertical cross-sectional view of a second exemplary structure after forming a memory opening according to the second embodiment of the present disclosure.

[0035] Fig. 10B It is along Fig. 10A A horizontal cross-sectional view of a second exemplary structure of a vertical plane BB'. The vertical plane AA' is Fig. 10A A plane of a vertical section.

[0036] Fig. 10C It is along Fig. 10B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0037] Fig.11A is a vertical cross-sectional view of a second exemplary structure after forming a memory opening filling structure in the memory opening according to the second embodiment of the present disclosure.

[0038] Fig. 11B It is along Fig.11A A horizontal cross-sectional view of a second exemplary structure of a vertical plane BB'. The vertical plane AA' is Fig.11A A plane of a vertical section.

[0039] Fig. 11C It is along Fig. 11B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0040] Fig. 12A is a vertical cross-sectional view of a second exemplary structure after forming backside trenches and barrier trenches according to a second embodiment of the present disclosure.

[0041] Fig. 12B It is along Fig. 12A A horizontal cross-sectional view of a second exemplary structure of a vertical plane BB'. The vertical plane AA' is Fig. 12A A plane of a vertical section.

[0042] Fig. 12C It is along Fig. 12B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0043] Fig.13A is a vertical cross-sectional view of a second exemplary structure after forming a sacrificial backside trench fill structure according to the second embodiment of the present disclosure.

[0044] Fig. 13B It is along Fig.13A A horizontal cross-sectional view of a second exemplary structure of a vertical plane BB'. The vertical plane AA' is Fig.13A A plane of a vertical section.

[0045] Fig. 13C It is along Fig. 13B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0046] Fig.14A is a vertical cross-sectional view of a second exemplary structure after forming a dielectric barrier structure according to the second embodiment of the present disclosure.

[0047] Fig. 14B It is along Fig.14A A horizontal cross-sectional view of a second exemplary structure of a vertical plane BB'. The vertical plane AA' is Fig.14A A plane of a vertical section.

[0048] Fig. 14C It is along Fig. 14B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0049] Fig.15A is a vertical cross-sectional view of a second exemplary structure after forming a contact via opening according to the second embodiment of the present disclosure.

[0050] Fig. 15B It is along Fig.15A A horizontal cross-sectional view of a second exemplary structure of a vertical plane BB'. The vertical plane AA' is Fig.15A A plane of a vertical section.

[0051] Fig. 15C It is along Fig. 15B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0052] Fig.16A is a vertical cross-sectional view of a second exemplary structure after forming a dielectric contact via liner according to the second embodiment of the present disclosure.

[0053] Fig. 16B It is along Fig.16A A horizontal cross-sectional view of a second exemplary structure of a vertical plane BB'. The vertical plane AA' is Fig.16A A plane of a vertical section.

[0054] Fig. 16C It is along Fig. 16B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0055] Fig.17A is a vertical cross-sectional view of a second exemplary structure after forming a laterally-extending cavity according to the second embodiment of the present disclosure.

[0056] Fig. 17B It is along Fig.17A A horizontal cross-sectional view of a second exemplary structure of a vertical plane BB'. The vertical plane AA' is Fig.17A A plane of a vertical section.

[0057] Fig. 17C It is along Fig. 17B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0058] Fig.18A is a vertical cross-sectional view of a second exemplary structure after removing a sacrificial backside trench fill structure and forming a backside recess according to a second embodiment of the present disclosure.

[0059] Fig.18B It is along Fig.18A A horizontal cross-sectional view of a second exemplary structure of a vertical plane BB'. The vertical plane AA' is Fig.18A A plane of a vertical section.

[0060] Fig.18C It is along Fig.18B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0061] Fig.19A is a vertical cross-sectional view of a second exemplary structure after forming an integration layer and a contact structure according to the second embodiment of the present disclosure.

[0062] Fig.19B It is along Fig.19A A horizontal cross-sectional view of a second exemplary structure of a vertical plane BB'. The vertical plane AA' is Fig.19A A plane of a vertical section.

[0063] Fig.19C It is along Fig.19B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0064] Fig. 20A is a vertical cross-sectional view of a second exemplary structure after forming a backside trench fill structure according to the second embodiment of the present disclosure.

[0065] Fig. 20B It is along Fig. 20A A horizontal cross-sectional view of a second exemplary structure of a vertical plane BB'. The vertical plane AA' is Fig. 20A A plane of a vertical section.

[0066] Fig. 20C It is along Fig. 20B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0067] Fig.20D According to the second embodiment of the present disclosure FIG. 20A to FIG. 20C Horizontal cross-sectional view of an alternative configuration of a second exemplary structure at a processing step of .

[0068] Fig.21A is a vertical cross-sectional view of the third exemplary structure after forming a memory opening fill structure, an optional dielectric capping layer, backside trenches, and contact via openings according to the third embodiment of the present disclosure.

[0069] Fig.21B It is along Fig.21A A horizontal cross-sectional view of the third exemplary structure taken along the vertical plane BB'. The vertical plane AA' is Fig.21A A plane of a vertical section.

[0070] Fig.22Ais a vertical cross-sectional view of a third exemplary structure after forming a first dielectric contact via liner according to the third embodiment of the present disclosure.

[0071] Fig. 22B It is along Fig.22A A horizontal cross-sectional view of the third exemplary structure taken along the vertical plane BB'. The vertical plane AA' is Fig.22A A plane of a vertical section.

[0072] Fig.23A is a vertical cross-sectional view of the third exemplary structure after vertically extending one of the contact via openings according to the third embodiment of the present disclosure.

[0073] Fig. 23B It is along Fig.23A A horizontal cross-sectional view of the third exemplary structure taken along the vertical plane BB'. The vertical plane AA' is Fig.23A A plane of a vertical section.

[0074] Fig.24A is a vertical cross-sectional view of a third exemplary structure after forming a second dielectric contact via liner according to the third embodiment of the present disclosure.

[0075] Fig. 24B It is along Fig.24A A horizontal cross-sectional view of the third exemplary structure taken along the vertical plane BB'. The vertical plane AA' is Fig.24A A plane of a vertical section.

[0076] Fig.25A is a vertical cross-sectional view of a third exemplary structure after forming insulating layer-level laterally-extending cavities according to a third embodiment of the present disclosure.

[0077] Fig.25B It is along Fig.25A A horizontal cross-sectional view of the third exemplary structure taken along the vertical plane BB'. The vertical plane AA' is Fig.25A A plane of a vertical section.

[0078] Fig.26A is a vertical cross-sectional view of a third exemplary structure after forming multi-level laterally-extending cavities and single-level laterally-extending cavities according to the third embodiment of the present disclosure.

[0079] Fig.26B It is along Fig.26A A horizontal cross-sectional view of the third exemplary structure taken along the vertical plane BB'. The vertical plane AA' is Fig.26A A plane of a vertical section.

[0080] Fig.27Ais a vertical cross-sectional view of a third exemplary structure after forming a backside recess according to a third embodiment of the present disclosure.

[0081] Fig.27B It is along Fig.27A A horizontal cross-sectional view of the third exemplary structure taken along the vertical plane BB'. The vertical plane AA' is Fig.27A A plane of a vertical section.

[0082] Fig.28A is a vertical cross-sectional view of a third exemplary structure after forming an integration layer and a contact structure according to a third embodiment of the present disclosure.

[0083] Fig.28B It is along Fig.28A A horizontal cross-sectional view of the third exemplary structure taken along the vertical plane BB'. The vertical plane AA' is Fig.28A A plane of a vertical section.

[0084] Fig.29A is a vertical cross-sectional view of the third exemplary structure after forming a backside trench fill structure according to the third embodiment of the present disclosure.

[0085] Fig.29B It is along Fig.29A A horizontal cross-sectional view of the third exemplary structure taken along the vertical plane BB'. The vertical plane AA' is Fig.29A A plane of a vertical section.

[0086] Fig. 30A is a vertical cross-sectional view of a fourth exemplary structure after forming a memory opening fill structure, an optional dielectric capping layer, backside trenches, and contact via openings according to a fourth embodiment of the present disclosure.

[0087] Fig. 30B It is along Fig. 30A A horizontal cross-sectional view of the fourth exemplary structure of the horizontal plane BB'. A vertical plane AA' is Fig. 30A A plane of a vertical section.

[0088] Fig.31A is a vertical cross-sectional view of a fourth exemplary structure after forming a dielectric contact via liner according to a fourth embodiment of the present disclosure.

[0089] Fig.31B It is along Fig.31A A horizontal cross-sectional view of the fourth exemplary structure of the horizontal plane BB'. A vertical plane AA' is Fig.31A A plane of a vertical section.

[0090] Fig.32Ais a vertical cross-sectional view of a fourth exemplary structure after vertically extending one of the contact via openings according to the fourth embodiment of the present disclosure.

[0091] Fig.32B It is along Fig.32A A horizontal cross-sectional view of the fourth exemplary structure of the horizontal plane BB'. A vertical plane AA' is Fig.32A A plane of a vertical section.

[0092] Fig.33A is a vertical cross-sectional view of a fourth exemplary structure after forming insulating layer-level laterally-extending cavities according to a fourth embodiment of the present disclosure.

[0093] Fig.33B It is along Fig.33A A horizontal cross-sectional view of the fourth exemplary structure of the horizontal plane BB'. A vertical plane AA' is Fig.33A A plane of a vertical section.

[0094] Fig.34A is a vertical cross-sectional view of a fourth exemplary structure after forming multi-level laterally-extending cavities and single-level laterally-extending cavities according to the fourth embodiment of the present disclosure.

[0095] Fig.34B It is along Fig.34A A horizontal cross-sectional view of the fourth exemplary structure of the horizontal plane BB'. A vertical plane AA' is Fig.34A A plane of a vertical section.

[0096] Fig.35A is a vertical cross-sectional view of a fourth exemplary structure after forming a backside recess according to a fourth embodiment of the present disclosure.

[0097] Fig.35B It is along Fig.35A A horizontal cross-sectional view of the fourth exemplary structure of the horizontal plane BB'. A vertical plane AA' is Fig.35A A plane of a vertical section.

[0098] Fig.36A is a vertical cross-sectional view of a fourth exemplary structure after forming an integration layer and a contact structure according to a fourth embodiment of the present disclosure.

[0099] Fig.36B It is along Fig.36A A horizontal cross-sectional view of the fourth exemplary structure of the horizontal plane BB'. A vertical plane AA' is Fig.36A A plane of a vertical section.

[0100] Fig.37Ais a vertical cross-sectional view of a fourth exemplary structure after forming a backside trench fill structure according to a fourth embodiment of the present disclosure.

[0101] Fig.37B It is along Fig.37A A horizontal cross-sectional view of the fourth exemplary structure of the horizontal plane BB'. A vertical plane AA' is Fig.37A A plane of a vertical section. DETAILED DESCRIPTION

[0102] As discussed above, embodiments of the present disclosure relate to stair-free three-dimensional memory devices and methods of forming the same by forming replacement word lines through memory openings, various aspects of which are described below. Embodiments of the present disclosure can be used to form various structures, including multi-level memory structures, non-limiting examples of which include semiconductor devices such as three-dimensional memory array devices including multiple NAND memory strings.

[0103] The accompanying drawings are not drawn to scale. Multiple instances of an element may be repeated in the case of a single instance of an element shown therein, unless explicitly described or otherwise clearly indicated that there is no repetition of an element. Serial numbers such as "first", "second" and "third" are used only to identify similar elements, and different serial numbers may be used throughout the specification and claims of the present disclosure. The same reference numerals represent the same element or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. As used herein, a first element positioned "on" a second element may be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components. As used herein, if there is a conductive path between a first electronic component and a second electronic component, the first electronic component is electrically connected to the second electronic component.

[0104] As used herein, "layer" refers to a portion of a material including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0105] As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0x10-6S / cm to 1.0x105S / cm. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0x10-6S / cm to 1.0x105S / cm in the absence of an electrical dopant, and is capable of producing a doped material having an electrical conductivity in the range of 1.0S / cm to 1.0x105S / cm when an electrical dopant is appropriately doped. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0x105S / cm. As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity less than 1.0x10-6S / cm. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with an electrical dopant at a sufficiently high atomic concentration to become a conductive material (i.e., having a conductivity greater than 1.0x105S / cm) when it is formed into a crystalline material or converted into a crystalline material (e.g., starting from an initial amorphous state) by an annealing process. "Doped semiconductor material" may be a heavily doped semiconductor material, or may be a semiconductor material including an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) at a concentration providing a conductivity in the range of 1.0x10-6S / cm to 1.0x105S / cm. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Therefore, a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material may be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material including at least one metal element therein. All conductivity measurements are performed under standard conditions.

[0106] Typically, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are bonded therein, for example, by flip chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some limitations. In the case where the die is a memory die (i.e., a die including a memory cell), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. Each plane includes multiple storage blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each storage block contains multiple pages, which are the smallest units that can be selected for programming.

[0107] refer to Figure 1 , shows a first exemplary structure according to a first embodiment of the present disclosure, which can be used, for example, to manufacture a device structure including a vertical NAND memory device. The first exemplary structure includes a substrate, which includes a semiconductor material layer at least at an upper portion thereof. The semiconductor material layer 9 includes at least one elemental semiconductor material (e.g., a doped well in a single crystal silicon wafer or a deposited silicon layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor material layer may include a doped semiconductor material having a first conductivity type.

[0108] A stack of alternating multiple insulating layers 32 and sacrificial material layers 42 may be formed above the semiconductor material layer 9. The alternating multiple stacks are referred to herein as alternating stacks (32, 42). In one embodiment, the alternating stacks (32, 42) may include an insulating layer 32 composed of a first material and a sacrificial material layer 42 composed of a second material, wherein the second material is different from the material of the insulating layer 32. The first material of the insulating layer 32 may be at least one insulating material. Therefore, each insulating layer 32 may be an insulating material layer. Insulating materials that can be used for the insulating layer 32 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal nitride oxides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the insulating layer 32 may be silicon oxide.

[0109] The second material of sacrificial material layer 42 is a sacrificial material that is selectively removable with respect to the first material of insulating layer 32. As used herein, removal of a first material is "selective with respect to" a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0110] The sacrificial material layer 42 may include a dielectric material. In one embodiment, the sacrificial material layer 42 may include silicon nitride and / or may consist essentially of silicon nitride. The insulating layer 32 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the insulating layer 32, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The sacrificial material layer 42 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0111] The thickness of the insulating layer 32 and the sacrificial material layer 42 can be in the range of 20nm to 50nm, but smaller and larger thicknesses can be used for each insulating layer 32 and each sacrificial material layer 42. The number of repetitions of the pair of insulating layers 32 and sacrificial material layers (e.g., control gate electrodes or sacrificial material layers) 42 can be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions can also be used. The top gate electrode and the bottom gate electrode in the stack can be used as select gate electrodes. In one embodiment, each sacrificial material layer 42 in the alternating stack (32, 42) can have a uniform thickness that is substantially constant within each corresponding sacrificial material layer 42.

[0112] Optionally, an insulating capping layer 70 may be formed over the alternating stack (32, 42). The insulating capping layer 70 includes a dielectric material different from the material of the sacrificial material layer 42. In one embodiment, the insulating capping layer 70 may include a dielectric material that may be used for the insulating layer 32 as described above. The insulating capping layer 70 may have a greater thickness than each insulating layer 32. The insulating capping layer 70 may be deposited by, for example, chemical vapor deposition. In one embodiment, the insulating capping layer 70 may be a silicon oxide layer.

[0113] refer to FIG. 2A to FIG. 2C , a photolithographic material stack (not shown) including at least a photoresist layer may be formed above the insulating cap layer 70 and may be photolithographically patterned to form an opening therein. The pattern in the photolithographic material stack may be transferred through the insulating cap layer 70 and through the alternating stack (32, 42) by at least one anisotropic etch using the patterned photolithographic material stack as an etching mask. The portion of the alternating stack (32, 42) below the opening in the patterned photolithographic material stack is etched to form a memory opening 49. As used herein, a "memory opening" refers to a structure in which a memory cell such as a memory stack structure is subsequently formed. In one embodiment, the memory opening 49 may have a horizontal cross-sectional shape of a circle. The diameter of the circle may be greater than the thickness of the sacrificial material layer 42.

[0114] The memory opening 49 extends through the entirety of the alternating stack (32, 42). The chemistry of the anisotropic etching process used to etch the material through the alternating stack (32, 42) can be alternating to optimize the etching of the first material and the second material in the alternating stack (32, 42). The anisotropic etching can be, for example, a series of reactive ion etchings. The sidewalls of the memory opening 49 can be substantially vertical, or can be tapered. The patterned photolithographic material stack can then be removed, for example, by ashing.

[0115] The memory opening 49 may extend from the top surface of the alternating stack (32, 42) to at least a horizontal plane including the topmost surface of the semiconductor material layer 9. In one embodiment, after the top surface of the semiconductor material layer 9 is physically exposed at the bottom of each memory opening 49, an overetch of the semiconductor material layer 9 may be optionally performed. The overetch may be performed before or after removing the photolithographic material stack. In other words, the recessed surface of the semiconductor material layer 9 may be vertically offset from the unrecessed top surface of the semiconductor material layer 9 by a recessed depth. The recessed depth may be in the range of, for example, 1 nm to 50 nm, but smaller and larger depths may also be used. Overetching is optional and may be omitted.

[0116] Generally speaking, the memory openings 49 may be arranged in a pattern that provides stripe-shaped areas that are free of memory openings 49 and extend laterally along a first horizontal direction (e.g., a word line direction) hd1. In addition, the pattern of memory openings 49 may include a plurality of discrete areas that are free of memory openings 49 located between adjacent pairs of stripe-shaped areas. In one embodiment, the memory openings 49 may be arranged in a pattern that includes multiple rows of memory openings 49 arranged along the first horizontal direction hd1.

[0117] refer to FIG. 3A to FIG. 3C , an isotropic etching process can be performed to selectively recess the physically exposed sidewalls of the sacrificial material layer 42 laterally relative to the material of the insulating layer 32 surrounding each memory opening 49. For example, if the insulating layer 42 comprises silicon oxide and if the sacrificial material layer 42 comprises silicon nitride, a wet etching process using hot phosphoric acid can be performed to selectively recess the sidewalls of the sacrificial material layer 42 isotropically relative to the insulating layer 32. A lateral recess is formed around each memory opening 49 at each level of the sacrificial material layer 42. The lateral recesses are referred to herein as memory opening side recesses or front lateral openings. The duration of the isotropic etching process can be selected so that the discrete lateral recesses merge with each other to form a plurality of interconnected lateral recesses. Each of the interconnected lateral recesses can be laterally spaced apart by a remaining portion of the sacrificial material layer 42. Each interconnected lateral recess laterally surrounds a corresponding plurality of memory openings 49, as shown in reference to FIG. FIG. 2A to FIG. 2C The process steps described are formed.

[0118] The remaining portion of the sacrificial material layer 42 includes various dielectric material portions (142, 242, 342, 442, 542) that provide lateral separation between adjacent pairs of interconnected lateral recesses. For example, the various dielectric material portions (142, 242, 342, 442, 542) may include dielectric material plates 142 having respective first lateral extents along a first horizontal direction hd1 that are greater than the center-to-center spacing between adjacent pairs of memory openings 49, and having respective second lateral extents along a second horizontal direction (e.g., a bit line direction) hd2 that are greater than the center-to-center spacing between adjacent pairs of memory openings 49. In one embodiment, each dielectric material plate 142 may have a respective first lateral extent along a first horizontal direction hd1 that is greater than twice the center-to-center spacing between adjacent pairs of memory openings 49, and may have a respective second lateral extent along a second horizontal direction hd2 that is greater than twice the center-to-center spacing between adjacent pairs of memory openings 49. In one embodiment, the dielectric material plate 142 may have a generally rectangular horizontal cross-sectional area with respective lateral undulations on the sides in plan view, such as Figure 3B The area of ​​the dielectric material plate 142 will be used to form a word line contact via structure in a subsequent step.

[0119] Furthermore, the various dielectric material portions (142, 242, 342, 442, 542) may include discrete dielectric material plates 242 that are laterally surrounded by corresponding interconnecting lateral recesses. The areas of the discrete dielectric material plates 142 will be used in subsequent steps to form drain side select gate electrode contact via structures.

[0120] The various dielectric material portions (142, 242, 342, 442, 542) may include a first dielectric material strip 342 that extends transversely generally along a first horizontal direction hd1 and transversely separates a pair of adjacent interconnected transverse recesses. The first dielectric material strip 342 does not abut the dielectric material plate 142. The various dielectric material portions (142, 242, 342, 442, 542) may also include a second dielectric material strip 442 that extends transversely generally along a first horizontal direction hd2 and transversely separates a pair of adjacent interconnected transverse recesses. The second dielectric material strip 442 abuts the respective dielectric material plate 142. Specifically, the second dielectric material strip 442 abuts the side of the respective dielectric material plate 142 that extends along the second horizontal direction hd2. The dielectric material strips (342, 442) may have a respective pair of transversely undulating longitudinal sidewalls that extend transversely along the first horizontal direction hd1 and have transverse undulations along the second horizontal direction hd2. The first and second dielectric material strips (332, 442) will be used in subsequent steps to separate adjacent memory blocks along a word line direction (ie, a first horizontal direction) hd1.

[0121] The various dielectric material portions (142, 242, 342, 442, 542) may also include dielectric isolation rails 542 extending generally laterally along the second horizontal direction (eg, bit line direction) hd2. The dielectric material rails 542 will be used in subsequent steps to separate adjacent memory blocks along the bit line direction (ie, second horizontal direction) hd2.

[0122] The isotropic etching process causes the material of the sacrificial material layer 42 to be isotropically laterally recessed. Thus, each interface between the interconnect lateral recess and the dielectric material portion (142, 242, 342, 442, 542) is equidistant from the nearest vertically extending plane containing the sidewalls of the insulating layer 32 surrounding the corresponding memory opening 49. In other words, a vertical plane (such as a cylindrical plane) can be defined so that the vertical plane contains the sidewalls of the insulating layer 32 surrounding the corresponding memory opening 49. Each interface between the interconnect lateral recess and the dielectric material portion (142, 242, 342, 442, 542) is equidistant from the nearest one of the vertical planes. The lateral separation distance between each interface and the nearest one of the vertical planes is the same as the lateral etching distance of the isotropic etching process.

[0123] In one embodiment, each of the memory openings 49 may have a corresponding circular horizontal cross-sectional shape. In this case, each interface between the interconnect lateral recess and the dielectric material portion (142, 242, 342, 442, 542) may be laterally offset from a vertical axis VA passing through the geometric center of the volume of the nearest memory opening 49 by a lateral distance that is the same as the sum of the radius of the memory opening 49 and the lateral etching distance of the isotropic etching process. Each interface between the interconnect lateral recess and the dielectric material portion (142, 242, 342, 442, 542) may be vertical in a vertical cross-sectional view and may have a radius of curvature Rc in a horizontal cross-sectional view. The radius of curvature Rc may be the same as the sum of the radius of the memory opening 49 and the lateral etching distance of the isotropic etching process. Each interface between the interconnecting lateral recesses and the dielectric material portion (142, 242, 342, 442, 542) may include a respective set of a plurality of vertically straight and horizontally concave surface segments of the dielectric material portion (142, 242, 342, 442, 542).

[0124] At least one conductive material (such as a combination of a metal barrier liner material and a metal fill material) may be conformally deposited in the continuous lateral recess, in the peripheral portion of the memory opening 49, and over the alternating stack (32, 42). The metal barrier liner material may include a conductive metal compound material such as TiN, TaN, WN, MoN, TiC, TaC, WC, their alloys, or combinations thereof. The metal fill material may include W, Ti, Ta, Mo, Co, Ru, Cu, their alloys, or combinations thereof. The total thickness of the at least one conductive material is greater than half the thickness of the dielectric material portion (142, 242, 342, 442, 542) and is less than the diameter (or minor axis) of the memory opening 49. Thus, after depositing the at least one conductive material, a continuous vertically extending cavity may exist within each memory opening 49.

[0125] A recess etching process may be performed to remove portions of the at least one conductive material that are present within the volume of the memory opening 49 and to remove horizontally extending portions of the at least one conductive material from above the insulating capping layer 70. The recess etching process may include an anisotropic etching process. Each remaining portion of the at least one conductive material that is located within a corresponding one of the continuous lateral recesses constitutes the conductive layer 46. In one embodiment, the sidewalls of the conductive layer 46 around the memory opening 49 may be vertically coincident with the sidewalls of the insulating layer 32 that are located around the memory opening 49 (i.e., located in the same cylindrical vertical plane as these sidewalls).

[0126] All of the material portions of the group between each vertically adjacent pair of insulating layers 32 or between the topmost insulating layer 32 and the insulating cap layer 70 constitute a composite layer (142, 242, 342, 442, 542, 46). In one embodiment, each of the composite layers (142, 242, 342, 442, 542, 46) includes a corresponding set of conductive layers 46 laterally spaced apart by a corresponding set of dielectric material portions (142, 242, 342, 442, 542). At least one topmost conductive layer 46 includes a drain side select gate electrode. At least one bottommost conductive layer 46 includes a source side select gate electrode. The remaining conductive layers 46 located between the drain side select gate electrode and the source side select gate electrode include word lines that serve as control gates for each vertical NAND string.

[0127] Generally speaking, portions of sacrificial material layer 42 proximate to memory openings 49 are replaced by conductive layer 46. In other words, proximal portions of sacrificial material layer 42 surrounding each of memory openings 49 may be replaced by conductive layer 46. Each of conductive layers 46 includes a respective set of conductive material portions and contacts the remaining portions of the respective sacrificial material layer 42 constituting dielectric material portions (142, 242, 342, 442, 542).

[0128] An alternating stack of insulating layers 32 and composite layers (142, 242, 342, 442, 542, 46) may be formed over the substrate. Each of the composite layers (142, 242, 342, 442, 542, 46) includes a respective set of conductive layers 46 laterally spaced apart by a respective set of dielectric material portions (142, 242, 342, 442, 542). In one embodiment, the memory opening 49 has a respective circular horizontal cross-sectional shape, and the surface segments within the vertically extending interface between the conductive layers 46 and the dielectric material portions (142, 242, 342, 442, 542) have respective radii of curvature Rc that are the same as the radial distance from a vertical axis VA that passes through the geometric center of the nearest memory opening 49 in the plan view.

[0129] 4A to 4F are sequential schematic vertical cross-sectional views of memory opening 49 within a first exemplary structure during formation of memory opening filling structure 58 therein according to a first embodiment of the present disclosure.

[0130] refer to Figure 4A , shows that in reference FIG. 3A to FIG. 3C Memory opening 49 after the processing steps described.

[0131] refer to Figure 4B, a set of material layers may be conformally deposited, the set of material layers may include an optional blocking dielectric layer 52, a memory material layer 54, and an optional dielectric liner 56. The blocking dielectric layer 52 may include at least one blocking dielectric material, such as silicon oxide and / or a dielectric metal oxide. The memory material layer 54 may include any memory material in which a memory bit may be stored. For example, the memory material layer 54 may include a charge storage layer, such as a silicon nitride layer. Alternatively, the memory material layer 54 may include a ferroelectric memory material, a resistive memory material, a phase change memory material, or any other memory material known in the art. In some embodiments, the memory material layer 54 may include a vertical stack of discrete memory material portions formed at the level of the conductive layer 46. Generally speaking, the memory material layer 54 may include a vertical stack of memory cells formed at the level of the conductive layer 46. In one embodiment, the vertical stack of memory cells includes a portion of the memory material layer 54 located at the level of the conductive layer 46. The optional dielectric liner 56, if present, may provide electrical isolation between the memory material layer 54 and the semiconductor channel to be formed subsequently. Where the memory material layer 54 comprises a charge storage material, the optional dielectric liner 56 may comprise a tunneling dielectric layer.

[0132] refer to Figure 4C , an anisotropic etching process may be performed to remove the horizontally extending portions of the optional blocking dielectric layer 52, the memory material layer 54, and the optional dielectric liner 56. The combination of the vertically extending portions of the optional blocking dielectric layer 52, the memory material layer 54, and the optional dielectric liner 56 remaining in the corresponding memory openings 49 constitutes the memory film 50.

[0133] refer to Figure 4D , a semiconductor channel layer 60L may be deposited over the memory film 50. The semiconductor channel layer 60L includes a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel layer 60L includes amorphous silicon or polycrystalline silicon. The semiconductor channel layer 60L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). In one embodiment, the semiconductor channel layer 60L may be deposited as an amorphous semiconductor material. The thickness of the semiconductor channel layer 60L may be in the range of 2nm to 10nm, but smaller and larger thicknesses may also be used. A memory cavity exists in the volume of each memory opening 49 that is not filled with the deposited material layer (52, 54, 56, 60L).

[0134] refer to Figure 4E, a dielectric core layer may be deposited to fill any remaining portion of the memory cavity within each memory opening. The dielectric core layer includes a dielectric material, such as silicon oxide or organosilicate glass. The dielectric core layer may be deposited by a conformal deposition method, such as low pressure chemical vapor deposition (LPCVD), or by a self-planarization deposition process, such as spin coating. Subsequently, the dielectric core layer may be selectively recessed relative to the material of the semiconductor channel layer 60L, for example by recess etching. The material of the dielectric core layer is vertically recessed below a horizontal plane including the top surface of the insulating cap layer 70. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0135] refer to Figure 4F , a doped semiconductor material having a second conductivity type of doping may be deposited in each recessed cavity located above the dielectric core 62. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. In one embodiment, the doped semiconductor material may be deposited as an amorphous semiconductor material. The dopant concentration in the doped semiconductor material having a second conductivity type of doping may be in the range of 5.0×1018 / cm3 to 2.0×1021 / cm3, but lower and higher dopant concentrations may also be used.

[0136] A planarization process may be performed to remove the doped semiconductor material having the second conductivity type and the portion of the semiconductor channel layer 60L from above the top surface of the insulating cap layer 70, for example, by chemical mechanical planarization (CMP) or recess etching, to form a drain region 63. Each remaining portion of the doped semiconductor material having the second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel layer 60L constitutes a vertical semiconductor channel 60. When the vertical NAND device including the vertical semiconductor channel 60 is turned on, current may flow through each vertical semiconductor channel 60. Within each memory opening 49, the dielectric liner 56 is surrounded by the memory material layer 54 and laterally surrounds the vertical semiconductor channel 60. Each set of adjacent blocking dielectric layers 52, memory material layers 54, and dielectric liner 56 together constitute a memory film 50, which can store charge at a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after forming the backside recess. As used herein, macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device, such as a retention time exceeding 24 hours. Each combination of a memory film 50 and a vertical semiconductor channel 60 constitutes a memory stack structure 55 .

[0137] Each adjoining combination of the vertical semiconductor channel 60 and the memory film 50 constitutes a memory stack structure 55. Thus, each memory stack structure 55 may include the vertical semiconductor channel 60, the dielectric liner 56, a plurality of memory cells including portions of the memory material layer 54, and an optional blocking dielectric layer 52. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 is referred to herein as a memory opening filling structure 58.

[0138] Reference 5A to Figure 5C , shows that in reference Figure 4F A first exemplary structure after the described processing steps. In one embodiment, when forming the memory opening filling structures 58, the conductive layer 46 laterally surrounds the corresponding plurality of memory opening filling structures 58. The memory opening 49 extends vertically through the portions of the alternating stack (32, 142, 242, 342, 442, 542, 46) of the insulating layer 32 and the composite layer (142, 242, 342, 442, 542, 46) and is laterally spaced apart from each of the dielectric material portions (142, 242, 342, 442, 542). In other words, the memory opening filling structures 58 are surrounded by the conductive layer 46 and offset from the dielectric material portions at the level of the composite layer. The vertically extending interface between the conductive layer 46 and the dielectric material portions (142, 242, 342, 442, 542) is laterally offset from the sidewall of the nearest one of the memory opening filling structures 58.

[0139] refer to FIG. 6A to FIG. 6C , contact via openings 89 are formed in the region of dielectric material plates 142. Each of the contact via openings 89 may extend vertically through the insulating capping layer 70 and optionally through a corresponding subset of dielectric material plates 142 and optionally through a corresponding subset of insulating layers 32, so that the top surface of a selected dielectric material plate 142 is physically exposed at the bottom of each contact via opening 89. In one embodiment, the contact via openings 89 may have different depths from each other, and the dielectric material plates 142 may be physically exposed to the corresponding overlying contact via openings 89 at each level of the conductive layer 46. In other words, for each conductive layer 46 overlying the semiconductor material layer 9, at least one dielectric material plate 142 located at the same level as the conductive layer 46 may be physically exposed to the corresponding overlying contact via opening 49.

[0140] A multiple mask anisotropic etching process may be employed to form contact via openings 89 having different depths. In an illustrative example, a patterned hard mask layer (not shown) including openings therethrough may be formed over the insulating capping layer 70. The patterned hard mask layer may include a dielectric material such as silicon nitride and / or a metal material such as TiN. The openings in the patterned hard mask layer may have a pattern of all contact via openings 89 that will be subsequently formed. An anisotropic etching process may be performed to transfer the pattern of the openings in the patterned hard mask layer through the insulating capping layer 70.

[0141] Subsequently, multiple iterations of a combination of a respective masking process and a respective anisotropic etching process may be performed to etch through a respective subset of dielectric material plates 142 and a respective subset of insulating layers 32. Each masking process forms a respective patterned photoresist layer that masks a respective subset of openings in the patterned hard mask layer while not masking a respective complementary subset of openings. Each anisotropic etching process etches a respective number of dielectric material plates 142 and a respective number of insulating layers 32 under each opening in the patterned hard mask layer that is not masked by the respective patterned photoresist layer. In one embodiment, the number of etched dielectric material plates 142 and etched insulating layers 32 under the unmasked openings in the patterned hard mask layer may be a non-negative integer power of 2, i.e., 1, 2, 4, 8, 16, 32, 64, etc. By using a combination of various masking patterns for the patterned photoresist layer, the overall depth of the contact via opening 89 can be varied so that the top surface of the dielectric material plate 142 can be physically exposed at each level of the conductive layer 46. The patterned hard mask layer can then be removed. The lateral dimensions (such as diameter) of the contact via opening 89 can be in the range of 30nm to 300nm, but smaller and larger lateral dimensions can also be used. In general, the contact via opening 89 can extend vertically through the alternating stack of insulating layers 32 and dielectric material plates 142.

[0142] Select gate electrode contact via openings 89S are formed in the region of discrete dielectric material plate 242. Discrete dielectric material plate 142 may be physically exposed to respective overlying select gate electrode contact via openings 89S at each level of one or more topmost conductive layers 46 used as drain side select gate electrodes.

[0143] refer to 7A to 7C, a dielectric material (such as silicon oxide) may be conformally deposited in the contact via opening 89, in the select gate electrode contact via opening 89S, and over the insulating cap layer 70 to form a conformal dielectric material layer. An anisotropic etching process may be performed to remove the horizontally extending portion of the conformal dielectric material layer. Each remaining tubular portion of the conformal dielectric material layer constitutes a tubular dielectric spacer 84. Each tubular dielectric spacer 84 is a dielectric contact via liner that contacts the sidewall of a corresponding one of the contact via opening 89 or the select gate electrode contact via opening 89S. The tubular dielectric liner 84 may be formed at the peripheral portion of each contact via opening 89 or the select gate electrode contact via opening 89S. A connecting via cavity 89' may be present within each unfilled volume of the contact via opening 89.

[0144] refer to FIG. 8A to FIG. 8C , an isotropic etching process may be performed to selectively etch the material of the dielectric material plates 142 and the discrete dielectric material plates 242 relative to the material of the insulating layer 32, the tubular dielectric liner 84, and the insulating cap layer 70. For example, if the dielectric material plates 142 include silicon nitride, a wet etching process using hot phosphoric acid may be performed to remove each dielectric material plate 142 that is physically exposed to the cavity within the corresponding contact via opening 89. A laterally extending cavity 143 may be formed within each void formed by removing the dielectric material plates 142 or the discrete dielectric material plates 242. In general, an isotropic etching process that selectively etches the material of the dielectric material portions (142, 242, 342, 442, 542) relative to the material of the conductive layer 46 and the tubular dielectric liner 84 may be performed after the tubular dielectric liner 84 is formed. Laterally extending cavities 143 may be formed below contact via openings 89 and select gate electrode contact via openings 89S such that the sidewalls of corresponding conductive layer 46 are physically exposed around each laterally extending cavity 143. In one embodiment, laterally extending cavities 143 located at different levels may be formed within the region of the vertical stack of dielectric material plates 142.

[0145] refer to 9A to 9C, at least one conductive material (such as a combination of a metal barrier liner material and a metal fill material) may be conformally deposited in the laterally extending cavity 143 and in the through-hole cavity (89', 89S) laterally surrounded by the tubular dielectric liner 84. The metal barrier liner material may include a conductive metal compound material such as TiN, TaN, WN, MoN, TiC, TaC, WC, their alloys, or combinations thereof. The metal fill material may include W, Ti, Ta, Mo, Co, Ru, Cu, their alloys, or combinations thereof. The total thickness of the at least one conductive material is greater than half the height of the laterally extending cavity 143 and greater than half the width of the through-hole cavity (89', 89S). Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the insulating cap layer 70 by performing a planarization process, which may include a recess etching process and / or a chemical mechanical polishing process.

[0146] Each remaining portion of the at least one conductive material filling the respective combination of the laterally extending cavity 143 and the via cavity (89', 89S) constitutes an integrated line and via structure (48, 84, 86). Each integrated line and via structure (48, 84, 86) may be formed in a continuous volume including the volume within the laterally extending cavity 143 and the contact via opening 89 or the select gate electrode contact via opening 89S. Each integrated line and via structure (48, 84, 86) includes a metal plate portion 48 that laterally contacts the respective conductive layer 46 and also includes a metal via portion 86 formed in the respective contact via opening 89 or the select gate electrode contact via opening 89S.

[0147] Comprehensive reference Figures 1 to 9C, a semiconductor structure is provided, the semiconductor structure comprising: an alternating stack (32, 46) of insulating layers 32 and composite layers (142, 242, 342, 442, 542, 46), wherein each of the composite layers (142, 242, 342, 442, 542, 46) comprises a corresponding set of conductive layers 46, the corresponding set of conductive layers being laterally spaced apart by a corresponding set of dielectric material portions (142, 242, 342, 442, 542); a memory opening 49, the memory opening extending vertically through the portions of the alternating stack (32, 46) and being laterally spaced apart from each of the dielectric material portions (142, 242, 342, 442, 542); a memory opening filling structure 58, the memory opening filling structure being located in the memory opening 49, wherein the conductive layers A vertically extending interface between the dielectric material portions (142, 242, 342, 442, 542) and the memory opening filling structures 58 is laterally offset from the sidewall of the nearest one of the memory opening filling structures 58, and wherein each of the memory opening filling structures 58 includes a corresponding vertical semiconductor channel 60 and a corresponding vertical stack of memory cells (such as portions of the memory material layer 54); and an integrated line and via structure (48, 84, 86) that includes a metal plate portion 48 that laterally contacts a first conductive layer 46 in the conductive layers 46 and also includes a metal through-hole portion 86 that vertically extends through a subset of the dielectric material portions (142, 242, 342, 442, 542) overlying the metal plate portion 48 (such as the dielectric material plate 142).

[0148] In one embodiment, metal via portions 86 also extend vertically through a subset of insulating layer 32 overlying metal plate portions 48; memory openings 49 have corresponding circular horizontal cross-sectional shapes; and surface segments within the vertically extending interface between conductive layer 46 and dielectric material portions (142, 242, 342, 442, 542) have corresponding radii of curvature Rc that are the same as the radial distance from a vertical axis that passes through the geometric center of the nearest one of memory openings 49 in plan view. In one embodiment, surface segments within the vertically extending interface INT between metal plate portion 48 and first conductive layer 46 have corresponding radii of curvature Rc that are the same as the radial distance in plan view.

[0149] In one embodiment, the integrated line and via structures (48, 84, 86) include a homogenous metal material portion that extends continuously from a volume within the metal plate portion 48 to a volume within the metal via portion 86 without a material junction therein. As used herein, a material junction refers to any surface where different materials contact each other, or any surface where a continuous microscopic interface extends over a macroscopic lateral dimension (such as greater than 1 mm).

[0150] The integrated line and via structure (48, 84, 86) can be a monolithic structure. As used herein, a monolithic structure refers to a structure in which any pair of two points within the structure can be connected by a continuous path that is completely contained within the structure.

[0151] In one embodiment, the metal via portion 86 is laterally surrounded by the tubular dielectric liner 84; and the tubular dielectric liner 84 is laterally surrounded by each dielectric material portion (such as the dielectric material plate 142) within a subset of the dielectric material portions (142, 242, 342, 442, 542) overlying the metal plate portion 48. In one embodiment, the annular bottom surface of the tubular dielectric liner 84 contacts the annular horizontal surface segment of the metal plate portion 48.

[0152] In one embodiment, the metal plate portion 48 includes: a first horizontal surface, which contacts the horizontal bottom surface of the overlying insulating layer 32 in the insulating layer 32; a second horizontal surface, which contacts the horizontal top surface of the underlying insulating layer 32 in the insulating layer 32; a laterally undulating vertical surface, which contacts the first conductive layer 46; and a pair of laterally raised and vertically straight surfaces, which contact corresponding dielectric material portions.

[0153] exist Fig.9A In one embodiment shown, at least one topmost conductive layer 46D in the conductive layer 46 includes a drain side selection gate electrode, at least one bottommost conductive layer 46S in the conductive layer includes a source side selection gate electrode, and the conductive layer 46W located between the drain side selection gate electrode and the source side selection gate electrode (46D, 46S) includes a word line.

[0154] exist Fig. 9BIn one embodiment shown, the set of dielectric material portions includes a dielectric material plate 142, a discrete dielectric material plate 242, a first dielectric material strip 342 extending generally laterally along a word line direction hd1 and laterally separating a first laterally adjacent pair of word lines 46W located in adjacent memory blocks (92, 94), a second dielectric material strip 442 extending generally laterally along the word line direction hd1 and laterally separating, together with the dielectric material plate 142, a second laterally adjacent pair of word lines 46W in the same memory block 92, and a dielectric isolation rail 542 extending generally laterally along a bit line direction hd2 and laterally separating adjacent memory blocks (92, 96) along the bit line direction hd2. A pair of discrete dielectric material plates 242 located in the same memory block 92 are laterally separated along the bit line direction hd2 by a respective one of the second dielectric material strips 442.

[0155] exist Fig. 9B In one embodiment shown, the metal via portion 86 includes a word line contact via portion 86W and a select gate electrode contact via portion 86S, wherein the word line contact via portion extends vertically through a subset of the dielectric material plates (e.g., one or more plates) 142 and contacts a corresponding one of the word lines 46W, and the select gate electrode contact via portion extends vertically through a subset of the discrete dielectric material plates (e.g., one or more plates) 242 and contacts a corresponding one of the drain side select gate electrodes 46D.

[0156] refer to FIG. 10A to FIG. 10C , by modifying the pattern of the memory opening 49, FIG. 2A to FIG. 2C The first exemplary structure shown leads to a second exemplary structure according to a second embodiment of the present disclosure. The pattern of memory openings may include multiple rows of memory openings 49 arranged along the first horizontal direction hd1 and laterally spaced apart along the second horizontal direction hd2. In one embodiment, the memory openings 49 may be arranged to laterally surround multiple discrete areas 77 that do not contain any memory openings 49. In one embodiment, each discrete area 77 may have an area with a lateral dimension in the range of 2 to 10 times the center-to-center distance between adjacent pairs of memory openings 49. In one embodiment, stripe areas that do not contain memory openings 49 and extend laterally along the first horizontal direction hd2 may be provided between adjacent clusters of memory openings 49 in adjacent memory blocks.

[0157] refer to FIG. 11A to FIG. 11C , executable reference 4A to 4F The processing steps are described to form a memory opening fill structure 58 within each memory opening 49 .

[0158] refer to FIG. 12A to FIG. 12C, a photoresist layer may be applied over the insulating cap layer 70 and may be photolithographically patterned to form various openings therethrough. The openings in the photoresist layer include: first slit-shaped openings formed in areas between adjacent clusters of memory openings 49 (e.g., between adjacent memory blocks) and extending laterally along a first horizontal direction hd1; and second slit-shaped openings located at peripheral portions of discrete regions 77 (e.g., regions located in one of the memory blocks) and extending laterally along the first horizontal direction hd1. The openings in the photoresist layer do not have any area overlap with the memory opening filling structure 58 in a plan view (such as a top view).

[0159] An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the alternating stack of insulating layers 32 and sacrificial material layers 42 and optionally into the upper portion of the semiconductor material layer 10. Backside trenches 79 are formed below the first slit-shaped openings in the photoresist layer, and blocking trenches 179 are formed below the second slit-shaped openings in the photoresist layer. Backside trenches 79 are formed between respective clusters of memory openings 49 to separate laterally adjacent memory blocks and extend laterally along a first horizontal direction hd1. Blocking trenches 179 are formed at peripheral regions of discrete regions 77 where memory opening filling structures 58 are not present. Blocking trenches 179 may extend laterally along the first horizontal direction hd1. In one embodiment, a pair of blocking trenches 179 may be formed in one, more, and / or each of the discrete regions 77 that do not contain memory opening filling structures 58. Each pair of blocking trenches 179 may be laterally spaced apart along a second horizontal direction hd2.

[0160] The blocking trench 179 may have a first width along the second horizontal direction hd2, which may be in the range of 20 nm to 200 nm, but smaller and larger first widths may also be adopted. The blocking trench 79 may have a second width along the second horizontal direction hd2, which may be in the range of 40 nm to 600 nm, but smaller and larger second widths may also be adopted. In one embodiment, the second width may be greater than the first width, and may be in the range from twice the first width to 6 times the first width. The lateral extent of each blocking trench 179 along the first horizontal direction hd1 may be substantially the same as the lateral extent of the discrete region 77 without the memory opening filling structure 58. The lateral extent of each backside trench 79 along the first horizontal direction hd1 may be greater than the lateral extent of the discrete region 77 without the memory opening filling structure 58, and may be greater than the total lateral extent of the plurality of discrete regions 77 arranged along the first horizontal direction hd1.

[0161] In one embodiment, a subset of the memory opening filling structures 58 may be located within a rectangular area RA having a lateral extent along a first horizontal direction hd1 that is the same as the lateral extent of a pair of barrier grooves 179 along the first horizontal direction hd1, and the rectangular area having a lateral extent along a second horizontal direction hd2 that is the same as the lateral distance between a proximal one of the pair of barrier grooves 179 and the nearest back side groove 79.

[0162] In alternative embodiments, the backside trenches 79 may be formed in a subsequent processing step after the laterally-extending cavities are formed.

[0163] refer to FIG. 13A to FIG. 13C , a sacrificial trench filling material may be deposited in the backside trench 79 and the blocking trench 179. The sacrificial trench filling material may include a semiconductor material such as amorphous silicon, polycrystalline silicon or a silicon germanium alloy, a carbon-based material such as amorphous carbon or diamond-like carbon, an organosilicate glass or a polymer material. In the case where the sacrificial trench filling material includes a semiconductor material, a sacrificial dielectric liner (such as a silicon oxide liner, not shown) may be formed on the physically exposed surface of the semiconductor material layer at the bottom of each backside trench 79, for example, by performing an oxidation process. Excess portions of the sacrificial trench filling material may be removed from above a horizontal plane including the top surface of the insulating cap layer 70. Each remaining portion of the sacrificial trench filling material that fills the corresponding backside trench 79 constitutes a sacrificial backside trench filling structure 75. Each remaining portion of the sacrificial trench filling material that fills the corresponding blocking trench 179 constitutes a sacrificial blocking trench filling structure.

[0164] A photoresist layer (not shown) may be applied over the insulating capping layer 70 and may be photolithographically patterned to form an opening over each of the sacrificial barrier trench fill structures. A selective etching process that etches the material of the sacrificial barrier trench fill structures may be performed to remove the sacrificial barrier trench fill structures without removing the alternating stack of insulating layers 32 and sacrificial material layers 42, the insulating capping layer 70, or the semiconductor material layer 9. A void is formed within the barrier trench 179. The photoresist layer may then be removed, for example, by ashing.

[0165] refer to Fig.14A To Figure Fig. 14C, a dielectric filling material different from the material of the sacrificial material layer 42 may be deposited in the blocking trench 179 and above the insulating cap layer 70. The dielectric filling material may include a silicon oxide material (such as undoped silicate glass or doped silicate glass) and / or a dielectric metal oxide material (such as aluminum oxide, hafnium oxide, titanium oxide, etc.). Excess portions of the dielectric filling material overlying a horizontal plane including the top surface of the insulating cap layer 70 may be removed by a planarization process that may employ a recess etching process and / or chemical mechanical planarization. Each remaining portion of the dielectric filling material that fills the corresponding blocking trench 179 comprises a dielectric barrier structure 176. Each dielectric barrier structure 176 extends vertically from the top surface of the insulating cap layer 70 to the semiconductor material layer 9.

[0166] A pair of dielectric isolation structures 176 may be formed at a peripheral portion of one, more or each of the discrete regions 77 located between a corresponding adjacent pair of sacrificial backside trench filling structures 75 and free of memory opening filling structures 58. Each pair of dielectric isolation structures 176 may be formed through the alternating stack (32, 42). Each pair of dielectric isolation structures 176 may be laterally spaced apart from the pair of backside trench filling structures (74, 76) and may be in direct contact with each insulating layer 32 within the alternating stack (32, 42). In one embodiment, the interface between the alternating stack (32, 42) and each pair of dielectric isolation structures 176 may extend laterally along a first horizontal direction hd1. In one embodiment, each pair of dielectric isolation structures 176 may extend laterally along the first horizontal direction hd1 and be laterally spaced apart from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0167] refer to FIG. 15A to FIG. 15C , contact via openings 89 may be formed within discrete regions 77 that do not contain a non-memory opening fill structure between a corresponding pair of dielectric isolation structures 176. Each of the contact via openings 89 may extend vertically through the insulating capping layer 70 and optionally through a corresponding subset of the sacrificial material layers 42 and optionally through a corresponding subset of the insulating layers 32, such that a top surface of a selected sacrificial material layer 42 is physically exposed at the bottom of each contact via opening 89. In one embodiment, the contact via openings 89 may have different depths from one another, and each sacrificial material layer 42 may be physically exposed to a corresponding overlying contact via opening 49.

[0168] The contact via openings 89 having different depths may be formed using a plurality of masked anisotropic etching processes, as described with respect to the first embodiment. Some of the contact via openings 89 may extend vertically through a corresponding subset of the sacrificial material layer 42. For each contact via opening 89, the nearest pair of dielectric isolation structures 176 are closer to the contact via opening 89 than the nearest pair of sacrificial backside trench filling structures 75 are to the contact via opening 89.

[0169] refer to FIG. 16A to FIG. 16C , a dielectric material (such as silicon oxide) may be conformally deposited in the contact via opening 89 and over the insulating cap layer 70 to form a conformal dielectric material layer. An anisotropic etching process may be performed to remove the horizontally extending portion of the conformal dielectric material layer. Each remaining tubular portion of the conformal dielectric material layer constitutes a tubular dielectric spacer 84. Each tubular dielectric spacer 84 is a dielectric contact via liner that contacts the sidewall of a corresponding one of the contact via openings 89. The tubular dielectric liner 84 may be formed at a peripheral portion of each contact via opening 89. A connecting via cavity 89' may be present within each unfilled volume of the contact via opening 89.

[0170] refer to FIG. 17A to FIG. 17C , an isotropic etching process may be performed to selectively etch the material of the sacrificial material layer 42 relative to the material of the insulating layer 32, the dielectric isolation structure 176, the tubular dielectric liner 84, and the insulating cap layer 70. For example, if the sacrificial material layer 42 includes silicon nitride, a wet etching process using hot phosphoric acid may be performed to remove a portion of the sacrificial material layer 42 that is close to the bottom surface of the contact through-hole cavity 89'. A laterally extending cavity 143 may be formed within each void formed by removing a portion of the sacrificial material layer 42. Generally speaking, an isotropic etching process that selectively etches the material of the sacrificial material layer 42 relative to the material of the dielectric isolation structure 176, the tubular dielectric liner 84, and the insulating cap layer 70 may be performed after forming the tubular dielectric liner 84. The dielectric isolation structure 176 may be used to limit the lateral extent of the laterally extending cavity 143 along the second horizontal direction hd2. Laterally extending cavities 143 may be formed below contact via cavities 89' such that sidewalls of a corresponding pair of dielectric barrier structures 176 are physically exposed around each laterally extending cavity 143. In one embodiment, at least one laterally extending cavity 143 may be formed at each level of sacrificial material layer 42.

[0171] refer to 18A to 18C, the sacrificial backside trench fill structure 75 can be selectively removed from the interior of the backside trench 79 relative to the material of the alternating stack (32, 42), the insulating cap layer 70, and the tubular dielectric liner 84. For example, if the sacrificial backside trench fill structure 75 includes a silicon material, a wet etching process (which uses hot trimethyl-2-hydroxyethylammonium hydroxide ("hot TMY") or tetramethylammonium hydroxide (TMAH)) can be used to remove the silicon material of the sacrificial backside trench fill structure 75. In this case, the sacrificial dielectric liner (not shown) can be used as an etch stop structure and can be removed later. Alternatively, the sacrificial backside trench fill structure 75 can be removed at this step in the process instead of at FIG. 12A to FIG. 12C Backside trenches 79 are formed by photolithography and etching through the alternating stack (32, 42) at the step shown in FIG.

[0172] Generally, the backside trench 79 may be formed through the alternating stack (32, 42) before or after forming the laterally extending cavity 143. An isotropic etching process may be performed to isotropically recess the sacrificial material layer 42 from around the backside trench 79. For example, an etchant that selectively etches the material of the sacrificial material layer 42 relative to the material of the outermost layers of the insulating layer 32, the insulating cap layer 70, the tubular dielectric liner 84, the semiconductor material layer 9, and the memory film 50 may be introduced into the backside trench 79, such as during the isotropic etching process. A backside recess 43 is formed in the volume from which the sacrificial material layer 42 is removed.

[0173] The isotropic etching process may include a wet etching process using a wet etching solution, and / or may include a vapor phase (dry) etching process in which the etchant is introduced into the backside trench 79 in the vapor phase. For example, if the sacrificial material layer 42 includes silicon nitride, the etching process may be a wet etching process in which the first exemplary structure is immersed in a wet etching bath including phosphoric acid, which etches silicon nitride in a manner selective to silicon oxide, silicon, and various other materials used in the art. The memory opening fill structure 58 provides structural support, and the backside recess 43 exists within the volume previously occupied by the sacrificial material layer 42.

[0174] The backside recesses 43 grow laterally from around the backside grooves 79 until the backside recesses 43 merge into a continuous backside recess 43 that extends continuously between adjacent pairs of backside grooves 79. In addition, the laterally extending cavities 143 extend laterally until each of the laterally extending cavities 143 merges with a corresponding backside recess 43. According to an aspect of the present disclosure, the duration of the isotropic etching process may be selected so that an unetched portion of the sacrificial material layer 42 remains between each adjacent pair of dielectric isolation structures 176. Generally speaking, the backside recesses 43 are formed in the volume from which the portion of the sacrificial material layer 42 is removed. Each laterally extending cavity 143 may be connected to at least one backside recess 43 to form a continuous void.

[0175] The remaining portion of the sacrificial material layer 42 after forming the backside recess 43 includes a dielectric material portion that laterally surrounds a corresponding contact via opening 89. Each remaining portion of the sacrificial material layer 42 is referred to herein as a dielectric material plate 142. Each dielectric material plate 142 that laterally surrounds the contact via cavity 89' includes an opening therethrough and overlies a corresponding laterally extending cavity 143. Each dielectric material plate 142 underlying the laterally extending cavity 143 may not have any openings therethrough. A vertical stack of dielectric material plates 142 may be formed between each adjacent pair of dielectric isolation structures 176. A dielectric material plate having a vertical stack of dielectric material plates 142 may be located at each level of the sacrificial material layer 42, as described in reference to FIG. FIG. 10A to FIG. 10C The process steps described are provided except that there is one level of laterally extending cavities 143 connected to the overlying contact via cavities 89'. Each backside recess 43 and each laterally extending cavity 143 may be vertically defined by the top surface of the underlying insulating layer 32 and the bottom surface of the overlying insulating layer 32 or insulating cap layer 70. In one embodiment, each backside recess 43 and each laterally extending cavity 143 may have a uniform height throughout.

[0176] Optionally, some of the memory opening filling structures extend through the dielectric material plate 142. Such memory opening filling structures may include dummy memory opening filling structures 58D that are not used to store data. Instead, they may serve as support pillars.

[0177] refer to FIG. 19A to FIG. 19C , at least one conductive material (such as a combination of a metal barrier liner material and a metal fill material) may be conformally deposited in the backside recess 43, the laterally extending cavity 143, and the contact via cavity 89' laterally surrounded by the tubular dielectric liner 84. The metal barrier liner material may include a conductive metal compound material such as TiN, TaN, WN, MoN, TiC, TaC, WC, their alloys, or combinations thereof. The metal fill material may include W, Ti, Ta, Mo, Co, Ru, Cu, their alloys, or combinations thereof. The total thickness of the at least one conductive material is greater than half the height of the backside recess 43 and the laterally extending cavity 143, and greater than half the width of the via cavity. Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the insulating cap layer 70 by performing a planarization process, which may include a recess etching process and / or a chemical mechanical polishing process.

[0178] Each remaining portion of the at least one conductive material filling the respective combination of the backside recess 43, the laterally extending cavity 143, and the contact via cavity 89' constitutes an integrated line and via structure (86, 46). Each integrated line and via structure (86, 46) may be formed in a continuous volume that includes the volume of the backside recess 43, the laterally extending cavity 143, and the contact via cavity 89' (which is the volume within the contact via opening 89). Each integrated line and via structure (86, 46) includes a conductive layer 46 and also includes a metal via portion 86 formed in a respective contact via opening 89. Portions of the conductive material deposited in the backside trench 79 or over the insulating cap layer 70 may be removed by performing an etch back process, which may include an isotropic etching process and / or an anisotropic etching process.

[0179] In general, at least one conductive material may be deposited in the volume of the backside recess 43, the laterally extending cavity 143, and the unfilled volume of the contact via opening 89. The portion of the conductive material deposited in the volume of the backside recess 43 and the laterally extending cavity 143 constitutes the conductive layer 46, and the portion of the conductive material filling the contact via opening 89 constitutes the metal via portion 86. In one embodiment, each integrated line and via structure (86, 46) includes a homogeneous metal material portion that extends continuously from the volume within the conductive layer 46 to the volume within the metal via portion 86 without material junctions therein. In one embodiment, each metal via portion 86 is laterally surrounded by a tubular dielectric liner 84, and each tubular dielectric liner 84 is laterally surrounded by each dielectric material plate 142 overlying the conductive layer 46 adjacent to the metal via portion 86.

[0180] Prior to depositing at least one conductive material, each backside recess 43 may be connected to a corresponding contact via cavity 89' by a corresponding laterally extending cavity 143. Thus, each adjacent combination of a backside recess 43, a laterally extending cavity 143, and a contact via cavity 89' may be filled with a corresponding integrated line and via structure (86, 46). In one embodiment, an annular bottom surface of the tubular dielectric liner 84 contacts an annular horizontal surface segment of a corresponding underlying conductive layer 46. The vertical stack of dielectric material plates 142 may be located at the level of a subset of the conductive layer 46 between each adjacent pair of dielectric isolation structures 176 spaced apart along the second horizontal direction hd2. The vertical stack of dielectric material plates 142 may contact each of the pair of dielectric isolation structures 176.

[0181] refer to FIG. 20A to FIG. 20C, an insulating material layer may be formed in the backside trenches 79 and over the insulating cap layer 70 by a conformal deposition process. Anisotropic etching is performed to remove horizontal portions of the insulating material layer from over the insulating cap layer 70 and at the bottom of each backside trench 79. Each remaining portion of the insulating material layer constitutes an insulating spacer 74. A backside cavity may exist within the volume enclosed by each insulating spacer 74. The top surface of the semiconductor material layer 9 may be physically exposed at the bottom of each backside trench 79.

[0182] A backside contact via structure 76 may be formed in each backside cavity. Each contact via structure 76 may fill a corresponding backside cavity. The backside contact via structure 76 may be formed by depositing at least one conductive material in the backside cavity. For example, the at least one conductive material may include a conductive liner and a conductive filling material portion. The conductive liner may include a conductive metal liner such as TiN, TaN, WN, TiC, TaC, WC, their alloys, or their stacks. The thickness of the conductive liner may be in the range of 3nm to 30nm, but smaller and larger thicknesses may also be used. The conductive filling material portion may include a metal or a metal alloy. For example, the conductive filling material portion may include W, Cu, Al, Co, Ru, Ni, their alloys, or their stacks. Excess portions of at least one conductive material may be removed from above a horizontal plane including the top surface of the insulating cap layer 70 by a planarization process. The planarization process may include a recessed etching process and / or a chemical mechanical polishing process. Each remaining portion of at least one conductive material constitutes a backside contact via structure 76. A pair of backside trench fill structures (74, 76) may laterally contact each alternating stack (32, 46) of insulating layer 32 and conductive layer 46. The pair of backside trench fill structures (74, 76) may be laterally spaced apart from each other by the alternating stacks (32, 46).

[0183] refer to Fig.20D , showing that in FIG. 20A to FIG. 20C An alternative embodiment of the second exemplary structure at the processing step of . An alternative embodiment of the second exemplary structure can be derived from the second exemplary structure by rearranging the position of the dielectric isolation structure 176. In one embodiment, the metal via portions 86 between an adjacent pair of backside trench filling structures (74, 76) can be arranged as multiple rows (e.g., two rows) of metal via portions 86 along the first horizontal direction hd1, rather than one row of metal via portions 86 in each memory block.

[0184] refer to 10A to 20DAnd according to various embodiments of the present disclosure, there is provided a semiconductor structure, the semiconductor structure comprising: an alternating stack (32, 46) of insulating layers 32 and conductive layers 46; a memory opening 49, the memory opening extending vertically through the alternating stack (32, 46); a memory opening filling structure 58, the memory opening filling structure being located in the memory opening 49 and comprising a corresponding vertical semiconductor channel 60 and a corresponding vertical stack of memory cells (such as a portion of a memory material layer 54); a pair of backside trench filling structures (74, 76), the pair of backside trench filling structures laterally contacting the alternating stack (32, 46) and extending through The alternating stacks (32, 46) are laterally spaced apart from each other; a pair of dielectric isolation structures 176 that extend vertically through the alternating stacks (32, 46); a vertical stack of dielectric material plates 142 that are located at the level of a subset of the conductive layers 46 and contact each of the pair of dielectric isolation structures 176; and an integrated line and via structure (86, 46) that is a unitary structure that includes a first conductive layer 46 of the conductive layers 46 and also includes a metal through-hole portion 86 that extends vertically through each of the dielectric material plates 142 that overly the first conductive layer 46.

[0185] In one embodiment, the integrated line and via structure (86, 46) includes a homogenous metallic material portion that extends continuously from a volume within the first conductive layer 46 to a volume within the metallic via portion 86 without material junctions therein.

[0186] In one embodiment, metal via portion 86 is laterally surrounded by tubular dielectric liner 84; and tubular dielectric liner 84 is laterally surrounded by each of dielectric material plates 142 overlying first conductive layer 46. In one embodiment, an annular bottom surface of tubular dielectric liner 84 contacts an annular horizontal surface segment of first conductive layer 46.

[0187] In one embodiment, each of the pair of dielectric isolation structures 176 is laterally spaced apart from the pair of backside trench fill structures (74, 76) and is in direct contact with each insulating layer 32 within the alternating stack (32, 46). In one embodiment, the interface between the alternating stack (32, 46) and the pair of dielectric isolation structures 176 extends laterally along a first horizontal direction hd1; and the pair of dielectric isolation structures 176 extends laterally along the first horizontal direction hd1 and is laterally spaced apart from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0188] In one embodiment, a subset of the memory opening filling structures 58 is located within a rectangular area RA having a lateral extent along a first horizontal direction hd1 that is the same as the lateral extent of the pair of dielectric isolation structures 176 along the first horizontal direction hd1, and the rectangular area having a lateral extent along a second horizontal direction hd2 that is the same as the lateral distance between the proximal dielectric isolation structure in the pair of dielectric isolation structures 176 and the proximal back-side trench filling structure in the pair of back-side trench filling structures (74, 76).

[0189] refer to Fig.21A and Fig.21B , showing a third exemplary structure according to the third embodiment of the present disclosure. Fig.21A and Fig.21B The third exemplary structure shown in FIG. 15A to FIG. 15C . Optionally, before forming the contact via opening 89, a dielectric capping layer 71 comprising a dielectric material may be formed over the insulating capping layer 70. In this case, the contact via opening 89 may be formed through the dielectric capping layer 71, the insulating capping layer 70, and (optionally) a respective subset of the insulating layer 32 and the sacrificial material layer 42. In an alternative embodiment, the backside trench 79 may be formed in a later processing step, which may be, for example, after forming the contact via opening 89.

[0190] refer to Fig.22A and Fig. 22B , a dielectric material (such as silicon oxide) may be conformally deposited in the contact via opening 89 and over the insulating cap layer 70 (and over the dielectric capping layer 71, if present) to form a conformal dielectric material layer. An anisotropic etching process may be performed to remove horizontally extending portions of the conformal dielectric material layer. Each remaining tubular portion of the conformal dielectric material layer constitutes a tubular dielectric spacer 84. Each tubular dielectric spacer 84 is a dielectric contact via liner that contacts the sidewall of a corresponding one of the contact via openings 89. The tubular dielectric liner 84 may be formed at a peripheral portion of each contact via opening 89. A contact via cavity 89' may be disposed within each volume laterally enclosed by the tubular dielectric spacer 84.

[0191] refer to Fig.23A and Fig. 23B, a photoresist layer 91 may be applied over the third exemplary structure and may be photolithographically patterned to form at least one opening 93 overlying a corresponding one of the contact via openings 89 while masking the remaining portion of the contact via opening 89. In the illustrated example, the central contact via opening 89 is underlying the opening 93 in the photoresist layer, and the two peripheral contact via openings 89 may be covered by the photoresist layer. When performing the first anisotropic etching process, the unmasked portion of the sacrificial material layer 42 under each contact via opening 89 that is not masked by the photoresist layer may be removed. For example, an anisotropic etching process may be performed that selectively etches the material of the sacrificial material layer 42 relative to the material of the insulating layer 32 and the dielectric capping layer 71. At least one contact via opening 89 may be vertically extended by the first selective etching process. The top surface of the insulating layer 32 may be physically exposed under each vertically extending contact via opening 89. Generally, one or more of the contact via openings 89 may extend vertically through the respective sacrificial material layer 42 such that the top surface of the underlying insulating layer 32 is physically exposed. After the anisotropic etching step, the photoresist layer 91 may be removed by ashing or selective etching.

[0192] refer to Fig.24A and Fig. 24B , a sacrificial material different from the material of the tubular dielectric liner 84 and the insulating layer 32 can be conformally deposited in the contact via cavity 89' and above the insulating cap layer 70 (and above the dielectric capping layer 71, if present) to form a conformal sacrificial material layer. An anisotropic etching process can be performed to remove the horizontally extending portions of the conformal sacrificial material layer. Each remaining tubular portion of the conformal sacrificial material layer constitutes a tubular sacrificial spacer. Each tubular sacrificial spacer is a sacrificial contact via liner that contacts the sidewall of a corresponding one of the tubular dielectric spacers 84. Each tubular sacrificial spacer 85A formed within the vertically extending contact via cavity 89' contacts the cylindrical sidewall of the corresponding sacrificial material layer 42 and the top surface segment of the underlying insulating layer 32. In reference to Fig.23A and Fig. 23B Each tubular sacrificial spacer 85B formed within a non-vertically extending contact via cavity 89' in the described processing steps may be formed directly on an annular top surface segment of a corresponding sacrificial material layer 42. In one embodiment, the tubular sacrificial spacers 85A and 85B may include silicon nitride or a dielectric metal oxide.

[0193] refer to Fig.25A and Fig.25B , a selective isotropic etching process may be performed to isotropically recess the unmasked portion of each insulating layer 32 underlying the corresponding tubular sacrificial spacer 85A. The duration of the isotropic etching process may be selected so that the isotropic etching process is not masked. Fig.24A and Fig. 24B In the processing steps described, a laterally extending cavity is formed below each tubular sacrificial spacer 85A, which is formed directly on an annular top surface segment of the corresponding insulating layer 32. Each laterally extending cavity is formed at the level of the corresponding insulating layer 32 by isotropically etching the corresponding insulating layer 32. Fig.25A and Fig.25B Each laterally extending cavity formed in the described processing steps is referred to herein as an insulating layer level laterally extending cavity 133. During the selective isotropic etching process, the sacrificial material layer 42 underlying the corresponding tubular sacrificial spacer 85B is not etched through.

[0194] The bottom surface of the overlying sacrificial material layer 42 and the top surface of the underlying sacrificial material layer 42 may be physically exposed to each insulating layer level laterally extending cavity 133. Each insulating layer level laterally extending cavity 133 may have a lateral extent greater than the maximum lateral extent of the overlying tubular dielectric liner 84. In one embodiment, the sidewalls of a corresponding pair of dielectric barrier structures 176 may be physically exposed to each insulating layer level laterally extending cavity 133. In one embodiment, each insulating layer level laterally extending cavity 133 may have a lateral extent along the second horizontal direction hd2 that is the same as the lateral separation distance between an adjacent pair of dielectric barrier structures 176. The lateral extent of each insulating layer level laterally extending cavity 133 along the first horizontal direction hd1 may be greater than the lateral extent of the corresponding insulating layer level laterally extending cavity 133 along the second horizontal direction hd2.

[0195] refer to Fig.26A and Fig.26B , an isotropic etching process may be performed to isotropically recess the material of the sacrificial material layer around each insulating layer level laterally extending cavity 133 and below each contact via cavity 89' around which the tubular dielectric liner 84 and tubular sacrificial liner 85B are in direct contact with the corresponding underlying sacrificial material layer 42. The isotropic etching process causes each insulating layer level laterally extending cavity 133 to vertically extend through the corresponding overlying sacrificial material layer 42 and through the corresponding underlying sacrificial material layer 42 to provide a cavity extending vertically above the levels of the insulating layer 32 and the two sacrificial material layers 42. Each vertically extended cavity is referred to herein as a multi-level laterally extending cavity 233.

[0196] In addition, in reference Fig.25A and Fig.25B After the processing steps described and in Fig.26A and Fig.26BPrior to the processing step of , a laterally extending cavity 143 may be formed below each contact via cavity 89', around which tubular dielectric liner 84 and tubular sacrificial liner 85B are in direct contact with the corresponding underlying sacrificial material layer 42. Each laterally extending cavity 143 only vertically extends through a single level (i.e., the level of the corresponding sacrificial material layer 42), and is therefore referred to herein as a single-level laterally extending cavity.

[0197] In one embodiment, tubular sacrificial liners 85A and 85B may be incidentally removed during an isotropic etching process that isotropically recesses the material of sacrificial material layer 42. In an illustrative example, sacrificial material layer 42 and tubular sacrificial liners (85A, 85B) may include silicon nitride, and the isotropic etching process may include a wet etching process using hot phosphoric acid. Generally speaking, each multi-level laterally-extended cavity 233 may be formed by isotropically etching a first sacrificial material layer 42 overlying insulating layer-level laterally-extended cavity 133 and by isotropically etching a second sacrificial material layer 42 overlying insulating layer-level laterally-extended cavity 133.

[0198] refer to Fig.27A and Fig.27B , the sacrificial backside trench fill structure 75 can be selectively removed from the interior of the backside trench 79 relative to the material of the alternating stack (32, 42), the insulating cap layer 70, and the tubular dielectric liner 84. For example, if the sacrificial backside trench fill structure 75 includes a semiconductor material, a wet etching process (which uses hot trimethyl-2-hydroxyethylammonium hydroxide ("hot TMY") or tetramethylammonium hydroxide (TMAH)) can be used to remove the semiconductor material of the sacrificial backside trench fill structure 75. In this case, the sacrificial dielectric liner (not shown) can be used as an etch stop structure and can be removed later. Alternatively, the sacrificial backside trench fill structure 75 can be removed at this step in the process instead of at FIG. 12A to FIG. 12C Backside trenches 79 are formed by photolithography and etching through the alternating stack (32, 42) at the step shown in FIG.

[0199] Generally, the backside trench 79 may be formed through the alternating stack (32, 42) before or after forming at least one multi-level laterally extending cavity 233 and the single-level laterally extending cavity 143. An isotropic etching process may be performed to isotropically recess the sacrificial material layer 42 from around the backside trench 79. For example, an etchant that selectively etches the material of the sacrificial material layer 42 relative to the material of the outermost layers of the insulating layer 32, the insulating cap layer 70, the tubular dielectric liner 84, the semiconductor material layer 9, and the memory film 50 may be introduced into the backside trench 79, such as during the isotropic etching process. A backside recess 43 is formed in the volume from which the sacrificial material layer 42 is removed.

[0200] The isotropic etching process may include a wet etching process using a wet etching solution, and / or may include a vapor phase (dry) etching process in which the etchant is introduced into the backside trench 79 in the vapor phase. For example, if the sacrificial material layer 42 includes silicon nitride, the etching process may be a wet etching process in which the first exemplary structure is immersed in a wet etching bath including phosphoric acid, which etches silicon nitride in a manner selective to silicon oxide, silicon, and various other materials used in the art. The memory opening fill structure 58 provides structural support, and the backside recess 43 exists within the volume previously occupied by the sacrificial material layer 42.

[0201] The backside recessed portion 43 grows from around the backside groove 79 until the backside recessed portion 43 merges into a continuous backside recessed portion 43 that extends continuously between adjacent pairs of backside grooves 79. Each multi-level laterally extending cavity 233 extends laterally until each multi-level laterally extending cavity 233 merges with a corresponding group of backside recessed portions 43. In addition, the single-level laterally extending cavity 143 extends laterally until each single-level laterally extending cavity in the single-level laterally extending cavity 143 merges with the corresponding backside recessed portion 43. According to an aspect of the present disclosure, the duration of the isotropic etching process can be selected so that the unetched portion of the sacrificial material layer 42 remains between each adjacent pair of dielectric isolation structures 176. Generally speaking, the backside recessed portion 43 is formed in the volume from which the portion of the sacrificial material layer 42 is removed. Each multi-level laterally extending cavity 233 can be connected to at least two backside recessed portions 43 to form a continuous gap. Each single-level laterally-extending cavity 143 may be connected to at least one backside recess 43 grown from a corresponding backside groove 79 to form a continuous void.

[0202] The remaining portion of the sacrificial material layer 42 after forming the backside recess 43 includes a dielectric material portion that laterally surrounds the corresponding contact via opening 89. Each remaining portion of the sacrificial material layer 42 is referred to herein as a dielectric material plate 142. Each dielectric material plate 142 that laterally surrounds the contact via cavity 89' includes an opening therethrough and overlies the multi-level laterally extending cavity 233 or the backside recess 43. Each dielectric material plate 142 underlying the multi-level laterally extending cavity 233 or the backside recess 43 may not have any openings therethrough. A vertical stack of dielectric material plates 142 may be formed between each adjacent pair of dielectric isolation structures 176. A dielectric material plate 142 may be located at each level of the sacrificial material layer 42, as shown in reference to FIG. FIG. 10A to FIG. 10C The process steps described are provided except at the level where there is a multi-level laterally extending cavity 233 connected to the overlying contact via cavity 89'. Each backside recess 43 can be vertically defined by the top surface of the underlying insulating layer 32 and the bottom surface of the overlying insulating layer 32 or insulating capping layer 70. In one embodiment, each backside recess 43 can have a uniform height throughout.

[0203] refer to Fig.28A and Fig.28B , at least one conductive material (such as a combination of a metal barrier liner material and a metal fill material) may be conformally deposited in the backside recess 43, in each multi-level laterally extending cavity 233, and in the contact via cavity 89' laterally surrounded by the tubular dielectric liner 84. The metal barrier liner material may include a conductive metal compound material such as TiN, TaN, WN, MoN, TiC, TaC, WC, their alloys, or combinations thereof. The metal fill material may include W, Ti, Ta, Mo, Co, Ru, Cu, their alloys, or combinations thereof. The total thickness of the at least one conductive material is greater than half the height of the backside recess 43 and greater than half the width of the via cavity. Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the insulating cap layer 70 by performing a planarization process, which may include a recess etching process and / or a chemical mechanical polishing process.

[0204] Each remaining portion of the at least one conductive material filling the corresponding combination of a pair of backside recesses 43, multi-level laterally extending cavities 233, and contact via cavities 89' constitutes a first integrated line and via structure (86, 461, 462, 148). Each first integrated line and via structure (86, 461, 462, 148) can be formed in a continuous volume that includes the volume of two backside recesses 43, multi-level laterally extending cavities 233, and contact via cavities 89' (which is the volume within the contact via opening 89). Each first integrated line and via structure (86, 461, 462, 148) includes a first conductive layer 461, a second conductive layer 462, a metal plate portion 148 adjacent to the first conductive layer 461 and the second conductive layer 462 (i.e., vertically positioned between and contacting the first conductive layer and the second conductive layer), and a metal via portion 86 formed in a corresponding contact via opening 89 contacting the first conductive layer 461. The conductive layer 46 includes a first conductive layer 461 filling a volume from which the first sacrificial material layer 42 was removed and a second conductive layer 462 filling a volume from which the second sacrificial material layer 42 was removed. The metal plate portion 148 fills the volume of the multi-level laterally extending cavity 233 and vertically connects the first conductive layer 461 and the second conductive layer 462. First conductive layer 461 , second conductive layer 462 , and metal plate portion 148 are part of an integrated line and via structure ( 86 , 461 , 462 , 148 ) that is a unitary structure and also includes metal via portion 86 .

[0205] The metal plate portion 148 includes a sidewall that contacts a sidewall of one of the insulating layers 32. A vertical interface INT between the metal plate portion 148 and one of the insulating layers 32 is laterally offset from the bottom periphery of the metal via portion 86 by a uniform lateral offset distance. The metal via portion 86 is laterally surrounded by the tubular dielectric liner 84, and the tubular dielectric liner 84 is laterally surrounded by each of the dielectric material plates 142 overlying the first conductive layer 461. The annular bottom surface of the tubular dielectric liner 84 contacts an annular horizontal surface segment of the first conductive layer 461.

[0206] The first conductive layer 461 and the second conductive layer 462 of the integrated line and via structure (86, 461, 462, 148) may act as a select gate electrode or as a dummy word line. For example, the first conductive layer 461 and the second conductive layer 462 may include an electrically connected drain side select gate electrode or a source side select gate electrode. Alternatively, the first conductive layer 461 and the second conductive layer 462 may include a dummy word line located below the drain side select gate electrode. The dummy word line facilitates electron conduction through the vertical semiconductor channel 60 during operation of the NAND string, but is not used to write, erase, or read data from adjacent memory cells.

[0207] Each remaining portion of the at least one conductive material filling the respective combination of the backside recess 43 and the contact via cavity 89' constitutes a second integrated line and via structure (86, 46). Each second integrated line and via structure (86, 46) may be formed in a continuous volume that includes the backside recess 43 and the volume of the contact via cavity 89' (which is the volume within the contact via opening 89). Each second integrated line and via structure (86, 46) includes a conductive layer 46 and also includes a metal via portion 86 formed in the respective contact via opening 89. In one embodiment, the conductive layer 46 of the second integrated line and via structure (86, 46) may serve as a word line. The portion of the conductive material deposited in the backside trench 79 or above the insulating cap layer 70 may be removed by performing an etch back process, which may include an isotropic etching process and / or an anisotropic etching process.

[0208] In general, at least one conductive material may be deposited in the volume of the backside recess 43 and the unfilled volume of the contact via opening 89. The portion of the conductive material deposited in the volume of the backside recess 43 and the laterally extending cavity 143 constitutes the conductive layer 46, and the portion of the conductive material filling the contact via opening 89 constitutes the metal via portion 86. In one embodiment, each first integrated line and via structure (86, 461, 462, 148) includes a homogeneous metal material portion that extends continuously from a volume within the first conductive layer 46, through a volume of the metal plate portion 148, through a volume of the second conductive layer 462, and to a volume within the metal via portion 86 without a material junction therein. Each second integrated line and via structure (86, 46) includes a homogeneous metal material portion that extends continuously from a volume within the conductive layer 46 to a volume within the metal via portion 86 without a material junction therein. In one embodiment, each metal via portion 86 is laterally surrounded by a tubular dielectric liner 84 , and each tubular dielectric liner 84 is laterally surrounded by each dielectric material plate 142 overlying the conductive layer 46 adjacent to the metal via portion 86 .

[0209] Prior to depositing at least one conductive material, each backside recess 43 may be connected to a corresponding contact via cavity 89'. Thus, each adjoining combination of a backside recess 43 and a contact via cavity 89' may be filled with a corresponding integrated line and via structure [(86, 461, 462, 148) or (86, 46)}. In one embodiment, an annular bottom surface of the tubular dielectric liner 84 contacts an annular horizontal surface segment of a corresponding underlying conductive layer 46. The vertical stack of dielectric material plates 142 may be located at the level of a subset of the conductive layer 46 between each adjacent pair of dielectric isolation structures 176 spaced apart along the second horizontal direction hd2. The vertical stack of dielectric material plates 142 may contact each of the pair of dielectric isolation structures 176.

[0210] In one embodiment, the surface segment within the vertically extending interface INT between the metal plate portion 148 and the insulating layer 32 has a corresponding radius of curvature Rc that is the same as the radial distance between the vertical axis passing through the geometric center of the metal via portion 86 in a plan view and the vertically extending interface INT.

[0211] refer to Fig.29A and Fig.29B, an insulating material layer may be formed in the backside trenches 79 and over the insulating cap layer 70 by a conformal deposition process. Anisotropic etching is performed to remove horizontal portions of the insulating material layer from over the insulating cap layer 70 and at the bottom of each backside trench 79. Each remaining portion of the insulating material layer constitutes an insulating spacer 74. A backside cavity may exist within the volume enclosed by each insulating spacer 74. The top surface of the semiconductor material layer 9 may be physically exposed at the bottom of each backside trench 79.

[0212] A backside contact via structure 76 may be formed in each backside cavity. Each contact via structure 76 may fill a corresponding backside cavity. The backside contact via structure 76 may be formed by depositing at least one conductive material in the backside cavity. For example, the at least one conductive material may include a conductive liner and a conductive filling material portion. The conductive liner may include a conductive metal liner such as TiN, TaN, WN, TiC, TaC, WC, their alloys, or their stacks. The thickness of the conductive liner may be in the range of 3nm to 30nm, but smaller and larger thicknesses may also be used. The conductive filling material portion may include a metal or a metal alloy. For example, the conductive filling material portion may include W, Cu, Al, Co, Ru, Ni, their alloys, or their stacks. Excess portions of at least one conductive material may be removed from above a horizontal plane including the top surface of the insulating cap layer 70 by a planarization process. The planarization process may include a recessed etching process and / or a chemical mechanical polishing process. Each remaining portion of at least one conductive material constitutes a backside contact via structure 76. A pair of backside trench fill structures (74, 76) may laterally contact each alternating stack (32, 46) of insulating layer 32 and conductive layer 46. The pair of backside trench fill structures (74, 76) may be laterally spaced apart from each other by the alternating stacks (32, 46).

[0213] refer to Fig. 30A and Fig. 30B , showing a fourth exemplary structure according to the fourth embodiment of the present disclosure. Fig. 30A and Fig. 30B The fourth exemplary structure shown in Fig.21A and Fig. 21B The same as the third exemplary structure shown in .

[0214] refer to Fig.31A and Fig.31B, a dielectric material different from the material of the insulating layer 32 and the sacrificial material layer 42 may be conformally deposited in the contact via opening 89 and over the insulating cap layer 70 (and over the dielectric capping layer 71, if present) to form a conformal dielectric material layer. An anisotropic etching process may be performed to remove horizontally extending portions of the conformal dielectric material layer. Each remaining tubular portion of the conformal dielectric material layer constitutes a tubular dielectric spacer 184. Each tubular dielectric spacer 184 is a dielectric contact via liner that contacts the sidewall of a corresponding one of the contact via openings 89. In one embodiment, the tubular dielectric spacer 184 may include a dielectric metal oxide material, such as aluminum oxide, hafnium oxide, tantalum oxide, lanthanum oxide, yttrium oxide, etc. The thickness of the tubular dielectric spacer 184 may be in the range of 5 nm to 100 nm, such as 10 nm to 50 nm, but smaller and larger thicknesses may also be used. A tubular dielectric liner 184 may be formed at a peripheral portion of each contact via opening 89. A contact via cavity 89' may be disposed within each volume laterally enclosed by the tubular dielectric spacer 184.

[0215] refer to Fig.32A and Fig.32B , executable reference Fig.23A and Fig. 23B The processing steps are described to cause at least one contact via cavity 89' to extend vertically through a respective sacrificial material layer 42. A top surface segment of the insulating layer 32 may be physically exposed beneath each vertically extending contact via cavity 89'.

[0216] refer to Fig.33A and Fig.33B , executable reference Fig.25A and Fig.25B The processing steps are described to form at least one insulating layer level laterally extending cavity 133. Each insulating layer level laterally extending cavity 133 may be formed below a corresponding vertically extending contact via cavity 89'.

[0217] refer to Fig.34A and Fig.34B , executable reference Fig.26A and Fig.26B The processing steps are described to cause the material of the sacrificial material layer to be isotropically recessed around each insulating layer level laterally extending cavity 133 and below each contact via cavity 89' around which the tubular dielectric liner 184 is in direct contact with the corresponding underlying sacrificial material layer 42. The isotropic etching process causes each insulating layer level laterally extending cavity 133 to be vertically extended through the corresponding overlying sacrificial material layer 42 and through the corresponding underlying sacrificial material layer 42 to provide a cavity extending vertically above the insulating layer 32 and the levels of the two sacrificial material layers 42. Each vertically extended cavity is referred to herein as a multi-level laterally extending cavity 233.

[0218] In addition, in reference Fig.33A and Fig.33B After the processing steps described and in Fig.34A and Fig.34B Prior to the processing step of , a laterally extending cavity 133 may be formed below each contact via cavity 89', with a tubular dielectric liner 184 surrounding the laterally extending cavity in direct contact with the corresponding underlying sacrificial material layer 42. Each laterally extending cavity 143 only vertically extends through a single level (i.e., the level of the corresponding sacrificial material layer 42), and is therefore referred to herein as a single-level laterally extending cavity. In general, each multi-level laterally extending cavity 233 may be formed by isotropically etching a first sacrificial material layer 42 overlying the insulating layer-level lateral extending cavity 133 and by isotropically etching a second sacrificial material layer 42 overlying the insulating layer-level lateral extending cavity 133.

[0219] refer to Fig.35A and Fig.35B , executable reference Fig.27A and Fig.27B Processing steps are described to selectively remove sacrificial backside trench fill structure 75 from inside backside trench 79 relative to the material of alternating stack (32, 42), insulating cap layer 70, and tubular dielectric liner 184. Backside recess 43 is formed in the volume from which sacrificial material layer 42 was removed.

[0220] refer to Fig.36A and Fig.36B , executable reference Fig.28A and Fig.28B Processing steps are described to form a first integrated line and via structure (86, 461, 462, 148) and a second integrated line and via structure (86, 46).

[0221] refer to Fig.37A and Fig.37B , executable Fig.29A and Fig.29B The processing steps are performed to form a backside trench fill structure (74, 76).

[0222] In the third embodiment, the number of metal via portions 86 can be reduced, which also reduces the number of corresponding driver switch transistors that control the metal via portions 86. Therefore, electrical connection wiring complexity and spacing can be reduced.

[0223] refer to Figure 1 , FIG. 10A to FIG. 14C as well as FIG. 21A to FIG. 37BAnd according to a third embodiment of the present disclosure, there is provided a semiconductor structure, the semiconductor structure comprising: an alternating stack (32, 46) of insulating layers 32 and conductive layers 46; a memory opening 49 extending vertically through the alternating stack (32, 46); a memory opening filling structure 58 located in the memory opening 49 and comprising a corresponding vertical semiconductor channel 60 and a corresponding vertical stack of memory cells (such as portions of the memory material layer 54); a dielectric material plate 14 2, the vertical stack being located at the level of a subset of the conductive layers 46; and an integrated line and via structure (86, 461, 462, 148), which is an integral structure including a first conductive layer 461 and a second conductive layer 462 in the conductive layer 46, a metal plate portion 148 vertically connecting the first conductive layer 461 and the second conductive layer 462, and a metal through-hole portion 86 vertically extending through each dielectric material plate in the dielectric material plate 142 overlying the first conductive layer 461.

[0224] In one embodiment, the semiconductor structure includes a pair of backside trench fill structures (74, 76) that laterally contact the alternating stacks (32, 46) and are laterally spaced apart from each other by the alternating stacks (32, 46). In one embodiment, each of the pair of backside trench fill structures (74, 76) includes a dielectric trench fill material portion (such as an insulating spacer 74) that contacts a respective sidewall of the alternating stacks (32, 46).

[0225] In one embodiment, the semiconductor structure includes a pair of dielectric barrier structures 176 extending vertically through the alternating stack (32, 46) and laterally spaced apart from the pair of backside trench fill structures (74, 76). In one embodiment, the vertical stack of dielectric material plates 142 is in direct contact with each of the pair of dielectric barrier structures 176. The pair of dielectric barrier structures 176 are laterally spaced apart from each other by the vertical alternating sequence of insulating layers 32 and dielectric material plates 142.

[0226] In one embodiment, metal plate portion 148 includes sidewalls that contact sidewalls of one of insulating layers 32. In one embodiment, vertical interface INT between metal plate portion 148 and one of insulating layers 32 is laterally offset from a bottom periphery of metal via portion 86 by a uniform lateral offset distance.

[0227] In one embodiment, the integrated line and via structure (86, 461, 462, 148) includes a homogenous metal material portion that extends continuously through the first conductive layer 461, the metal plate portion 148, the second conductive layer 462, and the metal via portion 86 without material junctions therein. In one embodiment, the metal via portion 86 is laterally surrounded by a tubular dielectric liner (84, 184); and the tubular dielectric liner (84, 184) is laterally surrounded by each of the dielectric material plates 142 overlying the first conductive layer 461. In one embodiment, the annular bottom surface of the tubular dielectric liner (84, 184) contacts an annular horizontal surface segment of the first conductive layer 461.

[0228] In one embodiment, each of the pair of dielectric isolation structures 176 is laterally spaced apart from the pair of backside trench fill structures ( 74 , 76 ) and is in direct contact with each insulating layer 32 within the alternating stack ( 32 , 46 ).

[0229] In one embodiment, the interface between the alternating stack (32, 46) and the dielectric isolation structure 176 extends laterally along a first horizontal direction hd1; and the dielectric isolation structure 176 extends laterally along the first horizontal direction hd1 and is laterally spaced apart from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0230] In one embodiment, a subset of the memory opening filling structures 58 is located within a rectangular area RA having a lateral extent along a first horizontal direction hd1 that is the same as the lateral extent of the pair of dielectric isolation structures 176 along the first horizontal direction hd1, and the rectangular area having a lateral extent along a second horizontal direction hd2 that is the same as the lateral distance between the proximal dielectric isolation structure in the pair of dielectric isolation structures 176 and the proximal back-side trench filling structure in the pair of back-side trench filling structures (74, 76).

[0231] Various embodiments of the present disclosure may be employed to provide an integrated contact via structure including at least one conductive layer 46 and a metal via portion 86. The metal via portion 86 may be electrically isolated from the surrounding conductive layer 46 by a combination of a tubular dielectric liner (84, 184), a dielectric material plate 142, and optionally by a pair of dielectric isolation structures 176. Electrical contact may be provided to the conductive layer 46 without forming any stepped surfaces or staircase areas. In some embodiments, no support post structure formation is required, which simplifies the process. By omitting the post structure in the region of the contact via opening 89, the etching of the contact via opening 89 is simplified, and pits that may cause short circuits between vertically separated word lines may be avoided or reduced in the contact via opening 89. Finally, in the first embodiment, the backside trench may be omitted to further simplify the process.

[0232] Although specific preferred embodiments are mentioned above, it will be understood that the claims are not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the claims. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments using specific structures and / or configurations are shown in the present disclosure, and it should be understood that the claims may be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not expressly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A semiconductor structure, comprising: an alternating stack of insulating layers and composite layers, wherein each of the composite layers comprises a respective set of conductive layers, the respective set of conductive layers being laterally spaced apart by a respective set of dielectric material portions; a memory opening extending vertically through the alternatingly stacked portions and laterally spaced apart from each of the dielectric material portions; a memory opening filling structure located in the memory opening, wherein a vertically extending interface between the conductive layer and the dielectric material portion is laterally offset from a sidewall of a nearest one of the memory opening filling structures, and wherein each of the memory opening filling structures includes a respective vertical semiconductor channel and a respective vertical stack of memory cells; and An integrated line and via structure includes a metal plate portion laterally contacting a first one of the conductive layers and also includes a metal via portion extending vertically through a subset of the dielectric material portions overlying the metal plate portion.

2. The semiconductor structure according to claim 1, wherein: The metal via portion also extends vertically through a subset of the insulating layer overlying the metal plate portion; The reservoir opening has a corresponding circular horizontal cross-sectional shape; and Surface segments within the vertically extending interface between the conductive layer and the dielectric material portion have respective radii of curvature that are the same as radial distances from a vertical axis that passes through a geometric center of a proximal one of the memory openings in plan view. 3 . The semiconductor structure of claim 2 , wherein a surface segment within a vertically extending interface between the metal plate portion and the first conductive layer has a corresponding radius of curvature that is the same as the radial distance in the plan view.

4. The semiconductor structure of claim 1 , wherein the integrated line and via structure comprises a homogenous metal material portion extending continuously from a volume within the metal plate portion to a volume within the metal via portion without material junctions therein.

5. The semiconductor structure of claim 1, wherein: The metal via portion is laterally surrounded by a tubular dielectric liner; said tubular dielectric liner being laterally surrounded by each dielectric material portion within said subset of said dielectric material portions overlying said metal plate portion; and The annular bottom surface of the tubular dielectric liner contacts the annular horizontal surface segment of the metal plate portion.

6. The semiconductor structure of claim 1 , wherein the metal plate portion comprises: a first horizontal surface that contacts a horizontal bottom surface of an overlying insulating layer in the insulating layer; a second horizontal surface contacting a horizontal top surface of an underlying one of the insulating layers; a laterally undulating vertical surface, the laterally undulating vertical surface contacting the first conductive layer; and A pair of laterally raised and vertically straight surfaces, the pair of laterally raised and vertically straight surfaces contacting respective dielectric material portions.

7. The semiconductor structure of claim 1, wherein: At least one topmost one of the conductive layers includes a drain side select gate electrode, at least one bottommost one of the conductive layers includes a source side select gate electrode, and the conductive layers between the drain side select gate electrode and the source side select gate electrode include a word line; the set of dielectric material portions comprising a plate of dielectric material, a discrete plate of dielectric material, a first strip of dielectric material extending generally laterally along a wordline direction and laterally separating a first laterally adjacent pair of the wordlines in adjacent memory blocks, a second strip of dielectric material extending generally laterally along the wordline direction and laterally separating, together with the plate of dielectric material, a second laterally adjacent pair of the wordlines in the same memory block, and a dielectric isolation rail extending generally laterally along a bitline direction and laterally separating adjacent memory blocks along the bitline direction; laterally adjacent pairs of said discrete dielectric material plates are laterally separated along said bitline direction by respective ones of said second dielectric material strips; and The metal via portion includes: a wordline contact via portion extending vertically through the subset of the dielectric material plate and contacting a respective one of the wordlines; and a select gate electrode contact via portion extending vertically through the subset of the discrete dielectric material plates and contacting a respective one of the drain side select gate electrodes.

8. A semiconductor structure, comprising: Alternating stacking of insulating and conducting layers; a reservoir opening extending vertically through the alternating stacks; a memory opening filling structure located in the memory opening and comprising a respective vertical semiconductor channel and a respective vertical stack of memory cells; a pair of backside trench-fill structures laterally contacting the alternating stacks and laterally spaced apart from each other by the alternating stacks; a pair of dielectric isolator structures extending vertically through the alternating stack; a vertical stack of plates of dielectric material located at the level of a subset of the conductive layers and contacting each of the pair of dielectric isolator structures; and An integrated line and via structure is a unitary structure including a first one of the conductive layers and also including a metal via portion extending vertically through each of the dielectric material plates overlying the first conductive layer.

9. The semiconductor structure of claim 8, wherein the integrated line and via structure comprises a homogeneous metal material portion extending continuously from a volume within the first conductive layer to a volume within the metal via portion without material junctions therein.

10. The semiconductor structure of claim 8, wherein: The metal via portion is laterally surrounded by a tubular dielectric liner; and The tubular dielectric liner is laterally surrounded by each of the plates of dielectric material overlying the first conductive layer.

11. The semiconductor structure of claim 10, wherein an annular bottom surface of the tubular dielectric liner contacts an annular horizontal surface segment of the first conductive layer.

12. The semiconductor structure of claim 8, wherein each dielectric barrier structure of the pair of dielectric barrier structures is laterally spaced apart from the pair of backside trench fill structures and is in direct contact with each insulating layer within the alternating stack.

13. The semiconductor structure of claim 12, wherein: An interface between the alternating stacks and the pair of dielectric barrier structures extends laterally along a first horizontal direction; and The pair of dielectric isolation structures extend laterally along the first horizontal direction and are laterally spaced apart from each other along a second horizontal direction perpendicular to the first horizontal direction.

14. The semiconductor structure of claim 8, wherein the subset of memory opening filling structures is located within a rectangular area, the rectangular area having a lateral extent along a first horizontal direction, the lateral extent being the same as the lateral extent of the pair of dielectric isolation structures along the first horizontal direction, and the rectangular area having a lateral extent along a second horizontal direction, the lateral extent being the same as the lateral distance between a proximal one of the pair of dielectric isolation structures and a proximal one of the pair of backside trench filling structures.

15. A method of forming a semiconductor structure, the method comprising: forming an alternating stack of insulating layers including dielectric material and layers of sacrificial material; forming a memory opening through the alternating stack; replacing a proximal portion of the sacrificial material layer surrounding each of the memory openings with a conductive layer, wherein each of the conductive layers includes a respective set of conductive material portions and contacts a remaining portion of a respective sacrificial material layer constituting a dielectric material portion; forming via openings extending vertically through a subset of the dielectric material portions; forming a laterally extending cavity below the via opening such that a sidewall of a first one of the conductive layers is physically exposed; as well as An integrated line and via structure is formed in a continuous volume including the laterally extending cavity and the volume within the via opening, wherein the integrated line and via structure includes a metal plate portion laterally contacting the first conductive layer and also includes a metal via portion formed in the via opening.

16. The method of claim 15, further comprising forming memory opening filling structures in the memory openings, wherein each of the memory opening filling structures comprises a respective vertical semiconductor channel and a respective vertical stack of memory cells. 17 . The method of claim 16 , wherein when forming the memory opening filling structures, the conductive layer laterally surrounds a corresponding plurality of memory opening filling structures.

18. The method of claim 15, wherein the integrated line and via structure comprises a homogenous metal material portion extending continuously from a volume within the metal plate portion to a volume within the metal via portion without material junctions therein.

19. The method of claim 15, further comprising forming a tubular dielectric liner at a peripheral portion of the via opening prior to forming the laterally extending cavity, wherein the metal via portion is formed on an inner sidewall of the tubular dielectric liner.

20. The method of claim 19, wherein the laterally-extending cavity is formed by performing an isotropic etching process that selectively etches material of the dielectric material portion relative to material of the conductive layer and the tubular dielectric liner.

21. A semiconductor structure, comprising: Alternating stacking of insulating and conducting layers; a reservoir opening extending vertically through the alternating stacks; a memory opening filling structure located in the memory opening and comprising a respective vertical semiconductor channel and a respective vertical stack of memory cells; a vertical stack of plates of dielectric material, said vertical stack being located at the level of a subset of said conductive layers; and An integrated line and via structure is an integral structure comprising a first conductive layer and a second conductive layer in the conductive layer, a metal plate portion vertically connecting the first conductive layer and the second conductive layer, and a metal through-hole portion vertically extending through each dielectric material plate in the dielectric material plates overlying the first conductive layer.

22. The semiconductor structure of claim 21, further comprising a pair of backside trench fill structures laterally contacting the alternating stacks and laterally spaced apart from each other by the alternating stacks.

23. The semiconductor structure of claim 22, wherein each backside trench fill structure of the pair of backside trench fill structures includes a dielectric trench fill material portion contacting a respective sidewall of the alternating stack.

24. The semiconductor structure of claim 22, further comprising a pair of dielectric barrier structures extending vertically through the alternating stacks and laterally spaced apart from the pair of backside trench fill structures.

25. The semiconductor structure of claim 24, wherein: The vertical stack of plates of dielectric material is in direct contact with each of the pair of dielectric isolator structures; and The pair of dielectric barrier structures are laterally spaced apart from one another by a vertically alternating sequence of the insulating layers and the plates of dielectric material.

26. The semiconductor structure of claim 21, wherein the metal plate portion includes a sidewall that contacts a sidewall of one of the insulating layers.

27. The semiconductor structure of claim 26, wherein a vertical interface between the metal plate portion and the one of the insulating layers is laterally offset from a bottom periphery of the metal via portion by a uniform lateral offset distance.

28. The semiconductor structure of claim 21, wherein the integrated line and via structure comprises a homogeneous metal material portion extending continuously through the first conductive layer, the metal plate portion, the second conductive layer, and the metal via portion without material junctions therein.

29. The semiconductor structure of Claim 28, wherein the metal via portion is laterally surrounded by a tubular dielectric liner.

30. The semiconductor structure of Claim 29 wherein said tubular dielectric liner is laterally surrounded by each of said plates of dielectric material overlying said first conductive layer.

31. The semiconductor structure of Claim 30, wherein an annular bottom surface of said tubular dielectric liner contacts an annular horizontal surface segment of said first conductive layer.

32. A method of forming a semiconductor structure, the method comprising: forming an alternating stack of insulating layers including dielectric material and layers of sacrificial material; forming a memory opening filling structure through the alternating stack; forming a via opening through an upper portion of the alternating stack such that a top surface of a first one of the sacrificial material layers is physically exposed; extending the via opening vertically through the first sacrificial material layer such that a top surface of a first one of the insulating layers is physically exposed; forming an insulating layer level laterally extending cavity by isotropically recessing the first insulating layer to expose a top surface of a second sacrificial material layer among the sacrificial material layers; forming a multi-level laterally extending cavity by isotropically etching the first sacrificial material layer and the second sacrificial material layer; forming a backside groove through the alternating stack before or after forming the multi-level laterally extending cavity; isotropically recessing the sacrificial material layer from around the backside trench to form a backside recess in the volume of the portion from which the sacrificial material layer is removed, wherein two of the backside recesses are connected to the multi-level laterally extending cavity to form a continuous void; as well as Conductive material is deposited in the back-side recess, the multi-level laterally extending cavity and the through-hole opening, wherein the portion of the conductive material deposited in the volume of the back-side recess and the laterally extending cavity constitutes a conductive layer, and the portion of the conductive material filling the through-hole opening constitutes a metal through-hole portion.

33. The method of claim 32, wherein a remaining portion of the sacrificial material layer after forming the backside recess comprises a dielectric material portion laterally surrounding the via opening.

34. The method of claim 33, further comprising forming a pair of dielectric barrier structures through the alternating stack, wherein the multi-level laterally extending cavity is laterally bounded by sidewalls of the pair of dielectric barrier structures.

35. The method of claim 32, wherein: The conductive layer includes a first conductive layer filling a volume from which the first sacrificial material layer is removed and a second conductive layer filling a volume from which the second sacrificial material layer is removed; and The metal plate partially fills the volume of the laterally extending cavity at the insulating layer level and vertically connects the first conductive layer and the second conductive layer.

36. The method of claim 35, wherein the first conductive layer, the second conductive layer, and the metal plate portion are part of an integrated line and via structure, the integrated line and via structure being a unitary structure and further comprising the metal via portion.

37. A method of forming a semiconductor structure, the method comprising: forming an alternating stack of insulating layers including dielectric material and layers of sacrificial material; forming a memory opening filling structure through the alternating stack; forming a through-hole opening through the upper portions of the alternating stacks; forming a laterally extending cavity beneath the via opening by isotropically recessing a first one of the sacrificial material layers; forming a backside groove through the alternating stack before or after forming the laterally extending cavity; isotropically recessing the sacrificial material layer from around the backside trench to form a backside recess in the volume of the portion from which the sacrificial material layer was removed, wherein one of the backside recesses is connected to the laterally extending cavity to form a continuous void; as well as A conductive material is deposited in the backside recess and the via opening, wherein the portion of the conductive material deposited in the backside recess and the volume of the laterally extending cavity constitutes a conductive layer and the portion of the conductive material filling the via opening constitutes a metal via portion.

38. The method of claim 37, wherein a remaining portion of the sacrificial material layer after forming the backside recess comprises a dielectric material portion laterally surrounding the via opening.

39. The method of claim 38, further comprising forming a pair of dielectric barrier structures through the alternating stack, wherein the pair of dielectric barrier structures are closer to the via opening than the backside trench.

40. The method of claim 37, wherein: The conductive layer includes a first conductive layer filling the laterally extending cavity; and The first conductive layer is part of an integrated line and via structure, which is a unitary structure and includes the first conductive layer and the metal via portion.

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