Integrated circuit package with internal circuitry to detect external component parameters and parasitic effects

Abstract

Devices and techniques for integrated circuit (IC) packages to automatically detect external component parameters and parasitic effects through input / output pins. An example IC package generally includes a pin for coupling to a component external to the IC package, and at least one of a resistance detector, an inductance detector, or a capacitance detector coupled to the pin and configured to detect at least one of a resistance, an inductance, or a capacitance for a lumped parametric model of the component external to the IC package, respectively. The resistance detector, inductance detector, or capacitance detector may also be configured to detect a parasitic effect associated with at least one of the component, the pin, or a connection between the component and the pin.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application serial number 17 / 808,357 filed on June 23, 2022, which is hereby incorporated by reference into this document. Technical Field

[0003]

[0006] Certain aspects of the present disclosure relate generally to electronic circuits, and more particularly, certain aspects of the present disclosure relate to integrated circuit packages having on-chip detection schemes for one or more off-chip components and parasitics. Background Art

[0004] Electronic devices, such as computers, wireless communication devices (e.g., cellular phones and Wi-Fi access points), and wearable devices, have come into widespread use in recent years. Electronic devices typically include one or more integrated circuits (ICs). These ICs are typically implemented as one or more semiconductor dies that can be coupled to other electronic components, all of which can be included in an IC package for assembly on a printed circuit board (PCB) for inclusion in an electronic device.

[0005] Packaging an integrated circuit die and other components together in a module (also referred to herein as a "package assembly") can enable electronic devices to have a smaller form factor while providing improved signal performance (e.g., reduced transient overshoot and undershoot), electrical performance (e.g., reduced power consumption), and thermal performance (e.g., reduced heat generation) compared to previously known electronic devices. For example, a cellular telephone can have improved battery life due to reduced power consumed by a transceiver module (in which the die and other components are assembled in a package assembly). Summary of the invention

[0006] The systems, methods, and devices of the present disclosure each have several aspects, no single aspect of which is solely responsible for its desirable attributes. Without limiting the scope of the present disclosure as expressed by the claims that follow, some features will now be briefly discussed. After considering this discussion, and particularly after reading the section entitled "Detailed Description of the Invention," it will be understood how the features of the present disclosure provide the advantages described herein.

[0007] In general, certain aspects of the present disclosure relate to apparatus and techniques for detecting external component parameters and parasitic effects of integrated circuit (IC) packages.

[0008] Certain aspects of the present disclosure are directed to an integrated circuit (IC) package. The IC package generally includes a pin for coupling to a component external to the IC package, and at least one of a resistance detector, an inductance detector, or a capacitance detector coupled to the pin and configured to detect at least one of a resistance, an inductance, or a capacitance of a lumped parameter model for a component external to the IC package and for parasitic effects associated with at least one of the component, the pin, or a connection between the component and the pin, respectively.

[0009] Certain aspects of the present disclosure are directed to a method for parameter determination. The method generally includes coupling at least one of a resistance detector, an inductance detector, or a capacitance detector inside an integrated circuit (IC) package to a pin of the IC package, the pin being coupled to a component outside the IC package. The method also includes using at least one of the resistance detector, the inductance detector, or the capacitance detector inside the IC package to respectively detect at least one of resistance, inductance, or capacitance of a lumped parameter model for a component outside the IC package and for a parasitic effect associated with at least one of the component, the pin, or a connection between the component and the pin.

[0010] Certain aspects of the present disclosure are directed to an integrated circuit (IC) package. The IC package generally includes a pin for coupling to a component external to the IC package, and at least one of: a unit for detecting a resistance of a lumped parameter model for the component external to the IC package and for parasitic effects associated with at least one of the component, the pin, or a connection between the component and the pin, a unit for detecting an inductance of the lumped parameter model, or a unit for detecting a capacitance of the lumped parameter model.

[0011] To achieve the above and related purposes, one or more aspects include features fully described below and specifically pointed out in the claims. The following description and the accompanying drawings set forth in detail certain illustrative features of one or more aspects. However, these features indicate only a few of the various ways in which the principles of the various aspects can be employed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to be able to understand the above-mentioned features of the present disclosure in detail, a more specific description of the invention briefly summarized above can be made by reference to various aspects (some of which are shown in the accompanying drawings). However, it should be noted that the accompanying drawings only show certain typical aspects of the present disclosure, and therefore will not be considered as limiting its scope, because the description may accept other equally effective aspects.

[0013] Figure 1A block diagram of an example device is shown in which aspects of the present disclosure may be implemented.

[0014] Figure 2 is a block diagram of an example circuit including an integrated circuit (IC) package and one or more external components according to certain aspects of the present disclosure.

[0015] Figure 3 An example implementation of an inductance detector according to certain aspects of the present disclosure is shown.

[0016] Figure 4 An example implementation of an example peak detector in accordance with certain aspects of the present disclosure is shown.

[0017] Figure 5 An example implementation of a resistance detector according to certain aspects of the present disclosure is shown.

[0018] Figure 6 An example implementation of a capacitance detector in accordance with certain aspects of the present disclosure is shown.

[0019] Figure 7 is a flow diagram of example operations for parameter determination in accordance with certain aspects of the present disclosure.

[0020] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0021] Certain aspects of the present disclosure provide circuit systems and techniques for automatically detecting external component parameters and parasitic effects for integrated circuit (IC) packages, the circuit systems being internal to the IC packages. Such circuit systems and techniques can adaptively change design parameters of the IC packages based on the detected external parameters and parasitic effects.

[0022] The various aspects of the present disclosure are described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete, and fully convey the scope of the present disclosure to those skilled in the art. Based on the teachings herein, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the present disclosure disclosed herein, whether implemented independently or in combination with any other aspect of the present disclosure. For example, using any number of aspects set forth herein, a device can be implemented or a method can be implemented. In addition, the scope of the present disclosure is intended to cover such a device or method implemented using other structures, functions, or structures and functions other than or different from the various aspects of the present disclosure described herein. It should be understood that any aspect of the present disclosure disclosed herein can be embodied by one or more elements of the claims.

[0023] As used herein, the term "connected with" in various tenses of the verb "connect" may mean that element A is directly connected to element B, or that other elements may be connected between elements A and B (i.e., element A is indirectly connected to element B). In the case of electrical components, the term "connected with" may also be used herein to mean that wires, traces, or other conductive materials are used to electrically connect components A and B (and any components electrically connected therebetween).

[0024] Example Device

[0025] Figure 1 An example device 100 is shown in which aspects of the present disclosure may be implemented. Device 100 may be a battery-powered device such as a cellular phone, a personal digital assistant (PDA), a handheld device, a wireless device, a laptop, a tablet device, a smartphone, a wearable device, or the like.

[0026] The device 100 may include a processor 104 that controls the operation of the device 100. The processor 104 may also be referred to as a central processing unit (CPU). A memory 106 (which may include both read-only memory (ROM) and random access memory (RAM)) provides instructions and data to the processor 104. A portion of the memory 106 may also include non-volatile random access memory (NVRAM). The processor 104 typically performs logical and arithmetic operations based on program instructions stored in the memory 106.

[0027] In some aspects, the device 100 may also include a housing 108, which may include a transmitter 110 and a receiver 112 to allow data to be sent and received between the device 100 and a remote location. For some aspects, the transmitter 110 and the receiver 112 may be combined into a transceiver 114. One or more antennas 116 may be attached or otherwise coupled to the housing 108 and electrically connected to the transceiver 114. The device 100 may also include (not shown) multiple transmitters, multiple receivers, and / or multiple transceivers.

[0028] The device 100 may also include a signal detector 118, which may be used to try to detect and quantify the level of the signal received by the transceiver 114. The signal detector 118 may detect signal parameters such as total energy, energy per subcarrier per symbol, and power spectral density, among other terms. The device 100 may also include a digital signal processor (DSP) 120 for processing signals.

[0029] The device 100 may further include a battery 122 for powering the various components of the device 100. The device 100 may also include a power management integrated circuit (power management IC or PMIC) 124 for managing power from the battery to the various components of the device 100. The PMIC 124 may perform various functions for the device, such as DC to DC conversion, battery charging, power selection, voltage scaling, power sequencing, etc. In certain aspects, the PMIC 124 may include at least a portion of a power supply circuit, which may include a switch mode power supply (SMPS) or a linear voltage regulator (such as a low dropout (LDO) regulator 125).

[0030] The device 100 may additionally include one or more speakers (not shown) for converting electrical signals into audio signals. In this case, the device 100 may include one or more amplifiers for driving the speakers, and these amplifiers may be powered by one or more power supply circuits, which may be part of the PMIC or receive a power supply voltage rail generated by the PMIC.

[0031] The various components of the device 100 may be coupled together via a bus system 126 (which, in addition to a data bus, may also include a power bus, a control signal bus, and / or a status signal bus).

[0032] Example IC package supporting internal inductance, capacitance and / or resistance sensing of external components

[0033] Figure 22 is a block diagram of an example circuit 200 in which aspects of the present disclosure may be implemented including an integrated circuit (IC) package 205. The IC package 205 may have pins 250 (e.g., input / output (I / O) pins) for coupling the IC package 205 to one or more external components 270 (i.e., components external to the IC package).

[0034] Many circuits, such as circuit 200, are not entirely on-chip (e.g., within a single IC package, such as IC package 205), but include pins, such as pin 250, for coupling the IC package to external components, such as external component 270. The entire circuit may be implemented on a printed circuit board (PCB). In some cases, external components and parasitic effects (e.g., of the pins, PCB, and / or the external components themselves) may introduce additional variables to consider when designing the circuit. Therefore, a single circuit design may not achieve optimized performance for all conditions in which the circuit may operate. Therefore, it is desirable to automatically detect, determine, and / or measure component parameters and parasitic effects so that automatic configuration of the IC package can be achieved.

[0035] Some aspects of circuit design can be adaptively configured using programmable components. However, while some components in a circuit may be programmable, adding programmable components typically involves performing additional circuit testing and tuning. Furthermore, while frequency domain measurement tools exist, frequency domain measurements of parasitic effects and component parameters are typically complex and consume additional power and real estate, which may make such implementations impractical or infeasible.

[0036] One approach to detecting external parasitics and component parameters involves using a sensor in the IC package that is coupled to the external component through one or more sensing pins that are separate from the input / output pins of the IC package. However, such a design includes additional pins and routing resources, which can be expensive and difficult to integrate. Furthermore, such a sensor may not be truly designed for measuring external passive component parameters and parasitics and therefore may not be reliable in such applications.

[0037] Therefore, certain aspects of the present disclosure provide techniques and internal circuit systems for detecting external parasitic effects and component parameters through input / output pins of an IC package without any additional sensing pins or sensor interfaces. The detection scheme can be automatically performed for certain aspects (e.g., during power-up of the IC package or during other idle times of the operation of the IC package).

[0038] Accordingly, if Figure 2As shown, IC package 205 may also include internal detection circuitry 210 for detecting external component parameters and parasitic effects through pin 250. Detection circuitry 210 may include one or more of inductance detector 220, resistance detector 230, and capacitance detector 240. IC package 205 may optionally include a switch network 215 including one or more switches coupled between pin 250 and at least one of inductance detector 220, resistance detector 230, or capacitance detector 240. The switch may allow the detector to be connected to pin 250 when a particular detector is being used, and disconnected from pin 250 during a mission mode of the IC package circuitry typically associated with pin 250.

[0039] The inductance detector 220, the resistance detector 230, and / or the capacitance detector 240 may be configured to respectively detect a lumped parameter model (eg, Figure 3 , Figure 5 and Figure 6 , also referred to as a “lumped element model”). Inductance detector 220, resistance detector 230, and / or capacitance detector 240 may be configured to detect parasitic effects 260 (e.g., due to PCB construction, vias, and / or trace routing) associated with at least one of external component 270, pin 250, or connection 265 (e.g., routing) between external component 270 and pin 250.

[0040] Based on the detected inductance, resistance, and / or capacitance of the lumped parameter model, one or more parameters can be selected (e.g., for tuning or setting of adjustable components in an IC package and / or other circuits), and one or more components can be adjusted based on the selected parameters (i.e., adaptive parameter selection). Such detection and selection can save testing, debugging, and / or calibration time and non-recurring engineering (NRE) costs. In addition, knowing the inductance, resistance, and / or capacitance looking outward from pin 250 and selecting parameters accordingly can improve various performance specifications, can increase stability margins, and avoid over-design.

[0041] Although the inductance detector 220, the resistance detector 230, or the capacitance detector 240 are depicted as separate detectors, it will be understood by those skilled in the relevant art that some components of one of these detectors may be used by one or more of the other detectors to perform the corresponding detection process described in more detail below. For example, in some cases, the resistance detector 230 and the capacitance detector 240 may be combined and may share components.

[0042] In some aspects, at least one of the inductance detector 220, the resistance detector 230, or the capacitance detector 240 can be configured to operate in the time domain. For example, in some aspects, at least one of the detectors can be configured to output a time domain drive signal (e.g., to the external component 270), and sense a time domain response signal (e.g., from the external component 270). The drive signal and the response signal can be used to determine at least one of the inductance, resistance, or capacitance of the lumped parameter model for the external component 270, as explained in more detail below.

[0043] Example Inductance Detection Circuitry

[0044] Figure 3 2 shows an example implementation of the inductance detector 220 according to certain aspects of the present disclosure. As shown, the external component 270 can be represented using a lumped parameter model 328, which can include a resistor R p A series resistor 330 having an inductance L p The series inductor 335 and the capacitor C L The inductance detector 220 may be configured to determine the inductance L of the inductor 335 in the lumped parameter model. p .

[0045] Inductance detector 220 may include a pulse generator 302, a switch driver 304, and a switch 306. Switch 306 may be coupled between power rail 308 and pin 250, and switch driver 304 may be coupled between an output of pulse generator 302 and a control input of switch 306 (e.g., a gate of a transistor implementing switch 306).

[0046] In some aspects, the switch driver 304 can be configured to drive the switch 306 at a plurality of different slew rates (where “slew rate” generally refers to the change in voltage or current per unit time). Thus, in some aspects, the switch driver 304 can include a plurality of drive circuits 322 that are coupled via switches 320 (labeled “D0, D1, . . . , D M-1”, and also represents a digital control signal for the switch) is selectively coupled between the output of the pulse generator 302 and the control input of the switch 306. In some aspects, at least one of the plurality of drive circuits 322 can be implemented as a plurality of serially connected inverters (as shown), a plurality of serially connected buffers, or a combination thereof. The paths associated with each drive circuit 322 can sometimes be individually referred to as a “switch driver path” and collectively referred to as “switch driver paths”. Each drive circuit 322 can have a different delay, which can be achieved by having a different number of inverters and / or buffers in each drive circuit. By having different drive strengths in each of the drive circuits 322, different switch driver paths can be configured to drive the switch 306 using control signals (e.g., pulses from the pulse generator 302) having different slew rates.

[0047] According to certain aspects, inductance detector 220 can further include peak detector 310, comparator 314, N-bit successive approximation register (SAR) 316, and digital logic 318. Peak detector 310 can have inputs coupled to pin 250 and switch 306. As shown, comparator 314 can have a first input coupled to the output of peak detector 310 and a second input coupled to reference voltage node 313. For certain aspects, reference voltage node 313 can be coupled to reference voltage generator 312, which can generate a reference voltage (labeled “V th ”). The output of comparator 314 may be coupled to the input of SAR 316, and the output of SAR 316 may be coupled to logic 318. For an N-bit SAR 316, N is the number of cycles through inductance detector 220 and represents the inductance resolution.

[0048] The inductance detector 220 can be used to detect the instantaneous voltage V across the inductor. L The inductance L of the inductor 335 is determined using the SAR-based charging scheme. p Thus, inductance detection can be based on introducing currents with different slew rates to pin 250 and detecting the peak voltage (V e ). Voltage V L It can be expressed by the following equation:

[0049]

[0050] Among them, dI L / dt is the change in current across the inductor over time (slew rate). With higher frequency slew rates, the DC component (resistance) and capacitance of the lumped parameter model 328 may be negligible, so that the sensed voltage represents the inductance of the lumped parameter model 328.

[0051] By using this equation and dividing dI L / dt is set to a very large value (eg, using the fast rise time of the pulse received at the control input of switch 306), even if the inductor L p Very small, inductance L p Also based on the measured voltage V e For example, in some cases, the inductance L p It may be in the nanohenry (nH) range. The various slew rates from the different switch driver paths allow the time (dt) that current is driven into the inductor 335 to be varied depending on which switch driver path is selected.

[0052] Inductance detector 220 may operate by successively using different switch driver paths to achieve different peak voltages at pin 250 based on the value stored in SAR 316, and encoding logic 318 for selecting the next switch driver path. Peak detector 310 may be configured to detect the peak voltage, and comparator 314 may be configured to compare the peak voltage to a reference voltage (also referred to as a “threshold voltage” and labeled “V th ”). In some examples, the reference voltage can be designed to be equal to half the voltage of the pulses from the pulse generator 302 (e.g., the midpoint of the highest possible peak voltage value). The comparator 314 is configured to compare the peak voltage to the reference voltage in each iteration (each cycle). If the comparator 314 determines that the peak voltage is less than the threshold voltage, the comparator will output a logic “0”. If the comparator 314 determines that the peak voltage is greater than the threshold voltage, the comparator will output a logic “1”.

[0053] SAR 316 may be configured to store (and shift) a 1-bit value from comparator 314 based on each of the N comparisons performed. Logic 318 may have one or more outputs coupled to control inputs of switches 320 in switch driver 304. Logic 318 may be configured to control selection of a switch driver path based on the digital value in SAR 316. Specifically, logic 318 may be used to control switch 320 based on a mapping of bits of SAR 316 to switches 320.

[0054] At the end of N cycles through the inductance detector 220, the selected switch driver path should result in a peak voltage on pin 250 that is close to the reference voltage, indicating that the SAR-based quantization of the external inductance has been successfully completed. After N cycles, based on the mapping of inductance to the digital code, the N-bit value stored in the SAR 316 can be used to determine the inductance, for example, as shown in graph 350, where N=4 cycles. For example, a SAR output of 0101b can indicate an inductance of approximately 5nH. The drive strength in the driver circuit 322 can be designed to provide a linear mapping of inductance to digital code, such as the linear relationship shown in graph 350.

[0055] Figure 4 An example implementation of a peak detector 310 according to certain aspects of the present disclosure is shown. Using the above detection scheme, the voltage across the inductor 335 in each cycle can be implemented as a very short pulse. The peak detector 310 can be configured to capture and hold the peak voltage of the short pulse.

[0056] The peak detector 310 may include a first transistor 402 having a drain coupled to the pin 250 and a first capacitive element C. The first capacitive element C may be coupled between the source of the first transistor 402 and a reference potential node (e.g., electrical ground) of the peak detector 310. If the gate and drain of the first transistor 402 are connected together, the first transistor will be a diode-connected transistor, so that the peak detector will effectively include a series diode coupled to a parallel capacitor (e.g., the first capacitive element C), wherein the output of the peak detector will be the cathode of the diode (e.g., the source of the first transistor 402). Thus, the first capacitive element C may be configured to charge when the voltage at the pin 250 is greater than the voltage across the first capacitive element C, and may be configured to stop charging when the voltage at the pin 250 is less than the voltage across the first capacitive element C. In this manner, the first capacitive element C may be configured to detect and maintain a peak voltage value at the pin 250 during a detection window.

[0057] According to certain aspects, the peak detector 310 may be implemented as an AC coupled diode peak detector, as shown. In this case, the peak detector 310 may include a second capacitive element C coupled between the drain and gate of the first transistor 402. C The second capacitive element C C The reverse leakage from the DC signal can be prevented from coupling to the pin 250. The peak detector 310 may further include a resistor element R coupled between the gate of the first transistor 402 and the reference potential node. C .

[0058] In some aspects, the peak detector 310 may also include a second transistor 404 having a drain coupled to the source of the first transistor 402. The source of the second transistor 404 may be coupled to the first capacitive element C and to the first input of the comparator 314 (e.g., at the input labeled “V e ” node, also referred to as the output of the peak detector 310 ). The second transistor 404 can be used as an isolation switch, which is configured to isolate the power supply ripple and leakage from the pin 250 .

[0059] The peak detector 310 may also include a control logic circuit system 414 for the second transistor 404, which may include a third transistor 406, a fourth transistor 408, a current source 410, and a switched capacitor array (also referred to as a "capacitor bank"). The switched capacitor array may be implemented by M parallel paths, each path including a switch 412 (labeled "C-Bank") coupled in series with a capacitive element. <0:M-1> ”). For certain aspects, M=2 N The source of the third transistor 406 can be coupled to the gate of the second transistor 404. The current source 410 can be coupled between the power rail 308 and the drain of the third transistor 406. The fourth transistor 408 can have a drain coupled to the gate of the second transistor 404 and the source of the third transistor 406, and can have a source coupled to the reference potential node of the peak detector 310. In some aspects, the control input signal (labeled “V drv "and ) may be a complementary signal. The control logic circuit system 414 may be configured to activate the second transistor 404 at the beginning of the detection window and deactivate the second transistor 404 at the end of the detection window. In some examples, the detection window may begin when a new switch driver path is selected and a new pulse is generated.

[0060] In some aspects, the switched capacitor array can be coupled between the gate of the second transistor 404 and the reference potential node of the peak detector 310. The switched capacitor array can be used to control the turn-off timing of the second transistor 404. The control signal (labeled “CTRL <0:M-1> ”) (Based on the selected switch driver path (and corresponding slew rate)), the capacitive element C-Bank in the switched capacitor array can be selected <0:M-1> For example, the faster the slew rate of the selected switch driver path, the smaller the on-time of the peak detector 310 will be. In this case, the switched capacitor array can be selected to have a smaller capacitance. This can be used to minimize (or at least reduce) the supply ripple effect on the voltage maintained on the peak detector 310.

[0061] Graphs 420 and 430 illustrate example input and output signals of peak detector 310, respectively. The input signal of peak detector 310 (represented by the y-axis and labeled “Vin” in graph 420) may be a return signal from an external component received at pin 250, and the output signal of peak detector 310 (represented by the y-axis and labeled “Ve” in graph 430) may indicate the peak voltage of the input signal detected during the detection window. In the example shown, at time 435 during the detection window, the input signal rises sharply to a peak value (labeled “Peak”), and peak detector 310 detects the peak value and holds the value (e.g., as a stored value Peak′). Even if a ripple voltage appears at the input of peak detector 310, as shown in graph 420 at time 440, the output of peak detector 310 will not change. Furthermore, if the input signal exceeds the peak voltage at time 445 outside the detection window, peak detector 310 will hold (e.g., not overwrite) the held peak value detected during the detection window.

[0062] Example Resistance Sense Circuitry

[0063] Figure 5 An example resistance detector 230 is shown in accordance with certain aspects of the present disclosure. The resistance detector 230 may be configured to determine the resistance R of the resistor 330 in the lumped parameter model 328. p .

[0064] The resistance detector 230 may include a control logic 502, a first current source 504 configured to supply a first current (labeled as "I1"), a first switch 508 coupled between the first current source 504 and the pin 250, a second current source 506 configured to supply a second current (labeled as "I2"), and a second switch 510 coupled between the second current source 506 and the pin 250. The second current should be different from the first current. The first current source 504 may be coupled between a power rail (e.g., the power rail 308) and the first switch 508, and the second current source 506 may be coupled between the power rail and the second switch 510. For example, the first current source 504, the second current source 506, the first switch 508, and / or the second switch 510 may each be implemented by one or more transistors. The resistance detector 230 may further include a first sample and hold (S&H) circuit 512 having an input coupled to pin 250, a second S&H circuit 514 having an input coupled to pin 250, and an analog-to-digital converter (ADC) 518 having one or more inputs coupled to an output of the first S&H circuit 512 and an output of the second S&H circuit 514.

[0065] The resistance detector 230 (and more specifically, the control logic 502) can be configured to close the first switch 508 at the beginning of the first time period to provide the first current from the first current source 504 to the pin 250. The first time period can have a time length t1. Providing the first current to the pin 250 can generate a resistor voltage across one or more external resistance elements (represented by the resistor 330) and charge one or more external capacitance elements (e.g., represented by the capacitor 340) to generate a capacitor voltage. This charging can be performed at a low frequency so that the DC component and the capacitance element in the lumped parameter model 328 dominate, while the inductance element has a negligible effect (e.g., there is almost no voltage drop across the inductance element). During the first time period, the first S&H circuit 512 can be configured to sample the first voltage (labeled as "V1") of the pin 250. At the end of the first time period, the resistance detector 230 can be further configured to open the first switch 508, and the first S&H circuit 512 can be configured to maintain the sampled first voltage. After the first time period, the external capacitance element can be discharged.

[0066] The resistance detector 230 (and more specifically, the control logic 502) can be further configured to close the second switch 510 at the beginning of the second period to provide a second current from the second current source 506 to the pin 250, thereby generating a voltage across the external resistance and capacitance elements, as described above. The second period can have a time length t2. During the second period, the second S&H circuit 514 can be configured to sample the second voltage (labeled "V2") of the pin 250. At the end of the second period, the resistance detector 230 can be further configured to open the second switch 510, and the second S&H circuit 514 can be configured to maintain the sampled second voltage. After the second period, the external capacitance element can be discharged.

[0067] The time allocated for discharging the external capacitive element may be based on the known value of the resistance of the pull-down network used to discharge the capacitive element and the capacitance C of capacitor 340 in the lumped parameter model. L Based on these values, a resistance-capacitance (RC) time constant can be estimated, and resistance detector 230 can be configured to wait a corresponding amount of time to ensure that the external capacitive element is actually discharged (e.g., substantially discharged to have a negligible effect on resistance detection purposes).

[0068] Based on the sequence described above, the voltage difference (eg, “ΔVout”) between the maintained first voltage and the maintained second voltage at pin 250 may be expressed as:

[0069]

[0070] Therefore, the first product of the value of the first current and the time length (t1) of the first time period can be configured to be equal to the second product of the value of the second current and the time length (t2) of the second time period. That is, the current and the time period can be set so that I1*t1=I2*t2. Therefore, since I1*t1=I2*t2, the capacitance C of the capacitor 340 in the lumped parameter model L That is, the voltage difference between the maintained first voltage and the maintained second voltage at pin 250 can be alternatively approximated as:

[0071] ΔVout=(I1-I2)*R p

[0072] The resistance detector 230 may be further configured to quantify the voltage difference between the held first voltage and the held second voltage using the ADC 518 and determine the resistance R of the resistor 330 in the lumped parameter model based on the rearranged equation: p :

[0073]

[0074] According to certain aspects, the resistance detector 230 may further include an amplifier 516 having a first input coupled to the output of the first S&H circuit 512, a second input coupled to the output of the second S&H circuit 514, and an output coupled to one or more inputs of the ADC 518. The amplifier 516 may be configured to amplify a voltage difference between the maintained first voltage and the maintained second voltage. In this case, the resistance detector 230 may be configured to quantize the amplified voltage difference using the ADC 518, and determine the resistance R of the resistor 330 in the lumped parameter model based on the value of the first current, the value of the second current, and the quantized amplified voltage difference. p .

[0075] Example Capacitance Detection Circuitry

[0076] Figure 6 3. An example capacitance detector 240 is shown in accordance with certain aspects of the present disclosure. The capacitance detector 240 may be configured to determine the capacitance C of the capacitor 340 in the lumped parameter model 328. L .

[0077] Capacitance detector 240 may include control logic 602, current source 604, switch 606, S&H circuit 608, and ADC 610. As shown, current source 604 may be coupled between a power rail (e.g., power rail 308) and switch 606, switch 606 may be coupled between current source 604 and pin 250, and S&H circuit 608 may be coupled between pin 250 and ADC 610. For example, current source 604 and / or switch may each be implemented by one or more transistors. Control logic 602 may have an output coupled to a control input of switch 606.

[0078] Capacitance detector 240 (and more specifically, control logic 602) can be configured to close switch 606 at the beginning of a period to charge one or more capacitive elements (represented by capacitor 340) external to the IC package with current from current source 604. This charging can be performed at a relatively low frequency so that the capacitive elements in lumped parameter model 328 dominate, while the resistive and inductive elements have negligible effects. Capacitance detector 240 can be further configured to sample the voltage at pin 250 during the period, hold the sampled voltage using S&H circuit 608 at the end of the period, and open switch 606 at the end of the period.

[0079] Capacitance detector 240 (and more specifically, control logic 602) may also be configured to quantize the held voltage using ADC 610 and determine capacitance C of capacitor 340 in lumped parameter model 328 based on the value of the current, the length of the time period, and the quantized voltage. L For example, capacitance detector 240 may be configured to determine capacitance C of capacitor 340 in the lumped parameter model using the following equation: L :

[0080]

[0081] Where I is the current from current source 604, t is the length of time for the period, and V C is the voltage sampled by the S&H circuit 608 .

[0082] Figure 6Also included are graphs 630 and 640, which respectively show the input and output voltages of the capacitance detector 240 as a function of time before, during, and after the detection period. As shown in graph 630, the control input for switch 606 can be changed from a logic low to a logic high, thereby closing switch 606. When switch 606 is closed, one or more capacitive elements (represented by capacitor 340) outside the IC package are charged by the current from current source 604. Switch 606 remains closed for a time length t, during which the voltage at pin 250 (represented by the y-axis and labeled "Output" in graph 640) increases and is sampled by S&H circuit 608. At the end of the period, switch 606 can be opened (as shown by the control input for switch 606 changing to a logic low), and S&H circuit 608 can hold the sampled voltage. The held voltage can then be quantized (e.g., by ADC 610), and the quantized value can be used to calculate the capacitance C of capacitor 340 in the lumped parameter model based on the above equation L .

[0083] Example Operations for Parameter Determination

[0084] Figure 7 2 is a flow chart of example operations 700 for determining parasitic effects and parameters of components external to an IC package, such as IC package 205, in accordance with certain aspects of the present disclosure. Operations 700 may be performed using detection circuitry in the IC package, such as Figure 2 The detection circuit system 210 in the IC package 205 is shown.

[0085] Operations 700 may begin at block 702 with coupling at least one of an inductance detector (e.g., inductance detector 220), a resistance detector (e.g., resistance detector 230), or a capacitance detector (e.g., capacitance detector 240) inside an IC package to a pin (e.g., pin 250) of the IC package. The pin may be coupled to a component (e.g., external component 270) outside the IC package. At block 704, operations 70 may further include using at least one of the resistance detector, the inductance detector, or the capacitance detector inside the IC package to detect at least one of resistance, inductance, or capacitance of a lumped parameter model (e.g., lumped parameter model 328) for a component outside the IC package and for a parasitic effect (e.g., parasitic effect 260) associated with at least one of the component, the pin, or a connection (e.g., connection 265) between the component and the pin, respectively.

[0086] According to certain aspects, coupling at block 702 may involve closing one or more switches (eg, switches in switch network 215 ) coupled between the pin and at least one of the resistance detector, the inductance detector, or the capacitance detector.

[0087] According to certain aspects, the detection at block 704 may involve operating at least one of a resistance detector, an inductance detector, or a capacitance detector in the time domain. In certain aspects, the detection at block 704 may involve generating a drive signal in the IC package (e.g., via the switch driver 304), outputting the drive signal to the component via a pin of the IC package, and receiving a response signal from the component and parasitic effects via the pin of the IC package. In this case, the drive signal may be a time domain drive signal, and the response signal may be a time domain response signal.

[0088] According to certain aspects, detecting the capacitance at block 704 may involve closing a switch (e.g., switch 606) coupled between a current source (e.g., current source 604) and a pin at the beginning of a period to detect the capacitance of a capacitive element (e.g., capacitor C) in a lumped parameter model using current from the current source. L ) to charge, and at the end of the period, the switch is turned off. In this case, detecting the capacitance may further involve sampling the voltage of the pin using a sample and hold (S&H) circuit (e.g., S&H circuit 608) during the period, and holding the sampled voltage using the S&H circuit at the end of the period. In some aspects, detecting the capacitance may further involve quantizing the held voltage using an analog-to-digital converter (ADC) (e.g., ADC 610), and determining the capacitance of the capacitive element in the lumped parameter model based on the value of the current, the length of time of the period, and the quantized voltage.

[0089] According to certain aspects, detecting the resistance at block 704 may involve closing a first switch (e.g., first switch 508) coupled between a first current source (e.g., first current source 504) and a pin at the beginning of a first period of time to provide a first current (e.g., I1) from the first current source to the pin, and opening the first switch at the end of the first period of time. In certain aspects, detecting the resistance may further involve sampling a first voltage of the pin during the first period of time using a first S&H circuit (e.g., S&H circuit 512), and maintaining the sampled first voltage at the end of the first period of time. Detecting the resistance may also involve closing a second switch (e.g., second switch 510) coupled between a second current source (e.g., second current source 506) and the pin at the beginning of a second period of time to provide a second current (e.g., I2) from the second current source to the pin, and opening the second switch at the end of the second period of time. In certain aspects, detecting the resistance may further involve sampling a second voltage of the pin during the second period of time using a second S&H circuit (e.g., S&H circuit 514), and maintaining the sampled second voltage at the end of the second period of time. Detecting the resistance may further involve quantifying a voltage difference between the maintained first voltage and the maintained second voltage using an analog-to-digital converter (ADC) (e.g., ADC 518), and determining a resistance element (e.g., resistor R) in the lumped parameter model based on the value of the first current, the value of the second current, and the quantized voltage difference. p In this case, a first product of a value of the first current and a time length of the first period may be substantially equal to a second product of a value of the second current and a time length of the second period, thereby making the capacitance of the lumped parameter model negligible.

[0090] In some aspects, detecting the resistance can further involve amplifying the voltage difference between the maintained first voltage and the maintained second voltage (e.g., using amplifier 516). In this case, quantizing the voltage difference between the maintained first voltage and the maintained second voltage can involve quantizing the amplified voltage difference.

[0091] According to certain aspects, detecting the inductance at block 704 may involve using a successive approximation register (SAR) based charging scheme (e.g., using SAR 316) to charge the component via the pin over a plurality of cycles. In certain aspects, detecting the inductance may involve generating a pulse using a pulse generator (e.g., pulse generator 302), selecting a path from among a plurality of paths (e.g., a plurality of drive circuits 322) in a switch driver (e.g., switch driver 304), modifying a slew rate of the pulse using the selected path in the switch driver (e.g., via logic 318), and driving a switch (e.g., switch 306) coupled between a power rail (e.g., power rail 308) and the pin using the pulse with the modified slew rate. In certain aspects, detecting the inductance may further involve detecting a peak value of a voltage signal received from the pin (e.g., via peak detector 310), comparing the detected peak value of the voltage signal with a reference voltage (e.g., generated using reference voltage generator 312) using a comparator (e.g., comparator 314). In this case, detecting the inductance may involve storing the digital value output from the comparator in a successive approximation register (SAR) (e.g., SAR 316). The multiple digital values ​​stored in the SAR may represent the inductance after multiple cycles of driving the switch at different slew rates. In some aspects, selecting a path in the switch driver involves selecting the path from among the multiple paths in the switch driver based on the multiple digital values ​​in the SAR.

[0092] According to certain aspects, operation 700 may further involve selecting one or more parameters for the IC package based on the detected at least one of the resistance, inductance, or capacitance of the lumped parameter model, and adjusting operation of one or more circuit components of the IC package based on the selected one or more parameters.

[0093] Example aspects

[0094] In addition to the various aspects described above, specific combinations of the various aspects are also within the scope of the present disclosure, some of which are described in detail below:

[0095] Aspect 1: An integrated circuit (IC) package, comprising: a pin for coupling to a component outside the IC package; and at least one of a resistance detector, an inductance detector, or a capacitance detector, which is coupled to the pin and is configured to respectively detect at least one of resistance, inductance, or capacitance of a lumped parameter model for a component outside the IC package and for parasitic effects associated with at least one of the component, the pin, or a connection between the component and the pin.

[0096] Aspect 2: The IC package of aspect 1, wherein at least one of the resistance detector, the inductance detector, or the capacitance detector is configured to operate in the time domain.

[0097] Aspect 3: The IC package of aspect 1 or 2, wherein at least one of the resistance detector, the inductance detector, or the capacitance detector is configured to output a time-domain drive signal and sense a time-domain response signal.

[0098] Aspect 4: The IC package of any of the preceding aspects, further comprising: one or more switches coupled between the pins and at least one of the resistance detector, the inductance detector, or the capacitance detector.

[0099] Aspect 5: An IC package as described in any of the preceding aspects, wherein the capacitance detector includes: a current source; a switch coupled between the current source and the pin; an analog-to-digital converter (ADC); and a sample and hold circuit coupled between the pin and the ADC.

[0100] Aspect 6: An IC package as described in Aspect 5, wherein the capacitance detector is configured to: close a switch at the beginning of a time period to charge the capacitance element in the lumped parameter model using the current from the current source; open the switch at the end of the time period; use a sampling and holding circuit to sample the voltage of the pin during the time period and hold the sampled voltage at the end of the time period; use an ADC to quantize the held voltage; and determine the capacitance of the capacitance element in the lumped parameter model based on the value of the current, the time length of the time period, and the quantized voltage.

[0101] Aspect 7: An IC package as described in any of the preceding aspects, wherein the resistance detector includes: a first current source configured to supply a first current; a first switch coupled between the first current source and a pin; a second current source configured to supply a second current, the second current being different from the first current; a second switch coupled between the second current source and the pin; a first sample and hold circuit having an input coupled to the pin; a second sample and hold circuit having an input coupled to the pin; and an ADC having one or more inputs coupled to an output of the first sample and hold circuit and an output of the second sample and hold circuit.

[0102] Aspect 8: An IC package as described in Aspect 7, wherein the resistance detector is configured to: close the first switch at the beginning of a first time period to provide a first current to the pin; open the first switch at the end of the first time period; use a first sampling and holding circuit to sample a first voltage of the pin during the first time period and hold the sampled first voltage at the end of the first time period; close the second switch at the beginning of a second time period to provide a second current to the pin; open the second switch at the end of the second time period; use a second sampling and holding circuit to sample a second voltage of the pin during the second time period and hold the sampled second voltage at the end of the second time period; quantize the voltage difference between the held first voltage and the held second voltage using an ADC; and determine the resistance of the resistance element in the lumped parameter model based on the value of the first current, the value of the second current, and the quantized voltage difference.

[0103] Aspect 9: An IC package as described in Aspect 8, wherein a first product of the value of the first current and the time length of the first time period is configured to be equal to a second product of the value of the second current and the time length of the second time period (so that the capacitance of the lumped parameter model becomes negligible).

[0104] Aspect 10: An IC package as described in any of Aspects 7-9, wherein the resistance detector further includes: an amplifier having a first input coupled to the output of the first sample and hold circuit, a second input coupled to the output of the second sample and hold circuit, and an output coupled to one or more inputs of the ADC.

[0105] Aspect 11: An IC package as described in Aspect 10, wherein the resistance detector is configured to: close the first switch at the beginning of a first time period to provide a first current to the pin; open the first switch at the end of the first time period; use a first sampling and holding circuit to sample a first voltage of the pin during the first time period and hold the sampled first voltage at the end of the first time period; close the second switch at the beginning of a second time period to provide a second current to the pin; open the second switch at the end of the second time period; use a second sampling and holding circuit to sample a second voltage of the pin during the second time period and hold the sampled second voltage at the end of the second time period; use an amplifier to amplify the voltage difference between the held first voltage and the held second voltage; use an ADC to quantize the amplified voltage difference; and determine the resistance of the resistance element in the lumped parameter model based on the value of the first current, the value of the second current, and the quantized voltage difference.

[0106] Aspect 12: An IC package as described in any of the preceding aspects, wherein the inductance detector includes: a pulse generator; a switch coupled between a power rail and a pin; and a switch driver coupled between an output of the pulse generator and a control input of the switch, the switch driver being configured to drive the switch using a plurality of different conversion rates.

[0107] Aspect 13: An IC package as described in Aspect 12, wherein the inductance detector further includes: a peak detector having an input coupled to the pin; a comparator having a first input coupled to the output of the peak detector and having a second input coupled to a reference voltage node; and a successive approximation register having an input coupled to the output of the comparator.

[0108] Aspect 14: The IC package of aspect 13, wherein the peak detector comprises an AC coupled diode peak detector.

[0109] Aspect 15: An IC package as described in Aspect 13 or 14, wherein the peak detector includes: a first transistor having a drain coupled to a pin; a first capacitor coupled between the drain and the gate of the first transistor; and a second capacitor coupled between the source of the first transistor and a reference potential node of the peak detector.

[0110] Aspect 16: An IC package as described in Aspect 15, wherein the peak detector further includes: a second transistor having a drain coupled to the source of the first transistor and having a source coupled to the second capacitor and the first input of the comparator; a third transistor having a source coupled to the gate of the second transistor; a current source coupled between a power rail and the drain of the third transistor; and a fourth transistor having a drain coupled to the gate of the second transistor and the source of the third transistor, and having a source coupled to the reference potential node of the peak detector.

[0111] Aspect 17: The IC package of aspect 16, wherein the peak detector further comprises a switched capacitor array coupled between the gate of the second transistor and a reference potential node of the peak detector.

[0112] Aspect 18: The IC package of any of Aspects 13-17, wherein the switch driver comprises: a plurality of drive circuits selectively coupled between the output of the pulse generator and the control input of the switch.

[0113] Aspect 19: The IC package of Aspect 18, further comprising: logic having an input coupled to the output of the successive approximation register and having an output coupled to a control input of a switch in the switch driver, the logic being configured to control selection of the drive circuit based on a digital value in the successive approximation register.

[0114] Aspect 20: The IC package of aspect 18 or 19, wherein at least one of the plurality of driver circuits comprises a plurality of inverters connected in series.

[0115] Aspect 21: A method for parameter determination, comprising: coupling at least one of a resistance detector, an inductance detector, or a capacitance detector inside an IC package to a pin of the IC package, the pin being coupled to a component outside the IC package; and using at least one of the resistance detector, the inductance detector, or the capacitance detector inside the IC package to respectively detect at least one of the resistance, inductance, or capacitance of a lumped parameter model for a component outside the IC package and for parasitic effects associated with at least one of the component, the pin, or a connection between the component and the pin.

[0116] Aspect 22: The method of aspect 21, wherein detecting comprises operating at least one of a resistance detector, an inductance detector, or a capacitance detector in the time domain.

[0117] Aspect 23: The method of aspect 21 or 22, wherein the detecting comprises: generating a driving signal in an IC package; outputting the driving signal to the component via a pin of the IC package; and receiving a response signal from the component and the parasitic effect via the pin of the IC package.

[0118] Aspect 24: The method of aspect 23, wherein the drive signal is a time-domain drive signal, and wherein the response signal is a time-domain response signal.

[0119] Aspect 25: The method of any of Aspects 21-24, wherein coupling comprises closing one or more switches coupled between the pin and at least one of a resistance detector, an inductance detector, or a capacitance detector.

[0120] Aspect 26: A method as described in any of Aspects 21-25, wherein detecting capacitance includes: closing a switch coupled between a current source and a pin at the beginning of a time period to charge a capacitive element in a lumped parameter model with a current from the current source; opening the switch at the end of the time period; sampling a voltage of the pin during the time period with a sampling and holding circuit; holding the sampled voltage at the end of the time period with a sampling and holding circuit; quantizing the held voltage with an ADC; and determining the capacitance of the capacitive element in the lumped parameter model based on the value of the current, the length of time of the time period, and the quantized voltage.

[0121] Aspect 27: A method as described in any of Aspects 21-26, wherein the detection resistor includes: closing a first switch coupled between a first current source and a pin at the beginning of a first time period to provide a first current from the first current source to the pin; opening the first switch at the end of the first time period; using a first sampling and holding circuit to sample a first voltage of the pin during the first time period, and maintaining the sampled first voltage at the end of the first time period; closing a second switch coupled between a second current source and the pin at the beginning of a second time period to provide a second current from the second current source to the pin; opening the second switch at the end of the second time period; using a second sampling and holding circuit to sample a second voltage of the pin during the second time period, and maintaining the sampled second voltage at the end of the second time period; quantizing a voltage difference between the maintained first voltage and the maintained second voltage using an ADC; and determining the resistance of the resistor element in the lumped parameter model based on the value of the first current, the value of the second current, and the quantized voltage difference.

[0122] Aspect 28: The method of Aspect 27, wherein a first product of the value of the first current and the time length of the first period is substantially equal to a second product of the value of the second current and the time length of the second period, so that the capacitance of the lumped parameter model becomes negligible.

[0123] Aspect 29: The method of aspect 27 or 28, wherein detecting the resistance further comprises amplifying a voltage difference between the maintained first voltage and the maintained second voltage, and wherein quantizing comprises quantizing the amplified voltage difference.

[0124] Aspect 30: The method of any of Aspects 21-29, wherein detecting the inductance comprises: using a SAR-based charging scheme to charge the component via the pin over a plurality of cycles.

[0125] Aspect 31: A method as described in any of Aspects 21-30, wherein detecting inductance includes: generating a pulse using a pulse generator; selecting a path from a plurality of paths in a switch driver; modifying a conversion rate of the pulse using the selected path in the switch driver; and driving a switch coupled between a power rail and a pin using the pulse with the modified conversion rate.

[0126] Aspect 32: A method as described in Aspect 31, wherein detecting the inductance further includes: detecting a peak value of a voltage signal received from a pin; comparing the detected peak value of the voltage signal with a reference voltage using a comparator; and storing the digital value output from the comparator in a successive approximation register, wherein the multiple digital values ​​stored in the successive approximation register represent the inductance after multiple cycles of driving the switch at different conversion rates.

[0127] Aspect 33: The method of aspect 32, wherein selecting comprises selecting a path from among a plurality of paths in the switch driver based on a plurality of digital values ​​in the successive approximation register.

[0128] Aspect 34: The method as described in any of Aspects 21-33 further includes: selecting one or more parameters for the IC package based on at least one detected item of resistance, inductance or capacitance of the lumped parameter model; and adjusting the operation of one or more circuit components of the IC package based on the selected one or more parameters.

[0129] Aspect 35: An IC package comprising: a pin for coupling to a component outside the IC package; and at least one of: a unit for detecting the resistance of a lumped parameter model for the component outside the IC package and for parasitic effects associated with at least one of the component, the pin, or a connection between the component and the pin, a unit for detecting the inductance of the lumped parameter model, or a unit for detecting the capacitance of the lumped parameter model.

[0130] Aspect 36: The IC package of aspect 35, further comprising: means for selectively coupling at least one of the means for detecting resistance, the means for detecting inductance, or the means for detecting capacitance to a pin of the IC package.

[0131] Aspect 37: The IC package of aspect 35 or 36, wherein at least one of the unit for detecting resistance, the unit for detecting inductance, or the unit for detecting capacitance is configured to output a time-domain driving signal and sense a time-domain response signal.

[0132] Additional Considerations

[0133] The various operations of the above method can be performed by any suitable unit capable of performing the corresponding functions. The unit may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs) or processors. In general, where there are operations shown in the accompanying drawings, those operations may have corresponding paired units plus functional components with similar numbers.

[0134] For example, the unit for detecting resistance may include a resistance detector such as in Figure 2 and Figure 5 The resistance detector 230 shown in FIG. 2 is a block diagram of a device for detecting inductance. The unit for detecting inductance may include an inductance detector such as Figure 2 and Figure 3 The inductance detector 220 depicted in FIG. The unit for detecting capacitance may include a capacitance detector such as in Figure 2 and Figure 6The unit for selective coupling may include one or more switches, such as in Figure 2 The switch network 215 is shown in FIG.

[0135] As used herein, the term "determining" includes a variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, a database, or another data structure), ascertaining, etc. In addition, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. Furthermore, "determining" may include resolving, selecting, choosing, establishing, etc.

[0136] As used herein, a phrase referring to "at least one" of a list of items refers to any combination of those items, including single members. As an example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc or any other ordering of a, b, and c).

[0137] The method disclosed herein includes one or more steps or actions for implementing the method. The method steps and / or actions can be interchanged with each other without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions can be modified without departing from the scope of the claims.

[0138] It is to be understood that the claims are not limited to the precise configuration and components shown above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. An integrated circuit (IC) package, comprising: pins for coupling to components external to the IC package; as well as At least one of a resistance detector, an inductance detector, or a capacitance detector coupled to the pin and configured to detect at least one of resistance, inductance, or capacitance of a lumped parameter model for the component external to the IC package and for parasitic effects associated with at least one of the component, the pin, or a connection between the component and the pin, respectively.

2. The IC package according to claim 1, wherein: The at least one of the resistance detector, the inductance detector, or the capacitance detector is configured to operate in the time domain.

3. The IC package according to claim 1, wherein: The at least one of the resistance detector, the inductance detector, or the capacitance detector is configured to output a time-domain drive signal and sense a time-domain response signal.

4. The IC package of claim 1 , further comprising: One or more switches are coupled between the pin and the at least one of the resistance detector, the inductance detector, or the capacitance detector.

5. The IC package according to claim 1, wherein: The capacitance detector comprises: Current source; a switch coupled between the current source and the pin; Analog-to-digital converter (ADC); and A sample and hold circuit is coupled between the pin and the ADC.

6. The IC package according to claim 5, wherein: The capacitance detector is configured as: closing the switch at the beginning of a time period to charge the capacitive element in the lumped parameter model with the current from the current source; opening the switch at the end of the time period; using the sample and hold circuit to sample the voltage of the pin during the period and to hold the sampled voltage at the end of the period; quantizing the maintained voltage using the ADC; as well as The capacitance of the capacitive element in the lumped parameter model is determined based on the value of the current, the time length of the period, and the quantized voltage.

7. The IC package according to claim 1, wherein: The resistance detector comprises: a first current source configured to supply a first current; a first switch coupled between the first current source and the pin; a second current source configured to supply a second current, the second current being different from the first current; a second switch coupled between the second current source and the pin; a first sample and hold circuit having an input coupled to the pin; a second sample and hold circuit having an input coupled to the pin; and An analog-to-digital converter (ADC) has one or more inputs coupled to the output of the first sample and hold circuit and the output of the second sample and hold circuit.

8. The IC package according to claim 7, wherein: The resistance detector is configured as: closing the first switch at the beginning of a first time period to provide the first current to the pin; turning off the first switch at the end of the first time period; Using the first sampling and holding circuit, sampling the first voltage of the pin during the first period, and holding the sampled first voltage at the end of the first period; closing the second switch at the beginning of a second time period to provide the second current to the pin; turning off the second switch at the end of the second time period; Using the second sampling and holding circuit, sampling the second voltage of the pin during the second period, and holding the sampled second voltage at the end of the second period; quantifying a voltage difference between the maintained first voltage and the maintained second voltage using the ADC; as well as The resistance of a resistance element in the lumped parameter model is determined based on a value of the first current, a value of the second current, and a quantized voltage difference.

9. The IC package according to claim 8, wherein: A first product of a value of the first current and a time length of the first period is configured to be equal to a second product of a value of the second current and a time length of the second period.

10. The IC package according to claim 7, wherein: The resistance detector further includes an amplifier having a first input coupled to the output of the first sample and hold circuit, having a second input coupled to the output of the second sample and hold circuit, and having an output coupled to the one or more inputs of the ADC.

11. The IC package according to claim 10, wherein: The resistance detector is configured as: closing the first switch at the beginning of a first time period to provide the first current to the pin; turning off the first switch at the end of the first time period; Using the first sampling and holding circuit, sampling the first voltage of the pin during the first period, and holding the sampled first voltage at the end of the first period; closing the second switch at the beginning of a second time period to provide the second current to the pin; turning off the second switch at the end of the second time period; Using the second sampling and holding circuit, sampling the second voltage of the pin during the second period, and holding the sampled second voltage at the end of the second period; amplifying a voltage difference between the maintained first voltage and the maintained second voltage using the amplifier; quantizing the amplified voltage difference using the ADC; as well as The resistance of a resistance element in the lumped parameter model is determined based on a value of the first current, a value of the second current, and a quantized voltage difference.

12. The IC package according to claim 1, wherein: The inductance detector comprises: Pulse generator; a switch coupled between the power rail and the pin; and A switch driver is coupled between the output of the pulse generator and a control input of the switch, the switch driver being configured to drive the switch at a plurality of different slew rates.

13. The IC package according to claim 12, wherein: The inductance detector further comprises: a peak detector having an input coupled to the pin; a comparator having a first input coupled to the output of the peak detector and having a second input coupled to a reference voltage node; and A successive approximation register has an input coupled to the output of the comparator.

14. The IC package according to claim 13, wherein: The peak detector comprises an AC coupled diode peak detector.

15. The IC package of claim 13, wherein: The peak detector comprises: a first transistor having a drain coupled to the pin; a first capacitor coupled between the drain and the gate of the first transistor; and A second capacitor is coupled between the source of the first transistor and a reference potential node of the peak detector.

16. The IC package of claim 15, wherein: The peak detector further comprises: a second transistor having a drain coupled to the source of the first transistor and having a source coupled to the second capacitor and the first input of the comparator; a third transistor having a source coupled to the gate of the second transistor; a current source coupled between the power rail and a drain of the third transistor; and a fourth transistor having a drain coupled to the gate of the second transistor and the source of the third transistor, and having a source coupled to the reference potential node of the peak detector.

17. The IC package of claim 16, wherein: The peak detector further includes a switched capacitor array coupled between a gate of the second transistor and the reference potential node of the peak detector.

18. The IC package of claim 13, wherein: The switch driver includes a plurality of drive circuits selectively coupled between the output of the pulse generator and the control input of the switch.

19. The IC package of claim 18, further comprising: Logic having an input coupled to the output of the successive approximation register and having an output coupled to a control input of a switch in the switch driver, the logic being configured to control selection of the driver circuit based on a digital value in the successive approximation register.

20. The IC package of claim 18, wherein: At least one of the plurality of drive circuits includes a plurality of inverters connected in series.

21. A method for determining a parameter, comprising: coupling at least one of a resistance detector, an inductance detector, or a capacitance detector inside an integrated circuit (IC) package to a pin of the IC package, the pin being coupled to a component outside the IC package; as well as Use at least one of the resistance detector, the inductance detector, or the capacitance detector inside the IC package to respectively detect at least one of the resistance, inductance, or capacitance of a lumped parameter model for a component outside the IC package and for parasitic effects associated with at least one of the component, the pin, or a connection between the component and the pin.

22. The method according to claim 21, wherein: The detecting includes operating the at least one of the resistance detector, the inductance detector, or the capacitance detector in a time domain.

23. The method according to claim 21, wherein: The detection includes: generating a drive signal in the IC package; outputting the drive signal to the component via the pin of the IC package; and Response signals from the components and the parasitic effects are received via the pins of the IC package.

24. The method according to claim 23, wherein: The drive signal is a time-domain drive signal, and wherein the response signal is a time-domain response signal.

25. The method according to claim 21, wherein: The coupling includes closing one or more switches coupled between the pin and the at least one of the resistance detector, the inductance detector, or the capacitance detector.

26. The method of claim 21, wherein: Detecting the capacitance includes: closing a switch coupled between a current source and the pin at the beginning of a time period to charge a capacitive element in the lumped parameter model with a current from the current source; opening the switch at the end of the time period; sampling the voltage of the pin using a sample and hold circuit during the period; holding the sampled voltage with the sample and hold circuit at the end of the time period; quantizing the held voltage using an analog-to-digital converter (ADC); and The capacitance of the capacitive element in the lumped parameter model is determined based on the value of the current, the time length of the period, and the quantized voltage.

27. The method of claim 21, wherein: Detecting the resistance includes: At the beginning of a first time period, closing a first switch coupled between a first current source and the pin to provide a first current from the first current source to the pin; turning off the first switch at the end of the first time period; Using a first sampling and holding circuit, sampling a first voltage of the pin during the first period, and holding the sampled first voltage at the end of the first period; closing a second switch coupled between a second current source and the pin at the beginning of a second time period to provide a second current from the second current source to the pin; turning off the second switch at the end of the second time period; Using a second sampling and holding circuit, sampling a second voltage of the pin during the second period, and holding the sampled second voltage at the end of the second period; quantifying a voltage difference between the maintained first voltage and the maintained second voltage using an analog-to-digital converter (ADC); and The resistance of a resistance element in the lumped parameter model is determined based on a value of the first current, a value of the second current, and a quantized voltage difference.

28. The method according to claim 27, wherein: A first product of a value of the first current and a time length of the first period is substantially equal to a second product of a value of the second current and a time length of the second period, so that the capacitance of the lumped parameter model becomes negligible.

29. The method according to claim 27, wherein: Detecting the resistance further comprises: The voltage difference between the maintained first voltage and the maintained second voltage is amplified, and wherein the quantizing includes quantizing the amplified voltage difference.

30. The method of claim 21, wherein: Detecting the inductance includes: A successive approximation register (SAR) based charging scheme is used to charge the component via the pin over multiple cycles.

31. The method of claim 21, wherein: Detecting the inductance includes: generating a pulse using a pulse generator; Selecting a path from among a plurality of paths in a switch actuator; modifying a slew rate of the pulses using the selected path in the switch driver; and A switch coupled between a power rail and the pin is driven with the pulse having the modified slew rate.

32. The method according to claim 31, wherein: Detecting the inductance further comprises: detecting a peak value of a voltage signal received from the pin; comparing the detected peak value of the voltage signal with a reference voltage using a comparator; and The digital value output from the comparator is stored in a successive approximation register, wherein the plurality of digital values ​​stored in the successive approximation register represent the inductance after a plurality of cycles of driving the switch at different slew rates.

33. The method of claim 32, wherein: The selecting includes selecting the path from among the plurality of paths in the switch driver based on the plurality of digital values ​​in the successive approximation register.

34. The method of claim 21, further comprising: selecting one or more parameters for the IC package based on the detected at least one of the resistance, the inductance, or the capacitance of the lumped parameter model; as well as Operation of one or more circuit components of the IC package is adjusted based on the selected one or more parameters.

35. An integrated circuit (IC) package, comprising: pins for coupling to components external to the IC package; as well as At least one of: a unit for detecting the resistance of a lumped parameter model for the component external to the IC package and for parasitic effects associated with at least one of the component, the pin, or a connection between the component and the pin, a unit for detecting the inductance of the lumped parameter model, or a unit for detecting the capacitance of the lumped parameter model.

36. The IC package of claim 35, further comprising: Means for selectively coupling the at least one of the means for detecting resistance, the means for detecting inductance, or the means for detecting capacitance to the pin of the IC package.

37. The IC package of claim 35, wherein: The at least one of the unit for detecting resistance, the unit for detecting inductance, or the unit for detecting capacitance is configured to output a time-domain driving signal and sense a time-domain response signal.

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