Electronic equipment and video coding and decoding method

Abstract

A method of performing decoder-end intra mode derivation (DIMD) that reduces hardware cost is provided. A video encoder receives data of a pixel block to be encoded or decoded as a current block of a current picture of a video. The video encoder derives a histogram of gradient (HoG) having a plurality of data pitches corresponding to a plurality of different intra prediction angles. A value of a cumulative gradient amplitude of each data pitch is stored, and the value is limited by a specific bit length. Each data pitch stores a value of cumulative gradient amplitude limited by a specific bit length. The video encoder identifies two or more intra prediction modes based on the HoG. The video encoder generates an intra prediction of one of the current blocks based on the identified two or more intra prediction modes. The video encoder encodes and decodes the current block using the generated intra prediction.

Description

[0001] Cross-pressure in related applications

[0002] This article claims priority to U.S. Provisional Application No. 63 / 351,505, filed on June 13, 2022, the subject matter of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to video coding, and more particularly to hardware-supported decoder-side intra mode derivation and prediction (DIMD). Background Art

[0004] Unless otherwise indicated herein, the methods described in this section are not prior art to the request data spacing listed below and are not admitted to be prior art by inclusion in this section.

[0005] High-efficiency video coding (HEVC) is an international video coding standard developed by the Joint Collaborative Team on Video Coding (JCT-VC). HEVC is a block-based discrete cosine transform (DCT)-like hybrid motion compensation coding and decoding architecture. The basic unit of compression is called a coding unit (CU), which is a square block of 2Nx2N pixels (pixel block), and each CU can be continuously divided into smaller CU units until a predefined minimum size is reached. Each CU includes one or more prediction units (PU).

[0006] Versatile video coding (VVC) is the latest video coding standard developed by the Joint Video Expert Team (JVET) of ITU-T SG1 6WP3 and ISO / IEC JTC1 / SC29 / WG11. The input video signal is predicted by a reconstructed signal from the coded image region. The prediction residual signal is processed by block transform. The transform coefficients are quantized and entropy coded in the bitstream along with other information. The reconstructed signal is generated by inverse transformation of the prediction signal and the reconstructed residual signal by de-quantizing the transform coefficients. The reconstructed signal is further processed by in-loop filtering to remove coding artifacts. The decoded image is stored in a frame buffer for prediction of subsequent images of the input video signal.

[0007] In VVC, a coded image is divided into non-overlapping square block areas, which are represented by related coding tree units (CTUs). A plurality of leaf nodes on a coding tree correspond to the coding units (CUs). A coded image can be represented as a set of slices, each slice corresponding to a positive integer number of CTUs. The independent CTUs in a slice are processed in raster-scan order. A bidirectional prediction (B) slice can be decoded using intra prediction or inter prediction and up to two motion vectors and reference indices to predict the sample values ​​of each block. A prediction (P) slice is decoded using intra prediction or inter prediction and up to one motion vector and reference indices to predict the sample values ​​of each block. An intra (I) slice is decoded only using intra prediction.

[0008] A CTU can be allocated into one or more non-overlapping coding units (CUs) using a nested multi-type-tree (MTT) structured quadtree (QT) to accommodate a variety of local dynamic and texture characteristics. A CU can be split into smaller CUs in five ways: quadtree partitioning, vertical binary tree partitioning, horizontal binary tree partitioning, vertical center-side ternary tree partitioning, and horizontal center-side ternary tree partitioning.

[0009] Each CU includes one or more prediction units (PUs). The above prediction units and the associated CU syntax form a basic unit for signaling the predictor information. A specified prediction procedure is used to predict the values ​​of the relevant pixel samples within the PU. Each CU may include one or more transform units (TUs) to represent prediction residual blocks. A transform unit (TU) includes a transform block (TB) of luma samples and two transform blocks of corresponding chroma samples, and each TB corresponds to a residual block of samples of a single color component. A positive integer transform is applied to a transform block. The level values ​​of the quantization coefficients are entropy encoded and decoded in the bitstream together with other information. Among them, coding tree block (CTB), coding block (CB), prediction block (PB) and transform block (TB) are defined to specify a two-dimensional sample array of a single color component associated with CTU, CU, PU and TU respectively. Therefore, a CTU is composed of a luma CTB, two chroma CTBs, and related syntax elements. The same can be said for CU, PU, ​​and TU.

[0010] For each inter-predicted CU, dynamic parameters consisting of a motion vector, a reference picture index and a reference picture list usage index, and other additional information are used for the generation of inter-prediction samples. The above dynamic parameters can be signaled in an explicit or implicit way. When a CU is encoded in skip mode, the above CU is associated with a PU and has no significant residual coefficients, coded motion vector delta or reference picture index. If the above dynamic parameters of the current CU come from neighboring CUs (including temporal and spatial neighbors) and the additional schedule brought by VVC, a merge mode will be specified. The above merge mode can be applied to any inter-predicted CU. An alternative to the above merge mode is the explicit transmission of dynamic parameters, where the motion vector, the corresponding reference picture index of each reference picture list, the reference picture list usage flag and other necessary information are explicitly passed to each CU. Summary of the invention

[0011] The following description is a preferred implementation of the invention, and its purpose is to describe the basic spirit of the invention, but it is not intended to limit the invention. The actual content of the invention must refer to the scope of the subsequent patent application.

[0012] Some embodiments of the present invention provide methods for performing decoder-side intra mode derivation (DIMD) with reduced hardware cost. A video codec receives data of a pixel block to be encoded or decoded as a current block of a current picture of a video. The video encoder derives a histogram of gradient (HoG) having a plurality of data spacings corresponding to a plurality of different intra prediction angles. A value of an accumulated gradient amplitude for each data spacing is stored, and the value is limited to a specific bit length. The video encoder identifies two or more intra prediction modes based on the HoG. The video encoder generates an intra prediction of the current block based on the two or more intra prediction modes. The video encoder encodes or decodes the current block using intra prediction.

[0013] In some embodiments, the stored cumulative gradient amplitude is clamped to be less than a specific value based on a specific bit length. In some embodiments, the specific bit length is 18 bits. In some embodiments, the specific bit length can be 12, 13, 14, 15, 16, 17, 18, 19, or 20 bits.

[0014] In some embodiments, two or more intra-frame prediction modes are identified from the data spacing of the HoG by a comparator structure having one or more N-input M-output comparator components. Each of the N-input M-output comparators selects M maximum values ​​from N values, where M and N are both positive integers and N>M≥2. Each input of the N-input M-output comparator component includes a value stored in the data spacing of the HoG and an index configured at the above data spacing. The index is attached to the value as the least significant bit of the input, and the index can be reversed in bits. In some embodiments, at least one input or at least one output of the N-input M-output comparator component is limited to a specific bit length.

[0015] In some embodiments, two or more intra prediction modes are identified from a plurality of data intervals of the HoG by two or more comparator trees, each comparator tree identifying a different intra prediction mode. A first comparator tree identifies a first intra prediction mode from a plurality of data intervals of the HoG having odd indices, and a second comparator tree identifies a second intra prediction mode from a plurality of data intervals of the HoG having even indices. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following drawings are included to provide a further understanding of the present invention and are incorporated into and constitute a part of the present invention. The drawings illustrate embodiments of the present invention and are used together with the description thereof to explain the principles of the present invention. It should be noted that the drawings are not necessarily drawn to scale, as some components may be represented as not proportional to the size in actual implementation in order to clearly illustrate the concepts of the present invention.

[0017] Figure 1 Several intra prediction modes in different directions are shown.

[0018] Figure 2A , 2B Conceptual illustration of multiple top and left reference templates with extended lengths to support wide-angle directional modes for non-square blocks of different aspect ratios.

[0019] Figure 3 It is shown how to utilize decoder-side intra mode derivation (DIMD) to indirectly derive an intra prediction for a current block.

[0020] Figure 4 It is conceptually demonstrated how to apply a complex comparator tree to the data spacing of odd-indexed and even-indexed HoGs respectively to identify DIMD intra-mode.

[0021] Figure 5A , 5B A cascade structure of a plurality of 3-input 2-output devices is shown, which is configured to generate a DIMD intra-frame mode.

[0022] Figure 6 An example of a video encoder that can implement DIMD is shown.

[0023] Figure 7 Several parts of a video encoder implementing DIMD based on reduced bit length are shown.

[0024] Figure 8 A process for performing reduced bit length DIMD is conceptually presented.

[0025] Fig. 9 A video decoder 900 that may implement DIMD is shown as an example.

[0026] Fig.10 Portions of a video decoder 900 that may implement DIMD based on reduced bit length are shown.

[0027] Fig.11 A process 1100 for implementing a reduced bit length DIMD is conceptually shown.

[0028] Fig.12An electronic system implemented in some embodiments of the present invention is conceptually illustrated. DETAILED DESCRIPTION

[0029] In the following detailed description, many specific details are described by way of example to provide a thorough understanding of the relevant teachings. Any variations, derivations and / or extensions based on the teachings described herein are within the scope of the present invention. In some cases, well-known methods, procedures, components and / or circuits associated with one or more implementation examples disclosed herein are described at a relatively high level without details to avoid unnecessarily obscuring the embodiments of the teachings of the present invention.

[0030] I. Intra-frame prediction mode

[0031] The intra prediction method uses a reference tier adjacent to the current prediction unit (PU) and one of a plurality of intra prediction modes to generate a predictor for the current prediction unit. The direction of the intra prediction can be selected from a set of modes, which include a plurality of prediction directions. For each PU encoded using intra prediction, an index is used and encoded to select one of the intra prediction modes, thereby generating the corresponding prediction, and then the residual can be derived and transformed.

[0032] Figure 1 The different directions of the above intra prediction modes are shown. These intra prediction modes are called directional modes and are not included in DC mode or planar mode. Figure 1 There are 33 directional modes (V: vertical direction; H: horizontal direction), so H, H+1~H+8, H-1~H-7, V, V+I~V+8, V-1~V-8 are used for labeling. General directional modes can be represented as H+k mode or V+k mode, where k=±1, ±2, ...±8. Each of the above intra-frame prediction modes can also be called an intra-frame prediction angle. In order to capture the random edge directions shown in naturally generated movies, the number of directional intra-frame modes can be expanded from 33 (as used in HEVC) to 65, so that the range of k becomes ±1 to ±1 6. These more dense directional intra-frame prediction modes are applied to blocks of all sizes, and also to luma and chroma intra predictions. Together with DC mode and planar mode, the number of the above intra-frame prediction modes is 35 (or 67).

[0033] Among the above 35 (or 67) intra prediction modes, some modes (such as mode 3 or mode 5) are defined as the most probable mode (MPM) for intra prediction of the current prediction block. Instead of reducing the bit rate by signaling an index to select one of the above 35 (or 67) intra prediction modes, the encoder may reduce the bit rate by signaling an index to select one of the above MPMs. For example, the intra prediction mode for the left prediction block and the intra prediction mode for the upper prediction block are used as MPMs. When the intra prediction modes of the above two adjacent blocks use the same intra prediction mode, the above intra prediction mode can be used as the MPM. When only one of the above two adjacent blocks is available and is encoded as a directional mode, the two directional modes adjacent to the above directional mode can be used as MPMs. DC mode and planar mode are also identified as MPMs to fill in the available fields of the MPM set, especially when the upper or upper neighboring block is not available or is not coded as intra-frame prediction, or when the intra-frame prediction mode in the neighboring block is not a directional mode. If the intra-frame prediction mode of the current prediction block is one of the modes in the MPM set, one or two bits will be used to indicate which mode it is. Otherwise, the intra-frame prediction mode of the current block is different from any mode in the MPM set, and the current block will be encoded as a non-MPM mode. There are a total of 32 non-MPM modes, and a fixed-length (five-bit) encoding method is used to indicate this mode.

[0034] The MPM list is constructed based on the intra modes of the left and above neighboring blocks. Assuming that the mode of the left neighboring block is marked as Left and the mode of the above neighboring block is marked as Above, the unified MPM list can be constructed as follows:

[0035] When a neighboring block is unavailable, the intra mode of the neighboring block is set to the planar mode by default.

[0036] If Left and Above are both non-angle modes:

[0037] MPM List → {Planar, DC, V, H, V-4, V+4}

[0038] If one of Left and Above is in angular mode and the other is in non-angular mode:

[0039] Set the larger of Left and Above to Max

[0040] MPM list → {Planar, Max, Max-1, Max+1, Max-2, Max+2}

[0041] 1. If Left and Above are both angular modes and they are different:

[0042] Set the larger of Left and Above to Max

[0043] Set the smaller of Left and Above to Min

[0044] If Max minus Min equals 1:

[0045] οMPM list → {Planar, Left, Above, Min-1, Max+1, Min-2}

[0046] Otherwise, if Max minus Min is greater than or equal to 62:

[0047] οMPM list → {Planar, Left, Above, Min+1, Max-1, Min+2}

[0048] Otherwise, if Max minus Min equals 2:

[0049] οMPM list → {Planar, Left, Above, Min+1, Min-1, Max+1}

[0050] ·otherwise:

[0051] οMPM list → {Planar, Left, Above, Min-1, Min+1, Max-1}

[0052] -If Left and Above are both angular modes and they are the same:

[0053] ·MPM list → {Planar, Left, Left-1, Left+1, Left-2, Left+2}

[0054] The traditional angular intra prediction direction is defined as 45 degrees to -135 degrees clockwise. In VVC, some traditional angular intra prediction modes are adaptively replaced with wide-angle intra prediction modes for non-square blocks. The replaced modes can be indicated by the original mode index, which is remapped to the index of the wide-angle mode after parsing.

[0055] For some embodiments, the total number of intra prediction modes does not change (i.e., 67), and the intra mode coding method does not change. To support these prediction directions, an upper reference template of length 2W+1 and a left reference template of length 2H+1 are defined. FIGS. 2A and 2B conceptually illustrate the upper reference template and the left reference template being extended in length to support wide-angle directional modes for non-square blocks of different aspect ratios.

[0056] The number of wide-angle directional modes replaced depends on the aspect ratio of a block. The intra-frame prediction modes replaced for different blocks with different aspect ratios are shown in Table 1 below.

[0057] Table 1: Intra prediction modes replaced by wide angle mode

[0058]

[0059] II. Decoding intra-mode derivation

[0060] Decoder side intra mode derivation (DIMD) is a technique where two intra prediction modes / angles / directions are derived from neighboring reconstructed samples (or templates) of a block and the two predictors are combined with the planar mode predictor with weights from the gradient. The DIMD mode is used as an alternative prediction mode and is always checked in high complexity rate distortion optimization (RDO) mode. To indirectly derive the intra prediction mode for a block, both the encoder and decoder perform a texture gradient analysis. The process starts with a blank histogram of gradient (HoG) with 65 bins, corresponding to the 65 angular / directional intra prediction modes. The accumulated gradient amplitudes (also called bin values) of the bins are determined in the texture gradient analysis.

[0061] A video encoder implementing DIMD performs the following steps: In a first step, the video encoder selects a template of T=3 columns and rows from the left and above the current block respectively. This area is used as a reference for gradient-based intra-frame prediction mode derivation. In a second step, horizontal and vertical Sobel filters are applied to all 3x3 window positions and the center point is placed on the pixels in the middle row of the template. At each window position, the Sobel filter calculates the intensity in the pure horizontal or pure vertical direction and records it as Gx and Gy respectively. Then, the texture angle of the window is calculated as follows:

[0062] Angle = arctan(Gx / Gy)

[0063] The texture angle of the window can be converted into one of the 65 angular intra prediction modes by the above calculation. Once the intra prediction mode index of the current window is derived as idx, the amplitude of the data interval representing the intra prediction mode of the current window in HoG[idx] is updated by the following addition:

[0064] Amplitude (ampl) = |Gx| + |Gy|

[0065] Figure 3 Decoder-side intra mode derivation (DIMD) is shown to indirectly derive an intra prediction for a current block. An exemplary histogram of gradient (HoG) 310 is calculated by applying the above procedure for all pixel positions of a template 315, which includes pixel samples of a plurality of adjacent rows of a current block 300. When the HoG is calculated, the two histogram bins (M1 and M2) with the highest index among all data intervals are selected as the two indirectly derived intra prediction modes (IPM or DIMD intra modes) for the block. The predictions of the two IPMs are further combined with the planar mode to form the prediction of the DIMD mode. The prediction fusion is obtained by averaging the weights of the three predictions (M1, M2 and planar mode). To achieve this goal, the weight of the planar mode can be set to 21 / 64 (~1 / 3). The remaining 43 / 64 (~2 / 3) weights are allocated by the above HoG IPM according to the corresponding HoG histogram bar amplitude ratio. The above prediction fusion or combined prediction of DIMD can be written as:

[0066] Pred DIMD=(43*(w1*pred M1 +w2*pred M2 )+21*pred planar )>>6

[0067] w1=amp M1 / (amp M1 +amp M2 )

[0068] w2=amp M2 / (amp M1 +amp M2 )

[0069] In addition, the two indirectly derived intra prediction modes are added to the most probable mode (MPM) list, so the DIMD process is performed before the MPM list is constructed. The primary derived intra modes of a DIMD block are stored in a block and used to construct the MPM list of neighboring blocks.

[0070] More generally, the DIMD process can be used to generate K IPMs or DIMD intra modes, where K ≥ 2. The K IPMs are determined based on the K data intervals in the HoG with the K highest amplitude gradient accumulations. The K IPMs are used for a weighted summation to generate the DIMD intra prediction Pred DIMD .

[0071] III. Hard pulp for DIMD

[0072] Some embodiments of the present invention provide an implementation of a structured DIMD hardware that reduces hardware cost by limiting the maximum bit length representing the value (bin value) or amplitude of the HoG data bin. To generate the two DIMD intra-frame modes (M1 and M2), a comparison process is used to extract the indexes of the two data bins with the highest and second highest gradient accumulation values ​​in the HoG. In some embodiments, the comparison process is used to extract the indexes of more than two (e.g., 5) data bins with the highest gradient accumulation values.

[0073] In some embodiments, the video encoder implements a sequential loop that traverses all data spacings of the HoG and continuously uploads the indexes of the data spacings of two (or more) data spacings with the highest and second highest data spacing values ​​(e.g., M1 and M2) in the HoG. In some embodiments, when the loop goes from the data spacing with the highest data spacing value to the data spacing with the second highest data spacing value and encounters a value in the HoG that is the same as the highest or second highest data spacing value, the video encoder ignores the index of the HoG data spacing corresponding to the new value. In some embodiments, if the loop encounters the new value when going from the second highest data spacing value (M2) to the highest data spacing value (M1), the index of the second highest data spacing value (M2) is retained. On the other hand, if the loop encounters the new value when going from the highest data spacing value (M1) to the second highest data spacing value (M2), the index of the highest data spacing value (M1) is retained. However, the sequential loop is not easily convertible into a form suitable for parallel computing flow and hardware implementation.

[0074] Some embodiments of the present invention provide a HoG data distance comparison / selection architecture that is applicable to parallel operation flow or hardware implementation. More specifically, two comparison trees are used to identify two intra-mode candidates.

[0075] In some embodiments, data spacings with even indices are assigned to a first comparator tree to generate a first intra-mode candidate, which is the index associated with the highest data spacing value in the first comparator tree. If two data spacing values ​​are equal in a particular mode of the comparator tree, the data spacing with the larger (or smaller) index is retained based on a selection strategy predefined or indicated in the encoded video (e.g., sequence parameter set (SPS) header). The same process is applied to odd indices to obtain a second intra-mode candidate based on a second comparator tree. The two intra-mode candidates are then compared, and the one with the higher data spacing value is the first DIMD intra-mode (M1), and the other is the second DIMD intra-mode (M2).

[0076] Figure 4The application of comparator trees to the odd and even indices of HoG data pitches respectively to identify DIMD intra-frame modes is conceptually shown. As shown, a first comparator tree 410 is used to identify the data pitch with the highest HoG data pitch value among all odd-indexed data pitches, and a second comparator tree 420 is used to identify the data pitch with the highest HoG data pitch value among all even-indexed data pitches. Each comparator (CMP) is a 2-input 1-output comparator for comparing two data items corresponding to two data pitches, each data item of a data pitch including the data pitch value (accumulated gradient amplitude) of the data pitch, and the index of the data pitch is appended to the least significant bit (LSB) of the data pitch value. The appended index is used as a tiebreaker when comparing with another data item of a data pitch having the same data pitch value. In some embodiments, the indexes in the data items are reversed in bit units (~idx), so that the smaller index is preferred in the tiebreaker. The first comparator tree 410 outputs the index of the data pitch having the highest data pitch value among the odd-indexed data pitches, and the second comparator tree 420 outputs the index of the data pitch having the highest data pitch value among the even-indexed data pitches.

[0077] In some embodiments, a first comparator tree is not used for data spacings with odd indices, and a second comparator tree is not used for data spacings with even indices; instead, the first comparator tree 410 may be applied to data spacings with indices greater than a threshold, and the second comparator tree 420 may be applied to data spacings with indices less than or equal to the threshold. There are also other possible classification schemes for comparing and selecting the above two DIMD intra-frame modes. In some embodiments, more than two comparator trees are applied to more than two different subsets of HoG data spacings to identify more than two DIMD intra-frame modes. In some embodiments, instead of using multiple comparator trees to identify multiple DIMD intra-frame modes, one comparator tree is used multiple times for multiple subsets of different HoG data spacings to identify multiple DIMD intra-frame modes.

[0078] Reference Figure 4 , Figure 4 The presented method of separating odd and even indices is parallelizable and hardware friendly. However, the above method may produce different DIMD intra-frame patterns than the single sequence loop search.

[0079] In some embodiments, in order to identify the same DIMD intra-frame pattern as generated by the above single sequence loop search of the HoG, a plurality of N-input M-output comparator elements are connected in series to identify M DIMD intra-frame patterns from all possible HoG data spacings. Each N-input M-output element is configured to identify and output the M maximum values ​​among the N input values. Thus, for example, in some embodiments, a 3-input 2-output element (also known as 13M2 element) cascade structure (or comparator tree) can be used to identify 2 DIMD intra-frame patterns from all possible HoG data spacings.

[0080] Figure 5A , 5B A cascade structure of 3-input 2-output components configured to generate a DIMD intra-frame pattern is shown. The cascade structure can be used to generate the same DIMD intra-frame pattern as the single sequence loop search described above.

[0081] Figure 5A The implementation details of an I3M2 component 500 are shown, in which two simple input procedures Max and Min are implemented. A procedure Min is to select the smaller one after comparing two input items. A procedure Max is to select the larger one after comparing two input items. The above I3M2 component receives three input items (I0, I1, I2) and outputs the two largest input items (M1, M2). The smallest input item is discarded.

[0082] Figure 5B A concatenated structure 510 of a plurality of I3M2s is shown for generating / identifying two final outputs as DIMD intra-frame modes. The inputs to the concatenated structure 510 are data items corresponding to data intervals of a HoG 505 of a DIMD. Each data item includes a cumulative gradient amplitude value of a data interval of the HoG, and the index of the data interval is appended to the least significant bit (LSB) of the data interval. The appended index of the data interval is used as a tiebreaker when the data interval is compared to another data interval having the same gradient amplitude value via I3M2. The index is inverted in bit units so that when two data intervals have the same value (in the most significant bit (MSB) of each of the two data intervals), the data interval with the smaller index value is selected as the final result. In some embodiments, the index is not inverted, so that the data interval with the larger index value is preferred in the tiebreaker.

[0083] The two final outputs of the cascade structure 510 correspond to the two inputs as the first highest and second highest input values. The two highest data spacing values ​​and the corresponding indexes are extracted from the two final outputs. The indexes are reversed back to the original values ​​in bits. The two extracted data spacing values ​​are compared, and the index with the higher data spacing value is designated as the first DIMD intra-frame mode, while the index with the smaller data spacing value is designated as the second DIMD intra-frame mode.

[0084] The HoG data spacing of DIMD accumulates gradient values ​​for different gradient directions. The highest bit precision required for the accumulated gradient values ​​may be limited by the maximum CU size. The gradient values ​​of the L-shaped surrounding positions of the above size are based on the maximum gradient values ​​of the filter coefficients. However, the above highest bit precision will increase the hardware cost to a certain extent.

[0085] In some embodiments, the accuracy of the amplitude of the accumulated gradient value is limited to a certain bit length in order to reduce hardware cost. In some embodiments, the above accuracy is set to W bits for each HoG data interval, and the result generated after adding a new gradient value at a certain data interval is limited to a maximum of 2 w -1 bits until the result is stored back in the HoG memory of the data pitch. For some embodiments, the N-input M-output comparator components (e.g., I3M2) are serially connected into a comparator structure (e.g., comparator structure 510) to identify M (e.g., 2, 5, etc.) DIMD intra-frame modes, and the input and output of the comparator (e.g., I0, I1, I2, M1, M2) are limited by the W.

[0086] By choosing an appropriate value of W, the encoding gain of the DIMD process can be maintained even though the storage cost of the HoG data spacing values ​​is reduced. For some embodiments, it has been empirically determined that reducing the bit length to W=18 does not negatively impact the quality of the encoded video. Therefore, for some embodiments, the DIMD gradient amplitude accumulation is limited to W=18 bits, but W=16, 17, 19, or 20 may also be used as the bit length for the gradient amplitude accumulation.

[0087] Any of the above methods may be implemented by an encoder and / or a decoder. For example, any of the above methods may be implemented by an external / internal / prediction module of an encoder and / or an external / internal / prediction module of a decoder. In addition, any of the above methods may be implemented as a circuit coupled to an external / internal / prediction module of an encoder and / or a decoder to provide information required by the external / internal / prediction module.

[0088] IV. Video Encoder Examples

[0089] Figure 6 An exemplary video encoder 600 that implements decoder-side intra mode derivation (DIMD) is shown. As shown, the video encoder 600 receives an input video signal from a video source 605 and encodes the signal into a bitstream 695. The video encoder 600 has an entropy encoder 690 and a plurality of components or modules for encoding the signal from the video source 605, including at least a plurality of components selected from a transform module 610, a quantization module 611, an inverse quantization module 614, an inverse transform module 615, an intra picture estimation module 620, an intra prediction module 625, a motion compensation module 630, a motion estimation module 635, an in-loop filter 645, a reconstructed picture buffer 650, a motion vector (MV) buffer 665, and an MV prediction module 675. The motion compensation module 630 and the motion estimation module 635 are both part of an inter-frame prediction module 640 .

[0090] In some embodiments, the entropy encoder 690, the conversion module 610, the quantization module 611, the inverse quantization module 614, the inverse conversion module 615, the intra-picture estimation module 620, the intra-prediction module 625, the motion compensation module 630, the motion estimation module 635, the in-loop filter 645, the reconstructed picture buffer 650, the motion vector buffer 665, the MV prediction module 675 and the inter-prediction module 640 are software instruction modules executed by one or more processing units (such as a processor) of a computer device or an electronic device. In some embodiments, the entropy encoder 690, the transform module 610, the quantization module 611, the inverse quantization module 614, the inverse transform module 615, the intra picture estimation module 620, the intra prediction module 625, the motion compensation module 630, the motion estimation module 635, the in-loop filter 645, the reconstructed picture buffer 650, the motion vector buffer 665, the MV prediction module 675, and the inter prediction module 640 are hardware circuit modules implemented by one or more integrated circuits (ICs) of an electronic device. Although the entropy encoder 690, the transform module 610, the quantization module 611, the inverse quantization module 614, the inverse transform module 615, the intra picture estimation module 620, the intra prediction module 625, the motion compensation module 630, the motion estimation module 635, the in-loop filter 645, the reconstructed picture buffer 650, the motion vector buffer 665, the MV prediction module 675, and the inter prediction module 640 are shown as separate modules, some of the modules may be combined into one module.

[0091] The video source 605 provides a raw video signal, which shows the uncompressed pixel data of each frame of video. A subtractor 608 calculates the prediction residual 609 using the difference between the predicted pixel data 613 from the motion compensation module 630 or the intra prediction module 625 and the original video pixel data of the video source 605. The transform module 610 converts the difference (or the residual pixel data or the residual signal 609) into transform coefficients (e.g., by performing a discrete cosine transform (DCT)). The quantization module 611 quantizes the transform coefficients into quantized data (or quantized coefficients) 612, and encodes them into a bitstream 695 using an entropy encoder 690.

[0092] The inverse quantization module 614 de-quantizes the quantized data (or quantized coefficients) 612 to obtain conversion coefficients, and the inverse quantization module 615 performs inverse conversion on the conversion coefficients to generate a reconstructed residual 619. The reconstructed residual 619 and the predicted pixel data 613 are summed to generate reconstructed pixel data 617. In some embodiments, the reconstructed pixel data 617 is temporarily stored in a line buffer (not shown) for intra picture prediction and spatial MV prediction. The reconstructed pixel 617 is filtered by the in-loop filter 645 and stored in a reconstructed picture buffer 650. In some embodiments, the reconstructed picture buffer 650 is an external memory of the video encoder 600. In some embodiments, the reconstructed picture buffer 650 is an internal memory of the video encoder 600.

[0093] The intra picture estimation module 620 performs intra prediction based on the reconstructed pixel data 617 to generate intra prediction data. The intra prediction data is provided to the entropy encoder 690 for encoding into the bitstream 695. The intra prediction data is also utilized by the intra prediction module 625 to generate predicted pixel data 613.

[0094] The motion estimation module 635 performs intra prediction by generating a plurality of MVs to reference pixel data of a frame previously decoded and stored in the reconstructed picture buffer 650. The MVs are provided to the motion compensation module 630 to generate predicted pixel data.

[0095] Instead of encoding the complete exact MV in the bitstream, the video encoder 600 uses the MV prediction result to generate a predicted MV, and the difference between the MV used for motion compensation and the predicted MV is encoded as motion data residual and stored in the bitstream 695.

[0096] The MV prediction module 675 generates a predicted MV based on a reference MV generated for encoding a previous video frame (i.e., a motion compensated MV for performing motion compensation). The MV prediction module 675 retrieves a reference MV from a previous video frame in the MV buffer 665. The video encoder 600 stores the MV generated for the current video frame in the MV buffer 665 as a reference MV and uses it to generate a predicted MV.

[0097] The MV prediction module 675 uses the reference MV to create a predicted MV. The predicted MV can be calculated by spatial MV prediction or temporal MV prediction. The difference between the predicted MV and the motion compensation MV (MC MV) of the current frame (motion data residual) is encoded into the bitstream 695 by the entropy encoder 690.

[0098] The entropy encoder 690 uses entropy coding techniques (e.g., context-adaptive binary arithmetic coding (CABAC) or Huffman encoding as previously referenced) to encode various parameters and data into a bitstream 695. The entropy encoder 690 encodes the motion data residual and various header components, flags, and quantized transform coefficients 612 as syntax elements and encodes them into the bitstream 695. The bitstream 695 is in turn stored in a storage device or transmitted to a decoder via a communication medium (e.g., a network).

[0099] The in-loop filter 645 performs filtering or smoothing on the reconstructed pixel data 617 to reduce coding artifacts, especially at pixel block boundaries. In some embodiments, the filtering or smoothing performed by the in-loop filter 645 includes a deblocking filter (DBF), a sample adaptive offset (SAO), and / or an adaptive loop filter (ALF).

[0100] Figure 7 Portions of a video encoder 600 that can implement DIMD based on reduced bit length are shown. More specifically, components of an intra prediction module 625 of the video encoder 600 are shown. As shown, the intra prediction module 625 includes a gradient accumulation module 730, a HoG storage 720, an intra mode selection module 710, and an intra prediction generation module 740. The intra prediction module 625 can utilize the gradient accumulation module 730, the HoG storage 720, the intra mode selection module 710, and the intra prediction generation module 740 to perform DIMD intra prediction of luma and chroma components.

[0101] The gradient accumulation module 730 receives a plurality of adjacent samples of the current block from the reconstructed picture buffer 650 and calculates the gradient amplitudes of different intra-mode directions. The accumulated gradient amplitude of each HoG data interval is limited (e.g., clamped) to a maximum value of 2 based on a predefined bit length W. w The above (clamped) cumulative gradient amplitude is stored in the HoG memory 720 with values ​​corresponding to different data intervals of different intra-mode directions.

[0102] The intra-mode selection module 710 detects different data bins stored in the HoG storage 720 to identify two (or more) final DIMD intra-modes 715. The intra-mode selection module 710 includes a comparator tree 705 for comparing bin data items 725 of data bins from different HoGs to identify two or more data bins with the highest cumulative gradient amplitude. In some embodiments, the bin data item of each data bin includes a bin value at the MSB and a bin index at the LSB. In some embodiments of the above embodiments, the bin index of each data item is inverted in bit units.

[0103] In some embodiments, the comparator structure 705 includes a comparator tree for identifying two (or more) data intervals with the highest cumulative data interval values ​​among all HoG data intervals. The comparator tree is a series connection structure (e.g., series connection structure 510) of N-input M-output comparator components (e.g., I3M2 components).

[0104] In some embodiments, the comparator structure 705 includes two (or more) comparator trees for identifying two (or more) data pitches with the highest cumulative data pitch values. Each comparator tree is used to identify a data pitch from a different subset of the HoG data pitches (e.g., odd vs. even). Each of the two or more comparator trees is a cascade structure consisting of 2-input 1-output comparator components (comparator; CMP) (e.g., comparator trees 410 and 420).

[0105] The intra prediction generation module 740 generates an intra prediction 745 for the current block using one or more final intra prediction modes 715. The one or more final intra prediction modes 715 may include two or more DIMD intra modes, and the intra prediction generation module 740 may obtain a plurality of predictions / predictor variables from the reconstructed picture buffer 650 based on the DIMD intra modes. The predictor variables are mixed to generate the intra prediction 745 for use as the prediction pixel data 613.

[0106] Figure 8 A process 800 for performing DIMD with reduced bit length is conceptually shown. In some embodiments, one or more processing units (e.g., a processor) in a computing device for implementing the video encoder 600 execute the process 800 by executing instructions stored in a computer-readable medium. In some embodiments, an electronic device implementing the video encoder 600 executes the process 800.

[0107] The encoder receives (at block 810) data of a pixel block to be encoded as a current block of a current picture of a video.

[0108] The encoder (at block 820) derives a histogram of gradient (HoG) having a plurality of data intervals corresponding to different intra prediction angles. A value of a cumulative gradient amplitude for each data interval is stored, and the value is limited to a specific bit length. In some embodiments, the stored value of the cumulative gradient amplitude is clamped to be less than a specific value based on the specific bit length. In some embodiments, the specific bit length is 18 bits. In some embodiments, the specific bit length can be 12, 13, 14, 15, 16, 17, 18, 19, or 20 bits.

[0109] The encoder (at block 830) identifies two or more intra-prediction modes based on the HoG. In some embodiments, the two or more intra-prediction modes are identified from the data spacing of the HoG by a comparator structure having one or more N-input M-output comparator components. Each N-input M-output component selects M maximum values ​​from N values, where N and M are positive integers and N>M≥2. Each input of the N-input M-output comparator component includes a value stored in a data spacing of the HoG and an index assigned to the data spacing. The index is appended to the value as the least significant bit of the input, and the index can be inverted in bits. In some embodiments, at least one input or at least one output of the N-input M-output comparator component is limited to the specific bit length. In some embodiments, the two or more intra-prediction modes are identified from the data spacing of the HoG by two or more comparator trees, each of the comparator trees identifying a different intra-prediction mode. A first comparator tree identifies a first intra prediction mode from data intervals of a plurality of HoGs having odd indices, and a second comparator tree identifies a second intra prediction mode from data intervals of a plurality of HoGs having even indices. The encoder (at block 840) generates an intra prediction for the current block based on the identified two or more intra prediction modes. The encoder (at block 850) encodes the current block using the generated intra prediction to generate a prediction residual.

[0110] V. Video Decoder Example

[0111] In some embodiments, an encoder may indicate (or generate) one or more syntax elements in a bitstream, so that a decoder may parse the one or more syntax elements from the bitstream.

[0112] Fig. 9 An example video decoder 900 for implementing decoder-side intra mode derivation (DIMD) is shown. As shown, the video decoder 900 is an image decoding or video decoding circuit for receiving a bit stream 995 and decoding the bit stream into pixel data of a plurality of video frames for display. The video decoder 900 has some components or modules for decoding the bit stream 995, including some components selected from an inverse quantization module 911, an inverse transform module 910, an intra prediction module 925, a motion compensation module 930, an in-loop filter 945, a decoded picture buffer 950, an MV buffer 965, an MV prediction module 975, and a parser 990. The motion compensation module 930 is a part of an inter prediction module 940.

[0113] In some embodiments, the inverse quantization module 911, the inverse transformation module 910, the intra-frame prediction module 925, the motion compensation module 930, the in-loop filter 945, the decoded picture buffer 950, the MV buffer 965, the MV prediction module 975, the parser 990, and the inter-frame prediction module 940 are software instruction modules executed by one or more processing units (e.g., a processor) of a computing device. In some embodiments, the inverse quantization module 911, the inverse transformation module 910, the intra-frame prediction module 925, the motion compensation module 930, the in-loop filter 945, the decoded picture buffer 950, the MV buffer 965, the MV prediction module 975, the parser 990, and the inter-frame prediction module 940 are hardware circuit modules implemented by one or more ICs of an electronic device. Although the inverse quantization module 911, the inverse transform module 910, the intra prediction module 925, the motion compensation module 930, the in-loop filter 945, the decoded picture buffer 950, the MV buffer 965, the MV prediction module 975, the parser 990, and the inter prediction module 940 are shown as separate multiple modules, some modules may be combined into a single module.

[0114] The parser 990 (or entropy decoder) receives the bitstream 995 and performs initial parsing according to the syntax defined by a video coding or image coding standard. The parsed syntax elements include a plurality of header components, flags, and quantization data (or quantization coefficients) 912. The parser 990 uses entropy coding and decoding techniques (such as context-adaptive binary arithmetic coding (CABAC) or Huffman encoding) to parse different syntax elements.

[0115] The inverse quantization module 911 dequantizes the quantized data (or quantized coefficients) 912 to obtain transform coefficients 916, and the inverse transform module 910 performs inverse transform on the transform coefficients 916 to generate a reconstructed residual signal 919. The reconstructed residual signal 919 is added to the predicted pixel data 913 from the intra-frame prediction module 925 or the motion compensation module 930 to generate decoded pixel data 917. The decoded pixel data 917 is filtered by the in-loop filter 945 and stored in the decoded picture buffer 950. In some embodiments, the decoded picture buffer 950 is an external memory of the video decoder 900. In some embodiments, the decoded picture buffer 950 is an internal memory of the video decoder 900.

[0116] The intra prediction module 925 receives the intra prediction data from the bitstream 995 and generates the predicted pixel data 913 based on the decoded pixel data 917 stored in the decoded picture buffer 950. In some embodiments, the decoded pixel data 917 is also stored in a line buffer (not shown) for intra picture prediction and MV spatial prediction.

[0117] In some embodiments, the contents of the decoded picture buffer 950 are used for display. A display device 955 can receive the contents of the decoded picture buffer 950 and display them directly, or retrieve the contents of the decoded picture buffer and pass them to a display buffer. In some embodiments, the display device receives the plurality of pixel values ​​from the decoded picture buffer 950 via a pixel transport.

[0118] The motion compensation module 930 generates predicted pixel data 913 from the decoded pixel data 917 stored in the decoded picture buffer 950 according to the motion compensation MV (MC MV) which is decoded by adding the motion data residual from the bitstream 995 and the predicted MV from the MV prediction module 975.

[0119] The MV prediction module 975 generates the predicted MV based on a reference MV generated by decoding a previous video frame (e.g., the motion compensated MV used to perform motion compensation). The MV prediction module 975 retrieves the reference MV of the previous video frame from the MV buffer 965. The video decoder 900 stores the motion compensated MV generated by decoding the current video frame in the MV buffer 965, and uses the motion compensated MV as a reference MV for generating the predicted MV.

[0120] The in-loop filter 945 performs filtering or smoothing on the decoded pixel data 917 to reduce coding byproducts, especially at pixel block boundaries. In some embodiments, the filtering or smoothing performed by the in-loop filter 945 includes a deblocking filter (DBF), a sample adaptive offset (SAO), and / or an adaptive loop filter (ALF).

[0121] Figure 1FIG. 0 shows a plurality of portions of a video decoder 900 that can implement DIMD based on reduced bit length. More specifically, the figure shows a plurality of components of an intra prediction module 925 of the video decoder 900. As shown, the intra prediction module 925 includes a gradient accumulation module 1030, a HoG storage 1020, an intra mode selection module 1010, and an intra prediction generation module 1040. The intra prediction module 925 can utilize the gradient accumulation module 1030, the HoG storage 1020, the intra mode selection module 1010, and the intra prediction generation module 1040 to perform DIMD intra prediction of luma and chroma components.

[0122] The accumulation module 1030 receives a plurality of adjacent samples of the current block from the decoded picture buffer 950 and calculates the gradient amplitudes of different intra-mode directions. The gradient amplitude accumulated for each HoG data interval is limited (eg, clamped) to a maximum value of 2 based on a predefined bit length W. w The above (clamped) cumulative gradient amplitude is stored in the HoG memory 1020 with values ​​corresponding to different data intervals of different intra-mode directions.

[0123] The intra-mode selection module 1010 detects different data pitches stored in the HoG storage 1020 to identify two (or more) final DIMD intra-modes 1015. The intra-mode selection module 1010 includes a comparator tree 1005 for comparing data items 1025 of different HoG data pitches, and the comparator tree 1005 is used to identify the above-mentioned two or more data pitches with the highest cumulative gradient amplitude. In some embodiments, the data item of each data pitch includes a data pitch value located at the MSB and a data pitch index located at the LSB. In some embodiments of the above embodiments, the data pitch index of each data item is inverted in bit units.

[0124] In some embodiments, the comparator structure 1005 includes a comparator tree for identifying the two (or more) data intervals with the highest cumulative data interval value among all HoG data intervals. The comparator tree is a series connection structure (e.g., series connection structure 510) of N-input M-output comparator components (e.g., I3M2 components).

[0125] In some embodiments, the comparator structure 1005 includes two (or more) comparator trees for identifying the two (or more) data pitches with the highest data pitch values. Each comparator tree is used to identify a data pitch of a different subset (e.g., cardinality vs. evenness) of the HoG data pitches. Each of the two or more comparator trees is a cascade structure of a 2-input 1-output comparator component (CMP) (e.g., comparator trees 410 and 420).

[0126] The intra prediction generation module 1040 generates an intra prediction 1045 for the current block using one or more final intra prediction modes 1015. The one or more final prediction modes 1015 may include two or more DIMD intra modes, and the intra prediction generation module 1040 may retrieve multiple predictions / prediction variables from the decoded picture buffer 950 based on the DIMD intra modes. The retrieved prediction variables are mixed to generate the intra prediction 1045 and used as the prediction pixel data 913.

[0127] Fig.11 A process 1100 for implementing reduced bit length DIMD is conceptually shown. In some embodiments, a computing device is used to implement one or more processing units (e.g., a processor) of the video decoder 900 to execute the process 1100 by executing instructions stored in a computer-readable medium. In some embodiments, an electronic device implementing the video decoder 900 executes the process 1100.

[0128] The decoder (at block 1110) receives data of a pixel block to be decoded as a current block of a current picture of a video.

[0129] The decoder (at block 1120) derives a histogram of gradient (HoG) having a plurality of data spacings corresponding to different intra prediction angles. A cumulative gradient amplitude value is stored for each data spacing, and the value is limited to a specific bit length. In some embodiments, the stored cumulative gradient amplitude is clamped to be less than a specific value based on the specific bit length. In some embodiments, the specific bit length is 18 bits. In some embodiments, the specific bit length can be 12, 13, 14, 15, 16, 17, 18, 19, or 20 bits.

[0130] The decoder (in block 1130) identifies two or more intra-frame prediction modes based on the HoG. In some embodiments, the two or more intra-frame prediction modes are identified from the data spacing of the HoG by a comparator structure, and the comparator structure has one or more N-input M-output comparator components. Each N-input M-output component selects M maximum values ​​from N values, where N and M are positive integers and N>M≥2. Each input of the N-input M-output comparator component includes a value stored in a data spacing of the HoG and an index assigned to the data spacing. The index is attached to the value as the least significant bit of the input, and the index can be inverted in bits. In some embodiments, at least one input or at least one output of the N-input M-output comparator component is limited to the specific bit length.

[0131] In some embodiments, the two or more intra prediction modes are identified from the data intervals of the HoG by two or more comparator trees, each of the comparator trees identifying a different intra prediction mode. A first comparator tree identifies a first intra prediction mode from a plurality of HoG data intervals having odd indices, and a second comparator tree identifies a second intra prediction mode from a plurality of HoG data intervals having even indices.

[0132] The decoder (at block 1140) generates an intra prediction of a current block based on the identified two or more intra prediction modes. The decoder (at block 1150) reconstructs the current block using the generated intra prediction. The decoder may then provide the reconstructed current block for display as part of the reconstructed current picture.

[0133] VI. Electronic System Examples

[0134] Most of the above embodiments and applications are implemented as a software program of a set of specified instructions recorded in a computer-readable storage medium (also referred to as a computer-readable medium). When one or more computing or processing units (such as one or more processors, multiple core processors or other processing units) execute the above instructions, the above instructions cause the above computing or processing units to perform the actions indicated by the above instructions. For example, computer-readable media include but are not limited to compact disc read-only memory (CD-ROM), flash drive, random-access memory (RAM) chip, hard disk, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), etc. The above computer-readable media does not include carrier waves and electronic signals that are wirelessly transmitted using wired connections.

[0135] In this specification, the term "software" includes firmware located in read-only memory or applications stored in magnetic storage and can be read into memory and executed by a processor. Furthermore, in some embodiments, multiple software inventions can be implemented as sub-parts of a larger program while maintaining their own uniqueness. In some embodiments, multiple software inventions can also be implemented as separate programs. Finally, any combination of separate programs described herein to implement a software invention is within the scope of the present invention. In some embodiments, when the above-mentioned software program is configured to execute on one or more electronic systems, the above-mentioned software program defines a specific machine implementation of one or more programs that can execute and display the above-mentioned software program.

[0136] Fig.12 An electronic system 1200 is conceptually shown in which some embodiments of the present invention may be implemented. The electronic system 1200 may be a computer (e.g., a desktop computer, a personal computer, a tablet computer, etc.), a mobile phone, a personal digital assistant (PDA), or any other type of electronic device. The electronic device may include different types of computer-readable media and interfaces with other types of computer-readable media. The electronic system 1200 includes a bus 1205, one or more processing units 1210, a graphics-processing unit (GPU) 1215, a system memory 1220, a network 1225, a read-only memory 1230, a permanent storage device 1235, a plurality of input devices 1240, and a plurality of output devices 1245.

[0137] Bus 1205 collectively represents all system, peripheral, and chipset buses that communicatively connect to the many internal devices of electronic system 1200. For example, bus 1205 communicatively connects one or more processing units 1210 to GPU 1215, read-only memory 1230, system memory 1220, and permanent storage device 1235.

[0138] One or more processing units 1210 obtain instructions to be executed and data to be processed from GPU 1215, read-only memory 1230, system memory 1220 and / or permanent storage device 1235 to execute the plurality of programs mentioned in the present invention. In different embodiments, the above-mentioned processing unit 1210 can be a single processor or a multi-core processor. Some instructions are passed to GPU 1215 for execution. GPU 1215 can offload different computations or complement the image processing provided by one or more processing units 1210.

[0139] The read-only-memory (ROM) 1230 stores static data and instructions for one or more processing units 1210 and other modules of the electronic system 1200. On the other hand, the permanent storage device 1235 is a read-write memory device. The read-write memory device is a non-volatile memory unit that can store instructions and data even when the electronic system 1200 is in a powered-off state. Some embodiments of the present invention utilize a mass storage device (e.g., a disk or optical disk and a corresponding disk drive) as the permanent storage device 1235.

[0140] Other embodiments utilize a removable storage device (e.g., a floppy disk, a flash memory device, etc., and a corresponding disk drive) as the above-mentioned permanent storage device 1235. Like the permanent storage device 1235, the system memory 1220 is a read-write memory device. However, unlike the permanent storage device 1235, the system memory 1220 is a volatile read-write memory, such as a random access memory. The system memory 1220 stores a portion of instructions and data used by the processor during runtime. In some embodiments, multiple programs of the present invention are stored in the system memory 1220, the permanent storage device 1235 and / or the read-only memory 1230. For example, according to some embodiments, multiple memory units store multiple instructions for processing multimedia clips. One or more processing units 1210 obtain the instructions to be executed and the data to be processed from the above-mentioned memory units to execute the multiple programs of some embodiments.

[0141] The bus 1205 also connects a plurality of input devices 1240 and a plurality of output devices 1245. The plurality of input devices 1240 enable a user to transmit information and select commands to the electronic system 1200. The plurality of input devices 1240 include a plurality of alphabetic and numeric keyboards and a plurality of pointing devices (also known as cursor control devices), a plurality of lenses (such as webcams), a plurality of microphones or other similar devices for receiving voice commands, etc. The plurality of output devices 1245 display images generated by the electronic system 1200 or other output data. The plurality of output devices 1245 include a plurality of copiers and a plurality of display devices (such as cathode ray tubes (CRT) or liquid crystal displays (LCD)), as well as a plurality of speakers or other similar sound output devices. Some embodiments include a plurality of devices, such as a touch screen that serves as both an output and an input device.

[0142] Finally, if Fig.12 As shown, bus 1205 also couples electronic system 1200 to a network 1225 via a network adapter (not shown). In this case, the computer may be part of a network of multiple computers (e.g., a local area network (LAN), a wide area network (WAN), or an intranet), or part of a network of multiple networks (e.g., the Internet). In the present invention, any or all components of electronic system 1200 may be connected.

[0143] Some embodiments include a plurality of electronic components, such as a plurality of microprocessors, a plurality of storages, and a plurality of memories, which are used to store computer program instructions in a machine-readable or computer-readable medium (also referred to as a computer-readable storage medium, a machine-readable medium, or a machine-readable storage medium). For example, the computer-readable medium includes RAM, ROM, read-only compact discs (CD-ROM), recordable CDs (CD-R), rewritable CDs (CD-RW), read-only digital versatile discs (DVD-ROM) (e.g., DVD-ROM, dual-layer DVD-ROM), various recordable / rewritable DVDs (e.g., DVD-RAM, DVD-RW, DVD+RW, etc.), flash memory (e.g., secure digital memory card (SD card), mini SD card, micro SD card, etc.), magnetic disk drives and / or solid-state hard disks, read-only recordable Blu-ray discs, ultra-density optical discs, any other optical or magnetic media, and floppy disks. The computer readable medium may store a computer program executable by at least one processing unit, the computer program comprising a set of multiple instructions for executing various programs. For example, the computer program or computer code comprises machine code (e.g., generated by a compiler) and multiple files, the files comprising higher-level codes executed by a computer, an electronic component or a microprocessor using an interpreter.

[0144] Although the above discussion mainly involves microprocessors or multi-core processors that execute software, most of the above embodiments and applications are executed by one or more integrated circuits, such as application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). In some embodiments, the integrated circuits execute instructions stored in the circuits themselves. In addition, some embodiments execute software stored in programmable logic devices (PLDs), ROM, or RAM devices.

[0145] Terms used in this specification or any claims of this application, such as "computer", "server", "processor" and "memory" refer to electronic devices or other technical devices. The above terms do not include people or groups of people. For the purpose of this specification, the term "display" means display on an electronic device. Terms used in this specification or any claims of this application, such as "computer-readable medium", "computer-readable medium" and "machine-readable medium" are all completely limited to tangible physical objects that store information in a computer-readable manner. The above terms do not include any wireless signals, wired download signals, and any other temporary signals.

[0146] Although the present invention has been described with reference to many specific details, it will be appreciated by those skilled in the art that the present invention may be implemented in other specific forms without departing from the spirit of the present invention. Figure 8 and Fig.11 ) conceptually illustrates a plurality of programs. The specific operations of the above-mentioned programs may not be performed in the exact order shown and described. Specific operations may not be performed in a continuous sequence of operations, and different specific operations may be performed in different embodiments. In addition, the above-mentioned programs can be implemented using multiple subroutines or as part of a larger program. Therefore, those with ordinary knowledge in the art will understand that the present disclosure is not limited by the foregoing illustrative details, but is limited by the scope of the attached patent claims.

[0147] [Additional notes]

[0148] The subject matter described herein sometimes illustrates different components included in or connected to different other components. It should be understood that the architecture depicted in this way is only an example, and in fact many other architectures can achieve the same function. Conceptually, any arrangement of components that achieve the same function is effectively "associated", thereby achieving the desired function. Therefore, regardless of the architecture or intermediate components, any two components that achieve a specific function through combination herein can be regarded as "associated" with each other to achieve the desired function. Similarly, any two components so associated can also be regarded as "operably connected" or "operably coupled" to each other to achieve the desired function, and any two components that can be so associated can also be regarded as "operably coupled" to each other to achieve the desired function. For example, "operably coupled" includes but is not limited to components that can be physically matched and / or physically interacted and / or components that can interact wirelessly and / or wirelessly interact and / or components that can interact logically and / or logically interact.

[0149] In addition, with respect to the use of substantially any plural and / or singular terms herein, those skilled in the art may translate from the plural to the singular and / or from the singular to the plural as appropriate, depending on the context and / or application. For clarity, various singular / plural arrangements are explicitly set forth herein.

[0150] In addition, those skilled in the art will understand that, in general, the terms used herein, and particularly the terms used in the appended claims (e.g., the body of the appended claims), are generally intended to be "open" terms, for example, the term "including" should be interpreted as "including but not limited to", the term "having" should be interpreted as "at least", the term "including" should be interpreted as "including but not limited to", etc. Those skilled in the art will further understand that if a specific number is intended to be introduced in the statement of the claims, the above intention will be explicitly stated in the claims, and in the absence of such statement, the above intention does not exist. For example, to aid understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce the description of the claim statement. However, even if a claim includes the introductory phrases "one or more" or "at least one" and an indefinite article, such as "a" (e.g., "a" and / or "an" should be interpreted as "at least one" or "one or more"), the use of the above phrases should not be interpreted as implying that the above claim including the indefinite article "a" will be limited to only one embodiment of the above claim; the same applies to the claim statement introduced by the definite article. In addition, even if a specific number is clearly stated in the claim, a person skilled in the art will recognize that such a statement should be interpreted as at least reaching the above specific number stated, for example, the statement "two" without other modifiers means at least two, or two or more. In addition, in those cases where a limitation similar to "at least one of A, B, and C, etc." is used, generally speaking, such a construction is based on the understanding of the above limitation by a person skilled in the art, for example, "a system having at least one of A, B, and C" will include but is not limited to a system having A alone, B alone, C alone, A and B together, A and C together, B and C together, and / or A, B, and C together, etc. In those cases where a limitation similar to "at least one of A, B, and C, etc." is used, generally speaking, such a construction is based on the understanding of the above limitation by a person skilled in the art, for example, "a system having at least one of A, B, and C" will include but is not limited to a system having A alone, B alone, C alone, A and B together, A and C together, B and C together, and / or A, B, and C together, etc. A person skilled in the art will further understand that in fact, whether in the specification, the scope of the claims or the drawings, any disjunctive words and / or phrases that appear with two or more alternative terms should be understood to contemplate the possibility of including one, either, or both terms. For example, the phrase "A or B" will be understood to include the possibilities of "A" or "B" or "A and B."

[0151] As can be understood from the above, various embodiments of the present invention are described herein for illustrative purposes, and various modifications can be made without departing from the scope and spirit of the present invention. Therefore, the various embodiments disclosed herein are not intended to be limiting, and the true scope and spirit are represented by the appended application rights.

Claims

1. A video encoding and decoding method, comprising: Receiving data of a pixel block to be encoded or decoded as a current block of a current picture of a video; deriving a gradient histogram (HoG) comprising a plurality of data intervals corresponding to a plurality of different intra prediction angles, wherein a value of the accumulated gradient amplitude of each of the data intervals is stored and the value is limited to a specific bit length; Based on the HoG, two or more intra prediction modes are identified; Based on the two or more intra prediction modes, generating an intra prediction of the current block; and The current block is encoded or decoded using the intra-frame prediction.

2. The video encoding and decoding method of claim 1, wherein the specific bit length is 18 bits.

3. The video encoding and decoding method of claim 1, wherein the specific bit length is one of 12, 13, 14, 15, 16, 17, 18, 19 and 20 bits.

4. The video encoding method of claim 1, wherein the accumulated gradient amplitude is limited to be less than a specific value based on the specific bit length.

5. The video encoding method of claim 1, wherein the two or more intra-frame prediction modes are identified from the data spacing of the HoG by a comparator structure, the comparator structure comprising one or more N-input M-output comparator components, wherein each of the N-input M-output components selects M maximum values ​​from N values, wherein M and N are positive integers, and M is greater than or equal to 2 and N is greater than M.

6. The video encoding and decoding method of claim 5, wherein each input of the N-input M-output comparator component includes a value stored in one of the data intervals of the HoG and an index to which the data interval is configured, wherein the index is appended to the value as the least significant bit of the input.

7. The video encoding method of claim 6, wherein the index is reversed in bit units.

8. The video encoding method of claim 5, wherein at least one input or at least one output of the N-input M-output comparator component is limited to the specific bit length.

9. The video coding method of claim 1, wherein the two or more intra prediction modes are identified from the data interval of the HoG by two or more comparator trees, each of the comparator trees identifying a different intra prediction mode.

10. The video coding method of claim 9, wherein a first comparator tree identifies a first intra prediction mode from a plurality of data intervals of HoGs with odd indices, and a second comparator tree identifies a second intra prediction mode from a plurality of data intervals of HoGs with even indices.

11. An electronic device, comprising: A video encoder circuit is configured to perform: Receiving data of a pixel block to be encoded or decoded as a current block of a current picture of a video; deriving a gradient histogram (HoG) including a plurality of data spans corresponding to a plurality of different intra prediction angles, a value of a cumulative gradient amplitude for each of the data spans being stored and the value being limited to a specific bit length; Based on the HoG, two or more intra prediction modes are identified; Based on the two or more intra prediction modes, generating an intra prediction of the current block; and The current block is encoded or decoded using the intra-frame prediction.

12. A video decoding method, comprising: Receiving data of a pixel block to be decoded as a current block of a current picture of a video; deriving a gradient histogram (HoG) comprising a plurality of data intervals corresponding to a plurality of different intra prediction angles, wherein a value of a cumulative gradient amplitude for each of the data intervals is stored and the value is limited to a specific bit length; Based on the HoG, two or more intra prediction modes are identified; Based on the two or more intra prediction modes, generating an intra prediction of the current block; and The current block is reconstructed using the intra-frame prediction.

13. A method for video encoding, comprising: Receiving data of a pixel block to be encoded as a current block of a current picture of a video; deriving a gradient histogram (HoG) comprising a plurality of data intervals corresponding to a plurality of different intra prediction angles, wherein a value of a cumulative gradient amplitude for each of the data intervals is stored and the value is limited to a specific bit length; Based on the HoG, two or more intra prediction modes are identified; Based on the two or more intra prediction modes, generating an intra prediction of the current block; and The current block is encoded using the intra-frame prediction.

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