Display device

Abstract

A sub-pixel of the display device includes: a first transistor including a gate electrode connected to a first node, a first terminal connected to a first power line, and a second terminal connected to a second node; a light emitting part connected between the second node and the second power line, the light emitting part including at least one light emitting element; and a capacitor formed between the first node and the second node. When viewed from above, the capacitor includes: a first capacitor electrode; and a second capacitor electrode overlapping the first capacitor electrode with the insulating layer interposed therebetween. When viewed from above, the second capacitor electrode includes: a first protruding member protruding from a periphery of the first capacitor electrode in an extension direction to receive a data signal; and a second protruding member protruding from a portion of the periphery of the second capacitor electrode in a direction opposite to the extending direction.

Description

Technical Field

[0001] The disclosure relates to a display device. Background Art

[0002] As interest in information display and demand for portable information media increase, research and commercialization have focused on display devices. Summary of the invention

[0003] Technical issues

[0004] The embodiment provides a display device capable of improving display quality.

[0005] Technical Solution

[0006] According to the disclosed aspects, a display device may include a sub-pixel. The sub-pixel may include: a first transistor including a gate electrode electrically connected to a first node, a first terminal electrically connected to a first power line, and a second terminal electrically connected to a second node; a light-emitting component electrically connected to a second node and a second power line, the light-emitting component including at least one light-emitting element; and a capacitor formed between the first node and the second node. The capacitor may include: a first capacitor electrode; and a second capacitor electrode overlapping the first capacitor electrode in a plan view. An insulating layer may be provided between the first capacitor electrode and the second capacitor electrode. The second capacitor electrode may include: a first protrusion component protruding further than an edge of the first capacitor electrode in an extension direction in a plan view to receive a data signal; and a second protrusion component protruding from a portion of an edge of the second capacitor electrode in a plan view in a direction opposite to the extension direction.

[0007] In a plan view, the second capacitor electrode may overlap the first capacitor electrode except for the first protrusion part and the second protrusion part.

[0008] The second protrusion part may not be directly connected to the external component.

[0009] The first width of the first protrusion part and the second width of the second protrusion part may be equal in a direction perpendicular to the extending direction.

[0010] Regardless of an alignment error between the first capacitor electrode and the second capacitor electrode, an overlapping area between the first capacitor electrode and the second capacitor electrode in a plan view can be constantly maintained due to the second protrusion part corresponding to the first protrusion part.

[0011] The first protruding feature and the second protruding feature may not be co-linear with each other.

[0012] The first protruding feature and the second protruding feature may be collinear with each other.

[0013] The second capacitor electrode may further include a main body part overlapping the first capacitor electrode in a plan view. The width of the main body part in a direction perpendicular to the extension direction may be greater than the width of the second protrusion part. The second protrusion part may protrude from the main body part in a direction opposite to the extension direction by about 3 μm.

[0014] The first capacitor electrode may be located below the semiconductor pattern of the first transistor in the cross-sectional view. The first insulating layer may be disposed between the first capacitor electrode and the semiconductor pattern. The second capacitor electrode may be disposed on the semiconductor pattern in the cross-sectional view. The second insulating layer may be disposed between the second capacitor electrode and the semiconductor pattern.

[0015] The capacitor may further include a third capacitor electrode overlapping the second capacitor electrode in a plan view. A third insulating layer may be provided between the third capacitor electrode and the second capacitor electrode.

[0016] The third capacitor electrode may be electrically connected to the first capacitor electrode through a contact hole penetrating the first insulating layer, the second insulating layer, and the third insulating layer.

[0017] The second capacitor electrode may be disposed on the semiconductor pattern of the first transistor. The first capacitor electrode may be disposed on the second capacitor electrode. An insulating layer may be disposed between the first capacitor electrode and the second capacitor electrode.

[0018] The sub-pixel may further include a second transistor electrically connected between the data line and the first node. The first protrusion part may protrude toward the second transistor in a plan view.

[0019] The data line may extend in the extending direction.

[0020] The data line may extend in a direction crossing the extending direction.

[0021] The light emitting component may further include: a first electrode and a second electrode, which are spaced apart from each other; a first pixel electrode, which is disposed on the first electrode, and the first pixel electrode is electrically connected to one end of the at least one light emitting element; and a second pixel electrode, which is disposed on the second electrode, and the second pixel electrode is electrically connected to the other end of the at least one light emitting element. The at least one light emitting element may be disposed between the first electrode and the second electrode.

[0022] The first pixel electrode may be electrically connected to the second terminal of the first transistor through a contact hole penetrating another insulating layer disposed under the first electrode and the second electrode.

[0023] The sub-pixel may further include a color conversion layer disposed on the at least one light emitting element, the color conversion layer converting a wavelength of light incident from the at least one light emitting element and releasing light having the converted wavelength.

[0024] The first power line may include: a first vertical power line extending in a first direction; and a second vertical power line extending in a second direction. The pixel circuits of a plurality of sub-pixels constituting one pixel may be arranged in a plan view in an area divided by the first vertical power line, the second vertical power line, and the second power line. Each of the pixel circuits may include a first transistor and a capacitor.

[0025] The pixel circuits in the region may be arranged in the first direction. The data lines for the sub-pixels may extend in the first direction and be arranged adjacent to each other.

[0026] Beneficial Effects

[0027] In the display device according to the disclosure, the second capacitor electrode of the storage capacitor may include a first protrusion part and a second protrusion part that protrude farther than the first capacitor electrode of the storage capacitor, and the second protrusion part may protrude in a direction opposite to an extending direction of the first protrusion part. Although an alignment error between the first capacitor electrode and the second capacitor electrode occurs, the capacitance of the storage capacitor may be constantly maintained by the second protrusion part corresponding to the first protrusion part, and a capacitance deviation of the storage capacitor between pixels and degradation of display quality caused by the capacitance deviation may be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

[0029] Figure 1 is a perspective view showing a light emitting element according to a disclosed embodiment.

[0030] Figure 2 is a schematic cross-sectional view showing a light emitting element according to a disclosed embodiment.

[0031] Figure 3 is a plan view showing a display device according to a disclosed embodiment.

[0032] Figure 4a According to the disclosed embodiment Figure 3 Schematic diagram of an equivalent circuit of a pixel in the display device shown in .

[0033] Figure 4b According to the disclosed embodiment Figure 3 Schematic diagram of an equivalent circuit of a pixel in the display device shown in .

[0034] Figure 4c According to the disclosed embodiment Figure 3 Schematic diagram of an equivalent circuit of a pixel in the display device shown in .

[0035] Figure 5 It is shown Figure 4a Schematic waveform diagram of the operation of the pixel shown in .

[0036] Figure 6 is a diagram showing the embodiment according to the disclosure Figure 3 A schematic cross-sectional view of a sub-pixel in a display device shown in FIG.

[0037] Figure 7a is a diagram showing the embodiment according to the disclosure Figure 3 A schematic cross-sectional view of a sub-pixel in a display device shown in FIG.

[0038] Figure 7b is a diagram showing the embodiment according to the disclosure Figure 3 Schematic cross-sectional view of a pixel in the display device shown in .

[0039] Figure 7c is a diagram showing the embodiment according to the disclosure Figure 3 Schematic cross-sectional view of a pixel in the display device shown in .

[0040] Figure 8 The invention is a diagram showing the embodiment according to the disclosure Figure 3 Layout diagram of pixels in the display device shown in .

[0041] Figure 9a According to the disclosed embodiment Figure 8 An enlarged plan view of a third pixel circuit in the pixel shown in FIG.

[0042] Figure 9b According to the disclosed embodiment Figure 8 An enlarged plan view of a third pixel circuit in the pixel shown in FIG.

[0043] Fig.10 is a diagram showing a method according to an embodiment of the disclosure Figure 9a Schematic cross-sectional view of a storage capacitor taken along line II′ shown in FIG.

[0044] Fig.11 is a view showing a pixel circuit according to a comparative embodiment.

[0045] Fig.12 It is shown along Fig.11 Schematic cross-sectional view of a comparative example of a storage capacitor taken along line II-II′ shown in FIG.

[0046] Fig.13 The invention is a diagram showing the embodiment according to the disclosure Figure 3A plan view of a pixel in the display device shown in FIG.

[0047] Fig.14 is a diagram showing the embodiment according to the disclosure Figure 8 A view of a pixel circuit included in a pixel shown in FIG.

[0048] Fig.15 is a diagram showing the embodiment according to the disclosure Figure 8 A view of a pixel circuit included in a pixel shown in FIG. DETAILED DESCRIPTION

[0049] Embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0050] The disclosure can apply various changes and different shapes, so only specific embodiments are described in detail. However, the embodiments are not limited to certain shapes, but are applicable to all changes and equivalent materials and replacements. The included drawings are shown in a way that the drawings are expanded for better understanding.

[0051] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intervening elements may also be present. The same reference numerals refer to the same elements throughout.

[0052] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the disclosed teachings, the "first" element discussed below may also be referred to as the "second" element. As used herein, unless the context clearly indicates otherwise, the singular form is intended to also include the plural form.

[0053] It will also be understood that when the terms "comprise" and / or "include" are used in this specification, the existence of the stated features, wholes, steps, operations, elements and / or components is indicated, but the existence and / or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof are not excluded. In addition, the expression that an element such as a layer, region, substrate or plate is placed "on" or "above" another element not only indicates the situation that the element is "directly" placed "on" or "immediately above" the other element, but also indicates the situation that another element is inserted between the element and the other element. Conversely, the expression that an element such as a layer, region, substrate or plate is placed "under" or "below" another element not only indicates the situation that the element is "directly" placed "under" or "immediately below" the other element, but also indicates the situation that another element is inserted between the element and the other element.

[0054] The effects and characteristics of the present disclosure and methods of achieving the effects and characteristics will become clear by referring to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed herein, but can be implemented in various forms.

[0055] When an element, such as a layer, is referred to as being "on," "connected to," or "bonded to" another element or layer, the element may be directly on, directly connected to, or directly bonded to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to being physically connected, electrically connected, and / or fluidly connected with or without intervening elements. In addition, when an element is referred to as being "in contact with" or "in contact with" another element, etc., the element may be "electrically in contact with" or "physically in contact with" the other element, or "indirectly in contact with" or "directly in contact with" the other element.

[0056] In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0057] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunction or disjunction sense and may be understood to be equivalent to "and / or".

[0058] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless clearly defined in the specification.

[0059] Hereinafter, a display device according to a disclosed embodiment will be described with reference to the accompanying drawings.

[0060] Figure 1 is a perspective view showing a light emitting element according to a disclosed embodiment. Figure 2 is a schematic cross-sectional view showing a light emitting element according to an embodiment of the disclosure. Figure 1 and Figure 2 , a pillar-shaped light emitting element LD is shown, but the type and / or shape of the light emitting element LD are not limited thereto.

[0061] Reference Figure 1 and Figure 2 The light emitting element LD may include a first semiconductor layer 11, an active layer 12 and a second semiconductor layer 13. When the extending direction of the light emitting element LD is the length L direction, the first semiconductor layer 11, the active layer 12 and the second semiconductor layer 13 may be sequentially stacked in the length L direction.

[0062] The light emitting element LD may be provided in a column shape extending in one direction. The light emitting element LD may have a first end portion EP1 and a second end portion EP2. One of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided at the first end portion EP1 of the light emitting element LD. The other of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided at the second end portion EP2 of the light emitting element LD.

[0063] In some embodiments, the light emitting element LD may be a light emitting element manufactured in a column shape by an etching process or the like. In the present specification, the term "column shape" may include a rod-like shape or a strip-like shape (such as a cylinder or a polygonal column) that is long in the length L direction (i.e., its aspect ratio is greater than 1), and the cross-sectional shape is not particularly limited. For example, the length L of the light emitting element LD may be greater than the diameter (or width in a cross-sectional view) D of the light emitting element LD.

[0064] The light emitting element LD may have a size of nanometer to micrometer. In an embodiment, the light emitting element LD may have a diameter (or width) D in the range of nanometer to micrometer and / or a length L in the range of nanometer to micrometer. However, the size of the light emitting element LD is not limited thereto, and the size of the light emitting element LD may be variously changed according to the design conditions of various types of devices (e.g., display devices, etc.) that use the light emitting device using the light emitting element LD as a light source.

[0065] The first semiconductor layer 11 may be a first conductive type semiconductor layer. For example, the first semiconductor layer 11 may include an n-type semiconductor layer. In an embodiment, the first semiconductor layer 11 may include at least one semiconductor material such as InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and include an n-type semiconductor layer doped with a first conductive type dopant such as Si, Ge, and Sn. However, the material constituting the first semiconductor layer 11 is not limited thereto. The first semiconductor layer 11 may be formed of various materials.

[0066] The active layer 12 may be formed on the first semiconductor layer 11 and may be formed as a single quantum well structure or a multi-quantum well structure. The active layer 12 may include GaN, InGaN, InAlGaN, AlGaN or AlN, etc. The active layer 12 may be formed of various materials. In some embodiments, a cladding layer (not shown) doped with a conductive dopant may be formed on the top and / or bottom of the active layer 12. In an embodiment, the cladding layer may include an AlGaN layer or an InAlGaN layer.

[0067] The second semiconductor layer 13 may be formed on the active layer 12, and may include a semiconductor layer having a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include a p-type semiconductor layer. In an embodiment, the second semiconductor layer 13 may include at least one semiconductor material such as InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and includes a p-type semiconductor layer doped with a second conductive type dopant such as Mg. However, the material constituting the second semiconductor layer 13 is not limited thereto. The second semiconductor layer 13 may be formed of various materials.

[0068] When a threshold voltage or more is applied to both ends of the light emitting element LD, the light emitting element LD can emit light due to the combination of electron-hole pairs in the active layer 12. By using this principle, the light emission of the light emitting element LD can be controlled, so that the light emitting element LD can be used as a light source for various light emitting devices (including pixels of display devices).

[0069] The light emitting element LD may further include an insulating film 14 disposed on a surface thereof. The insulating film 14 may be formed on the surface of the light emitting element LD to surround at least the outer circumferential surface of the active layer 12. The insulating film 14 may also surround at least a portion of the circumferential surface of each of the first semiconductor layer 11 and the second semiconductor layer 13.

[0070] In some embodiments, the insulating film 14 may expose two end portions EP1 and EP2 of the light emitting element LD having different polarities. For example, the insulating film 14 may expose one end of each of the first semiconductor layer 11 and the second semiconductor layer 13 located at the first end portion EP1 and the second end portion EP2 of the light emitting element LD. In another embodiment, the insulating film 14 may expose the side portions of each of the first semiconductor layer 11 and the second semiconductor layer 13 adjacent to the first end portion EP1 and the second end portion EP2 of the light emitting element LD having different polarities.

[0071] In some embodiments, the insulating film 14 may be configured to include at least one insulating material (such as silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) and titanium oxide (TiO x )) of a single layer or multiple layers (for example, made of aluminum oxide (AlO x ) and silicon oxide (SiO x ) formed of a double layer), but the disclosure is not limited thereto. For example, according to another embodiment, the insulating film 14 may be omitted.

[0072] When the insulating film 14 is provided to cover the surface of the light emitting element LD (for example, the outer circumferential surface of the active layer 12), the active layer 12 can be prevented from being short-circuited with the first pixel electrode or the second pixel electrode to be described later, etc. Therefore, the electrical stability of the light emitting element LD can be ensured.

[0073] In addition, when the insulating film 14 is provided on the surface of the light emitting element LD, surface defects of the light emitting element LD can be minimized, thereby improving the life and efficiency of the light emitting element LD. Even when a plurality of light emitting elements LD are densely arranged, an undesirable short circuit between the light emitting elements LD can be prevented.

[0074] In an embodiment, the light emitting element LD may include additional components in addition to the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and / or the insulating film 14 surrounding them. For example, the light emitting element LD may include at least one phosphor layer, at least one active layer, at least one semiconductor layer, and / or at least one electrode layer disposed at one end of the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13.

[0075] Although already Figure 1 and Figure 2 , a pillar-shaped light emitting element LD is shown, but the kind, structure and / or shape of the light emitting element LD may be variously changed. For example, the light emitting element LD may be formed in a core-shell structure having a polygonal pyramid shape.

[0076] The light emitting device including the above-mentioned light emitting element LD can be used in various types of devices (including display devices) that require a light source. For example, a plurality of light emitting elements LD can be arranged in each pixel of a display panel and can be used as a light source for each pixel. However, the application field of the light emitting element LD is not limited to the above-mentioned example. For example, the light emitting element LD can be used in other types of devices (such as lighting devices) that require a light source.

[0077] Figure 3 is a plan view showing a display device according to an embodiment of the disclosure. Figure 3 In the embodiment, the display panel PNL provided in the display device will be shown as being usable Figure 1 and Figure 2 An example of an electronic device in which the light emitting element LD is described in the embodiment shown in FIG.

[0078] For ease of description, Figure 3 , the structure of the display panel PNL will be briefly illustrated based on the display area DA. In some embodiments, at least one driving circuit (e.g., at least one of a scan driver and a data driver), a line and / or a pad (also referred to as a "pad" or "pad") may be disposed in the display panel PNL.

[0079] The disclosure can be applied as long as the display device is an electronic device in which a display surface is applied to at least one surface thereof (such as a smart phone, a television, a tablet personal computer (PC), a mobile phone, a video phone, an e-book reader, a desktop PC, a laptop PC, a netbook computer, a workstation, a server, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, a medical device, a camera, or a wearable device).

[0080] Reference Figure 3, the display panel PNL may include a first substrate SUB1 and pixels PXL disposed on the first substrate SUB1.

[0081] The first substrate (or substrate layer) SUB1 may constitute a substrate member of the display panel PNL, and may be a rigid substrate (or film) or a flexible substrate (or film). In an embodiment, the first substrate SUB1 may be configured as a rigid substrate made of glass or tempered glass, a flexible substrate (or film) made of plastic or metal, or at least one insulating layer. The material and / or properties of the first substrate SUB1 are not particularly limited.

[0082] In an embodiment, the first substrate SUB1 may be substantially transparent. The term "substantially transparent" may mean that light may be transmitted at a predetermined (or optional) transmittance or greater transmittance. In another embodiment, the first substrate SUB1 may be translucent or opaque. In some embodiments, the first substrate SUB1 may include a reflective material.

[0083] The display panel PNL and the first substrate SUB1 may include a display area DA for displaying an image and a non-display area NDA except for the display area DA.

[0084] The pixels PXL may be arranged in the display area DA. Various lines, pads, and / or built-in circuits connected to the pixels PXL in the display area DA may be provided in the non-display area NDA.

[0085] The pixel PXL may include sub-pixels SPXL1 to SPXL3. For example, the pixel PXL may include a first sub-pixel SPXL1, a second sub-pixel SPXL2, and a third sub-pixel SPXL3.

[0086] Each of the sub-pixels SPXL1 to SPXL3 may emit light of a predetermined (or optional) color. In some embodiments, the sub-pixels SPXL1 to SPXL3 may emit light of different colors. In an embodiment, the first sub-pixel SPXL1 may emit light of a first color, the second sub-pixel SPXL2 may emit light of a second color, and the third sub-pixel SPXL3 may emit light of a third color. For example, the first sub-pixel SPXL1 may be a red pixel emitting red light, the second sub-pixel SPXL2 may be a green pixel emitting green light, and the third sub-pixel SPXL3 may be a blue pixel emitting blue light. However, the disclosure is not limited thereto.

[0087] In an embodiment, the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may have a light-emitting element of a first color, a light-emitting element of a second color, and a light-emitting element of a third color as a light source to emit light of a first color, light of a second color, and light of a third color, respectively. In another embodiment, the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may have a light-emitting element that emits light of the same color, and include a color conversion layer and / or a color filter of different colors disposed above each light-emitting element to emit light of a first color, light of a second color, and light of a third color, respectively. However, the color, type, and / or number of the sub-pixels SPXL1 to SPXL3 constituting each pixel PXL are not particularly limited. For example, the color of the light emitted by each pixel PXL may be changed differently.

[0088] The sub-pixels SPXL1 to SPXL3 may be arranged in a stripe structure or a PENTILE TM The sub-pixel SPXL1 to SPXL3 are regularly arranged in a structure, etc. For example, the first sub-pixel SPXL1, the second sub-pixel SPXL2 and the third sub-pixel SPXL3 can be sequentially and repeatedly arranged in the first direction DR1. In addition, the first sub-pixel SPXL1, the second sub-pixel SPXL2 and the third sub-pixel SPXL3 can be repeatedly arranged in the second direction DR2. At least one first sub-pixel SPXL1, at least one second sub-pixel SPXL2 and at least one third sub-pixel SPXL3 can constitute a pixel PXL capable of emitting light of various colors. However, the arrangement structure of the sub-pixels SPXL1 to SPXL3 is not limited thereto, and the sub-pixels SPXL1 to SPXL3 can be arranged in the display area DA in various structures and / or various patterns.

[0089] In an embodiment, each of the sub-pixels SPXL1 to SPXL3 may be configured as an active pixel. For example, each of the sub-pixels SPXL1 to SPXL3 may include at least one light source (e.g., at least one light-emitting element) driven by a predetermined (or optional) control signal (e.g., a scan signal and a data signal) and / or a predetermined (or optional) power supply (e.g., a first power supply and a second power supply). However, the type, structure and / or driving method of the sub-pixels SPXL1 to SPXL3 that can be applied to the display device are not particularly limited.

[0090] Figure 4a , Figure 4b and Figure 4c Each is according to the disclosed embodiment Figure 3 Schematic diagram of an equivalent circuit of a pixel in the display device shown in .

[0091] For example, Figure 4a , Figure 4b and Figure 4c An embodiment of the electrical connection relationship of the components included in each of the sub-pixels SPXL1 to SPXL3 applicable to an active matrix display device is shown. However, the connection relationship of the components included in each of the sub-pixels SPXL1 to SPXL3 is not limited thereto. In the following embodiments, the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may be collectively referred to as sub-pixels SPXL.

[0092] Reference Figure 3 , Figure 4a , Figure 4b and Figure 4c The sub-pixel SPXL may include a light emitting unit (or light emitting part) EMU that generates light having brightness corresponding to the data signal. The sub-pixel SPXL may selectively include a pixel circuit PXC for driving the light emitting unit EMU.

[0093] In some embodiments, the light emitting unit EMU may include a plurality of light emitting elements LD connected in parallel between a first power line PL1 and a second power line PL2. The first power line PL1 may be connected to a first driving power source VDD so that a voltage of the first driving power source VDD is applied to the first power line PL1, and the second power line PL2 may be connected to a second driving power source VSS so that a voltage of the second driving power source VSS is applied to the second power line PL2.

[0094] For example, the light emitting unit EMU may include a first pixel electrode (or first electrode) CNE1 connected to a first driving power source VDD via a pixel circuit PXC and a first power line PL1, a second pixel electrode (or second electrode) CNE2 connected to a second driving power source VSS via a second power line PL2, and a plurality of light emitting elements LD connected in parallel between the first pixel electrode CNE1 and the second pixel electrode CNE2 in the same direction. In an embodiment, the first pixel electrode CNE1 may be an anode (or anode electrode), and the second pixel electrode CNE2 may be a cathode (or cathode electrode).

[0095] Each of the light emitting elements LD included in the light emitting unit EMU may include a first end connected to a first driving power source VDD through a first pixel electrode CNE1 and a second end connected to a second driving power source VSS through a second pixel electrode CNE2. The first driving power source VDD and the second driving power source VSS may have different potentials. In an embodiment, the first driving power source VDD may be a high potential power source, and the second driving power source VSS may be a low potential power source. During the emission period of each sub-pixel SPXL, the potential difference between the first driving power source VDD and the second driving power source VSS may be equal to or higher than the threshold voltage of the light emitting element LD.

[0096] As described above, the light emitting elements LD connected in parallel between the first pixel electrode CNE1 and the second pixel electrode CNE2 in the same direction (eg, forward direction) to which voltages having different potentials are supplied may form respective effective light sources.

[0097] Each of the light emitting elements LD of the light emitting unit EMU can emit light having a brightness corresponding to the driving current supplied by the corresponding pixel circuit PXC. For example, the pixel circuit PXC can supply a driving current corresponding to the grayscale value of the corresponding frame data to the light emitting unit EMU during each frame period. The driving current supplied to the light emitting unit EMU can be divided to flow through each of the light emitting elements LD. Therefore, the light emitting unit EMU can emit light having a brightness corresponding to the driving current, while each light emitting element LD emits light having a brightness corresponding to the current flowing therethrough.

[0098] Although an embodiment has been described in which both ends of the light emitting element LD are connected between the first driving power source VDD and the second driving power source VSS in the same direction, the disclosure is not limited thereto. In some embodiments, in addition to the light emitting elements LD forming each effective light source, the light emitting unit EMU may further include at least one ineffective light source (e.g., a reverse light emitting element LDr). The reverse light emitting element LDr may be connected between the first pixel electrode CNE1 and the second pixel electrode CNE2 in parallel with the other light emitting elements LD forming the effective light source, and may be connected between the first pixel electrode CNE1 and the second pixel electrode CNE2 in a direction opposite to the direction along which the other light emitting elements LD are connected. Even if a driving voltage (e.g., a forward driving voltage) is applied between the first pixel electrode CNE1 and the second pixel electrode CNE2, the reverse light emitting element LDr may remain in an inactive state, and therefore, substantially no current may flow through the reverse light emitting element LDr.

[0099] The pixel circuit PXC of the sub-pixel SPXL can be connected to the scan line (or the first gate line) SLi and the data line DLj. The pixel circuit PXC of the sub-pixel SPXL can also be connected to the control line (or the second gate line) CLi and the sensing line (or readout line) SENj. In an embodiment, when the sub-pixel SPXL is set in the i-th row and j-th column of the display area DA, the pixel circuit PXC of the sub-pixel SPXL can connect the i-th scan line SLi, the j-th data line DLj, the i-th control line CLi and the j-th sensing line SENj of the display area DA. In some embodiments, the control line CLi can be connected to the scan line SLi or can be the scan line SLi.

[0100] The pixel circuit PXC may include transistors T1 to T3 and a storage capacitor (or capacitor) Cst.

[0101] The first transistor T1 may be a driving transistor for controlling a driving current applied to the light emitting unit EMU, and may be connected between the first driving power source VDD and the light emitting unit EMU. For example, the first terminal (or first transistor electrode) of the first transistor T1 may be electrically connected to the first driving power source VDD through the first power line PL1, the second terminal (or second transistor electrode) of the first transistor T1 may be electrically connected to the second node N2, and the gate electrode of the first transistor T1 may be electrically connected to the first node N1. The first transistor T1 may control the amount of driving current applied to the light emitting unit EMU from the first driving power source VDD through the second node N2 according to the voltage applied to the first node N1. In an embodiment, the first terminal of the first transistor T1 may be a drain electrode, and the second terminal of the first transistor T1 may be a source electrode. However, the disclosure is not limited thereto. In some embodiments, the first terminal may be a source electrode, and the second terminal may be a drain electrode.

[0102] The second transistor T2 may be a switching transistor that selects the sub-pixel SPXL in response to the scan signal and activates the sub-pixel SPXL, and may be connected between the data line DLj and the first node N1. The first terminal of the second transistor T2 may be connected to the data line DLj, the second terminal of the second transistor T2 may be connected to the first node N1, and the gate electrode of the second transistor T2 may be connected to the scan line SLi. The first terminal and the second terminal of the second transistor T2 may be different terminals. For example, in the case where the first terminal is a drain electrode, the second terminal may be a source electrode.

[0103] The second transistor T2 may be turned on when a scan signal having a gate-on voltage (e.g., a high-level voltage) is supplied from the scan line SLi to electrically connect the data line DLj and the first node N1 to each other. The first node N1 may be a point at which the second terminal of the second transistor T2 and the gate electrode of the first transistor T1 are connected to each other, and the second transistor T2 may transmit a data signal to the gate electrode of the first transistor T1.

[0104] The first terminal of the third transistor T3 may be connected to a sensing line SENj, the second terminal of the third transistor T3 may be connected to the second terminal of the first transistor T1, and the gate electrode of the third transistor T3 may be connected to the control line CLi. A voltage (initialization voltage) from an initialization power supply may be applied to the sensing line SENj. The third transistor T3 may be an initialization transistor capable of initializing the second node N2, and may be turned on when a sensing control signal is supplied from the control line CLi to transmit the voltage of the initialization power supply to the second node N2. Therefore, the second storage electrode electrically connected to the second node N2 of the storage capacitor Cst may be initialized. In some embodiments, the third transistor T3 may connect the first transistor T1 to the sensing line SENj to obtain a sensing signal through the sensing line SENj, and detect the characteristics of the sub-pixel SPXL (including the threshold voltage of the first transistor) by using the sensing signal, etc. Information about the characteristics of the sub-pixel SPXL may be used to convert image data so that characteristic deviations between the sub-pixels SPXL may be compensated.

[0105] The storage capacitor Cst may be formed between the first node N1 and the second node N2, or may be electrically connected between the first node N1 and the second node N2. The storage capacitor Cst may charge a data voltage corresponding to a data signal supplied to the first node N1 during one frame period. Thus, the storage capacitor Cst may store a voltage corresponding to a difference between a voltage of the gate electrode of the first transistor T1 and a voltage of the second node N2.

[0106] A parasitic capacitor (or parasitic capacitance) Cpara may be formed between the first node N1 and a signal line adjacent to the first node N1. For example, the signal line may be a scan line SLi, a data line DLj, and / or a power line to which the voltages of the first driving power source VDD and the second driving power source VSS are applied. The parasitic capacitor Cpara may have an influence on the voltage (or voltage fluctuation) of the first node N1, and thus, the sub-pixel SPXL may not emit light with a desired brightness. In order to reduce or eliminate the influence of the parasitic capacitor Cpara, it may be necessary to increase the capacitance of the storage capacitor Cst. This will be referred to later. Figure 5 The effect of the parasitic capacitor Cpara is described and will be referred to later. Fig.10 A storage capacitor Cst having increased capacitance is described.

[0107] The light emitting unit EMU may include at least one series stage (or stages) including a plurality of light emitting elements LD electrically connected in parallel to each other.

[0108] In an embodiment, the light emitting unit EMU may be configured to have a series / parallel hybrid structure. Figure 4bAs shown in , the light emitting unit EMU may be constructed to include a first series stage SET1 and a second series stage SET2. Figure 4c As shown in FIG, the light emitting unit EMU may be configured to include a first series stage SET1, a second series stage SET2, a third series stage SET3, and a fourth series stage SET4. The number of series stages included in the light emitting unit EMU may be changed differently. For example, the light emitting unit EMU may include three or five or more series stages.

[0109] Reference Figure 4b , the light emitting unit EMU may include a first series stage SET1 and a second series stage SET2 sequentially connected between a first driving power source VDD and a second driving power source VSS. Each of the first series stage SET1 and the second series stage SET2 may include two electrodes (CNE1 and CTE_S1 or CTE_S2 and CNE2) constituting an electrode pair of the corresponding series stage and a plurality of light emitting elements LD connected in parallel between the two electrodes (CNE1 and CTE_S1 or CTE_S2 and CNE2) in the same direction.

[0110] The first series stage (or first stage) SET1 may include a first pixel electrode CNE1 (or a second pixel electrode) and a first sub intermediate electrode CTE_S1, and include at least one first light emitting element LD1 connected between the first pixel electrode CNE1 and the first sub intermediate electrode CTE_S1. The first series stage SET1 may further include a reverse light emitting element LDr connected between the first pixel electrode CNE1 and the first sub intermediate electrode CTE_S1 in a direction opposite to the other first light emitting elements LD1.

[0111] The second series stage (or second stage) SET2 may include a second sub intermediate electrode CTE_S2 and a second pixel electrode CNE2 (or a first pixel electrode), and includes at least one second light emitting element LD2 connected between the second sub intermediate electrode CTE_S2 and the second pixel electrode CNE2. The second series stage SET2 may also include a reverse light emitting element LDr connected between the second sub intermediate electrode CTE_S2 and the second pixel electrode CNE2 in a direction opposite to the other second light emitting elements LD2.

[0112] The first sub-intermediate electrode CTE_S1 of the first series stage SET1 and the second sub-intermediate electrode CTE_S2 of the second series stage SET2 may be integrated with each other. In an embodiment, the first sub-intermediate electrode CTE_S1 and the second sub-intermediate electrode CTE_S2 may constitute a first intermediate electrode CTE1 for electrically connecting the continuous first series stage SET1 and the second series stage SET2. In the case where the first sub-intermediate electrode CTE_S1 and the second sub-intermediate electrode CTE_S2 are integrated with each other, the first sub-intermediate electrode CTE_S1 and the second sub-intermediate electrode CTE_S2 may be different parts of the first intermediate electrode CTE1. The terms "pixel electrode" and "intermediate electrode" are used to distinguish electrodes from each other, and the corresponding components (i.e., electrodes) are not limited by the terms.

[0113] Reference Figure 4c , the light emitting unit EMU may include a first series stage SET1 , a second series stage SET2 , a third series stage SET3 , and a fourth series stage SET4 sequentially connected between the first driving power source VDD and the second driving power source VSS.

[0114] Figure 4c The first cascade stage SET1 shown in FIG. Figure 4b The first cascade stage SET1 shown in FIG. 1 is substantially identical.

[0115] The second series stage SET2 may include at least one second light emitting element LD2 connected between the second sub intermediate electrode CTE_S2 and the third sub intermediate electrode CTE_S3. The third series stage SET3 may include at least one third light emitting element LD3 connected between the fourth sub intermediate electrode CTE_S4 and the fifth sub intermediate electrode CTE_S5. The fourth series stage SET4 may include at least one fourth light emitting element LD4 connected between the sixth sub intermediate electrode CTE_S6 and the second pixel electrode CNE2. The third sub intermediate electrode CTE_S3 and the fourth sub intermediate electrode CTE_S4 may be integrated with each other and may constitute the second intermediate electrode CTE2. The fifth sub intermediate electrode CTE_S5 and the sixth sub intermediate electrode CTE_S6 may be integrated with each other and may constitute the third intermediate electrode CTE3.

[0116] The light emitting unit EMU including the series stages SET1 to SET4 (or the light emitting element LD) connected in a series / parallel hybrid structure of the sub-pixel SPXL can easily control the driving current / voltage to be suitable for the specifications of the product to which the light emitting unit EMU is applied.

[0117] For example, compared with a light emitting unit having a structure in which the light emitting elements LD are connected only in parallel, the light emitting unit EMU including the series stages SET1 to SET4 of the sub-pixel SPXL can reduce the driving current. In other words, the light emitting unit EMU including the series stages SET1 to SET4 of the sub-pixel SPXL can emit light with higher brightness at the same driving current.

[0118] Furthermore, the light emitting unit EMU including the series stages SET1 to SET4 of the subpixel SPXL can reduce a driving voltage applied to both ends of the light emitting unit EMU compared to a light emitting unit having a structure in which the same number of light emitting elements LD are simply connected in series.

[0119] Despite Figure 4a , Figure 4b and Figure 4c 1 and 2 show a case where all the transistors T1 to T3 included in the pixel circuit PXC are n-type transistors, but the disclosure is not necessarily limited thereto. For example, at least one of the transistors T1 to T3 may be changed to a p-type transistor.

[0120] The structure and driving method of the sub-pixel SPXL may be changed variously. For example, the pixel circuit PXC may be configured to have Figure 4a , Figure 4b and Figure 4c The embodiments shown in the drawings have different pixel circuits with various structures and / or various driving methods.

[0121] In an embodiment, the pixel circuit PXC may not include the third transistor T3. In addition, the pixel circuit PXC may include other circuit elements such as a compensation transistor for compensating for a threshold voltage of the first transistor T1, an initialization transistor for initializing a voltage of the first node N1 and / or the first pixel electrode CNE1, an emission control transistor for controlling a period in which a driving current is supplied to the light emitting unit EMU, and / or a boost capacitor for boosting a voltage of the first node N1.

[0122] Figure 5 It is shown Figure 4a Schematic waveform diagram of the operation of the pixel shown in .

[0123] Reference Figure 4a and Figure 5In the first period P1, the scan signal (or the first gate signal) SC applied to the scan line SLi may have a gate-on voltage (e.g., a high level voltage), and the sensing control signal (or the second gate signal) SS applied to the control line CLi may have a gate-on voltage. The first period P1 may be a period allocated for writing a data signal to the sub-pixel SPXL in one frame FRAME. The first period P1 may be a non-emission period, and a period other than the first period P1 (i.e., another period of the frame FRAME, in particular, a period after the first period P1) may be an emission period.

[0124] The second transistor T2 may be turned on in response to a scan signal SC having a gate-on voltage, a data signal may be applied from the data line DLj to the first node N1, and a voltage of the first node N1 (i.e., a first node voltage V_N1) may be changed. Similarly, the third transistor T3 may be turned on in response to a sense control signal SS having a gate-on voltage, a voltage of an initialization power source may be applied to the second node N2, and a voltage of the second node N2 (i.e., a second node voltage V_N2) may be changed. A voltage corresponding to a difference between the first node voltage V_N1 and the second node voltage V_N2 may be charged in the storage capacitor Cst.

[0125] As the driving current flows through the first transistor T1 after the first period P1, the second node voltage V_N2 may increase, and the first node voltage V_N1 may increase correspondingly to the increase of the second node voltage V_N2 due to the storage capacitor Cst. The ideal voltage difference Vgs2 between the first node voltage V_N1 and the second node voltage V_N2 after the first period P1 may be equal to the voltage difference Vgs1 in the first period P1. However, due to the parasitic capacitor Cpara and the change in the threshold voltage of the first transistor T1 (e.g., a negative shift in the threshold voltage), the actual voltage difference Vgs3 may be different from the voltage difference Vgs1 in the first period P1, and the sub-pixel SPXL may emit light of a brightness different from the desired brightness. In order to eliminate the influence of the parasitic capacitor Cpara, the sub-pixel SPXL may be set to have a storage capacitor Cst with an increased capacitance.

[0126] Figure 6 The invention is a diagram showing the embodiment according to the disclosure Figure 3 A schematic cross-sectional view of a sub-pixel in a display device shown in FIG. Figure 6 In the embodiment, the first transistor T1 (see Figure 4a ) and the first and second power lines PL1 and PL2 are shown as examples of circuit elements that may be provided in the pixel circuit layer PCL.

[0127] Reference Figure 6, the sub-pixel SPXL (or the display device) may include a pixel circuit layer PCL and a display element layer DPL disposed on the first substrate SUB1.

[0128] The pixel circuit layer PCL may include a first transistor T1, a first power line PL1 and a second power line PL2, and a plurality of insulating layers BFL, GI, ILD, PSV, and VIA. The first transistor T1 may include a bottom metal layer BML, a semiconductor pattern SCP, a gate electrode GE, a source electrode (a second transistor electrode or a second terminal) SE, and a drain electrode (a first transistor electrode or a first terminal) DE.

[0129] The first conductive layer may be located between the first substrate SUB1 and the buffer layer BFL. The first conductive layer may include a conductive material. The conductive material may include at least one metal among various metal materials including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc., or their alloys. The first conductive layer may be configured as a single layer, a double layer, or a multilayer.

[0130] The first conductive layer may include a bottom metal layer BML, a first power line PL1, and a second power line PL2. The bottom metal layer BML and the gate electrode GE of the first transistor T1 may overlap each other with a buffer layer BFL interposed therebetween. The bottom metal layer BML may be disposed under the semiconductor pattern SCP of the first transistor T1. The bottom metal layer BML may serve as a light blocking pattern, thereby stabilizing the operating characteristics of the first transistor T1.

[0131] In some embodiments, the first transistor T1 may not include the bottom metal layer BML. The buffer layer BFL may be directly located on the first substrate SUB1. The bottom metal layer BML may be physically and / or electrically connected to the source electrode SE of the first transistor T1 to be described later through the contact hole of the insulating layer. Therefore, the threshold voltage of the first transistor T1 may move in the negative direction or the positive direction.

[0132] The buffer layer (or first insulating layer) BFL may cover the first conductive layer and may be located on the first substrate SUB1.

[0133] The buffer layer BFL may prevent impurities from diffusing into the pixel circuit layer PCL. The buffer layer BFL may include an inorganic material. For example, the inorganic material may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and such as aluminum oxide (AlO xThe buffer layer BFL may be omitted according to the material of the first substrate SUB1, process conditions, etc.

[0134] The semiconductor pattern SCP may be located on the buffer layer BFL. The semiconductor pattern SCP may include a first region (e.g., source region) connected to the source electrode SE, a second region (e.g., drain region) connected to the drain electrode DE, and a channel region between the first region and the second region. The channel region may overlap with the gate electrode GE of the first transistor T1 in the third direction DR3 (thickness direction of the first substrate SUB1). The semiconductor pattern SCP may be made of polycrystalline silicon, amorphous silicon, oxide semiconductor, etc.

[0135] The gate insulating layer (or second insulating layer) GI may be disposed on the semiconductor pattern SCP. The gate insulating layer GI may be disposed only on the semiconductor pattern SCP, or may be disposed on the entire area of ​​the first substrate SUB1. The gate insulating layer GI may include an inorganic material. However, the disclosure is not limited thereto, and the gate insulating layer GI may include an organic material. For example, the organic material may include at least one of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0136] The second conductive layer may be disposed on the gate insulating layer GI. Similar to the first conductive layer, the second conductive layer may include a conductive material. The second conductive layer may include a gate electrode GE, an eleventh connection pattern CP11, and a twenty-first connection pattern CP21.

[0137] The gate electrode GE may be disposed on the gate insulating layer GI to overlap the channel region of the semiconductor pattern SCP. The eleventh connection pattern CP11 may overlap the first power line PL1 in the third direction DR3, and the twenty-first connection pattern CP21 may overlap the second power line PL2 in the third direction DR3.

[0138] The interlayer insulating layer (first interlayer insulating layer or third insulating layer) ILD may cover the second conductive layer and may be disposed on the entire region of the first substrate SUB1. Similar to the gate insulating layer GI, the interlayer insulating layer ILD may include an inorganic material. The interlayer insulating layer ILD may include an organic material.

[0139] The third conductive layer may be disposed on the interlayer insulating layer ILD. Similar to the first conductive layer, the third conductive layer may include a conductive material. The third conductive layer may include a source electrode SE, a drain electrode DE, a twelfth connection pattern CP12, and a twenty-second connection pattern CP22.

[0140] The source electrode SE may be in contact with or connected to the first region of the semiconductor pattern SCP through a contact hole penetrating the interlayer insulating layer ILD, and may be in contact with or connected to the bottom metal layer BML through a contact hole penetrating the interlayer insulating layer ILD and the buffer layer BFL. The drain electrode DE may be in contact with or connected to the second region of the semiconductor pattern SCP through a contact hole penetrating the interlayer insulating layer ILD. Similar to the source electrode SE, the twelfth connection pattern CP12 may be in contact with or connected to the first power line PL1 and the eleventh connection pattern CP11, and the twenty-second connection pattern CP22 may be in contact with or connected to the second power line PL2 and the twenty-first connection pattern CP21. The eleventh connection pattern CP11 and the twelfth connection pattern CP12 may be connected to the first power line PL1 to reduce the resistance of the first power line PL1. Similarly, the twenty-first connection pattern CP21 and the twenty-second connection pattern CP22 may be connected to the second power line PL2 to reduce the resistance of the second power line PL2.

[0141] A protective layer (or second interlayer insulating layer) PSV may be provided on the entire area of ​​the first substrate SUB1 to cover the third conductive layer. The protective layer PSV may include an inorganic material. The protective layer PSV may be provided as a single layer or a multilayer including two or more layers. In some embodiments, the protective layer PSV may be omitted.

[0142] A via layer (or passivation layer) VIA may be disposed on the protection layer PSV. The via layer VIA may be disposed on the entire area of ​​the first substrate SUB1. The via layer VIA may include an organic material. A flat surface may be provided on the top of the via layer VIA.

[0143] The display element layer DPL may be located on the via layer VIA.

[0144] The display element layer DPL may include a first embankment pattern BNP1 and a second embankment pattern BNP2, a first electrode (a first alignment electrode or a first reflective electrode) ELT1 and a second electrode (a second alignment electrode or a second reflective electrode) ELT2, a first embankment BNK1, a light emitting element LD, a first pixel electrode (or a first contact electrode) CNE1 and a second pixel electrode (or a second contact electrode) CNE2, and a plurality of insulating layers INS1 to INS3.

[0145] The first bank pattern BNP1 and the second bank pattern BNP2 may be disposed on the via layer VIA.

[0146] Each of the first bank pattern BNP1 and the second bank pattern BNP2 may have a trapezoidal shape in a cross-sectional view, the width of which narrows as it approaches its top along the third direction DR3 from the surface (e.g., upper surface) of the via layer VIA. In some embodiments, each of the first bank pattern BNP1 and the second bank pattern BNP2 may include a curved surface having a semi-elliptical shape, a semi-circular shape (or a hemispherical shape), etc. in a cross-sectional view, the width of which narrows as it approaches its top along the third direction DR3 from the surface of the via layer VIA. However, the cross-sectional shape of each of the first bank pattern BNP1 and the second bank pattern BNP2 is not limited to the above-described embodiments, and may be variously changed within a range so that the efficiency of light emitted from each of the light emitting elements LD can be improved.

[0147] The first bank pattern BNP1 and the second bank pattern BNP2 may include an inorganic material and / or an organic material and may be configured as a single layer or multiple layers. In some embodiments, the first bank pattern BNP1 and the second bank pattern BNP2 may be omitted. For example, a structure corresponding to the first bank pattern BNP1 and the second bank pattern BNP2 may be formed in the via layer VIA.

[0148] The first and second electrodes ELT1 and ELT2 may be disposed on the via layer VIA and the first and second bank patterns BNP1 and BNP2 .

[0149] The first electrode ELT1 may be disposed on the first bank pattern BNP1, ​​and the second electrode ELT2 may be disposed on the second bank pattern BNP2. The first and second electrodes ELT1 and ELT2 may have surface profiles corresponding to shapes of the first and second bank patterns BNP1 and BNP2, respectively, in a cross-sectional view.

[0150] Each of the first electrode ELT1 and the second electrode ELT2 may include a reflective conductive material to reflect light emitted from the light emitting element LD to an image display direction (eg, third direction DR3) of the display device. Each of the first electrode ELT1 and the second electrode ELT2 may be configured as a single layer or multiple layers.

[0151] The second electrode ELT2 (or the first electrode ELT1) may be in contact or connected to the twelfth connection pattern CP12 through the first contact hole CNT1 penetrating the via layer VIA and the protective layer PSV. The second electrode ELT2 (or the first electrode ELT1) may be electrically connected to the first power line PL1. The second electrode ELT2 may be directly connected to the twelfth connection pattern CP12, but the disclosure is not limited thereto. For example, the second electrode ELT2 may be connected to the twelfth connection pattern CP12 (the eleventh connection pattern CP11 or the first power line PL1) through a bridge electrode.

[0152] The first electrode ELT1 and the second electrode ELT2 may be used as alignment electrodes for aligning the light emitting element LD in a manufacturing process of the display device.

[0153] The first insulating layer INS1 may be disposed on the via layer VIA to cover at least a portion of the first electrode ELT1 and the second electrode ELT2. The first insulating layer INS1 may be located between the first electrode ELT1 and the second electrode ELT2 and may prevent a short circuit (e.g., an electrical short circuit) between the first electrode ELT1 and the second electrode ELT2. The first insulating layer INS1 may include an inorganic material or an organic material.

[0154] The light emitting element LD may be disposed on the first insulating layer INS1 and may be aligned between the first electrode ELT1 and the second electrode ELT2 such that a first end EP1 of the light emitting element LD faces the first electrode ELT1 and a second end EP2 of the light emitting element LD faces the second electrode ELT2.

[0155] The first end portion EP1 of the light emitting element LD may partially overlap the first electrode ELT1 in the third direction DR3 , and the second end portion EP2 of the light emitting element LD may partially overlap the second electrode ELT2 in the third direction DR3 .

[0156] The first bank BNK1 may be disposed on the first insulating layer INS1. The first bank BNK1 may have a dam structure that prevents a solution including the light emitting element LD from being introduced into an adjacent sub-pixel SPXL or controls a certain amount of solution to be supplied to each sub-pixel SPXL. In addition, the first bank BNK1 may define an emission area EA. For example, the emission area EA may correspond to the opening OPA1 of the first bank BNK1.

[0157] The first bank BNK1 may include an organic material. In some embodiments, the first bank BNK1 may include a light blocking material and / or a reflective material. The first bank BNK1 may prevent a light leakage defect in which light (or a light beam) leaks between adjacent sub-pixels SPXL. For example, the first bank BNK1 may include a color filter material or a black matrix material. In another example, a reflective layer may be separately provided and / or formed on the first bank BNK1 to further improve the efficiency of light emitted from the sub-pixel SPXL to the outside.

[0158] The second insulating layer (or second insulating pattern) INS2 may be disposed on the light emitting element LD. The second insulating layer INS2 may be located on a portion of the top surface of the light emitting element LD so that the first end EP1 and the second end EP2 of the light emitting element LD are not covered by the second insulating layer INS2. In some embodiments, the second insulating layer INS2 may be disposed on the first insulating layer INS1 and the first bank BNK1.

[0159] The second insulating layer INS2 may include an inorganic material or an organic material according to design conditions of a display device including the light emitting element LD, etc. After the light emitting element LD is aligned on the first insulating layer INS1, the second insulating layer INS2 may be formed on the light emitting element LD so that the light emitting element LD may be prevented from being dislocated at the position where the light emitting element LD is aligned. In the case where there is an empty gap (or space) between the first insulating layer INS1 and the light emitting element LD before the second insulating layer INS2 is formed, the empty gap may be filled with the second insulating layer INS2 in the process of forming the second insulating layer INS2.

[0160] The first pixel electrode CNE1 may be disposed on the first electrode ELT1. The first pixel electrode CNE1 may be in direct contact with the first end EP1 of the light emitting element LD. The first pixel electrode CNE1 may be in contact or connected with the source electrode SE of the first transistor T1 through a second contact hole CNT2 penetrating the second insulating layer INS2, the first insulating layer INS1, the via layer VIA, and the protective layer PSV. For example, the first pixel electrode CNE1 may electrically connect the first end EP1 of the light emitting element LD to the source electrode SE of the first transistor T1.

[0161] The first pixel electrode CNE1 and the second pixel electrode CNE2 may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ) or indium gallium zinc oxide (IGZO) transparent conductive materials.

[0162] The third insulating layer INS3 may be located above the second insulating layer INS2 and the first pixel electrode CNE1 to cover the second insulating layer INS2 and the first pixel electrode CNE1. The third insulating layer INS3 may be located so that an edge of the third insulating layer INS3 contacts one end of the second insulating layer INS2. Therefore, the second end EP2 of the light emitting element LD may be exposed.

[0163] The third insulating layer INS3 may include an inorganic material or an organic material.

[0164] The second pixel electrode CNE2 may be disposed on the second electrode ELT2. The second pixel electrode CNE2 may be in direct contact with the second end EP2 of the light emitting element LD. The second pixel electrode CNE2 may be in contact or connected with the twenty-second connection pattern CP22 through a third contact hole CNT3 penetrating the third insulating layer INS3, the second insulating layer INS2, the first insulating layer INS1, the via layer VIA, and the protective layer PSV. For example, the second pixel electrode CNE2 may electrically connect the second end EP2 of the light emitting element LD to the second power line PL2.

[0165] Compared with a conductive material (or metal material) having a certain reflectivity, a transparent conductive material (e.g., ITO) may have excellent bonding and low contact resistance with a conductive layer (e.g., source electrode SE and the second connection pattern CP22) in the pixel circuit layer PCL. Therefore, the first pixel electrode CNE1 and the second pixel electrode CNE2 may be directly connected to the components in the pixel circuit layer PCL without being connected to the first electrode ELT1 and the second electrode ELT2. However, the disclosure is not limited thereto.

[0166] Despite Figure 6 The case where the first pixel electrode CNE1 and the second pixel electrode CNE2 are located at different layers and the third insulating layer INS3 is interposed therebetween has been described above, but the disclosure is not limited thereto. For example, the first pixel electrode CNE1 and the second pixel electrode CNE2 may be disposed at the same layer (eg, on the second insulating layer INS2) by the same process.

[0167] Figure 7a The invention is a diagram showing the embodiment according to the disclosure Figure 3 Schematic cross-sectional view of a sub-pixel in a display device shown in FIG. Figure 7b and Figure 7c Each of the embodiments shown in FIG. Figure 3 Schematic cross-sectional view of a pixel in the display device shown in . Figure 7c Shown with Figure 7b The embodiment in the embodiment is compared to another embodiment of the pixel having a modified position of the color conversion layer CCL. For example, in Figure 7b An embodiment in which a color conversion layer CCL is located on top of a display element layer DPL by a continuous process is disclosed in Figure 7c An embodiment is disclosed in which a second substrate SUB2 including a color conversion layer CCL is located on a display element layer DPL through a bonding process. Figure 7a , Figure 7b and Figure 7c The embodiments shown in will be described in conjunction with the above-mentioned embodiments (for example, Figure 6 The embodiments shown in FIG. 1 and FIG. 2 are different from each other to avoid redundancy.

[0168] Reference Figure 6 and Figure 7a The sub-pixel SPXL (or the display device) may further include a light conversion layer LCPL disposed on the display element layer DPL.

[0169] The light conversion layer LCPL may include a second bank BNK2, a color conversion layer CCL, and color filters CF1 to CF3.

[0170] The second bank BNK2 may be disposed on the display element layer DPL. The second bank BNK2 may be located in the non-emission area NEA (see FIG. Figure 7b ) and may have a structure that defines a position where a color conversion layer CCL is to be supplied.

[0171] The second bank BNK2 may include an organic material. In some embodiments, the second bank BNK2 may include a light blocking material. In an embodiment, the second bank BNK2 may be a black matrix. In some embodiments, the second bank BNK2 may include at least one light blocking material and / or at least one reflective material. Therefore, the second bank BNK2 reflects the light emitted from the color conversion layer CCL to the image display direction (or the third direction DR3) of the display device, thereby improving the light emission efficiency of the sub-pixel SPXL.

[0172] The color conversion layer CCL may be disposed on the display element layer DPL (or the light emitting element LD) in a region surrounded by the second bank BNK2.

[0173] The color conversion layer CCL may include color conversion particles (or wavelength conversion particles) QD corresponding to a specific color. In an embodiment, the color conversion layer CCL may include color conversion particles QD for converting light of a first color (or a first wavelength band) incident from the light emitting element LD into light of a second color (specific color or second wavelength band) and releasing light having the converted wavelength.

[0174] Reference Figure 7b In the case where the first subpixel SPXL1 is a red pixel (or a red subpixel), the first color conversion layer CCL1 of the first subpixel SPXL1 may include first color conversion particles QDr of red quantum dots, which convert the first color light emitted from the light emitting element LD into second color light (e.g., red light).

[0175] When the second subpixel SPXL2 is a green pixel (or green subpixel), the second color conversion layer CCL2 of the second subpixel SPXL2 may include second color conversion particles QDg of green quantum dots, which convert the first color light emitted from the light-emitting element LD into a third color light (e.g., green light).

[0176] When the third subpixel SPXL3 is a blue pixel (or blue subpixel), the third color conversion layer CCL3 of the third subpixel SPXL3 may include color conversion particles of blue quantum dots, which convert the first color light emitted from the light emitting element LD into a fourth color light (e.g., blue light).

[0177] In some embodiments, when the third sub-pixel SPXL3 is a blue pixel (or a blue sub-pixel) and the light-emitting element LD emits a blue series of light, the third sub-pixel SPXL3 may include a light scattering layer containing light scattering particles SCT. In some embodiments, the light scattering layer may be omitted. In other embodiments, when the third sub-pixel SPXL3 is a blue pixel (or a blue sub-pixel), a transparent polymer may be provided instead of the third color conversion layer CCL3.

[0178] Return to reference Figure 7a , a fourth insulating layer INS4 may be disposed on the color conversion layer CCL and the second bank BNK2.

[0179] The fourth insulating layer INS4 may be disposed on the entire area of ​​the first substrate SUB1 to cover the second bank BNK2 and the color conversion layer CCL. The fourth insulating layer INS4 may include an inorganic material and / or an organic material. In some embodiments, the fourth insulating layer INS4 may totally reflect the light emitted from the color conversion layer CCL (e.g., light advancing in an oblique direction) by using the refractive index difference between the fourth insulating layer INS4 and adjacent components and improve the light emission efficiency of the sub-pixel SPXL. To this end, the fourth insulating layer INS4 may have a lower refractive index than the color conversion layer CCL.

[0180] In some embodiments, the fourth insulating layer INS4 may reduce a step difference caused by components disposed thereunder and may have a flat surface.

[0181] In an embodiment, the first capping layer CAP1 and the second capping layer CAP2 may be disposed on the top and the bottom of the fourth insulating layer INS4, respectively.

[0182] The first capping layer CAP1 may be disposed on the color conversion layer CCL and prevent moisture (or a solution used in a subsequent process) from penetrating into the color conversion layer CCL from the bottom thereof. The first capping layer CAP1 may include an inorganic material.

[0183] The first capping layer CAP1 may be disposed on the color conversion layer CCL and prevent moisture (or a solution used in a subsequent process) from penetrating into the color conversion layer CCL from the bottom thereof. The first capping layer CAP1 may include an inorganic material.

[0184] The second capping layer CAP2 may be disposed on the fourth insulating layer INS4 and include an inorganic material. The second capping layer CAP2 may prevent moisture from penetrating into the fourth insulating layer INS4. In some embodiments, the second capping layer CAP2 may increase adhesion between the fourth insulating layer INS4 and the color filter layer.

[0185] A color filter layer may be disposed on the fourth insulating layer INS4.

[0186] Reference Figure 7b , the color filter layer may include a color filter CF corresponding to the color of each of the adjacent sub-pixels. For example, the first color filter CF1 may be disposed on the first color conversion layer CCL1 of the first sub-pixel SPXL1, the second color filter CF2 may be disposed on the second color conversion layer CCL2 of the second sub-pixel SPXL2, and the third color filter CF3 may be disposed on the third color conversion layer CCL3 of the third sub-pixel SPXL3. Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a color filter material for selectively transmitting light of a specific color converted in the color conversion layer CCL. In an embodiment, the first color filter CF1 may be a red color filter, the second color filter CF2 may be a green color filter, and the third color filter CF3 may be a blue color filter. The above-mentioned color filters CF may be disposed on the surface of the fourth insulating layer INS4 to correspond to the color conversion layer CCL.

[0187] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed to overlap each other in the non-emission area NEA to block light interference between adjacent sub-pixels. In some embodiments, a separate light blocking pattern instead of the stacked structure of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed in the non-emission area NEA.

[0188] The fifth insulating layer INS5 may be disposed above the color filter layer. The fifth insulating layer INS5 may include an inorganic material or an organic material. The fifth insulating layer INS5 may entirely cover the components located therebelow, thereby blocking moisture, humidity, etc. from being introduced into the color filter layer and the display element layer DPL from the outside. In an embodiment, the fifth insulating layer INS5 may be formed as a multilayer. For example, the fifth insulating layer INS5 may include at least two inorganic layers and at least one organic layer interposed between the at least two inorganic layers. However, the material and / or structure of the fifth insulating layer INS5 may be changed differently. In some embodiments, at least one covering layer, at least one filler layer, and / or an upper substrate may be further provided on the fifth insulating layer INS5.

[0189] Although the above-mentioned embodiment has described the case where the color conversion layer CCL is directly formed on the display element layer DPL, the disclosure is not limited thereto. In some embodiments, the color conversion layer CCL may be formed on a separate substrate (e.g., Figure 7c The substrate SUB2 is shown in the figure to be bonded to the display element layer DPL through an adhesive material. For example, the adhesive material may be an optically transparent adhesive, but the disclosure is not limited thereto.

[0190] The second substrate (or upper substrate) SUB2 may constitute an encapsulation substrate and / or a window member of the display device. The second substrate SUB2 and the first substrate SUB1 may be formed of the same material or different materials.

[0191] Reference Figure 7c , the color conversion layer CCL and the color filter CF may be disposed under the second substrate SUB2 to face the display element layer DPL.

[0192] The light blocking pattern LBP may be positioned adjacent to the color conversion layer CCL and the color filter CF. The light blocking pattern LBP may be disposed under the second substrate SUB2 corresponding to the non-emission area NEA. The light blocking pattern LBP may be a black matrix.

[0193] In the case where the sub-pixel SPXL includes a light conversion layer LCPL on the display element layer DPL (i.e., in the case where the sub-pixel SPXL includes a color conversion layer CCL and a color filter CF arranged above the light-emitting element LD), light with excellent color reproducibility can be emitted through the color conversion layer CCL and the color filter CF, and the light emission efficiency of the sub-pixel SPXL can be improved.

[0194] Figure 8 The invention is a diagram showing the embodiment according to the disclosure Figure 3 Layout diagram of pixels in a display device shown in FIG. Figure 8 In the pixel circuit (see Figure 4a ) shows an embodiment of a pixel PXL. Figure 9a and Figure 9b Each is according to the disclosed embodiment Figure 8 An enlarged plan view of a third pixel circuit in the pixel shown in FIG. Fig.10 is a diagram showing a method according to an embodiment of the disclosure Figure 9a Schematic cross-sectional view of a storage capacitor taken along line II′ shown in FIG.

[0195] Reference Figure 3 , Figure 8 , Figure 9a and Fig.10 , the pixel PXL may include a first sub-pixel SPXL1 (see Figure 3) of the first pixel circuit PXC1, for the second sub-pixel SPXL2 (see Figure 3 ) and for the second pixel circuit PXC2 and for the third sub-pixel SPXL3 (see Figure 3 ). The first pixel circuit PXC1 may have a structure symmetrical to that of the third pixel circuit PXC3 in the first direction DR1, and the second pixel circuit PXC2 may have a structure substantially the same as or similar to that of the third pixel circuit PXC3. Therefore, common components of the pixel circuits PXC1 to PXC3 (or sub-pixels SPXL1 to SPXL3) are described based on the third pixel circuit PXC3 (or third sub-pixel SPXL3), and repeated descriptions will not be repeated.

[0196] Each of the first vertical power line PL1_V, the sensing line SEN, the first data line DL1, the second data line DL2, the third data line DL3, the second vertical power line PL2_V, and the first vertical scan line SL1_V may extend substantially in the second direction DR2, and the first vertical power line PL1_V, the sensing line SEN, the first data line DL1, the second data line DL2, the third data line DL3, the second vertical power line PL2_V, and the first vertical scan line SL1_V may be arranged in the first direction DR1. The second vertical scan line SL2_V may correspond to the first vertical scan line SL1_V. For example, the first vertical scan line SL1_V may be a component for the pixel PXL, and the second vertical scan line SL2_V may be a component for a pixel adjacent to the pixel PXL in the first direction DR1 (or the opposite direction of the first direction DR1). Similar to the first vertical scan line SL1_V and the second vertical scan line SL2_V, the first vertical power line PL1_V, the sensing line SEN, the first data line DL1, the second data line DL2, the third data line DL3, the second vertical power line PL2_V may be repeatedly arranged in the first direction DR1 for other pixels included in the same row as the pixel PXL. The first vertical power line PL1_V, the sensing line SEN, the first data line DL1, the second data line DL2, the third data line DL3, the second vertical power line PL2_V, and the first vertical scan line SL1_V may be included in the reference direction DR1. Figure 6 For example, the first vertical power line PL1_V, the sensing line SEN, the first data line DL1, the second data line DL2, the third data line DL3, the second vertical power line PL2_V and the first vertical scan line SL1_V may be connected to Figure 6 The bottom metal layer BML shown in FIG. 5 is disposed at the same layer and is formed through the same process as the bottom metal layer BML.

[0197] The first horizontal power line PL1_H, the first horizontal scan line SL1_H, and the second horizontal power line PL2_H may extend substantially in the first direction DR1, and the first horizontal power line PL1_H, the first horizontal scan line SL1_H, and the second horizontal power line PL2_H may be arranged in the second direction DR2. The first horizontal power line PL1_H, the first horizontal scan line SL1_H, and the second horizontal power line PL2_H may include a first horizontal power line PL1_H, a first horizontal power line SL1_H, and a second horizontal power line PL2_H. Figure 6 For example, the first horizontal power line PL1_H, the first horizontal scan line SL1_H and the second horizontal power line PL2_H may be connected to Figure 6 The source electrode SE and the drain electrode DE shown in FIG. 8 are provided at the same layer and are formed by the same process as the source electrode SE and the drain electrode DE.

[0198] The first vertical scan line SL1_V and the first horizontal scan line SL1_H may constitute one scan line (eg, Figure 4a The first vertical scan line SL1_V may be omitted depending on the arrangement of a scan driver for supplying a scan signal to the scan line. The first vertical power line PL1_V and the first horizontal power line PL1_H may constitute the first power line PL1 (see Figure 4a ), the second vertical power line PL2_V and the second horizontal power line PL2_H may constitute the second power line PL2 (see Figure 4a The first power line PL1 may extend throughout the display panel PNL through the first vertical power line PL1_V and the first horizontal power line PL1_H (see FIG. Figure 3 ) has a mesh structure throughout the entire area. Similarly, the second power line PL2 can be spread over the display panel PNL through the second vertical power line PL2_V and the second horizontal power line PL2_H (see Figure 3 ) has a mesh structure throughout the entire area. Figure 6 As described, the first horizontal power line PL1_H may be connected to the second electrode ELT2 through the first contact hole CNT1.

[0199] As reference Figure 6 As described, the twenty-first connection pattern CP21 and the twenty-second connection pattern CP22 may overlap the second vertical power line PL2_V and be connected to the second vertical power line PL2_V through the contact hole CH. Similarly, the first sub-pattern CP_S1 and the second sub-pattern CP_S2 may overlap the first vertical scan line SL1_V and be connected to the first vertical scan line SL1_V through the contact hole CH.

[0200] The pixel circuits PXC1 to PXC3 of the pixel PXL may be located in an area (or pixel area) divided by at least some of the first vertical power line PL1_V, the first horizontal power line PL1_H, the second vertical power line PL2_V, and the second horizontal power line PL2_H. The first pixel circuit PXC1 may be located adjacent to the third pixel circuit PXC3 in the second direction DR2, and the second pixel circuit PXC2 may be located adjacent to the third pixel circuit PXC3 in the opposite direction of the second direction DR2.

[0201] In the third pixel circuit PXC3, the first semiconductor pattern SCP1 may extend from the first vertical power line PL1_V in the first direction DR1. The first semiconductor pattern SCP1 may constitute the first transistor T1. One end of the first semiconductor pattern SCP1 may be connected to the first vertical power line PL1_V through the contact hole CH. The other end of the first semiconductor pattern SCP1 may overlap with the capacitor electrodes CE1 to CE3 and be connected to the first capacitor electrode CE1 and the third capacitor electrode CE3 through the contact hole CH.

[0202] The first capacitor electrode CE1 and the third capacitor electrode CE3 may have an "L" planar shape and have substantially the same or similar areas to each other except for the protrusion. In a plan view, except for the protrusion, the second capacitor electrode CE2 (or the gate electrode of the first transistor T1) may be covered by the first capacitor electrode CE1. For example, in a plan view, the second capacitor electrode CE2 may be positioned a specific distance (e.g., about 1 μm to about 2 μm) inward from the edge of the first capacitor electrode CE1 (or the third capacitor electrode CE3) as a whole. The second capacitor electrode CE2 may overlap with the first capacitor electrode CE1 and the third capacitor electrode CE3 in most of the area except for the area in which the contact hole CH is formed. For example, the second capacitor electrode CE2 may have a "W" planar shape. However, the disclosure is not limited thereto, and the shape of the second capacitor electrode CE2 may vary according to the position of the contact hole CH adjacent to the second capacitor electrode CE2.

[0203] Reference Figure 6 and Fig.10 , the first capacitor electrode CE1 may be included in the first conductive layer between the first substrate SUB1 and the buffer layer BFL, the second capacitor electrode CE2 may be included in the second conductive layer between the gate insulating layer GI and the interlayer insulating layer ILD, and the third capacitor electrode CE3 may be included in the third conductive layer on the interlayer insulating layer ILD. The first capacitor electrode CE1 and the second capacitor electrode CE2 may overlap each other to form a first sub-capacitor. The second capacitor electrode CE2 and the third capacitor electrode CE3 may overlap each other to form a second sub-capacitor. Figure 8 and Figure 9a As shown in FIG. 1 , the third capacitor electrode CE3 may be formed by a contact hole CH (ie, a hole penetrating the capacitor electrode CE3). Fig.10 The contact hole CH of the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD in the embodiment of the present invention is connected to the first capacitor electrode CE1, and thus the first sub-capacitor and the second sub-capacitor may be connected in parallel to constitute the storage capacitor Cst. In the case where the storage capacitor Cst includes the first sub-capacitor and the second sub-capacitor formed by the capacitor electrodes CE1 to CE3, a sufficient capacitance of the storage capacitor Cst may be ensured compared to a storage capacitor including only the first sub-capacitor or the second sub-capacitor. Therefore, the reference capacitor Cst may be reduced or excluded. Figure 5 Describe the influence of parasitic capacitor Cpara.

[0204] Return to reference Figure 8 and Figure 9a , one end of the second capacitor electrode CE2 may overlap with the channel region of the first semiconductor pattern SCP1, and the second capacitor electrode CE2 may constitute the gate electrode of the first transistor T1. In a plan view, the other end of the second capacitor electrode CE2 may extend farther than the first capacitor electrode CE1 and the third capacitor electrode CE3 in the second direction DR2. The other end of the second capacitor electrode CE2 may be connected to the first bridge pattern BRP1 (or the second transistor T2) through the contact hole CH. The portion of the second capacitor electrode CE2 overlapping with the first capacitor electrode CE1 and the third capacitor electrode CE3 may be referred to as a main body part BODY, and the portion extending from the main body part BODY and protruding farther than the first capacitor electrode CE1 and the third capacitor electrode CE3 (or their edges) may be referred to as a first protrusion part (or a first protrusion pattern) PRT1. The first protrusion part PRT1 may protrude toward the second transistor T2. The direction along which the first protrusion part PRT1 protrudes or extends from the main body part BODY may be defined as an extension direction EDR. Figure 9a In the embodiment shown in FIG, the extension direction EDR may be parallel to the second direction DR2. The first line width W1 of the first protrusion part PRT1 (ie, the width in a direction perpendicular to the extension direction EDR) may be smaller than the width of the body part BODY (ie, the width in the first direction DR1).

[0205] In an embodiment, the second capacitor electrode CE2 may further include a second protrusion part (or a second protrusion pattern) PRT2 extending from the body part BODY and protruding farther than the first capacitor electrode CE1 and the third capacitor electrode CE3 (or their edges) in the opposite direction of the extension direction EDR. The second protrusion part PRT2 may not be directly connected to a component other than the body part BODY. The second line width W2 (i.e., the width in a direction perpendicular to the extension direction EDR) of the second protrusion part PRT2 may be equal to or similar to the first line width W1 of the first protrusion part PRT1.

[0206] In the process of forming the capacitor electrodes CE1 to CE3, an alignment error may occur between the capacitor electrodes CE1 to CE3. An alignment error may occur between the second capacitor electrode CE2 as an electrode of the storage capacitor Cst and the first capacitor electrode CE1 and the third capacitor electrode CE3 as the other electrodes of the storage capacitor Cst. For example, the second capacitor electrode CE2 may be moved by 1 μm in the second direction DR2 relative to the first capacitor electrode CE1 and the third capacitor electrode CE3. The overlapping area of ​​the first protrusion part PRT1 relative to the first capacitor electrode CE1 and the third capacitor electrode CE3 may be reduced or increased. On the contrary, the overlapping area of ​​the second protrusion part PRT2 relative to the first capacitor electrode CE1 and the third capacitor electrode CE3 may be increased or reduced. For example, the increment / decrement of the overlapping area of ​​the second protrusion part PRT2 may offset the decrement / increment of the overlapping area of ​​the first protrusion part PRT1. Therefore, although there is an alignment error between the capacitor electrodes CE1 to CE3, the overlapping area of ​​the second capacitor electrode CE2 relative to the first capacitor electrode CE1 and the third capacitor electrode CE3 can be constantly maintained, and the capacitance of the storage capacitor Cst can be constantly maintained. The pixels PXL in the display device may have storage capacitors Cst having the same capacitance or uniform capacitance, and degradation of display quality (eg, brightness deviation and mura) caused by capacitance deviation between the storage capacitors Cst may be reduced or prevented.

[0207] Compared with the second capacitor electrode not including the second protrusion part PRT2, the area of ​​the second capacitor electrode CE2 including the second protrusion part PRT2 overlapping with the first capacitor electrode CE1 and the third capacitor electrode CE3 can be increased, and thus the capacitance of the storage capacitor Cst can be more sufficiently ensured. Figure 5 Describe the influence of parasitic capacitor Cpara.

[0208] In an embodiment, the second protrusion part PRT2 of the second capacitor electrode CE2 may protrude from the main body part BODY by about 2 μm to about 4 μm or about 3 μm. For example, the length or margin MR of the second protrusion part PRT2 may be about 2 μm to about 4 μm or about 3 μm. For example, by considering that the process error (e.g., the alignment error between the capacitor electrodes CE1 to CE3) is about 2 μm, the second protrusion part PRT2 may protrude from the main body part BODY by about 2 μm or more. In the case where the capacitor electrodes CE1 and CE3 (e.g., the corner portions of the first capacitor electrode CE1 and the third capacitor electrode CE3) have a circular shape, even if the overlapping area of ​​the second capacitor electrode CE2 may vary according to the arrangement position of the second protrusion part PRT2, the overlapping area of ​​the second capacitor electrode CE2 may be additionally changed. In view of this, the second capacitor electrode CE2 may also additionally protrude by about 1 μm or more. Considering the distance between adjacent pixel circuits (eg, the third pixel circuit PXC3 and the second pixel circuit PXC2 ), the second protrusion part PRT2 may protrude from the body part BODY by about 4 μm or less. However, the disclosure is not limited thereto.

[0209] In an embodiment, the first protrusion feature PRT1 and the second protrusion feature PRT2 may be aligned or may not be aligned in the extension direction EDR. Figure 9a As shown in , the first protrusion part PRT1 and the second protrusion part PRT2 may not be collinear with each other in the extension direction EDR. Figure 9b As shown in FIG. 1 , the first protrusion part PRT1 and the second protrusion part PRT2 may be collinear with each other in the extension direction EDR.

[0210] A portion of the third capacitor electrode CE3 of the third pixel circuit PXC3 may extend toward the second data line DL2 and be connected to the third bridge electrode BRE3 overlapping the second data line DL2. The third bridge electrode BRE3 may be connected to the first pixel electrode CNE1 of the third subpixel SPXL3 through the first contact hole CNT1 (see Figure 6 ).like Figure 8 As shown in FIG. 1 , a portion of the third capacitor electrode CE3 of the first pixel circuit PXC1 may extend toward the first vertical power line PL1_V and be connected to the first bridge electrode BRE1. The first bridge electrode BRE1 may be connected to the first pixel electrode CNE1 of the first sub-pixel SPXL1 through the first contact hole CNT1 (see FIG. 1 ). Figure 6 ). Similarly, a portion of the third capacitor electrode CE3 of the second pixel circuit PXC2 may extend toward the first vertical power line PL1_V and be connected to the second bridge electrode BRE2. The second bridge electrode BRE2 may be connected to the first pixel electrode CNE1 of the second sub-pixel SPXL2 through the first contact hole CNT1 (see Figure 6 The fourth bridge electrode BRE4 may be connected to the second vertical power line PL2_V or the second horizontal power line PL2_H, and connected to the second pixel electrode CNE2 through the third contact hole CNT3 (see FIG. 2 ). Figure 6 ). The bridge electrodes BRE1 to BRE4 together with the second capacitor electrode CE2 may be included in the second conductive layer.

[0211] In the third pixel circuit PXC3, the second semiconductor pattern SCP2 may be positioned to be spaced apart from the first semiconductor pattern SCP1 in an oblique direction (e.g., a direction between the first direction DR1 and the second direction DR2) and extend in the first direction DR1. The second semiconductor pattern SCP2 may constitute a second transistor T2. One end of the second semiconductor pattern SCP2 may be connected to the first bridge pattern BRP1 through a contact hole CH. The other end of the second semiconductor pattern SCP2 may overlap with the third data line DL3 and be connected to the third data line DL3 through a bridge pattern (e.g., a second bridge pattern BRP2).

[0212] In the third pixel circuit PXC3, the third semiconductor pattern SCP3 may be positioned to be spaced apart from the second semiconductor pattern SCP2 in the opposite direction of the second direction DR2 and extend in the first direction DR1. The third semiconductor pattern SCP3 may constitute a third transistor T3. One end of the third semiconductor pattern SCP3 may be connected to the first capacitor electrode CE1 and the third capacitor electrode CE3 through the contact hole CH. The other end of the third semiconductor pattern SCP3 may overlap with the sensing line SEN and be connected to the sensing line SEN through a bridge pattern (e.g., a third bridge pattern BRP3). The bridge patterns BRP1 to BRP3 together with the third capacitor electrode CE3 may be included in the third conductive layer.

[0213] One end of the first scan link line SL1_C may be connected to the first horizontal scan line SL1_H, extend from the first horizontal scan line SL1_H in the second direction DR2, and overlap the second and third semiconductor patterns SCP2 and SCP3 of each of the pixel circuits PXC1 to PXC3, thereby constituting a gate electrode of each of the second and third transistors T2 and T3.

[0214] As described above, the storage capacitor Cst may include a first sub-capacitor and a second sub-capacitor configured to have the first capacitor electrode CE1, the second capacitor electrode CE2, and the third capacitor electrode CE3 overlapped with each other, and the capacitance of the storage capacitor Cst may be sufficiently ensured compared to a storage capacitor including only the first sub-capacitor or the second sub-capacitor.

[0215] The second capacitor electrode CE2 may include a second protrusion part PRT2, which protrudes from the first capacitor electrode CE1 and the third capacitor electrode CE3 in the opposite direction of the extension direction EDR, corresponding to the first protrusion part PRT1 (i.e., the first protrusion part PRT1 protruding from the first capacitor electrode CE1 and the third capacitor electrode CE3 along the extension direction EDR and connected to the second transistor T2). Despite the alignment error between the capacitor electrodes CE1 to CE3, the overlapping area of ​​the second capacitor electrode CE2 relative to the first capacitor electrode CE1 and the third capacitor electrode CE3 can be constantly maintained by the second protrusion part PRT2, and the capacitance of the storage capacitor Cst can be constantly maintained. Therefore, the capacitance deviation of the storage capacitor Cst between the pixels PXL and the degradation of the display quality caused by the capacitance deviation (for example, brightness deviation and unevenness) can be reduced or prevented.

[0216] In addition, compared with the second capacitor electrode not including the second protrusion part PRT2, the area of ​​the second capacitor electrode CE2 including the second protrusion part PRT2 overlapping the first capacitor electrode CE1 and the third capacitor electrode CE3 can be increased, and thus the capacitance of the storage capacitor Cst can be more sufficiently ensured. Figure 5 Describe the influence of parasitic capacitor Cpara.

[0217] Fig.11 is a view showing a pixel circuit according to a comparative embodiment. Fig.12 It is shown along Fig.11 Schematic cross-sectional view of a comparative example of a storage capacitor taken along line II-II′ shown in FIG.

[0218] Reference Figure 9a , Fig.10 , Fig.11 and Fig.12 , except for the second protruding part PRT2, Fig.11 The pixel circuit PXC_C shown in FIG. Figure 9a The third pixel circuit PXC3 shown in FIG. 1 is substantially the same as or similar to that in FIG. 1 , and thus, a repeated description will not be repeated.

[0219] Fig.11 and Fig.12 The second capacitor electrode CE2_C of the storage capacitor Cst_C shown in FIG. Figure 9a and Fig.10 The second protrusion part PRT2 is shown in FIG.

[0220] In the manufacturing process of the display device, an alignment error may occur between the second capacitor electrode CE2_C, which is an electrode of the storage capacitor Cst_C, and the first capacitor electrode CE1 and the third capacitor electrode CE3, which are the other electrodes of the storage capacitor Cst_C. For example, the second capacitor electrode CE2_C may be moved by about 1 μm in the second direction DR2 relative to the first capacitor electrode CE1 and the third capacitor electrode CE3. The overlapping area of ​​the first protrusion part PRT1 relative to the first capacitor electrode CE1 and the third capacitor electrode CE3 may be reduced, and the capacitance of the storage capacitor Cst_C may be reduced. The capacitance variation or capacitance deviation of the storage capacitor Cst_C caused by the process error may cause brightness deviation between pixels.

[0221] therefore, Figures 8 to 10 The second capacitor electrode CE2 shown in the figure may include a second protrusion part PRT2 protruding from the first capacitor electrode CE1 and the third capacitor electrode CE3 in the opposite direction of the extension direction EDR of the first protrusion part PRT1, and therefore, the capacitance deviation of the storage capacitor Cst and the degradation of display quality caused by the capacitance deviation can be reduced or prevented.

[0222] Fig.13 The invention is a diagram showing the embodiment according to the disclosure Figure 3 A plan view of a pixel in a display device shown in FIG. Fig.13 In the light-emitting unit EMU (see Figure 4c ) briefly shows the pixel PXL.

[0223] Reference Figure 3 and Fig.13 The first sub-pixel SPXL1, the second sub-pixel SPXL2 and the third sub-pixel SPXL3 may have structures substantially the same as or similar to each other (or light emitting units EMU (see Figure 4c )). Therefore, common components of the first subpixel SPXL1, the second subpixel SPXL2, and the third subpixel SPXL3 are described based on the first subpixel SPXL1, and the overlapping description will not be repeated.

[0224] The pixel PXL may be formed in a pixel region disposed in the first substrate SUB1 (or via layer VIA). The pixel region may include an emission region EA and a non-emission region NEA other than the emission region EA. The non-emission region NEA may be a region disposed adjacent to the emission region EA, and the emission region EA may be defined by the first bank BNK1. However, the disclosure is not limited thereto.

[0225] The pixel PXL may include first and second electrodes ELT1 and ELT2 , a light emitting element LD, first and second pixel electrodes CNE1 and CNE2 , and intermediate electrodes CTE1 to CTE3 , but the disclosure is not limited thereto.

[0226] Each of the first and second electrodes ELT1 and ELT2 may extend in the second direction DR2, and the first and second electrodes ELT1 and ELT2 may be spaced apart from each other in the first direction DR1. The first and second electrodes ELT1 and ELT2 may be alternately arranged in the first direction DR1.

[0227] The first electrode ELT1 and the second electrode ELT2 may be separated from the first electrode ELT1 and the second electrode ELT2 included in the pixel adjacent to the pixel PXL in the second direction DR2, respectively, but the disclosure is not limited thereto. For example, at least one of the first electrode ELT1 and the second electrode ELT2 of the pixel PXL may be connected to an electrode corresponding to a pixel adjacent to the pixel PXL in the second direction DR2.

[0228] The first electrode ELT1 and the second electrode ELT2 can be used as alignment electrodes by inputting a mixed liquid (e.g., ink) including the light emitting element LD into the emission area EA and applying an alignment voltage. The first electrode ELT1 can become a first alignment electrode, and the second electrode ELT2 can become a second alignment electrode. The light emitting element LD can be aligned in a desired direction and / or at a desired position by an electric field formed between the first alignment electrode and the second alignment electrode.

[0229] The first and second electrodes ELT1 and ELT2 may have a bar shape extending in the second direction DR2 in a plan view, but the disclosure is not limited thereto. The shapes of the first and second electrodes ELT1 and ELT2 may be variously changed.

[0230] The light emitting element LD may be disposed between the first electrode ELT1 and the second electrode ELT2 such that the length L direction (see FIG. Figure 1 ) is substantially parallel to the first direction DR1. For example, in the first subpixel SPXL1, the first light emitting element LD1 may be disposed in the upper region of the first region (or the first path) between the first electrode ELT1 and the second electrode ELT2 on the left side in a plan view, and the second light emitting element LD2 may be disposed in the lower region of the first region in a plan view. The third light emitting element LD3 may be disposed in the lower region of the second region (or the second path) between the second electrode ELT2 and the first electrode ELT1 on the right side in a plan view, and the fourth light emitting element LD4 may be disposed in the upper region of the second region in a plan view.

[0231] The first pixel electrode CNE1 may be positioned to overlap the first end of the first light emitting element LD1 and the first electrode ELT1. The first pixel electrode CNE1 may be connected to the first end of the first light emitting element LD1. The first pixel electrode CNE1 may constitute the light emitting unit EMU (see Figure 4c ) and is connected to the first transistor T1 (see Figure 4c and Figure 8 ). The first pixel electrode CNE1 may be electrically separated from the first electrode ELT1. Corresponding to the first electrode ELT1, the first pixel electrode CNE1 may extend in the second direction DR2.

[0232] The first intermediate electrode CTE1 may be positioned to overlap with the second end of the first light emitting element LD1 and the second electrode ELT2. In addition, the first intermediate electrode CTE1 may be positioned to overlap with the first end of the second light emitting element LD2 and the first electrode ELT1. A portion of the first intermediate electrode CTE1 may have a bent shape. The first intermediate electrode CTE1 may physically and / or electrically connect the second end of the first light emitting element LD1 and the first end of the second light emitting element LD2 to each other.

[0233] The second intermediate electrode CTE2 may be positioned to overlap with the second end of the second light emitting element LD2 and the second electrode ELT2. In addition, the second intermediate electrode CTE2 may be positioned to overlap with the first end of the third light emitting element LD3 and the first electrode ELT1. The second intermediate electrode CTE2 may have a shape that bypasses the third intermediate electrode CTE3. The second intermediate electrode CTE2 may physically and / or electrically connect the second end of the second light emitting element LD2 and the first end of the third light emitting element LD3 to each other.

[0234] The third intermediate electrode CTE3 may be positioned to overlap with the second end of the third light emitting element LD3 and the second electrode ELT2. In addition, the third intermediate electrode CTE3 may be positioned to overlap with the first end of the fourth light emitting element LD4 and the first electrode ELT1. A portion of the third intermediate electrode CTE3 may have a bent shape. The third intermediate electrode CTE3 may physically and / or electrically connect the second end of the third light emitting element LD3 and the first end of the fourth light emitting element LD4 to each other.

[0235] The second pixel electrode CNE2 may be positioned to overlap the second end of the fourth light emitting element LD4 and the second electrode ELT2. The second pixel electrode CNE2 may be connected to the second end of the fourth light emitting element LD4. The second pixel electrode CNE2 may constitute the light emitting unit EMU (see Figure 4c ) of the cathode, and through the third contact hole CNT3 (see Figure 8) etc. are connected to the second power line. The second pixel electrodes CNE2 of the sub-pixels SPXL1 to SPXL3 may be connected to each other, but the disclosure is not limited thereto. Corresponding to the second electrode ELT2, the second pixel electrode CNE2 may extend in the second direction DR2.

[0236] Fig.14 and Fig.15 is a diagram showing the embodiment according to the disclosure Figure 8 A view of a pixel circuit included in a pixel shown in FIG.

[0237] Reference Figure 8 , Figure 9a , Fig.14 and Fig.15 , in addition to the arrangement of the first protruding part PRT1 and the second protruding part PRT2, Fig.14 The pixel circuit PXC_1 and Fig.15 Each of the pixel circuits PXC_2 shown in FIG. Figure 9a The third pixel circuit PXC3 shown in FIG. 1 is substantially the same as or similar to the third pixel circuit PXC3 shown in FIG. Fig.14 The portion taken along line III-III' shown in FIG. Fig.15 Each of the sections cut by line IV-IV' shown in FIG. Fig.10 The cross-sectional views shown in FIG. 1 are substantially the same or similar. Therefore, the repeated description will not be repeated.

[0238] like Fig.14 As shown in , the storage capacitor Cst_1 of the pixel circuit PXC_1 may include a second capacitor electrode CE2_1. The first protrusion part PRT1 of the second capacitor electrode CE2_1 may extend from the body part BODY in the first direction DR1 and protrude further than the first capacitor electrode CE1 and the third capacitor electrode CE3 (or their edges). The second protrusion part PRT2 may extend from the body part BODY and protrude further than the first capacitor electrode CE1 and the third capacitor electrode CE3 (or their edges) in the opposite direction of the first direction DR1. For example, in Fig.14 In the embodiment shown in , the extending direction EDR along which the first protrusion part PRT1 extends may be parallel to the first direction DR1 .

[0239] like Fig.15As shown in , the storage capacitor Cst_2 of the pixel circuit PXC_2 may include a second capacitor electrode CE2_2. The first protrusion part PRT1 of the second capacitor electrode CE2_2 may extend from the main body part BODY in an oblique direction between the first direction DR1 and the second direction DR2, and protrude further than the first capacitor electrode CE1 and the third capacitor electrode CE3 (or their edges). The second protrusion part PRT2 may extend from the main body part BODY and protrude further than the first capacitor electrode CE1 and the third capacitor electrode CE3 (or their edges) in a direction opposite to the oblique direction. For example, in Fig.15 In the embodiment shown in , the extension direction EDR may be an inclined direction.

[0240] As described above, the first protrusion part PRT1 of the second capacitor electrode CE2_1 or CE2_2 may extend or protrude in a specific direction, and the second protrusion part PRT2 of the second capacitor electrode CE2_1 or CE2_2 may extend or protrude in an opposite direction to the specific direction.

[0241] The above description is an example of the disclosed technical features, and a person skilled in the art to which the disclosure pertains will be able to make various modifications and changes.Therefore, the disclosed embodiments described above may be implemented individually or in combination with each other.

[0242] Therefore, the embodiments disclosed in the disclosure are not intended to limit the disclosed technical spirit, but to describe the disclosed technical spirit, and the scope of the disclosed technical spirit is not limited by these embodiments. The disclosed protection scope should be interpreted by the claims, and should be interpreted as all technical spirits within the equivalent scope are included in the disclosed scope.

Claims

1. A display device, comprising: sub-pixel, where The subpixel includes: a first transistor including a gate electrode electrically connected to a first node, a first terminal electrically connected to a first power line, and a second terminal electrically connected to a second node; a light emitting component electrically connected to the second node and the second power line, the light emitting component including at least one light emitting element; and a capacitor formed between the first node and the second node. The capacitor includes: a first capacitor electrode; a second capacitor electrode overlapping the first capacitor electrode in a plan view; and an insulating layer provided between the first capacitor electrode and the second capacitor electrode, and The second capacitor electrode includes: a first protrusion part protruding further than an edge of the first capacitor electrode in an extension direction in a plan view to receive a data signal; and a second protrusion part protruding from a portion of an edge of the second capacitor electrode in a direction opposite to the extension direction in a plan view.

2. The display device according to claim 1, wherein: In a plan view, the second capacitor electrode overlaps the first capacitor electrode except for the first protrusion part and the second protrusion part.

3. The display device according to claim 2, wherein: The second protrusion member is not directly connected to the external component.

4. The display device according to claim 1, wherein: A first width of the first protruding part and a second width of the second protruding part are equal in a direction perpendicular to the extending direction.

5. The display device according to claim 4, wherein: Regardless of an alignment error between the first capacitor electrode and the second capacitor electrode, an overlapping area between the first capacitor electrode and the second capacitor electrode in a plan view is constantly maintained due to the second protrusion part corresponding to the first protrusion part.

6. The display device according to claim 1, wherein: The first protrusion feature and the second protrusion feature are not co-linear with each other.

7. The display device according to claim 1, wherein: The first protrusion feature and the second protrusion feature are collinear with each other.

8. The display device according to claim 1, wherein: The second capacitor electrode further includes a body part, the body part overlapping the first capacitor electrode in a plan view, In a direction perpendicular to the extending direction, the width of the main body part is greater than the width of the second protrusion part, and The second protrusion part protrudes from the main body part by 3 μm in the direction opposite to the extending direction.

9. The display device according to claim 1, wherein: The first capacitor electrode is located below the semiconductor pattern of the first transistor in a cross-sectional view, A first insulating layer is disposed between the first capacitor electrode and the semiconductor pattern, The second capacitor electrode is disposed on the semiconductor pattern in a cross-sectional view, and A second insulating layer is disposed between the second capacitor electrode and the semiconductor pattern.

10. The display device according to claim 9, wherein: The capacitor further includes a third capacitor electrode that overlaps the second capacitor electrode in a plan view, and A third insulating layer is provided between the third capacitor electrode and the second capacitor electrode.

11. The display device according to claim 10, wherein: The third capacitor electrode is electrically connected to the first capacitor electrode through a contact hole penetrating the first insulating layer, the second insulating layer, and the third insulating layer.

12. The display device according to claim 1, wherein: The second capacitor electrode is disposed on the semiconductor pattern of the first transistor, The first capacitor electrode is disposed on the second capacitor electrode, and The insulating layer is disposed between the first capacitor electrode and the second capacitor electrode.

13. The display device according to claim 1, wherein: The sub-pixel further includes a second transistor electrically connected between the data line and the first node, and The first protrusion part protrudes toward the second transistor in a plan view.

14. The display device according to claim 13, wherein: The data line extends in the extending direction.

15. The display device according to claim 13, wherein: The data line extends in a direction intersecting the extending direction.

16. The display device according to claim 1, wherein: The light emitting component further includes: a first electrode and a second electrode, which are spaced apart from each other; a first pixel electrode, which is disposed on the first electrode, and the first pixel electrode is electrically connected to one end of the at least one light emitting element; and a second pixel electrode, which is disposed on the second electrode, and the second pixel electrode is electrically connected to the other end of the at least one light emitting element, and The at least one light emitting element is disposed between the first electrode and the second electrode.

17. The display device according to claim 16, wherein: The first pixel electrode is electrically connected to the second terminal of the first transistor through a contact hole that penetrates another insulating layer disposed below the first electrode and the second electrode.

18. The display device according to claim 16, wherein: The sub-pixel further includes a color conversion layer disposed on the at least one light emitting element, the color conversion layer converting a wavelength of light incident from the at least one light emitting element and releasing light having the converted wavelength.

19. The display device according to claim 1, wherein: The first power line includes: a first vertical power line extending in a first direction; and a second vertical power line extending in a second direction. Pixel circuits of a plurality of sub-pixels constituting one pixel are arranged in a region divided by the first vertical power line, the second vertical power line, and the second power line in a plan view, and Each of the pixel circuits includes the first transistor and the capacitor.

20. The display device according to claim 19, wherein: The pixel circuits in the region are arranged in the first direction, and The data lines for the sub-pixels extend in the first direction and are arranged adjacent to each other.

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