Test fixture host, assembly method and automatic test method

Abstract

The invention discloses a test fixture host, an assembly method and an automatic test method. The test fixture host comprises a test fixture mainboard, an extension test board and an outer frame body. The test fixture mainboard comprises a plurality of first interfaces; the extension test board comprises a plurality of second interfaces; the periphery of the outer frame body is provided with a plurality of first openings exposing the first interfaces and a plurality of second openings exposing the second interfaces. According to the test fixture host, the outer frame body is provided with the first opening and the second opening, so that the interfaces on the test fixture mainboard and the expansion test board are connected with the outside; the extension test board can integrate more test functions to the test fixture mainboard on the premise that the test fixture mainboard is not added, the test fixture host has the advantages of being extensible, small in size, long in service life, good in compatibility of to-be-tested chip types, high in operability and the like, and the test efficiency can be greatly improved while the test quality can be guaranteed.

Description

Technical Field

[0001] The present invention relates to the field of display driver chip testing, and in particular to a test fixture host, an assembly method and an automatic testing method. Background Art

[0002] During the production process of the screen, the display driver chip of the screen needs to be tested to ensure that the chip is in good condition when it leaves the factory. The same manufacturer often produces multiple different screens at the same time. Different screens correspond to different display driver chips and need to be tested separately; even the same chip will be tested in different ways, so it is necessary to connect the chip under test to the test fixture motherboard through different forms of interfaces or communicate with different types of interface protocols.

[0003] An existing test fixture mainboard only has MCU (Microcontroller Unit, or single-chip microcontroller, also referred to as single-chip microcomputer), SPI (Serial Peripheral Interface, serial peripheral interface), QSPI (Quad Serial Peripheral Interface, four-wire serial peripheral interface) interface; some test fixture mainboards only have MIPI-DPHY (MIPI Display Physical Layer, a physical layer of MIPI, its protocols include CSI and DSI, CSI is used for image access, DSI is used for image output) interface, RGB (RGB interface is a digital signal interface between display devices and other devices, mainly used to transmit color images and video signals, RGB interface is also called DPI (display pixel interface) interface).

[0004] The existing test fixture mainboard has a single test performance and provides a relatively single protocol interface, which is difficult to adapt to the testing requirements of different types of chips, hindering the further improvement of test efficiency and failing to meet the needs of chip mass production testing. In addition, most existing test fixtures are connected to the chip under test in the form of pins. Such interfaces are generally connected using DuPont wires during testing. DuPont wires will be damaged after multiple plugging and unplugging, making it difficult to meet the needs of chip aging testing. Summary of the invention

[0005] The purpose of the present invention is to provide a test fixture host, an assembly method and an automatic testing method. The test fixture host is small in size, and in particular, the interface layout and the outer frame assembly are reasonable, which can make it more convenient and more user-friendly to build a test platform, and can meet the testing needs of various LCD chips, and can realize chip automatic testing while reducing the testing cost. Among them, the extended test board of the test fixture host can be used independently, and can also be connected with the test fixture mainboard to complete the test.

[0006] To achieve the above object, the present invention provides a test fixture host, which comprises:

[0007] A test fixture mainboard, comprising a plurality of first interfaces, wherein the first interfaces are arranged along an edge of the test fixture mainboard;

[0008] An extended test board, comprising a plurality of second interfaces, wherein the extended test board is coupled to a middle area of ​​one side of the test fixture main board to be stacked on the test fixture main board;

[0009] The outer frame body, the test fixture mainboard and the extended test board are placed in the outer frame body, and the periphery of the outer frame body is provided with a plurality of first openings for exposing the first interface, and the front middle area of ​​the outer frame body is provided with a plurality of second openings for exposing the second interface.

[0010] Optionally, the outer frame includes a top plate, a bottom plate and side plates to form a frame.

[0011] Optionally, the top plate includes an independent first top plate and a second top plate, the second top plate is adjacent to an edge of the first top plate, a middle area of ​​the second top plate is used for opening a second interface opening exposing the second interface; and an edge area of ​​the second top plate is used for opening a first interface opening exposing a portion of the first interfaces.

[0012] Optionally, the side panel includes a first side panel, a second side panel, a third side panel, and a fourth side panel, and the first side panel, the second side panel, the third side panel and the fourth side panel are arranged between the first top panel, the second top panel and the bottom panel, and surround the test fixture main board and the extended test board.

[0013] Optionally, a display screen opening and a button opening are provided on the first top plate.

[0014] Optionally, a card slot is provided on the first top plate, and protrusions opposite to the card slot are respectively provided on the third side plate and the fourth side plate, and the card slot and the protrusions are card-connected.

[0015] Optionally, the first side panel, the second side panel, the third side panel, and the fourth side panel are provided with first interface openings that expose another portion of the first interfaces.

[0016] Optionally, a plurality of connecting through holes and binding holes are provided on the bottom plate, the bottom plate is respectively connected to the third side plate and the fourth side plate through the connecting through holes, and the bottom plate is connected to the test fixture mainboard through the binding holes.

[0017] Optionally, the first side panel and the third side panel are screwed together, the first side panel and the fourth side panel are screwed together, the second side panel and the third side panel are screwed together, the second side panel and the fourth side panel are screwed together, the first top panel and the third side panel are screwed together, the first top panel and the fourth side panel are screwed together, the second top panel and the third side panel are screwed together, and the second top panel and the fourth side panel are screwed together.

[0018] The present invention also provides a method for assembling the test fixture host as described above, the method comprising:

[0019] S10, coupling the extended test board to the test fixture main board and binding them through a first binding structure of the two;

[0020] S20, binding the test fixture mainboard and the base plate through a second binding structure;

[0021] S30, screwing the third side plate and the fourth side plate to the bottom plate respectively;

[0022] S40, screwing the first side plate, the second side plate, the third side plate and the fourth side plate in sequence;

[0023] S50, clamping the first top plate and the third side plate and the fourth side plate respectively, and screwing the first top plate and the third side plate and the fourth side plate;

[0024] S60, placing the second top plate against the edge of the first top plate, with the second top plate being higher than the first top plate, and screwing the second top plate to the third side plate and the fourth side plate.

[0025] The present invention also provides an automatic testing method, which is implemented using the test fixture host as described above, and the automatic testing method comprises:

[0026] S101, the chip under test realizes screen touch through a plurality of first interfaces on the host;

[0027] S102, receiving the test signals of the tested chip through the plurality of second interfaces on the host, and the host controlling the extended test board through the test fixture mainboard to automatically sample the test signals to perform the automated test and process the test results.

[0028] In summary, compared with the prior art, the test fixture host, assembly method and automatic testing method provided by the present invention have the following beneficial effects:

[0029] The present invention can stack and couple the extended test board and the test fixture mainboard and integrate them into the outer frame, provide rich protocol interface types and reasonably arrange the opening positions, thereby expanding more test functions without increasing the size of the whole machine, building a test platform that can be easily operated, and realizing automatic testing of chips by extending the test board and the test fixture mainboard to work alone or in collaboration. It is suitable for chip testing scenarios with various working protocols, quantity scales, and test types, has good compatibility, can ensure test quality while improving test efficiency, and meet mass production test needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a three-dimensional structural schematic diagram of the test fixture host of the present invention.

[0031] Figure 2 It is a front schematic diagram of the test fixture host of the present invention.

[0032] Figure 3 It is a schematic diagram of assembling a guard plate and a sub-top plate on a test fixture host of the present invention.

[0033] Figure 4 It is a schematic diagram of the test fixture mainboard of the present invention.

[0034] Figure 5 It is a front schematic diagram of the extended test board of the present invention.

[0035] Figure 6 It is a schematic diagram of the back side of the extended test board of the present invention.

[0036] Figure 7 It is a schematic diagram of the test fixture main board and the extended test board of the present invention being stacked and coupled.

[0037] Figure 8 Schematic diagram of the first top plate of the present invention.

[0038] Fig. 9 Schematic diagram of the second top plate of the present invention.

[0039] Fig.10 Schematic diagram of the first side panel of the present invention.

[0040] Fig.11 It is a schematic diagram of the test fixture host facing the first side plate in the present invention.

[0041] Fig.12 Schematic diagram of the second side panel of the present invention.

[0042] Fig.13 It is a schematic diagram of the test fixture main unit with a protective corner plate when facing the second side plate in the present invention.

[0043] Fig.14 It is a schematic diagram of the test fixture main unit with the protective corner plate removed when facing the second side plate in the present invention.

[0044] Fig.15 Schematic diagram of the third side panel of the present invention.

[0045] Fig.16 It is a schematic diagram of the test fixture host facing the third side plate in the present invention.

[0046] Fig.17 Schematic diagram of the fourth side panel of the present invention.

[0047] Fig.18 It is a schematic diagram of the test fixture host facing the fourth side plate in the present invention.

[0048] Fig.19 4 is a top view of the fourth side plate of the present invention.

[0049] Fig. 20 It is a schematic diagram of the assembly position of the first top plate and the fourth side plate of the present invention.

[0050] Fig.21 It is a schematic diagram of the assembly position of the second top plate, the first top plate and the fourth side plate of the present invention.

[0051] Fig. 22 It is a schematic diagram of the base plate of the present invention.

[0052] Fig.23 It is a flow chart of the assembly method of the test fixture host of the present invention.

[0053] Fig.24 It is a flow chart of the automatic testing method of the present invention.

[0054] Fig.25 It is a schematic diagram of the automated test process of lighting up the chip under test according to the present invention.

[0055] Fig.26 It is a schematic diagram of the automated test flow of the power-on test of the chip under test of the present invention.

[0056] Fig. 27 It is a schematic diagram of the automated test flow of the power-off test of the chip under test of the present invention. DETAILED DESCRIPTION

[0057] The technical solutions, structural features, objectives and effects of the embodiments of the present invention are described in detail below in conjunction with the accompanying drawings.

[0058] It should be noted that the drawings are in a very simplified form and use non-precise proportions. They are only used to conveniently and clearly assist in explaining the embodiments of the present invention, and are not used to limit the conditions for the implementation of the present invention. Therefore, they have no substantive technical significance. Any structural modification, change in proportional relationship or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical content disclosed by the present invention.

[0059] It should be noted that, in the present invention, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only the elements explicitly listed, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0060] like Figure 1 , Figure 2 , Figure 3 As shown, the present invention provides a test fixture host, which includes a test fixture mainboard 100 (such as Figure 4 As shown), the extended test board 200 (as shown Figure 5 The test fixture main board 100 and the extended test board 200 are stacked and coupled to each other and placed together in the outer frame. The outer frame allows several first interfaces set along the edge of the test fixture main board 100 to be exposed from several first openings opened on the periphery of the outer frame; at the same time, several second interfaces set on the extended test board 200 can be exposed from several second openings opened in the middle area of ​​the front of the outer frame. The first interface and the second interface are used to connect the display driver chip (hereinafter referred to as chip) to be tested.

[0061] Among them, the test fixture mainboard 100 (such as Figure 4The test fixture mainboard 100 (as shown) can be used independently to complete a part of the chip test, or other tests on the chip can be completed through the cooperation of the test fixture mainboard 100 and the extended test board 200. In this way, on the basis of not increasing the size and area of ​​the test fixture mainboard 100, more test functions can be expanded for the test fixture mainboard 100 through the circuits and functional modules arranged on the extended test board 200, so as to realize the test of chips with different interface forms or protocols, meet the mass production test needs of the chip, and improve the test efficiency. For example, in this embodiment, the test fixture mainboard 100 can not only independently complete a small part of the voltage and current test of the chip (taking the display chip as an example), but also independently complete the point screen, thereby independently completing the aging test of the chip (aging test is the chip reliability test (RA, Reliability Test) is an important test item required for chip mass production); the extended test board 200 can expand various tests on the voltage, current, diode, resistance, etc. of the chip. Through the collaborative work of the two boards, the voltage, current, and even frequency, resistance, and diode of dozens or hundreds of categories of chips can be tested, such as the voltage or current test required by the common power supplies such as the three power supplies VSN, VSP, IOVCC, the two power supplies VCI, IOVCC, and the power supplies commonly used for backlights of LCD chips, as well as a large number of external voltage tests, etc. In particular, through the collaborative work after the test fixture mainboard 100 is connected to the extended test board 200, the extended test board 200 can also be used to monitor the electrical parameters of the chip while performing the aging test.

[0062] like Figure 4 As shown, the test fixture mainboard 100 includes a first printed circuit board, and the first printed circuit board has a first area A1 and a second area A2 arranged around the first area A1. The first area A1 is shielded by the extended test board 200 stacked on the test fixture mainboard 100, and several groups of extended interfaces for coupling the test fixture mainboard 100 and the extended test board 200 can be arranged on the back of the extended test board 200 and the first area A1 on the front of the test fixture mainboard 100, so as to realize the electrical connection and signal communication between the two boards; the first interface on the test fixture mainboard 100 is arranged in the second area A2 that is not shielded by the extended test board 200, and can be further exposed through the first opening on the outer frame. By designing the shape of the extended test board 200 itself and controlling the area scale of the extended test board 200, the range of the unshielded second area A2 can be optimized, so as to flexibly plan the distribution position of each first interface on the second area A2, and realize a stable and reliable connection with the chip under test.

[0063] like Figure 4 , Figure 5As shown, the first printed circuit board of the test fixture mainboard 100 is rectangular as a whole; the extended test board 200 includes a second printed circuit board, which is in the shape of an inverted "7" as a whole, and the shape of the first area A1 is consistent with the projection shape of the second printed circuit board, which is an inverted "7" shape. That is, the second printed circuit board in this example has a horizontal area B1 and a vertical area B2; wherein, the width of the vertical area B2 is smaller than the width of the horizontal area B1, the left edges of the horizontal area B1 and the vertical area B2 are aligned, and the right edge of the vertical area B2 is retracted by a preset distance relative to the right edge of the horizontal area B1, thereby leaving more space for the second interface to be exposed near the lower right corner of the second area A2 for the test fixture mainboard 100 below.

[0064] like Figure 1 , Figure 2 , Figure 3 As shown, the outer frame of the test fixture host includes a top plate (F1 & F2), a bottom plate F0 and a plurality of side plates (F3 to F6), which cooperate to form a frame structure with a certain internal accommodation space for placing the assembly obtained by connecting the test fixture main board 100 and the extended test board 200. The top plate and the bottom plate F0 of the outer frame are arranged opposite to each other, respectively located above and below the assembly; the side plates surround the periphery of the assembly and are fixedly connected to the top plate and the bottom plate F0, respectively. The side plates include a first side plate F3 and a second side plate F4 arranged opposite to each other, and a third side plate F5 and a fourth side plate F6 arranged opposite to each other (hereinafter, the proximal end or distal end of a component or a region is referred to as the proximal end or the distal end of the component or a region). Figure 2 The proximal end refers to the end of the component or region closer to the second side panel F4, and the distal end refers to the end of the component or region closer to the first side panel F3). For example, the top panel includes an independent first top panel F1 and a second top panel F2; the proximal edge of the first top panel F1 is arranged adjacent to the distal edge of the second top panel F2.

[0065] When coupling the stacked extended test board 200 and the test fixture main board 100, multiple groups of extended plug structures can be used as extended interfaces, and the two boards can be connected into a detachable assembly using these extended plug structures; wherein each group of extended plug structures includes pin modules and socket modules that match and couple with each other, each socket module is located on the back of the upper extended test board 200, and each matching pin module is located on the front of the first area A1 of the lower test fixture main board 100, and the position of each pin module corresponds to the projection position of the matching socket module, so that each pin of the pin module is plugged and connected with each socket of the socket module, thereby building a channel for transmitting electrical energy and / or data signals for this group of extended plug structures. The pin module and the socket module are easy to plug and unplug, and can quickly connect or disconnect the relevant circuits between the test fixture mainboard 100 and the extended test board 200, which is convenient for the installation, maintenance and board replacement of the host; moreover, the connection stability of the pin module and the socket module is high, and the transmission distance of the power and / or data signal between the two boards can be shortened, effectively reducing loss and interference, and improving the transmission quality and efficiency of the power and / or data signal. By utilizing the module height after the pin module and the socket module are docked, a certain spacing distance can be formed between the first printed circuit board of the test fixture mainboard 100 and the second printed circuit board of the extended test board 200. The setting of the spacing distance provides convenience for the stacking of the extended test board 200 and the test fixture mainboard 100, and sufficient height space is reserved between the two boards, which can prevent the circuit elements and functional modules arranged on the relative surfaces of the test fixture mainboard 100 and the extended test board 200 from scratching each other.

[0066] As an example of an extended plug structure, Figure 4 , Figure 6 , Figure 7As shown, the first area A1 of the test fixture mainboard 100 is provided with a first pin module 101, a second pin module 102 and a third pin module 103 on the front side, which can be matched and coupled with the first socket module 216, the second socket module 217 and the third socket module 218 on the back side 200-2 of the extended test board respectively; wherein, the voltage and current measurement module of the extended test board 200 can obtain the measured signal related to the voltage and current detection from the test fixture mainboard 100 by means of the channel built by coupling the first pin module 101 and the first socket module 216, so that the extended test board 200 can perform sampling test on the measured signal; for example, the channel can extend the various ADC modules for sampling voltage or current on the test board 200 to provide measured signals such as 3 power supplies VSN, VSP, IOVCC, 2 power supplies VCI, IOVCC and the like commonly used in LCD chips. If the extended test board 200 is not provided with a frequency monitoring module, the frequency detection signal received by the frequency detection interface 205 of the extended test board 200 can be transmitted to the test fixture mainboard 100 by means of a channel constructed by coupling the second pin module 102 and the second socket module 217, so that the frequency detection signal can be processed by the FPGA (Field-Programmable Gate Array) module on the test fixture mainboard 100. The extended test board 200 obtains all the power supply required by the extended test board 200 from the test fixture mainboard 100 by means of the channel constructed by coupling the third pin module 103 and the third socket module 218, and can also communicate with the test fixture mainboard 100 by means of the channel constructed by coupling the third pin module 103 and the third socket module 218 (for example, SPI communication in full-duplex mode, and the transmitted signals include a BUSY signal indicating whether the extended test board 200 is working, an INT signal indicating notification to the mainboard 100 to obtain data from the extended test board 200, etc., and these signals can be controlled or processed by the main control microcontroller module of the mainboard 100). A plurality of pin modules are distributed and arranged at a certain distance on the test fixture mainboard 100 (such as the first pin module 101, the second pin module 102 and the third pin module 103 are separated from each other and are respectively located at different positions in the first area A1, close to the proximal edge, close to the middle, and close to the distal edge), and a corresponding plurality of socket modules are also distributed and arranged at a certain distance on the back side 200-2 of the extended test board (such as the first socket module 216, the second socket module 217, and the third socket module 218 are respectively located at different positions in the extended test board 200, close to the proximal edge, close to the middle, and close to the distal edge). In this way, the stable structure formed by connecting each group of socket modules with the pin modules can be utilized to form multiple stable support points between the test fixture mainboard 100 and the extended test board 200, so that the pressure distribution when the two boards are stacked is more uniform, the stability is higher, and the coupling quality is improved.

[0067] In addition to the extended plug-in structure, the first binding structure can also be used in this embodiment to physically bind the test fixture mainboard 100 and the extended test board 200 to form a detachable assembly, thereby improving the reliability and stability of the connection between the two boards. Multiple first binding structures can be distributed, each of which includes a mainboard binding hole opened in the first area A1 on the test fixture mainboard 100, and an extended board binding hole opened at a corresponding position on the back of the extended test board 200-2. The corresponding extended board binding hole and the mainboard binding hole are connected vertically, and the two are fixedly connected by a mechanical connection structure.

[0068] like Figures 4 to 7 As shown, the first mainboard binding hole 128-1, the second mainboard binding hole 128-2, and the third mainboard binding hole 128-3 distributed in the first area A1 of the test fixture mainboard 100 are respectively arranged opposite to the first extension board binding hole 201-1, the second extension board binding hole 201-2, and the third extension board binding hole 201-3 distributed on the extension test board 200, and the three groups of relatively arranged binding holes are respectively connected by three mechanical connection structures. Among them, the three mainboard binding holes on the test fixture mainboard 100 are not arranged in the same straight line: for example, the first mainboard binding hole 128-1 and the second mainboard binding hole 128-2 are separately opened at the far end near the first area A1, so that the first mainboard binding hole 128-1 is close to the left side boundary of the first area A1, and the second mainboard binding hole 128-2 is located in the middle right of the first area A1; the third mainboard binding hole 128-3 is opened near the proximal end of the first area A1 and is located in the middle right of the first area A1. The three expansion board binding holes on the extended test board 200 are not arranged in the same straight line: for example, the first expansion board binding hole 201-1 and the second expansion board binding hole 201-2 are separately opened near the far end of the horizontal area B1, and the first expansion board binding hole 201-1 is close to the left boundary of the horizontal area B1, and the second expansion board binding hole 201-2 is located in the middle right of the horizontal area B1; the third expansion board binding hole 201-3 is opened near the proximal end of the vertical area B2 and is located in the middle right of the vertical area B2. By setting multiple first binding structures that are not in the same straight line, the stability of the connection between the test fixture mainboard 100 and the extended test board 200 can be improved. In this example, when opening each group of binding holes, the lower left corner of the test fixture mainboard 100 and the extended test board 200 is avoided, that is, the position of each board close to the left boundary and the proximal edge is avoided to prevent the opening of the binding holes from affecting the dense wiring at this position. Moreover, by uniformly planning the layout positions of multiple first binding structures and multiple extended plug-in structures, the points at which stable support is achieved between the test fixture main board 100 and the extended test board 200 through the first binding structure and the extended plug-in structure are jointly optimized, thereby improving space utilization, enhancing the connection strength between the two boards, effectively avoiding stress concentration, and improving the stability of the overall structure.

[0069] It should be noted that Figure 5 The second expansion board binding hole 201-2 shown in the figure is indicated by a dotted line to illustrate its approximate position. The hole and the upper end of the mechanical connection structure arranged therein are actually blocked by the display screen 207-1 and cannot be observed from the front of the expansion test board 200. Specifically, a support column whose upper end is directly integrated into the second printed circuit board is arranged corresponding to the second expansion board binding hole 201-2. The lower end of the support column has a screw hole, which can be screwed to the corresponding second main board binding hole 128-2 to achieve a fixed connection between the two boards; the support column is arranged on the expansion test board 200 within the range for arranging the display module 207, providing a more stable and reliable support for the display screen 207-1; using the support column whose upper end is integrated into the second printed circuit board as the mechanical connection structure therein, instead of using an additional external connection component here, can prevent the external connection component from scratching the display screen 207-1, so that the fragile display screen 207-1 is better protected. The mechanical connection structure between the other two groups of mainboard binding holes and the expansion board binding holes can be set as needed, for example, by using rivets, so that the lower end of the rivet is connected to the mainboard binding hole, and the upper end of the rivet is connected to the corresponding expansion board binding hole, so that the test fixture mainboard 100 and the expansion test board 200 are reliably connected and a stable support is formed between the two boards ( Figure 7 The rivet 201 - 3 a connecting the third mainboard binding hole 128 - 3 and the third expansion board binding hole 201 - 3 is shown as an example).

[0070] like Figure 4 , Fig. 22 As shown, the host of this embodiment can also further bind and connect the combination obtained by connecting the test fixture mainboard 100 and the extended test board 200 to the bottom plate F0 of the outer frame by setting a plurality of second binding structures. In this example, four second binding structures are provided, including binding holes 131 provided at the four corners of the second area A2 of the test fixture mainboard 100, and binding holes 1011 provided at the four corners of the bottom plate F0. The binding holes 131 at corresponding positions are connected vertically with the binding holes 1011. The test fixture mainboard 100 is fixedly connected to the bottom plate F0 by mechanical connection structures (such as rivets, screws, etc.) respectively arranged in the holes at both ends, so as to realize a reliable connection between the combination of the test fixture mainboard 100 and the extended test board 200 and the outer frame.

[0071] In order to expose various interfaces (including but not limited to the first interface that can be connected to the chip under test) distributed at different positions on the edge of the test fixture mainboard 100 and with different interface forms or orientations, in this embodiment, some openings opened on the outer frame have only a single opening direction, such as an opening that runs through the front edge area of ​​the outer frame alone, or an opening that runs through a certain side of the outer frame alone; and other openings on the outer frame each have openings that are opened in multiple adjacent directions of the outer frame and are interconnected, such as openings that run through the front edge area of ​​the outer frame and a certain side of the outer frame. In order to expose the interface (including but not limited to the second interface that can be connected to the chip under test) set on the front side 200-1 of the extended test board, in this embodiment, the openings opened on the outer frame corresponding to the interface on the front side 200-1 of the extended test board each have only a single opening direction, and these openings are distributed and opened in the middle of the front side of the outer frame. By stacking the test fixture main board 100 and the extended test board 200, and rationally arranging the aforementioned interfaces and their corresponding openings, the overall structure of the test fixture host of the present invention is compact, the space is effectively utilized, and the test chip can be plugged in and out or various control operations of human-computer interaction can be performed from multiple sides of the host.

[0072] When planning the position or direction of each interface and its opening on the host, for example, interfaces that are not related to functions or test items are dispersed to different positions on the circuit board, or these unrelated interfaces have different orientations, so as to form a reasonable functional partition, reduce signal interference between different interfaces, avoid local overheating of the host, and prevent user misoperation. For another example, multiple interfaces with related functions or implementing related tests can be arranged relatively compactly in adjacent positions, and these interfaces are oriented in the same direction or in adjacent directions, thereby reducing the difficulty of wiring on the circuit board, and at the same time, it is beneficial to concentrate on opening some openings on the outer frame to expose multiple interfaces at adjacent positions together, reducing the difficulty of mold opening and manufacturing costs of the outer frame; the chip under test can be subsequently connected to multiple interfaces at adjacent positions simultaneously or separately according to test needs, so that there is no need to frequently change the position of the chip, effectively simplifying the operation and improving the test efficiency.

[0073] The following will further illustrate an example scheme for setting the interface and its corresponding opening in the present invention. Figure 1 , Figure 2 , Figure 8 , Fig. 9As shown, in the top plate of the outer frame, a first top plate F1 and a second top plate F2 are preferably provided, and the first top plate F1 is provided with a display opening 302 and a plurality of button openings, through which the display screen 207-1 on the extended test board 200, the test fixture mainboard 100 and a plurality of buttons on the extended test board 200 can be exposed respectively, so as to facilitate viewing various information and performing necessary operations during the test process; a portion of the first interface on the test fixture mainboard 100 and a portion of the second interface on the extended test board 200 can be exposed respectively through the first interface opening and the second interface opening opened at corresponding positions of the second top plate F2; some of the first interface openings on the second top plate F2 will be further connected with the first interface opening opened on a certain side plate, and the first interface exposed through these first interface openings on the front side will also be exposed from the first interface opening connected to the side.

[0074] See also Figure 1 , Figure 2 , Figure 5 , Figure 8 As shown, the display screen opening 302 is roughly opened in the middle of the first top plate F1; a display module 207 is provided on the extended test board 200, which is located in the wider horizontal area B1 on the extended test board 200; the display module 207 includes a display screen 207-1, which can be exposed on the front side of the outer frame through the display screen opening 302 on the first top plate F1, and is used to view various information such as the current screen point protocol, real-time voltage / current conditions, register readback results, electrical test data, etc.

[0075] The button openings provided on the first top plate F1 include openings 303, so that the buttons 206 provided by the display interface control module on the extended test board 200 can be exposed on the front side of the outer frame. The exemplary display interface control module includes four buttons 206, which can control the display interface on the display screen 207-1, and are respectively used to lock the display interface, turn pages down, turn pages up, pause data, etc. These four buttons 206 are arranged in a row vertically beside the display screen 207-1, and are provided on the front edge of the lateral area B1 of the extended test board 200 close to the right side, and can be exposed respectively through the four corresponding openings 303 on the first top plate F1.

[0076] See also Figure 1 , Figure 2 , Figure 4 , Figure 8As shown, the button opening opened on the first top plate F1 also includes an opening 301, which can be used for the button 130 set by the test display control module on the test fixture mainboard 100 to be exposed on the front of the outer frame. The test display control module is used for human-computer interaction with the chip under test, and the test display control module is provided with four buttons 130: the "enter" key is used to control the continuation of the execution of the initialization code; the "loop" key is used to control the loop refresh; the "up" key is used to control the flipping of the previous picture, and the "down" key is used to control the flipping of the next picture. The four buttons 130 set by the test display control module can meet most of the test adjustment interaction needs, but other function buttons can be added according to actual needs. The four buttons 130 are arranged in a row vertically, and are set on the edge of the second area A2 on the test fixture mainboard 100 close to the left side, and are exposed through the same opening 301 on the first top plate F1; the opening 301 and the aforementioned four openings 303 are respectively opened on the left and right sides of the display screen opening 302.

[0077] The button opening on the first top plate F1 also includes an opening 304, which allows the power switch button 122 on the test fixture mainboard 100 to be exposed on the front of the outer frame, and is used to control the conduction or cutoff of the entire power supply of the host. For example, the power switch button 122 is set on the edge near the far end of the second area A2 of the test fixture mainboard 100, and then the opening 304 corresponding to the position of the power switch button 122 is opened on the edge near the far end of the first top plate F1, so that the button 122 can be operated from the front of the host. Operating the power switch button 122 can control the power provided by the external power supply device to the test fixture mainboard 100, so that the power can be introduced into the circuit module of the test fixture mainboard 100 or the circuit module of the test fixture mainboard 100 can be disconnected from the power supply; in addition to being used by the test fixture mainboard 100 itself, the power introduced in this way can also be transmitted to the extended test board 200 for use through the channel coupled and constructed by the aforementioned third pin module 103 and the third socket module 218, so that the extended test board 200 obtains all the power required for work, thereby simplifying the circuit arrangement on the extended test board 200. In other embodiments, the extended test board 200 may be additionally provided with a direct power supply module so that it can be coupled to an external power supply device separately to obtain an independent power supply. In this scenario, the third pin module 103 and the third socket module 218 may be omitted, or the two are merely physically connected to support the stacked boards, or only the channel for coupling the two is used to exchange information between the two boards without transmitting electrical energy through the channel. In some applications, an extended test board 200 with an independent power supply can realize some commonly used multimeter functions by using some circuit elements and functional modules on the board that do not need to cooperate with the test fixture mainboard 100. In this way, the extended test board 200 can be operated separately to perform part of the test on the chip under test and display the test data.

[0078] See also Figure 1 , Figure 2 , Figure 5 , Figure 8 , Fig. 9 , Fig.21 As shown, the second interface opening on the second top plate F2 includes an opening 406, which is opened at the distal edge of the second top plate F2, adjacent to the opening 306 opened at the proximal edge of the first top plate F1 and connected to form an opening, so that the second debugging interface 211 set on the extended test board 200 can be exposed on the front side of the outer frame, and is used to connect an external debugger to download the debugging program required for debugging the host so that the host can meet the working conditions required for chip testing (the debugger can be further connected to the host computer through the USB2.0 interface, and the host computer burns the debugging program to the host through the program download debugging circuit of the debugger); the debugging program obtained by the second debugging interface 211 can be burned into the MCU (Microcontroller Unit) control module on the extended test board 200, or can be transmitted from the extended test board 200 to the test fixture mainboard 100 via the coupled expansion interface, and burned into the main control microcontroller module of the test fixture mainboard 100. As an example, the second debugging interface 211 here is a DAP interface (Debug Access Port) in the form of a pin, with two rows of pins arranged upward, which can be connected to the socket module on the signal transmission line of the external debugger to download the debugging program; in this embodiment, other forms of debugging interfaces will be exposed through openings in other directions on the outer frame (detailed below).

[0079] The second interface opening also includes openings 404 and 405; wherein, the opening 405 opened at the distal edge of the second top plate F2 is adjacent to the opening 305 opened at the proximal edge of the first top plate F1, and the two openings 305 and 405 are connected to form an opening, so that the frequency detection interface 205 and the adjustable dial switch 208 set on the extended test board 200 can be exposed on the front of the outer frame. The opening 404 is opened separately, and the opening 404 is located near the left side of the opening 405, adjacent to the distal edge of the second top plate F2 but not connected to the distal edge, so that the frequency output interface 202 set on the extended test board 200 can be exposed. The two connected openings 305 and 405 are further connected to the two openings 306 and 404 opened at the adjacent edges of the first top plate F1 and the second top plate F2 and connected to each other, forming a larger opening. In this example, the first top plate F1 and the second top plate F2 are not in the same plane, the first top plate F1 is arranged lower than the second top plate F2 as a whole, and a portion of the distal edge of the second top plate F2 is overlapped on the proximal region z along the proximal edge of the first top plate F1 (see Fig. 20 , Fig.21 ), so when connected to form a larger opening, at least a portion of the opening 305 opened at the proximal edge of the first top plate F1 is arranged vertically through a portion of the opening 405 opened at the distal edge of the second top plate F2, and similarly, at least a portion of the opening 306 opened at the proximal edge of the first top plate F1 is arranged vertically through a portion of the opening 406 opened at the distal edge of the second top plate F2. Since the second top plate is distributed with a large number of openings for exposing interfaces, it is an area where a large number of plugging and unplugging occur during the test connection process, and the maintenance, repair, and further improvement of the components in this area will occur frequently. By arranging the first top plate F1 and the second top plate F2 not in the same plane, and the second top plate F2 is above the first top plate F1, the disassembly of the second top plate F2 can be facilitated, so that when maintenance, repair, and further improvement are required, it can be easily completed by only removing part of the second top plate F2, and at the same time, it can also avoid frequent disassembly of the first top plate F1 to cause damage to the display module 207 (the display module 207 is a precision instrument, which is relatively harsh to the environmental conditions of the application scene).

[0080] When the extended test board 200 and the test fixture mainboard 100 work together to perform frequency-related tests on the chip, the frequency output interface 202 and the frequency detection interface 205 can be connected to the chip under test; the frequency output interface 202 and the frequency detection interface 205 are arranged at intervals on the front side 200-1 of the extended test board near the proximal edge of the lateral area B1. Among them, the frequency output interface 202 provides the chip with some specific working conditions required for testing, for example, the frequency output interface 202 is used for the output of waveform frequency to transmit a signal with a set waveform and frequency to the chip under test (for example, the voltage range of the output signal of the frequency output interface 202 in this example can be 1.25V~3.3V, and the maximum frequency is 230MHz). The frequency detection interface 205 can receive a frequency detection signal from the chip under test, for example, for duty cycle detection, to detect the duty cycle and other frequency data of any waveform of the chip under test (in this example, the voltage range of the frequency detection signal that the frequency detection interface 205 can receive can be -5V to 5V, and the maximum frequency is 60MHz; the dip switch 208 can adjust the amplitude of the frequency detection signal, for example, it can be adjusted to a 4-fold attenuation level, so that the voltage range is expanded to -20V to 20V, so as to adapt to a wider range of frequency testing needs). In different examples, the extended test board 200 can process the received frequency detection signal by setting a frequency detection module (in this case, the frequency detection signal does not need to be transmitted between the two boards, and the aforementioned second pin module 102 and second socket module 217 can be omitted), or if the extended test board 200 itself does not have a frequency detection module, the frequency detection signal received by the frequency detection interface 205 can be transmitted to the FPGA module of the test fixture mainboard 100 for processing through the channel built by coupling the second pin module 102 and the second socket module 217. In this way, the extended test board 200 can jointly realize the frequency detection function of any signal in any period including the chip under test with the help of the FPGA module of the test fixture mainboard 100. Through the frequency output interface 202 and the frequency detection interface 205 in this example, 2 clock outputs and 2 waveform frequency or duty cycle detection can be provided for the chip under test.

[0081] The second interface opening on the second top plate F2 also includes openings 402 and 403, and the two can be connected to form an opening; the external voltage output interface 228 and the dial switch 212 that can adjust the external voltage provided on the extended test board 200 can be exposed on the front of the outer frame through the openings 402 and 403. In this example, the external voltage output interface 228 (having a row of pins arranged upward) and the dial switch 212 are arranged at the left edge of the junction of the horizontal area B1 and the vertical area B2 on the front of the extended test board 200-1. The external voltage output interface 228 can provide the external voltage required for the test of the chip under test, and can also perform voltage and current sampling on the external voltage. For example, the external voltage output interface 228 can provide a measurement of the voltage and current of an external power supply. Through the adjustment of the dial switch 212, the voltage range of the external voltage can be 0.6V~5V, and the maximum current is 80mA.

[0082] See also Figure 1 , Figure 2 , Figure 4 , Fig. 9 As shown, the first interface opening on the second top plate F2 includes an opening 401, through which the drive control integrated interface 106 on the test fixture mainboard is exposed from the front of the outer frame. The opening 401 is opened at the left edge of the second top plate F2, and can be connected with the aforementioned openings 402 and 403 to form an opening located on the front of the outer frame to simplify the opening design of the second top plate F2 at this location; at the same time, the opening 401 is also connected to the opening 802 opened on the third side plate F5 (see Fig.15 , Fig.16 ) is connected so that the different forms of interfaces included in the drive control integrated interface 106 can be exposed on the front and side directions of the outer frame, which is convenient for connecting with different forms of signal transmission lines of the chip under test or its furnace plate (the furnace plate is a carrier for the chip under test).

[0083] The drive control integrated interface 106 may include an SPI interface, a QSPI interface, an MCU interface, an RGB interface, and the like. The drive control integrated interface 106 in this embodiment includes an LCD driver IC coaxial line interface 106-1 (for example, it can support RGB (Red, Green, Blue) + SPI, SPI, QSPI, MCU and other protocols), and an LCD driver IC DuPont line interface 106-2 (for example, it can support RGB + SPI, SPI, QSPI, MCU and other protocols). These two interfaces 106-1 and 106-2 are adjacently arranged at the lower half of the second area A2 of the test fixture mainboard 100 near the left edge. The signal is expanded through the drive control integrated interface 106 to meet the test needs of a large number of chips; for example, the signal transfer fixture is extended and connected through the LCD driver IC coaxial line interface 106-1 or the LCD driver IC DuPont line interface 106-2, and the signal transfer fixture can perform large-scale branching of the drive control signal of the display panel to achieve a host computer to test a large number of chips.

[0084] The functions realized by the LCD driver IC coaxial line interface 106-1 and the LCD driver IC DuPont line interface 106-2 are roughly equivalent. When applied, one of the interfaces can be selected to build a test platform. Among them, the LCD driver IC coaxial line interface 106-1 uses a coaxial line to transmit signals, which can meet the requirements of signal transmission over a long distance and can adapt to extreme environments such as high temperature and high humidity. It is more suitable for aging testing than DuPont lines. The LCD driver IC DuPont line interface 106-2 includes a pin module (two rows of upward pins are provided in this example), which is used by connecting DuPont lines, thereby providing another wiring method different from using coaxial lines, which can be flexibly selected when facing different situations. Preferably, on the test fixture mainboard 100, the LCD driver IC coaxial line interface 106-1 is closer to the left edge of the second area A2 relative to the LCD driver IC DuPont line interface 106-2, so that the LCD driver IC coaxial line interface 106-1 will not be scratched by the pins of the LCD driver IC DuPont line interface 106-2 when connected to a longer coaxial line.

[0085] See also Figure 1 , Figure 2 , Figure 5 , Fig. 9As shown, the second interface opening on the second top plate F2 also includes a separately opened opening 410, and the diode / resistance detection interface 203 set on the extended test board 200 can be exposed on the front of the outer frame through the opening 410, and connected to the signal transmission line on the chip under test or its furnace board to obtain the test signal sent by the chip in the diode and resistance test. The diode / resistance detection interface 203 of this example is roughly located at the middle left position of the vertical area B2 on the extended test board 200, and the opening 410 is correspondingly opened at the middle left position of the second top plate F2; the diode / resistance detection interface 203 can provide 16 sampling channels, such as a single column of pins 203-1 (16) corresponding to the negative pole, and two columns of pins 203-2 (16 each) corresponding to the negative pole and the positive pole are set next to it. The number of these sampling channels can be flexibly set according to actual needs, and is not limited to the aforementioned 16 channels.

[0086] The second interface opening on the second top plate F2 also includes openings 407-1, 407-2, and 407-3, which can be used to extend the voltage test interfaces 204-1, 204-2, and 204-3 on the test board 200 to be exposed on the front of the outer frame, respectively, and connected to the signal transmission line on the chip under test or its furnace board to obtain the test signal sent by the chip during the voltage test. The voltage test interface in this example can test a voltage range of -45V to 45V, and provides 20 sampling channels for external voltage measurement, such as the first voltage test interface 204-1 is provided with two rows of pins (9 each), the second voltage test interface 204-2 has another two rows of pins (9 each), and the third voltage test interface 204-3 has two rows of pins (4 each). The number of these sampling channels can be flexibly set according to actual needs, and is not limited to the aforementioned 20 channels. These voltage test interfaces 204-1, 204-2, and 204-3 are arranged from far to near, and are spaced apart on the extended test board 200 near the right edge of the vertical area B2. The openings 407-1, 407-2, and 407-3 are correspondingly opened on the right side of the second top plate F2, and the openings 407-1 and 407-2 are respectively connected to another opening 408 on the second top plate F2, and the opening 408 is further connected to the right edge of the second top plate F2; and the opening 407-3 is opened separately and is not connected to the opening 408.

[0087] See also Figure 1 , Figure 2 , Figure 3 , Figure 4 , Fig. 9As shown, the first interface opening on the second top plate F2 also includes the aforementioned opening 408 connected to the right edge of the second top plate F2, and another opening 409 connected to the proximal edge of the second top plate F2. The opening 408 is also connected to a first interface opening (such as openings 903, 904 and 905) opened on the fourth side plate F6 ( Fig.17 , Fig.18 ), and the opening 409 is also connected to another first interface opening (such as the opening 702) provided on the second side plate F4 ( Fig.13 , Fig.14 ). The test fixture mainboard 100 is provided with a MIPI-DPHY output interface 108 and a MIPI-CPHY input interface 109 located in the second area A2; wherein the MIPI-DPHY output interface 108 includes a MIPI-DPHY output DuPont line interface 108-1 and a MIPI-DPHY output HDMI line interface 108-2, which are used to support the construction of a test platform for the MIPI-DPHY chip under test; the MIPI-CPHY input interface 109 includes a MIPI-CPHY output DuPont line interface 109-1 and a MIPI-CPHY output HDMI line interface 109-2, which are used to support the construction of a test platform for the MIPI-CPHY chip under test.

[0088] The MIPI-DPHY output DuPont line interface 108-1 and the MIPI-CPHY output DuPont line interface 109-1 are each provided with pins arranged upward, and the MIPI-DPHY output HDMI line interface 108-2 and the MIPI-CPHY output HDMI line interface 109-2 are each provided with an HDMI interface arranged toward the right side of the outer frame. The MIPI-DPHY output HDMI line interface 108-2 and the MIPI-CPHY output HDMI line interface 109-2 allow the host to establish a connection with the chip under test or its furnace board through the HDMI line to provide drive, and the HDMI line is easy to plug and unplug, suitable for long-distance signal transmission, and the host can be allowed to maintain a predetermined distance (for example, at least 1.5 meters) from the chip under test or its furnace board during testing, thereby allowing the host to avoid being thrown into the furnace during the aging test and improving the service life of the host. The MIPI-DPHY output DuPont line interface 108-1 and the MIPI-CPHY output DuPont line interface 109-1 are respectively used by connecting DuPont lines, thereby providing another wiring method different from using HDMI lines, which can be flexibly selected when facing different situations.

[0089] Among them, the MIPI-DPHY output DuPont line interface 108-1, the MIPI-DPHY output HDMI line interface 108-2 and the MIPI-CPHY output HDMI line interface 109-2 are adjacently arranged near the right edge of the second area A2; the pins of the MIPI-DPHY output DuPont line interface 108-1 are arranged in several rows, and these pins are exposed on the front of the outer frame through the opening 408 of the second top plate F2, so that one end of the corresponding DuPont line can be connected to these pins from the front of the outer frame; the pin side of the interface 108-1 and the module body fixing these pins can be exposed from the right side of the outer frame through the opening 905 on the fourth side panel F6, so that the other end of the DuPont line connected to the interface 108-1 can be further extended to the right of the host. The HDMI interfaces of the MIPI-DPHY output HDMI line interface 108-2 and the MIPI-CPHY output HDMI line interface 109-2 are respectively exposed from the right side of the outer frame through openings 903 and 904 provided on the fourth side panel F6 to be connected to one end of the corresponding HDMI cable, and the other end of the HDMI cable can extend outward to the right of the host; the top surfaces of the HDMI interface shielding covers of the two interfaces 108-2 and 109-2 can be observed from the front of the outer frame through the same opening 408 mentioned above on the second top panel F2. The MIPI-CPHY output DuPont line interface 109-1 is separately set at a position close to the proximal edge of the second area A2. The pins of the interface 109-1 are arranged in several rows. These pins are exposed on the front side of the outer frame through the opening 409 of the second top plate F2, so that one end of the DuPont line can be connected to these pins from the front side of the outer frame; the pin side of the interface 109-1 and the module body fixing these pins can be exposed from the proximal side of the outer frame through the opening 702 opened in the second side plate F4, so that the other end of the DuPont line connected to the interface 109-1 can extend outward on the proximal side of the host.

[0090] Among them, the MIPI-DPHY output DuPont line interface 108-1 and the MIPI-DPHY output HDMI line interface 108-2 are adjacently arranged on the right side of the second area A2 of the test fixture mainboard 100, so that the two interfaces 108-1 and 108-2 can share the circuit supporting the MIPI-DPHY protocol; similarly, the MIPI-CPHY output DuPont line interface 109-1 and the MIPI-CPHY output HDMI line interface 109-2 are adjacently arranged (located on the right and proximal parts of the second area A2 respectively, and not far apart), so that the two interfaces 109-1 and 109-2 can share the circuit supporting the MIPI-CPHY protocol, thereby simplifying the arrangement of related circuits on the test fixture mainboard 100. In particular, the MIPI-DPHY output HDMI line interface 108-2 and the MIPI-CPHY output HDMI line interface 109-2 are arranged closer to the right edge of the second area A2 than the MIPI-DPHY output DuPont line interface 108-1, and the two interfaces 108-2 and 109-2 are oriented differently from the MIPI-DPHY output DuPont line interface 108-1, so as to prevent the HDMI line connected to the two interfaces 108-2 and 109-2 from scratching the pins of the MIPI-DPHY output DuPont line interface 108-1. Since the two interfaces 108-2 and 109-2 are arranged to the right, which is different from the upward pin direction of the MIPI-CPHY output DuPont line interface 109-1, the HDMI lines connected to the two interfaces 108-2 and 109-2 will not scratch the pins of the MIPI-CPHY output DuPont line interface 109-1.

[0091] In some examples, it is not necessary to use the extended test function of the extended test board 200, or it is not necessary to provide the voltage and current detection related measured signals through the test fixture mainboard 100. In this case, the first socket module 216 can be omitted, or the channel between the first socket module 216 and the first pin module 101 can be disconnected; at this time, after the two rows of pins of the first pin module 101 on the test fixture mainboard 100 are short-circuited one by one, the power pins of certain interfaces on the test fixture mainboard 100 are powered by connecting the DuPont line. For example, the power pins of the LCD driver IC DuPont line interface 106-2, the MIPI-DPHY output DuPont line interface 108-1, and the MIPI-CPHY output DuPont line interface 109-1 can obtain power through the short-circuited first pin module 101. Taking into account the limitations of using DuPont cables for testing (such as DuPont cables can only meet some general testing needs such as non-aging tests and low-volume chip tests, and DuPont cables have limitations in the aging tests required for chip mass production), this embodiment, while setting a certain DuPont cable interface, will add other different forms of interfaces (such as HDMI, RGB+SPI) for the same protocol to meet more types of testing needs.

[0092] See also Figure 1 , Figure 2 , Figure 3 As shown, the host further includes a first sub-top plate f10 and a second sub-top plate f20, both of which can be provided or omitted as needed. The first sub-top plate f10 and the second sub-top plate f20 are respectively used to shield the exposed parts of the test fixture mainboard 100 next to the MIPI-DPHY output HDMI line interface 108-2 and the MIPI-CPHY output HDMI line interface 109-2 (i.e., the mainboard 100 parts p1, p2). The first sub-top plate f110 and the second sub-top plate f20 are respectively screwed on the first step portion 901-1 and the second step portion 902-1 of the fourth side plate F6; the first step portion 901-1 and the second step portion 902-1 are respectively located on both sides of the opening 903 of the fourth side plate F6, and cooperate to define the adjacent boundaries of the three openings 903, 904, and 905 on the fourth side plate F6; wherein, the first step portion 901-1 is located on the distal side of the opening 903, and the second step portion 902-1 is located on the proximal side of the opening 903 (that is, between the openings 903 and 904); the two step portions 901-1 and 902-1 correspond to two separate lower edges of the opening 905, and are both higher than the lower edges of the two openings 903 and 904. By utilizing the thickness of the fourth side panel F6, the top surfaces of the two step portions 901-1 and 902-1 are formed into bearing surfaces that can respectively support the right edge portions of the first sub-top panel f10 and the second sub-top panel f20. The screw hole 901-2 opened on the top surface of the first step portion 901-1 is correspondingly arranged with the through hole 501 opened on the right edge of the first sub-top panel f10 and is threaded with screws for screw connection. The right edge portion of the first sub-top panel f10 is fixed on the first step portion 901-1, and the other portions of the first sub-top panel f10 are extended to the top of the exposed portion p1 of the main board 100 next to the MIPI-DPHY output HDMI line interface 108-2 for protection. Similarly, the screw hole 902-2 opened on the top surface of the second step portion 902-1 is arranged corresponding to the through hole 502 opened on the right edge of the second sub-top plate f20 and is screwed with screws to fix the right edge of the second sub-top plate f20 on the second step portion 902-1, so that the other parts of the second sub-top plate f20 extend to the exposed part p2 of the main board 100 between the MIPI-DPHY output HDMI line interface 108-2 and the MIPI-CPHY output HDMI line interface 109-2 for protection.

[0093] See also Figure 1 , Figure 2 , Figure 3 , Fig.13 , Fig.14 , Fig.17 , Fig.18As shown, the host further includes a protective angle plate f30 for shielding the opening 409 on the front of the outer frame and the opening 702 on the proximal side of the outer frame. According to the above, the opening 409 is opened at the proximal edge of the second top plate F2, and the opening 702 is opened at the upper edge of the second side plate F4. Different parts of the MIPI-CPHY output DuPont line interface 109-1 will be exposed from the front and proximal side of the outer frame through these two connected openings 409 and 702. The protective angle plate f30 includes a vertically connected inverted L-shaped angle plate top and an angle plate side ( Figure 2 and Fig.13 These two parts are shown respectively); the MIPI-CPHY output DuPont line interface 109-1 is seldom used, so when the interface 109-1 is not used, the protective angle plate f30 can be placed on the outer frame, so that the top of the angle plate arranged horizontally covers the opening 409 on the front side of the outer frame from above, and the side of the angle plate arranged vertically covers the opening 702 on the proximal side of the outer frame from the proximal side, thereby protecting the MIPI-CPHY output DuPont line interface 109-1 and the exposed parts of the test fixture mainboard 100 around it. Among them, the area of ​​the top of the angle plate is slightly larger than the range of the opening 409, so that the top of the angle plate can completely cover the opening 409 and at the same time, the top of the angle plate can be supported by the second top plate F2 around the opening 409; screw holes 411 are provided on the second top plates F2 on the left and right sides of the opening 409, which are corresponding to the through holes 503 (with or without internal threads) provided on the top of the angle plate near the left and right edges and are screwed together by screws passed through the holes, so that a detachable connection is formed between the protective angle plate f30 and the outer frame.

[0094] See also Figure 4 , Fig.10 , Fig.11 As shown, the first side plate F3 corresponds to the distal side of the outer frame, and the first side plate F3 is provided with openings 601, 602, and 603, and the three openings 601, 602, and 603 are connected to form a substantially U-shaped opening ( Fig.10); On the test fixture mainboard 100, along the far edge of the second area A2, there are arranged in sequence a main power interface 123, a host computer communication interface, and a first debugging interface. After the host assembly is completed, these interfaces are all arranged toward the far end of the outer frame, and then exposed through openings 601, 602, and 603 provided on the first side panel F3. Among them, the main power interface 123 exposed from the far side of the outer frame through the opening 603 is used to connect to the power supply device outside the host, obtain the power required for the host to work, and supply power to the test fixture mainboard 100 or further transmit from the test fixture mainboard 100 to the extended test board 200 through the channel coupled and constructed by the aforementioned third pin module 103 and the third socket module 218, so as to supply power to the extended test board 200; the power switch button 122 arranged adjacent to the main power interface 123 but exposed from the front of the outer frame through the opening 304 can control the conduction or disconnection between the host and the power supply.

[0095] The exemplary host computer communication interface includes a USB-FS (Full Speed) interface 124 and a USB-HS (High Speed) interface 125, both of which are exposed from the far side of the outer frame through the opening 602 of the first side panel F3 and are used for communication between the host and the host computer. The first debugging interface of the example includes a DAP interface 126 in the form of a USB, and also includes a UART (Universal Asynchronous Receiver / Transmitter) interface or a JTAG (Joint Test Action Group) interface 127; these interfaces 126 and 127 are respectively exposed from the far side of the outer frame through the openings 602 and 601 of the first side panel F3, and are used to connect an external debugger to download the debugging program required for debugging the host (the debugger can be further connected to the host computer through the USB2.0 interface, and the host computer burns the debugging program to the host through the program download debugging circuit of the debugger); the debugging program obtained by the first debugging interface can be burned into the main control microcontroller module of the test fixture mainboard 100, or can be transmitted from the test fixture mainboard 100 to the extended test board 200 via the coupled expansion interface, and burned into the MCU control module on the extended test board 200.

[0096] See also Figure 1 to Figure 4 , Figure 12 to Figure 14As shown, the second side panel F4 corresponds to the proximal side of the outer frame, and the second side panel F4 is provided with openings 701 and 702; according to the above, the opening 702 is connected to the upper edge of the second side panel F4, and is connected to the opening 409 opened at the proximal edge of the second top panel F2, so that different parts of the MIPI-CPHY output Dupont line interface 109-1 are exposed. The opening 702 is roughly opened at the right position of the middle of the second side panel F4, the opening 701 is on the left side of the opening 702, and the right edge of the opening 701 is connected to the opening 702; the side of the protective corner panel f30 can shield the opening 702, but the opening 701 is always open; the power-off time control module set on the test fixture mainboard 100 includes a plurality of sliding rheostats 121 located at the proximal part of the second area A2, and these sliding rheostats 121 are exposed from the side of the outer frame through the opening 701 of the second side panel F4, which is convenient for user operation.

[0097] See also Figure 1 , Figure 2 , Fig.15 , Fig.16 As shown, the third side panel F5 corresponds to the left side of the outer frame, and the third side panel F5 is provided with openings 801 and 802; according to the above, the opening 802 is connected to the upper edge of the third side panel F5, and is connected to the opening 401 opened on the left edge of the second top panel F2, so that the LCD driver IC coaxial line interface 106-1 included in the drive control integrated interface 106 can be exposed from the left side of the outer frame, so that the coaxial line of the interface 106-1 can be extended and placed on the left side of the host. The left edge of the second area A2 on the test fixture mainboard 100 is provided with a memory card slot 129, which can be exposed from the left side of the outer frame through the opening 801 separately opened on the third side panel F5; the memory card slot 129 is used to insert a memory card, such as an SD card; the memory card can be used to store pictures. When the power-on screen test is performed, the FPGA module on the test fixture mainboard 100 can convert the picture in the memory card into a protocol and send it to the chip under test, avoiding the temporary transmission of the picture from the host computer, which is conducive to shortening the communication time required for the test.

[0098] See also Figure 1 to Figure 4 , Fig.17 , Fig.18As shown, the fourth side panel F6 is the right side of the outer frame, and the fourth side panel F6 is provided with interconnected openings 903, 904 and 905, and two other separately opened openings 906 and 907. According to the above, the interconnected openings 903, 904 and 905 will be connected to the upper edge of the fourth side panel F6, and connected to the opening 408 opened on the right edge of the second top panel F2; these three openings 903, 904 and 905 are connected to form a roughly W-shaped opening, and the MIPI-DPHY output HDMI line interface 108-2 and the MIPI-CPHY output HDMI line interface 109-2 can be exposed through the openings 903 and 904 respectively to connect with their corresponding HDMI lines. The side panel portion on the fourth side panel F6, which is located on the far side of the opening 903 and corresponds to a section of the lower edge of the opening 905, forms a first step portion 901-1 by utilizing the thickness of the fourth side panel F6 itself and the height difference between the top surface of the side panel portion and the lower edge of the opening 903, and is used to support and screw the right edge portion of the first sub-top panel f10, so that other portions of the first sub-top panel f10 can cover the exposed portion p1 of the main board 100 next to the MIPI-DPHY output HDMI line interface 108-2 for protection. The side panel portion on the fourth side panel F6 is located between the openings 903 and 904 and corresponds to the other lower edge of the opening 905. The second step portion 902-1 is formed by utilizing the thickness of the fourth side panel F6 itself and the height difference between the top surface of the side panel portion and the lower edges of the openings 903 and 904. The second step portion 902-1 is used to support and screw the right edge portion of the second sub-top panel f20, so that other portions of the second sub-top panel f20 can cover the exposed portion p2 of the main board 100 between the MIPI-DPHY output HDMI line interface 108-2 and the MIPI-CPHY output HDMI line interface 109-2 for protection.

[0099] A reset button 107 is provided on the test fixture mainboard 100 near the far end and right edge of the second area A2 (i.e., near the upper right corner of the second area A2). The reset button 107 is arranged toward the right side of the outer frame and is exposed through the opening 907 of the fourth side panel F6. The reset button 107 can be operated to restart the host with one click.

[0100] The opening 906 of the fourth side panel F6 can be opened or omitted as needed. If the debugging interface provided on the extended test board 200 is arranged toward the right side of the outer frame, it can be exposed through the opening 906 provided on the fourth side panel F6 to connect with the signal transmission line of the external debugger to obtain the debugging program. According to the foregoing content, the extended test board 200 of this embodiment does not use a debugging interface arranged toward the side, but is provided with a second debugging interface 211 exposed from the front of the outer frame. In this case, the opening 906 on the fourth side panel F6 is not needed, so the opening 906 can be omitted in some embodiments. However, the opening 906 can still be retained on the fourth side panel F6. In this way, even if the host needs to expand other functions and another extended test board 200 with a lateral debugging interface is replaced to couple with the test fixture main board 100, the same outer frame with the opening 906 retained on the fourth side panel F6 can be directly applied to the lateral debugging interface of the replaced extended test board 200. There is no need to prepare two sets of outer frames with different opening schemes, which effectively reduces the cost of mold opening or spare parts and simplifies the disassembly and assembly operations when replacing parts.

[0101] See also Figure 1 , Figure 15 to Figure 18 As shown, the first top plate F1 and the second top plate F2 of this embodiment are not in the same plane, and the second top plate F2 is arranged higher than the first top plate F1 as a whole, so that the pins set on the test fixture mainboard 100 and the various interfaces that can be exposed from the front of the outer frame through the corresponding openings on the second top plate F2 on the extended test will not exceed the top surface of the second top plate F2 in height, thereby protecting these pins from collision and wear, ensuring the plugging effect of these pins. Fig.15 , Fig.16 From the left side of the mainframe shown, the top surface of the side panel on the third side panel F5 that carries the second top panel F2 is higher than the top surface of the side panel on the third side panel F5 that carries the first top panel F1 by a height difference of h1; preferably, the thickness of the first top panel F1 is made equivalent to the height difference h1. Then, after the left edge of the first top panel F1 is placed on the corresponding top surface of the side panel on the third side panel F5, the top surface of the first top panel F1 can be roughly on the same horizontal plane with the top surface of the side panel on the third side panel F5 for carrying the second top panel F2, and the top surface of the second top panel F2 is further higher than the top surface of the first top panel F1 by a height difference of h2 (the height difference h2 is equivalent to the thickness of the second top panel F2).

[0102] Similarly, from Fig.17 , Fig.18From the right side of the mainframe shown, the top surface of the side panel on the fourth side panel F6 that carries the second top panel F2 is higher than the top surface of the side panel on the fourth side panel F6 that carries the first top panel F1 by a height difference of h1; preferably, the thickness of the first top panel F1 is equivalent to the height difference h1. Then, after the right edge of the first top panel F1 is placed on the corresponding top surface of the side panel on the fourth side panel F6, the top surface of the first top panel F1 can be roughly on the same horizontal plane as the top surface of the side panel on the fourth side panel F6 for carrying the second top panel F2, and the top surface of the second top panel F2 is further higher than the top surface of the first top panel F1 by a height difference of h2 (the height difference h2 is equivalent to the thickness of the second top panel F2).

[0103] See also Figure 8 , Fig. 9 , Figure 15 to Figure 21 As shown, the first top plate F1 of this embodiment is provided with slots 308 at two corner positions on its proximal side, and the third side plate F5 and the fourth side plate F6 are respectively provided with protrusions 803 and 908 at positions corresponding to the slots 308. The protrusions 803 and 908 can be snapped into the corresponding slots 308 and support the left and right edges of the second top plate F2. Among them, the raised portion 803 on the third side panel F5 is located at the farthest end of the top surface of the side panel of the third side panel F5 used to support the second top panel F2 (roughly in the middle of the third side panel F5), and the top surface of the raised portion 803 is higher than the lower edge of the opening 802 next to it, and higher than the top surface of the side panel on the third side panel F5 used to support the first top panel F1. Therefore, the raised portion 803 is formed by utilizing the thickness of the third side panel F5 itself, and the raised portion 803 is just snapped into the slot 308 on the left side of the first top panel F1 to prevent the first top panel F1 from sliding to the left or proximally in the horizontal direction. Similarly, the raised portion 908 on the fourth side panel F6 is located at the farthest end of the top surface of the side panel of the fourth side panel F6 for supporting the second top panel F2 (roughly in the middle of the fourth side panel F6), and the top surface of the raised portion 908 is higher than the top surface of the first step portion 901-1 next to it for supporting the first sub-top panel f10, and higher than the top surface of the side panel on the fourth side panel F6 for supporting the first top panel F1, thereby utilizing the thickness of the fourth side panel F6 itself to form the raised portion 908; the raised portion 908 is just engaged with the slot 308 on the right side of the first top panel F1 to prevent the first top panel F1 from sliding to the right or proximally in the horizontal direction.

[0104] See also Figure 1 , Figure 2 , Figure 10 to Figure 17As shown, in this embodiment, the left and right sides of the first side plate F3 are respectively screwed to the distal ends of the third side plate F5 and the fourth side plate F6; the left and right sides of the second side plate F4 are respectively screwed to the proximal ends of the third side plate F5 and the fourth side plate F6; the third side plate F5 and the fourth side plate F6 are further screwed to the edges of the left and right sides of the bottom plate F0 of the outer frame. Fig.10 , Fig.11 As shown, through holes 604 are provided at four corners of the first side plate F3 (each through hole 604 may or may not have internal threads), and two screw holes are respectively provided at the distal ends of the third side plate F5 and the distal ends of the fourth side plate F6 and are arranged opposite to the through holes 604. Screws are inserted between the oppositely arranged through holes and screw holes to fix the first side plate F3 with the third side plate F5 and the fourth side plate F6. Figure 12 to Figure 14 As shown, through holes 703 are provided at the four corners of the second side panel F4 (each through hole 703 may or may not have an internal thread), and the proximal end of the third side panel F5 and the proximal end of the fourth side panel F6 each have two screw holes arranged opposite to these through holes 703, and screws are inserted between the relatively arranged through holes and the screw holes to fix the second side panel F4 with the third side panel F5 and the fourth side panel F6, thereby connecting the first side panel F3, the second side panel F4, the third side panel F5, and the fourth side panel F6 into a rectangular frame that passes through from top to bottom.

[0105] like Fig. 22 As shown, the through holes 1012 (with or without internal threads) opened at the four corners of the bottom plate F0 of the outer frame are respectively arranged opposite to the screw holes opened on the bottom surfaces of the third side plate F5 and the fourth side plate F6, and screws are inserted between the relatively arranged through holes and the screw holes to fix the third side plate F5 and the fourth side plate F6 to the bottom plate F0, respectively, thereby stably and reliably connecting the rectangular frame surrounded by the four side plates to the bottom plate F0. According to the above, binding holes 1011 are respectively opened at the four corners of the base plate F0, which are arranged opposite to the binding holes 131 of the second area A2 of the test fixture main board 100 and are bound and connected through a mechanical connection structure (such as rivets, screws, etc.) penetrated in the holes; then, the four through holes 1012 on the base plate F0 will be closer to the left or right boundary of the base plate F0, so that these through holes 1012 are adapted to the position of the third side plate F5 or the fourth side plate F6; and the four binding holes 1011 are located on the inner side of the four through holes 1012, so that the position of these binding holes 1011 and the test fixture main board 100 is more adapted.

[0106] The rectangular frame formed by the four side panels can further support the first top panel F1 and the second top panel F2. That is, the distal, left and right edges of the first top panel F1 are supported by the top surfaces of the first side panel F3, the third side panel F5 and the fourth side panel F6, respectively. The proximal, left and right edges of the second top panel F2 are supported by the top surfaces of the second side panel F4, the third side panel F5 and the fourth side panel F6, respectively; at the same time, the distal edge of the second top panel F2 covers the proximal region z of the proximal edge of the first top panel F1 and is supported by the proximal region z. Figure 1 , Figure 2 , Figure 8 , Fig. 9 As shown, the left edges of the first top plate F1 and the second top plate F2 are also screwed to the corresponding bearing surfaces of the third side plate F5; the right edges of the first top plate F1 and the second top plate F2 are also screwed to the corresponding bearing surfaces of the fourth side plate F6.

[0107] That is, four through holes 307 (with or without internal threads) are provided on the first top plate F1, of which the two through holes 307 near the left edge of the first top plate F1 are respectively arranged opposite to the two screw holes provided on the top surface of the side plate for supporting the first top plate F1 on the third side plate F5, and connecting screws are inserted into the oppositely arranged through holes and screw holes; the other two through holes 307 near the right edge of the first top plate F1 are respectively arranged opposite to the two screw holes provided on the top surface of the side plate for supporting the first top plate F1 on the fourth side plate F6, and connecting screws are inserted into the oppositely arranged through holes and screw holes, thereby fixing the first top plate F1 with the third side plate F5 and the fourth side plate F6. Similarly, four through holes 412 (with or without internal threads) are provided on the second top plate F2, of which the two through holes 412 near the left edge of the second top plate F2 are respectively arranged opposite to the two screw holes provided on the top surface of the side plate for supporting the second top plate F2 on the third side plate F5, and connecting screws are inserted into the oppositely arranged through holes and screw holes; the other two through holes 412 near the right edge of the second top plate F2 are arranged opposite to the two screw holes provided on the top surface of the side plate for supporting the second top plate F2 on the fourth side plate F6, and connecting screws are inserted into the oppositely arranged through holes and screw holes, thereby fixing the second top plate F2 to the third side plate F5 and the fourth side plate F6, respectively.

[0108] Preferably, the two through holes 307 at the proximal end of the first top plate F1 are provided next to the slots 308 at the left and right corners, and the two corresponding screw holes are provided at the proximal end of the top surface of the third side plate F5 and the fourth side plate F6, respectively, for supporting the first top plate F1, so that the first top plate F1 is more firmly screwed with the third side plate F5 and the fourth side plate F6 near the two slots 308. The through holes 412 provided at the two distal corners of the second top plate F2 are respectively arranged opposite to the screw holes provided at the protrusions 803 of the third side plate F5 and the protrusions 908 of the fourth side plate F6, so that the second top plate F2 is more firmly screwed with the protrusions 803 and 908.

[0109] Therefore, an assembly method of the test fixture host described in this embodiment is proposed, such as Fig.23 As shown, the assembly method comprises the following steps:

[0110] S10, coupling the extended test board 200 to the test fixture main board 100, and binding the two through a first binding structure; at this time, the extended test board 200 is spatially overlapped above the test fixture main board 100, and the two are coupled through a number of correspondingly set groups of expansion interfaces.

[0111] S20, binding the test fixture mainboard 100 and the bottom plate F0 through a second binding structure; that is, fixing a combination formed by coupling and binding the extended test board 200 and the test fixture mainboard 100 to the bottom plate F0.

[0112] S30, screw the third side plate F5 and the fourth side plate F6 to the bottom plate F0 respectively. Align the through holes on the bottom plate F0 with the screw holes on the third side plate F5 and the fourth side plate F6 and insert the screws to connect them.

[0113] S40, screw the first side panel F3 to the third side panel F5 and the fourth side panel F6, respectively, and screw the second side panel F4 to the third side panel F5 and the fourth side panel F6, respectively. The through holes on the first side panel F3 are aligned with the screw holes on the third side panel F5 and the fourth side panel F6, and screws are inserted to connect them, and the through holes on the second side panel F4 are aligned with the screw holes on the third side panel F5 and the fourth side panel F6, and screws are inserted to connect them.

[0114] S50, clamp the first top plate F1 with the third side plate F5 and the fourth side plate F6 respectively, and screw the first top plate F1 with the third side plate F5 and the fourth side plate F6. At this time, the first top plate F1 is supported by the first side plate F3, the third side plate F5 and the fourth side plate F6 respectively, the protrusions of the third side plate F5 and the fourth side plate F6 are clamped in the corresponding clamping grooves of the first top plate F1, the through holes on the first top plate F1 are aligned with the screw holes on the third side plate F5 and the fourth side plate F6, and screws are inserted to connect them.

[0115] S60, place the second top plate F2 against the edge of the first top plate F1, the second top plate F2 being arranged higher than the first top plate F1 as a whole, and screwing the second top plate F2 to the third side plate F5 and the fourth side plate F6. At this time, the second top plate F2 is supported by the edge of the first top plate F1, the second side plate F4, the third side plate F5, and the fourth side plate F6 respectively, and the through holes on the second top plate F2 are aligned with the screw holes on the third side plate F5 and the fourth side plate F6 and screws are inserted to connect them.

[0116] At this point, the assembly of the test fixture host is completed. For example, specific examples of the expansion interface, the first binding structure, the second binding structure, etc., and the positions of the openings on each plate, etc., can all be referred to above and will not be described in detail.

[0117] The assembly method described in this embodiment may further include the step of screwing the first sub-top plate f10 and the second sub-top plate f20 to the fourth side plate F6, so as to shield and protect the two mainboard 100 parts p1 and p2 exposed from the opening of the second top plate F2 through the first sub-top plate f10 and the second sub-top plate f20 (the mainboard 100 parts p1 and p2 are respectively located beside the MIPI-DPHY output HDMI line interface 108-2 and the MIPI-CPHY output HDMI line interface 109-2). The through holes of the first sub-top plate f10 and the second sub-top plate f20 are respectively aligned with the screw holes of the two step portions of the fourth side plate F6 and screws are inserted to connect. Since after step S30, the test fixture main board 100 and the fourth side plate F6 have been installed to the specified position, and whether the first sub-top plate f10 and the second sub-top plate f20 are set or not does not affect the installation of other panels, the step of screwing the first sub-top plate f10 and the second sub-top plate f20 to the fourth side plate F6 can be performed before or after any step after S30. Alternatively, the entire step of setting the first sub-top plate f10 and the second sub-top plate f20 can be omitted.

[0118] The assembly method described in this embodiment may also include the step of screwing the protective angle plate to the second top plate F2, so as to shield the openings connected to the second top plate F2 and the second side plate F4 through the protective angle plate, so as to protect the MIPI-CPHY output Dupont line interface 109-1 and the surrounding test fixture mainboard 100 or extended test board 200 that can be exposed from the opening. Among them, a through hole is provided on the top of the angle plate of the protective angle plate, which is aligned with the screw hole of the second top plate F2 and inserted with a screw to connect. The protective angle plate can be pre-screwed to the second top plate F2 before or after any one of steps S10 to S50, and fixed to other panels of the outer frame together with the second top plate F2 in step S60. Alternatively, there is no need to set the protective angle plate in steps S10 to S60, and the protective angle plate is screwed to the second top plate F2 installed on the host separately after step S60. Alternatively, the entire step of setting the protective angle plate can be omitted.

[0119] In the test fixture host described in the present embodiment, the test fixture mainboard 100 can not only independently complete a small part of the voltage and current test, but also independently complete the point screen to independently complete the aging test of the chip. Through the cooperation of the test fixture mainboard 100 and the extended test board 200, more types of voltage, current test, frequency detection, diode / resistance test can also be performed on the tested chip. For this reason, in addition to the various interfaces described above and the corresponding modules configured for their respective detection functions, the test fixture mainboard 100 is also provided with, for example, a main control microcontroller module, an FPGA module, a storage module, an internal power conversion module, a level conversion communication interface module, a signal conversion module, an LED backlight circuit module, etc.; the extended test board 200 is also provided with, for example, an MCU control module, a power adjustment module, and various sampling modules, etc. It is possible to arrange various modules and auxiliary components (not shown in the figure) that do not need to be connected to the tested chip or the host external device, and do not need to be manipulated by the user in the test, in a position that does not affect the exposure of each interface, such as being arranged in the first area A1 on the front of the test fixture mainboard 100, the back of the test fixture mainboard 100 or the extended test board 200, etc.

[0120] Among them, the main control microcontroller module of the test fixture mainboard 100 can exchange information with the host computer (such as various display data, touch data, etc., or download the debugging program from the external debugger connected to the host computer, etc.), the main control microcontroller module can control other modules on the mainboard 100, and can also be coupled with the MCU control module of the extended test board 200 via the channel built by the expansion interface to control at least some of the functional modules on the extended test board 200. The FPGA module on the test fixture mainboard 100 is controlled by the main control microcontroller module, and is used for the logic control of functional modules such as SDRAM (Synchronous Dynamic Random Access Memory), level conversion communication interface, MIPI bridge chip, etc. on the chip test fixture mainboard 100. Most importantly, FPGA is used to implement the communication protocol between the test fixture mainboard 100 and the chip under test. In addition, the FPGA module can also be set to assist in the data processing of the extended test board 200, for example, in the frequency test, the frequency detection signal received by the extended test board 200 is obtained for processing. The first storage module (such as SDRAM, Flash, SD card, etc.) of the test fixture mainboard 100 can be used by the microcontroller main control module; the second storage module (such as SDRAM, etc.) can be used by the FPGA module as needed. For example, SDRAM provides additional memory for the FPGA module, and the FPGA module realizes read and write operations by controlling SDRAM, etc.

[0121] The internal power conversion module of the test fixture mainboard 100 includes a power regulation output circuit and a current limiting protection circuit module. The power regulation output circuit (for example, for outputting the three power supplies / two power supplies required by the chip) is controlled by the main control microcontroller module and is used to output the three power supplies VSP (Positive Voltage Supply, positive voltage supply) / VSN (Negative Voltage Supply, negative voltage supply) IOVCC required by common LCD drivers, or the two power supplies VCI and IOVCC required by common LCD drivers, and other common power supply voltages for display drivers. These voltages can be provided to the extended test circuit board through the channel coupled by the first pin module 101 and the first socket module 216. The input end of the power regulation output circuit is connected to an external power supply, and the external power supply is provided to the power regulation output circuit to be converted into the required internal power supply voltage category, and then converted into a suitable voltage and provided to each module that needs power. After being provided to the extended test circuit board through the test fixture mainboard 100, these voltages can be sampled by the extended test board 200 as test signals. The extended test circuit board will feed back the sampled data to the main control microcontroller module of the test fixture mainboard 100, and then feed back to the host computer to facilitate testers to automatically obtain data, thereby realizing test automation.

[0122] The level conversion communication interface module of the test fixture mainboard 100 is used to adjust the level of the DP (display signal) signal, and is also used to output the level of the TP (touch signal) signal. The DP signal is, for example, RGB / I80 (Inter 8080-series) / SPI / QSPI, and the TP signal includes, for example, SPI / IIC / int (interrupt) / Reset (reset), etc. The final output of the level conversion communication interface module can be output through the aforementioned drive control integrated interface 106, MIPI-DPHY output interface 108, MIPI-CPHY input interface 109, etc. The signal conversion module of the test fixture mainboard 100, for example, includes a MIPI bridge chip module (which can receive RGB+SPI and process the RGB signal, and finally output the MIPI signal), which is used to convert the RGB signal into a MIPI signal output. The MIPI signal may include MIPI-DPHY, MIPI-CPHY, etc., and can be output through the aforementioned MIPI-DPHY output interface 108 and MIPI-CPHY input interface 109.

[0123] The LED backlight circuit module of the test fixture mainboard 100 is used to power the display screen backlight module driven by the chip under test, and drive the display screen backlight module of the chip under test under the control of the dimming pulse timing. Optionally, the output of the LED backlight circuit module can also be transmitted to the current detection interface of the extended test board 200 (the current detection interface is located at a part of the pin pins of the third pin module 103) through the channel coupled and constructed by the aforementioned first pin module 101 and the first socket module 216, so as to facilitate the chip under test to obtain the detection of this type of current from the current detection interface of the extended test board 200.

[0124] The MCU control module on the extended test board 200 can be connected to other modules on the extended test board 200 and control these modules through the SPI bus, IIC1 bus, IIC2 bus, etc. For example, the MCU control module is used to cooperate with the operation of each button to control the display content of the display screen 207-1; the extended test board 200 is provided with a backlight module as a backlight driving module of the display screen 207-1. For another example, the MCU control module can connect and control the sampling modules on the extended test board 200 for sampling various test indicators of the chip under test, such as 20-way external voltage sampling modules, 5-way power supply voltage sampling modules and 1-way backlight voltage sampling modules, 5-way power supply current sampling modules and 1-way backlight current sampling modules, as well as 16-way scale diode, resistor sampling modules, 1-way external injection voltage sampling module, 1-way external injection current sampling module, 2-way waveform frequency or duty cycle sampling modules, etc. The extended test board 200 may be provided with an independent power supply adjustment module, which is used to transform the power supply voltage from the test fixture mainboard 100 or the power supply voltage applied by other external modules (for example, converting the input 12V voltage into 5V, 5V, 3.3V, 2.5V, ±5V, 0.5V, -12V and other potentials) for use by various modules on the extended test board 200. The many test functions of the extended test board 200 can be realized automatically by means of the coordination of the main control microcontroller module and the FPGA module set on the test fixture mainboard 100, so that the chip testing method can be realized automatically.

[0125] The following provides an automatic testing method for the test fixture host described in this embodiment. Fig.24 As shown, the automatic testing method comprises the following steps:

[0126] S101. The chip under test realizes screen touch through a plurality of first interfaces on a host.

[0127] S102, receiving the test signal of the tested chip through several second interfaces on the host, and the host controls the extended test board through the test fixture mainboard to automatically sample the test signal to perform automated testing and process the test results.

[0128] like Fig.25 As shown, as an example of an automatic testing method, in the automatic testing process of lighting up the chip under test, the following steps are included:

[0129] S201, connecting the chip under test to the host (for example, connecting the corresponding power interface and communication interface between the chip and the host, which are used to power the chip under test through the host, transmit various data information required for the test from the host to the chip, and receive feedback information from the chip into the host for processing).

[0130] S202, the host computer configures the interface protocol, interface parameters, power supply, initialization code, pictures and other data.

[0131] S203, the host computer is connected to the host through the host computer communication interface (such as USB-FS interface, USB-HS interface) of the host computer, and sends the configuration data to the host.

[0132] S204: The host stores the received configuration data into an internal memory of the host (eg, a Flash memory).

[0133] S205: The host computer restarts, parses the configuration data, and sends an initialization code to the chip under test.

[0134] After the chip under test is successfully lit up, the screen test can be ended. By clicking the screen, the software and firmware of the chip can be verified, for example, whether the chip's data transmission, command parsing, display control and other functions are normal can be tested.

[0135] In some point-screen examples, for example, the image can be pre-set on the host's memory card, and the FPGA module in the host converts the protocol and sends it to the chip, without transmitting the image from the host computer, effectively shortening the communication time.

[0136] like Fig.26 As another example of the automatic test method, after the test chip is connected to the host, the screen will be touched first, and then the chip will be tested while the chip is powered on. The automatic test process of this example includes the following steps:

[0137] S301, connecting the chip under test to the host (for example, connecting the corresponding power interface and communication interface between the chip and the host, which are used to power the chip under test through the host, transmit various data information required for the test from the host to the chip, and receive feedback information from the chip into the host for processing).

[0138] S302, the host computer configures the interface protocol, interface parameters, power supply, initialization code, pictures and other data.

[0139] S303, the host computer connects to the host through the host computer communication interface (such as USB-FS interface, USB-HS interface) of the host computer, and sends the configuration data to the host.

[0140] S304: The host stores the received configuration data into the host's internal memory (such as Flash memory).

[0141] S305: The host computer restarts, parses the configuration data, and sends an initialization code to the chip under test.

[0142] S305, determine whether the chip under test is successfully lit up; if the chip is not lit up, re-execute the process from step S301 of connecting the chip under test to the host; if the chip is successfully lit up, further execute S306.

[0143] S306 , connecting the tested interface on the tested chip to the sampling channel on the host.

[0144] S307, the host computer configures sampling settings.

[0145] S308. The host computer sends a sampling instruction and reads back the result.

[0146] In S306, for example, one or more pins on the chip are connected to a sampling channel (for example, corresponding to an attached pin) on the host for voltage, frequency, and external voltage detection through a corresponding signal transmission line. Figure 5 The second interface shown, such as interface 202, 204, 228, etc.) (It should be noted that when sampling current, for example, sampling can be performed through an interface that has been connected between the chip and the host (for example, a pin module connected between the test fixture mainboard and the extended test board, a pin corresponding to the current parameter indicator in the socket module combination, etc.), without the need to connect a sampling channel separately (that is, without connecting a sampling channel in the attached Figure 5 The second interface position shown corresponds to the setting interface), S306 can be omitted); in S307 and S308, the host computer can configure the sampling settings in real time through a graphical interface or code, etc., and send corresponding sampling instructions to the host, so that the host can switch to a suitable sampling mode, open the corresponding sampling channel, provide the required test conditions for the chip under test and sample related test indicators, and realize the detection of items such as voltage, current, frequency, and external input voltage; the feedback data of the chip can be processed by the host or sent by the host to the host for processing, and the test results can be viewed through the host computer or on the display screen of the host.

[0147] like Fig. 27 As shown in FIG. 1 , as another example of the automatic testing method, a test is performed on the chip while keeping the chip powered off. The automatic testing process of this example includes the following steps:

[0148] S401 , connecting the tested interface of the tested chip to the sampling channel of the host. The sampling channel in this example includes a sampling channel for resistance and diode detection.

[0149] S402, the host computer configures sampling settings.

[0150] S403, the host computer sends a sampling instruction and reads back the result.

[0151] In the automatic test process of this example, the chip itself does not need to be connected to a power supply; in S401, for example, two pins on the chip are connected to a sampling channel (for example, corresponding to Figure 5 The second interface shown, for example, the diode / resistance detection interface 203 shown, has a positive pin and a negative pin connected; in S402 and S403, the host computer can configure the sampling settings in real time through a graphical interface or code, etc., and send the corresponding sampling instructions to the host, so that the host can open the corresponding sampling channel, provide a suitable voltage for the chip under test, and measure the electrical parameters between the two pins; in diode detection, if there is a diode between the two pins of the chip, then a specific forward voltage drop should be measured under forward bias, and no obvious current will be measured under reverse bias; in resistance detection, the resistance value between the two pins of the chip under test can be calculated based on the voltage provided by the host and the measured current. The detection data obtained from the chip can be processed by the host or sent by the host to the host for processing, and the test results can be viewed by the host or on the display screen of the host.

[0152] To sum up, the test fixture host of the present invention can stack and couple the extended test board and the test fixture main board and integrate them into the outer frame, provide a variety of protocol interface types and reasonably arrange the opening positions, thereby expanding more test functions without increasing the size of the whole machine, building a test platform that can be easily operated, and realizing automatic testing of chips through each board working alone or in collaboration. It is suitable for chip testing scenarios with various working protocols, quantity scales, and test types, has good compatibility, can ensure test quality while improving test efficiency, and meet mass production test needs.

[0153] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. A test fixture host, characterized in that: The test fixture host comprises: A test fixture mainboard, comprising a plurality of first interfaces, wherein the first interfaces are arranged along an edge of the test fixture mainboard; An extended test board, comprising a plurality of second interfaces, wherein the extended test board is coupled to a middle area of ​​one side of the test fixture main board to be stacked on the test fixture main board; The outer frame body, the test fixture mainboard and the extended test board are placed in the outer frame body, and the periphery of the outer frame body is provided with a plurality of first openings for exposing the first interface, and the front middle area of ​​the outer frame body is provided with a plurality of second openings for exposing the second interface.

2. The test fixture host according to claim 1, characterized in that: The outer frame includes a top plate, a bottom plate and side plates to form a frame.

3. The test fixture host according to claim 2, characterized in that: The top plate comprises an independent first top plate and a second top plate, the second top plate is close to the edge of the first top plate, and the middle area of ​​the second top plate is used to open a second interface opening for exposing the second interface; Furthermore, the edge area of ​​the second top plate is used to open first interface openings that expose a portion of the plurality of first interfaces.

4. The test fixture host according to claim 3, characterized in that: The side panel includes a first side panel, a second side panel, a third side panel, and a fourth side panel. The first side panel, the second side panel, the third side panel, and the fourth side panel are arranged between the first top panel, the second top panel, and the bottom panel, and surround the test fixture main board and the extended test board.

5. The test fixture host according to claim 4, characterized in that: The first top plate is provided with a display opening and a button opening.

6. The test fixture host according to claim 4, characterized in that: The first top plate is provided with a slot, and the third side plate and the fourth side plate are respectively provided with protrusions opposite to the slot, and the slot and the protrusions are engaged with each other.

7. The test fixture host according to claim 4, characterized in that: The first side plate, the second side plate, the third side plate and the fourth side plate are provided with first interface openings which expose another part of the first interfaces.

8. The test fixture host according to claim 4, characterized in that: The bottom plate is provided with a plurality of connecting through holes and binding holes, the bottom plate is respectively connected to the third side plate and the fourth side plate through the connecting through holes, and the bottom plate is connected to the test fixture mainboard through the binding holes.

9. The test fixture host according to claim 4, characterized in that: The first side plate and the third side plate are screwed together, the first side plate and the fourth side plate are screwed together, the second side plate and the third side plate are screwed together, the second side plate and the fourth side plate are screwed together, the first top plate and the third side plate are screwed together, the first top plate and the fourth side plate are screwed together, the second top plate and the third side plate are screwed together, and the second top plate and the fourth side plate are screwed together.

10. An assembly method for the test fixture host according to any one of claims 1 to 9, characterized in that: The method comprises: S10, coupling the extended test board to the test fixture main board and binding them through a first binding structure of the two; S20, binding the test fixture mainboard and the base plate through a second binding structure; S30, screwing the third side plate and the fourth side plate to the bottom plate respectively; S40, screwing the first side plate, the second side plate, the third side plate and the fourth side plate in sequence; S50, clamping the first top plate, the third side plate and the fourth side plate respectively, and screwing the first top plate, the third side plate and the fourth side plate; S60, placing the second top plate against the edge of the first top plate, with the second top plate being higher than the first top plate, and screwing the second top plate to the third side plate and the fourth side plate.

11. An automatic testing method, characterized in that: The automatic testing method is implemented by using the test fixture host according to any one of claims 1 to 9, comprising: S101, the chip under test realizes screen touch through a plurality of first interfaces on the host; S102, receiving the test signals of the tested chip through the plurality of second interfaces on the host, and the host controlling the extended test board through the test fixture mainboard to automatically sample the test signals to perform the automated test and process the test results.

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