Chip testing device and method and computer readable medium

Abstract

The embodiment of the invention provides a chip testing device and method and a computer readable medium. The chip testing device comprises a testing machine which comprises a power supply output port and a first signal output port; a switch chip in which multiple paths of switch circuits are integrated, one end of each path of switch circuit is connected to the power supply output port, and the other end of each path of switch circuit is used for connecting a chip to be tested; wherein the switch chip comprises a first controlled port, the first controlled port is connected with a first signal output port of the test machine, and a control signal output by the first signal output port is used for controlling a specified switch circuit in the switch chip to be conducted. And the power supply output port transmits electric energy to the to-be-tested chip connected with the specified switching circuit for test processing. According to the technical scheme provided by the embodiment of the invention, the occupation of resources of the testing machine can be effectively reduced on the premise of ensuring that the chip has a relatively high simultaneous testing number during testing.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip technology, and in particular, to a chip testing device, method and computer-readable medium. Background Art

[0002] Integrated circuit semiconductor chips need to be tested before production, shipment or use, that is, to test each function of the chip, such as CP (Chip Probe) test and FT (Final test) test. Due to the huge number of chips to be tested, it is usually necessary to expand the number of simultaneous tests (that is, the number of chips tested at the same time) to save chip testing time. However, the number of tester resources is limited. In this case, how to save the resource occupation of the tester as much as possible while ensuring a high number of simultaneous tests is a technical problem that needs to be solved urgently. Summary of the invention

[0003] The embodiments of the present application provide a chip testing device, method and computer-readable medium, which can effectively reduce the occupancy of tester resources while ensuring a high number of simultaneous tests during chip testing.

[0004] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0005] According to a first aspect of an embodiment of the present application, a chip testing device is provided, comprising: a tester, the tester comprising a power output port and a first signal output port; a switch chip, the switch chip integrating a plurality of switch circuits, one end of each switch circuit being connected to the power output port, and the other end being used to connect a chip to be tested; wherein the switch chip comprises a first controlled port, the first controlled port being connected to a first signal output port of the tester, and the control signal output by the first signal output port being used to control the conduction of a designated switch circuit in the switch chip, so as to transmit electric energy to the chip to be tested connected to the designated switch circuit through the power output port for testing.

[0006] In some embodiments of the present application, based on the aforementioned scheme, the switch chip further includes a second controlled port, and the test machine further includes a second signal output port; the second controlled port of the switch chip is connected to the second signal output port of the test machine, and the second signal output port of the test machine is used to transmit a clock signal to the second controlled port of the switch chip.

[0007] In some embodiments of the present application, based on the aforementioned solution, the multi-way switch circuit integrated in the switch chip is connected to the same power output port on the tester.

[0008] In some embodiments of the present application, based on the aforementioned scheme, the switch chip also includes a data output port, and the data output port is used to output a synchronization signal obtained after shifting the control signal input to the first controlled port; the chip testing device includes multiple switch chips, and the multiple switch chips are connected in a cascade mode; wherein the first controlled port of the first-level switch chip among the multiple switch chips is connected to the first signal output port of the tester, and the first controlled ports of other switch chips among the multiple switch chips except the first-level switch chip are connected to the data output port of the previous-level switch chip.

[0009] In some embodiments of the present application, based on the aforementioned scheme, the switch chip further includes a second controlled port, and the test machine further includes a second signal output port; the second controlled ports of the multiple switch chips are connected to the same second signal output port of the test machine, and the second signal output port is used to transmit clock signals to the second controlled ports of the multiple switch chips.

[0010] In some embodiments of the present application, based on the aforementioned scheme, the multi-way switch circuits integrated in each of the switch chips are connected to the same power output port on the tester, and the power output ports connected to the switch circuits integrated in different switch chips are different.

[0011] In some embodiments of the present application, based on the aforementioned scheme, the test machine further includes a third signal output port, and the switch chip further includes a third controlled port; the third controlled ports of the multiple switch chips are connected to the same third signal output port of the test machine, and the third signal output port of the test machine is used to transmit an enable signal to the third controlled ports of the multiple switch chips.

[0012] In some embodiments of the present application, based on the aforementioned scheme, the test machine further includes a fourth signal output port, and the switch chip further includes a fourth controlled port; the fourth controlled ports of the multiple switch chips are connected to the same fourth signal output port of the test machine, and the fourth signal output port of the test machine is used to transmit a reset signal to the fourth controlled ports of the multiple switch chips.

[0013] In some embodiments of the present application, based on the aforementioned scheme, the chip testing device includes multiple switch chips, and the first controlled ports of the multiple switch chips are respectively connected to different first signal output ports on the tester to respectively receive the control signals output by the corresponding first signal output ports.

[0014] In some embodiments of the present application, based on the aforementioned solution, the switch chip is arranged on a probe card, the probe card is arranged on a head of the tester, and the probe card is used to contact the chip to be tested to connect the switch circuit to the chip to be tested.

[0015] According to the second aspect of the embodiments of the present application, a chip testing method is provided, which is applied to the chip testing device as described in the aforementioned embodiments, and the chip testing method includes: generating a control signal including a multi-bit command, each bit command in the multi-bit command is used to control a switching circuit; transmitting the control signal to the first controlled port of the switch chip through the first signal output port of the tester to control the conduction of the designated switch circuit in the switch chip; and delivering electric energy to the chip to be tested connected to the designated switch circuit through the power output port of the tester to perform test processing on the chip to be tested.

[0016] According to a third aspect of an embodiment of the present application, a computer-readable medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the chip testing method as described in the above embodiment is implemented.

[0017] According to the fourth aspect of the embodiments of the present application, an electronic device is provided, comprising: one or more processors; a storage device for storing one or more computer programs, wherein when the one or more computer programs are executed by the one or more processors, the electronic device implements the chip testing method as described in the above embodiments.

[0018] According to a fifth aspect of the embodiments of the present application, a computer program product is provided, the computer program product comprising a computer program, the computer program being stored in a computer-readable storage medium. A processor of an electronic device reads and executes the computer program from the computer-readable storage medium, so that the electronic device performs the chip testing method provided in the above-mentioned various optional embodiments.

[0019] In the technical solutions provided in some embodiments of the present application, a plurality of switch circuits are integrated in a switch chip, one end of each switch circuit is connected to a power output port of a test machine, and the other end is used to connect a chip to be tested, and at the same time, a first controlled port of the switch chip is connected to a first signal output port of the test machine, and a control signal output by the first signal output port of the test machine is used to control the conduction of a designated switch circuit in the switch chip, so as to transmit electric energy to the chip to be tested connected to the designated switch circuit through the power output port for testing, so that the switch chip can be used to control the test control of multiple chips to be tested, thereby ensuring a high number of simultaneous tests during chip testing, and at the same time, since the first controlled port of the switch chip is connected to the first signal output port of the test machine to control the control of multiple switch circuits, the test processing of multiple chips to be tested can be achieved by occupying fewer test machine resources (i.e., the signal output port of the test machine).

[0020] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of signal transmission between a test machine and a chip to be tested is shown;

[0022] Figure 2 A schematic diagram showing the principle of a chip testing scenario is shown;

[0023] Figure 3 A schematic diagram of a chip testing scheme is shown;

[0024] Figure 4 Shows Figure 3 A schematic diagram of a switching device used in a chip testing solution shown;

[0025] Figure 5 Shows Figure 3 The signal control flow chart of the chip test scheme shown;

[0026] Figure 6 A structural diagram of a chip testing device according to an embodiment of the present application is shown;

[0027] Figure 7 A cascade structure diagram of a multi-switch chip according to an embodiment of the present application is shown;

[0028] Figure 8 A schematic diagram showing a principle of a chip testing solution according to an embodiment of the present application is shown;

[0029] Fig. 9 A schematic diagram of the structure of a chip testing solution according to an embodiment of the present application is shown;

[0030] Fig.10 A signal control flow chart of a chip testing solution according to an embodiment of the present application is shown;

[0031] Fig.11 A flow chart of a chip testing method according to an embodiment of the present application is shown;

[0032] Fig.12 A schematic diagram of the structure of a computer system suitable for implementing an electronic device of an embodiment of the present application is shown. DETAILED DESCRIPTION

[0033] The exemplary embodiments are now described in a more comprehensive manner with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be understood as being limited to these examples; on the contrary, the purpose of providing these embodiments is to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0034] In addition, the features, structures or characteristics described in the present application may be combined in one or more embodiments in any suitable manner. In the following description, there are many specific details so that the embodiments of the present application can be fully understood. However, those skilled in the art will appreciate that when implementing the technical scheme of the present application, all the detailed features in the embodiments may not be needed, one or more specific details may be omitted, or other methods, elements, devices, steps, etc. may be adopted.

[0035] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0036] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0037] It should be noted that the "multiple" mentioned in this article refers to two or more. "Chip" refers to the general term for semiconductor component products, specifically, electronic components, circuits (especially integrated circuits IC), systems, etc. integrated on the surface of a tiny semiconductor wafer to realize the functions of electronic equipment.

[0038] The embodiments of the present application mainly relate to the testing process of semiconductor chips, and can be specifically applied to the CP testing process or FT testing process of chips. Among them, CP testing refers to the process of connecting the exposed chip pins to the tester through probes on the entire wafer after wafer manufacturing and before packaging to perform chip testing. The main purpose of CP testing is to test the electrical performance parameters of the grains, maintain production quality and pass rate, improve yield, and reduce subsequent packaging and testing costs.

[0039] FT testing refers to the final test performed on the chip after packaging. FT testing is a test of the function and electrical parameter performance of the packaged chip to ensure that the function and performance indicators of each chip leaving the factory can meet the design specification standards.

[0040] When testing the chip, a test machine is needed, such as Figure 1 As shown, the test machine includes a PEM (Pin Electronic Module) board and a PSM (Power Supply Module) board. Among them, the PSM board integrates the PPS (Programmable Power Supply) pin and the GND pin. The PEM board integrates various input and output pins, such as DRV (Driver) pin, IO (Input / Output) pin, MCW (Macro Control Work) pin and High Current DRV pin. The DRV pin is used to generate and output digital signals, the IO pin is used to generate and receive digital signals, the MCW pin can be switched between 0V and 5V states, and the High Current DRV pin is used to provide power and measurement functions. Usually, a PEM board of the test machine contains 128 DRV pins, 160 IO pins, 40 MCW pins and 64 High Current DRV pins.

[0041] When using a tester to test a chip, the tester cannot directly measure the chip; Figure 2 As shown, the probes in the probe card make electrical contact with the pads or bumps on the wafer of the chip to be tested, and then the test signals measured by the probes are sent to the automatic test equipment for analysis and judgment, so as to obtain the test results of the electrical characteristics of each die on the wafer.

[0042] like Figure 3The figure shows a schematic diagram of a chip testing solution. The probe card includes multiple switch devices, each of which corresponds to a device under test (DUT), and each switch device is controlled by an MCW pin on the tester. Figure 4 As shown, MCW1 controls the switch device connected to the chip under test 1, MCW2 controls the switch device connected to the chip under test 2, MCW3 controls the switch device connected to the chip under test 3, and MCW4 controls the switch device connected to the chip under test 4. If the control signal output by a certain MCW pin turns on the switch device, the power supply on the tester will be output to the chip under test, and then the chip under test starts working, so that the test work of various performances of the chip under test can be started.

[0043] exist Figure 3 In the test scheme shown, one MCW pin on the tester controls one switch device, and the multiple chips to be tested share the power output pin of the tester. If there are x chips to be tested and they need to share y pins of the tester (such as power output pins or other pins that need to output corresponding resources during testing), the tester will be required to generate x×y MCW signals. Figure 5 In the example shown, if there are 8 chips to be tested, then 8 MCW pins are required to output control signals respectively.

[0044] In the actual chip testing scenario, the number of chips to be tested is very large. Assuming that 1280 chips need to be tested and these 1280 chips need to share 4 pins of the tester, then 1280×4=5120 MCW signals are required for control. Figure 1 As can be seen from the figure, the number of test machine resources is limited. Each PEM board has only 40 MCW pins, and the current test machine can only install 32 PEM boards at most. Therefore, when the test machine is fully equipped, it only has 1280 MCW pins. Figure 3 The test scheme shown will cause excessive occupation of tester resources when increasing the number of chips tested simultaneously, which will lead to a smaller number of chips tested simultaneously by the tester, thus reducing test efficiency.

[0045] Based on this, the technical solution of the embodiment of the present application proposes a new chip testing solution, which can effectively reduce the occupancy of tester resources while ensuring a high number of simultaneous tests during chip testing, thereby improving the efficiency of chip testing.

[0046] The implementation details of the technical solution of the embodiment of the present application are described in detail below:

[0047] Reference Figure 6 As shown, a chip testing device according to an embodiment of the present application includes a tester 601 and a switch chip 602. The tester 601 includes a power output port and a first signal output port; the switch chip 602 includes a first controlled port, which can be Figure 6 The SDI (Serial Data Input) port shown in .

[0048] The switch chip 602 integrates multiple switch circuits ( Figure 6 In the example, the switch chip 602 integrates 8 switch circuits. In other embodiments of the present application, the switch chip 602 may integrate more switch circuits. Figure 6 The S end shown in FIG. 1 is connected to the power output port of the test machine 601, and the other end (i.e. Figure 6 The D end shown in FIG. 6 is used to connect the chip to be tested. The first controlled port of the switch chip 602 is connected to the first signal output port of the test machine 601. The control signal output by the first signal output port of the test machine 601 is used to control the designated switch circuit in the switch chip 602 to be turned on, so as to transmit electric energy to the chip to be tested connected to the designated switch circuit through the power output port for testing. For example, if the switch circuit between S1 and D1 is controlled to be turned on, the power output port will transmit electric energy to the chip to be tested connected to the switch circuit, and then the chip to be tested will start working, so that the test work of various performances of the chip to be tested can be started.

[0049] It should be noted that the designated switch circuit may be one switch circuit in the switch chip 602 or multiple switch circuits, that is, the switch circuits in the switch chip 602 may conduct 0, 1, multiple or all of them at the same time. The multi-way switch circuit integrated in the switch chip 602 may be as follows: Figure 6 As shown, they are connected to the same power output port on the test machine 601, which can save excessive occupation of the test machine port. Of course, in other embodiments of the present application, if the power output ports of the test machine are relatively idle, then the multiple switch circuits integrated in the switch chip 602 can also be connected to different power output ports.

[0050] exist Figure 6 In the chip testing device shown, the test control of multiple chips to be tested is realized by using the switch chip 602, which ensures a high number of simultaneous tests during chip testing. At the same time, since the first controlled port of the switch chip 602 is connected to the first signal output port of the tester to realize the control of multiple switch circuits, the occupancy of the tester resources (i.e., the signal output port of the tester) can be reduced, thereby improving the efficiency of chip testing.

[0051] In some optional embodiments, continue to refer to Figure 6 As shown, the test machine 601 may further include a second signal output port, and the switch chip 602 may further include a second controlled port, which may be Figure 6 The second controlled port of the switch chip 602 can be connected to the second signal output port of the test machine 601, and the second signal output port of the test machine 601 can transmit a clock signal to the second controlled port of the switch chip 602.

[0052] In some optional embodiments, continue to refer to Figure 6 As shown, the test machine 601 may further include a third signal output port, and the switch chip 602 may further include a third controlled port, which may be Figure 6 The CS port shown in . And the third controlled port of the switch chip 602 can be connected to the third signal output port of the test machine 601, and then the third signal output port of the test machine 601 can transmit an enable signal to the third controlled port of the switch chip 602. The switch chip 602 works only during the effective period of the enable signal (for example, it can be set to be effective at a low level).

[0053] In some optional embodiments, continue to refer to Figure 6 As shown, the test machine 601 may further include a fourth signal output port, and the switch chip 602 may further include a fourth controlled port. The fourth controlled port may be Figure 6 The V L And the fourth controlled port of the switch chip 602 can be connected to the fourth signal output port of the test machine 601, and then the fourth signal output port of the test machine 601 can transmit a reset signal to the fourth controlled port of the switch chip 602, and the reset signal is used to perform a hardware reset process on the switch chip 602. After the switch chip 602 performs the hardware reset process, all switch circuits can be in a disconnected state.

[0054] In some optional embodiments, such as Figure 6 As shown, the switch chip 602 includes a SPI (Serial Peripheral Interface), and the SPI interface can provide the aforementioned various controlled ports to be connected to the corresponding ports of the test machine 601 .

[0055] In some optional embodiments, the switch chip 602 may also include a data output port, which may be Figure 6The SDO (Serial Data Output) port shown in . The data output port is used to output a synchronization signal obtained by shifting the control signal input to the first controlled port of the switch chip 602. Specifically, the switch chip 602 can shift the control signal input to the first controlled port (i.e., the SDI port), and then output the synchronization signal obtained after the shift processing through the data output port (i.e., the SDO port), and the shift processing can be performed by 8 bits or 16 bits, etc.

[0056] Based on the technical solutions of the aforementioned embodiments, in some optional embodiments of the present application, the data output port of the switch chip 602 can be used to realize the cascade connection of multiple switch chips, thereby achieving the purpose of using fewer tester resources to test more chips. Specifically, the first controlled port of the first-stage switch chip among the multiple switch chips is connected to the first signal output port of the tester 601 (for example, Figure 6 The switch chip 602 shown is used as the first-stage switch chip), and the first controlled ports (i.e., SDI ports) of the other switch chips among the plurality of switch chips except the first-stage switch chip are connected to the data output port (i.e., SDO port) of the previous-stage switch chip. Figure 7 , two switch chips 602a and 602b are taken as an example for explanation.

[0057] like Figure 7 As shown, the switch chip 602a is the first-stage switch chip, and the switch chip 602b is the second-stage switch chip. Then, the connection method between the switch chip 602a and the tester 601 is as shown in FIG. Figure 6 As shown, the first controlled port (ie, SDI port) of the switch chip 602a is connected to the first signal output port (ie, Figure 7 The second controlled port (ie, CLK port) of the switch chip 602a is connected to the second signal output port (ie, DRV1) of the test machine 601. Figure 7 The third controlled port (ie, CS port) of the switch chip 602a is connected to the third signal output port (ie, DRV2) of the test machine 601. Figure 7 CS in the figure) is connected to the fourth controlled port of the switch chip 602a (i.e., V L port) and the fourth signal output port ( Figure 7 V L to indicate) connected.

[0058] Since the switch chip 602b is a second-stage switch chip, the first controlled port (i.e., SDI port) of the switch chip 602b is connected to the data output port (i.e., SDO port) of the first-stage switch chip (i.e., switch chip 602a). In this case, since the signal output by the SDO port of the switch chip 602a is a synchronous signal after the control signal input by the SDI port of the switch chip 602a is shifted, the switch chip 602b can also control the switch circuit included in the switch chip 602b according to the synchronous signal after the shifting process, thereby controlling the corresponding chip to be tested.

[0059] In some optional embodiments, if the chip testing device includes multiple switch chips, the second controlled ports (i.e., CLK ports) of the multiple switch chips can be connected to the same second signal output port of the tester 601, and then the second signal output port of the tester 601 can simultaneously transmit clock signals to the second controlled ports of the multiple switch chips, which can reduce the occupation of the tester resources. Figure 7 As shown, the CLK ports of the switch chip 602a and the switch chip 602b are connected to each other and then connected to a port of the test machine ( Figure 7 DRV2 is used in the representation).

[0060] In some optional embodiments, if the chip testing device includes multiple switch chips, the third controlled ports (i.e., CS ports) of the multiple switch chips can be connected to the same third signal output port of the tester 601, and then the third signal output port of the tester 601 can simultaneously transmit an enable signal to the third controlled ports of the multiple switch chips, which can reduce the occupation of the tester resources. Figure 7 As shown, the CS ports of the switch chip 602a and the switch chip 602b are connected to each other and then connected to a port of the test machine ( Figure 7 CS in the text).

[0061] In some optional embodiments, if the chip testing device includes a plurality of switch chips, the fourth controlled ports (ie, V L The fourth signal output port of the test machine 601 can be connected to the same fourth signal output port of the test machine 601, and then the fourth signal output port of the test machine 601 can simultaneously transmit a reset signal to the fourth controlled ports of the multiple switch chips, which can reduce the occupation of the test machine resources. Figure 7 As shown, the V of the switch chip 602a and the switch chip 602b L port, and then connect to a port on the test machine ( Figure 7 V L to indicate).

[0062] In some optional embodiments, if the chip testing device includes a plurality of switch chips, the multi-way switch circuit integrated in each switch chip can be as follows: Figure 6 As shown, the power supply output port of the tester 601 is connected to the same power supply output port of the tester 601, which can save excessive occupation of the tester port, and the power supply output ports connected to the switch circuits integrated in different switch chips can be different, so that different power supply output ports of the tester 601 can be connected to different switch chips. Of course, in other embodiments of the present application, if the power supply output ports of the tester are relatively idle, then multiple switch circuits integrated in the switch chip can also be connected to different power supply output ports.

[0063] In one embodiment of the present application, if the chip testing device includes a plurality of switch chips, then the plurality of switch chips may not be used. Figure 7 Instead of connecting them in a cascaded manner as shown, they can be connected as separate entities and in a similar way Figure 6 In this case, the multiple switch chips are independent of each other, and the tester can control the multiple switch chips separately. The technical solution of this embodiment can also reduce the occupation of the tester resources (i.e., the signal output port of the tester) while ensuring a high number of simultaneous tests during chip testing, thereby improving the efficiency of chip testing.

[0064] In some optional embodiments, the switch chip in the present application can be arranged in Figure 2 On the probe card shown, the probe card is set on the head of the test machine. After the probe card contacts the chip to be tested, the switch circuit in the switch chip can be connected to the chip to be tested, and then the control method in the aforementioned embodiment can be used to control the switch circuit, thereby realizing the test processing of the chip to be tested.

[0065] In order to further highlight the advantages of the technical solutions of the embodiments of the present application, Figure 3 The technical solution of the embodiment shown is used as a comparison. Figures 8 to 10 The technical solution of the preferred embodiment of the present application is described again:

[0066] like Figure 8 As shown, the probe card includes multiple switch chips, which can be used Figure 7The cascade mode shown is connected, each switch chip contains multiple switch circuits, and each switch circuit is connected to a chip to be tested, so that each switch chip corresponds to a chip set to be tested. Two signal output ports (i.e., DRV1 and DRV2) can be used in the tester to provide clock signals and control signals to the first-level switch chip, so that the first-level switch chip can shift the control signal and output it to the second-level switch chip, and the second-level switch chip will shift the received signal again and output it to the third-level switch chip, and so on, so that the control of multiple switch chips can be achieved through a small amount of tester resources (i.e., signal output ports), and each switch chip is connected to multiple chips to be tested, so the test control of multiple chips can be achieved.

[0067] Specific as Fig. 9 As shown, five switch chips (i.e., switch chip 902, switch chip 903, switch chip 904, switch chip 905, and switch chip 906) are used as an example for explanation. Among them, switch chip 902 is a first-level switch chip, switch chip 903 is a second-level switch chip, switch chip 904 is a third-level switch chip, switch chip 905 is a fourth-level switch chip, and switch chip 906 is a fifth-level switch chip. Then the connection method between switch chip 902 and test machine 901 is that the SDI port of switch chip 902 is connected to the first signal output port ( Fig. 9 The CLK port of the switch chip 902 is connected to the second signal output port ( Fig. 9 The CS port of the switch chip 902 is connected to the third signal output port ( Fig. 9 At the same time, one end of each switch circuit included in the switch chip 902 is connected to the power output port ( Fig. 9 The other end is connected to a chip to be tested.

[0068] It should be noted that Fig. 9 Other controlled ports of the switch chip, such as V L For the connection mode of the port not shown, the technical solution of the above embodiment can be referred to, or it can be set according to actual needs, for example, the V L The port is connected to a signal output port of the test machine 901.

[0069] Fig. 9The switch chip 903 shown in the figure is a second-stage switch chip, so the SDI port of the switch chip 903 is connected to the SDO port of the first-stage switch chip (i.e., the switch chip 902). In this case, since the signal output by the SDO port of the switch chip 902 is a synchronous signal after the control signal input by the SDI port of the switch chip 902 is shifted, the switch chip 903 can also control the switch circuit included in the switch chip 903 according to the synchronous signal after the shifting process, thereby controlling the corresponding chip to be tested.

[0070] Fig. 9 The switch chip 904 shown in the figure is a third-stage switch chip, so the SDI port of the switch chip 904 is connected to the SDO port of the second-stage switch chip (i.e., the switch chip 903). In this case, since the signal output by the SDO port of the switch chip 903 is a synchronous signal after the control signal input by the SDI port of the switch chip 903 is shifted, the switch chip 904 can also control the switch circuit included in the switch chip 904 according to the synchronous signal after the shifting process, and then control the corresponding chip to be tested.

[0071] Fig. 9 The switch chip 905 shown in the figure is a fourth-level switch chip, so the SDI port of the switch chip 905 is connected to the SDO port of the third-level switch chip (i.e., the switch chip 904). In this case, since the signal output by the SDO port of the switch chip 904 is a synchronous signal after the control signal input by the SDI port of the switch chip 904 is shifted, the switch chip 905 can also control the switch circuit included in the switch chip 905 according to the synchronous signal after the shifting process, and then control the corresponding chip to be tested.

[0072] Fig. 9 The switch chip 906 shown in the figure is a fifth-stage switch chip, so the SDI port of the switch chip 906 is connected to the SDO port of the fourth-stage switch chip (i.e., the switch chip 905). In this case, since the signal output by the SDO port of the switch chip 905 is a synchronous signal after the control signal input by the SDI port of the switch chip 905 is shifted, the switch chip 906 can also control the switch circuit included in the switch chip 906 according to the synchronous signal after the shifting process, thereby controlling the corresponding chip to be tested.

[0073] At the same time, Fig. 9 In the embodiment shown, the CLK ports of the five switch chips can be connected and then connected to a port of the test machine ( Fig. 9The CS ports of the five switch chips can be connected and then connected to a port of the test machine ( Fig. 9 In addition, the switch circuits integrated in the five switch chips may be connected to different power output ports of the test machine, for example Fig. 9 The power output port connected to the switch circuit integrated in the switch chip 902 is PPS1, the power output port connected to the switch circuit integrated in the switch chip 903 is PPS2, the power output port connected to the switch circuit integrated in the switch chip 904 is PPS3, the power output port connected to the switch circuit integrated in the switch chip 905 is PPS4, and the power output port connected to the switch circuit integrated in the switch chip 906 is PPS5.

[0074] exist Figure 8 and Fig. 9 In the test scheme shown, multiple switch chips are connected in cascade mode, each switch chip contains multiple switch circuits, and each switch chip corresponds to a set of chips to be tested. If 5 switch chips are used, and each switch chip contains 8 switch circuits, 5×8=40 chips can be tested and controlled through the two DRV ports of the tester. If 8 chips to be tested are tested, then Fig.10 As shown, without considering the power output port, only the two DRV ports of the test machine are needed to output the clock signal and the control signal. Figure 3 The technical solution shown effectively reduces the occupancy of the test machine resources.

[0075] It can be seen that the chip testing scheme proposed in the above embodiment of the present application can reduce the occupation of the tester resources (i.e., the signal output port of the tester) while ensuring a high number of simultaneous tests during chip testing, thereby improving the efficiency of chip testing. And because the switch chip can be controlled using serial signals, compared to using parallel signals, a large number of control signal routings in the probe card can be reduced, thereby reducing the degree of signal crosstalk, shortening the design cycle of the probe card, and reducing the development cost of the probe card.

[0076] based on Figures 6 to 10 In the embodiment shown in the present application, a chip testing method is also proposed in the embodiment, referring to Fig.11 As shown, the chip testing method at least includes the following steps S1110 to S1130:

[0077] S1110, generating a control signal including a multi-bit command, where each bit command in the multi-bit command is used to control a switch circuit.

[0078] It should be noted that the number of bit commands in the control signal is consistent with the number of switch circuits included in the switch chip. For example, if the switch chip contains 8 switch circuits, then the control signal contains 8-bit commands, and each bit command is used to control one switch circuit.

[0079] S1120, transmitting a control signal to a first controlled port of the switch chip through a first signal output port of the tester, so as to control a designated switch circuit in the switch chip to be turned on.

[0080] Optionally, the command in the control signal may be to control the switch circuit to be turned on when the level is high, and to control the switch circuit to be turned off when the level is low; conversely, the command in the control signal may be to control the switch circuit to be turned on when the level is low, and to control the switch circuit to be turned off when the level is high.

[0081] S1130, delivering electric energy to the chip to be tested connected to the designated switch circuit through the power output port of the tester, so as to perform testing on the chip to be tested.

[0082] Optionally, when the chip to be tested is tested, either a CP test or a FT test may be performed.

[0083] Fig.11 The implementation details of the connection relationship and control method between the switch chip and the tester in the chip testing method shown in the figure can refer to the technical scheme of the aforementioned embodiment and will not be repeated here.

[0084] Fig.12 A schematic diagram of the structure of a computer system of an electronic device suitable for implementing an embodiment of the present application is shown. The electronic device may be the test machine in the aforementioned embodiment or a control device corresponding to the test machine.

[0085] It should be noted that Fig.12 The computer system 1200 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0086] like Fig.12As shown, the computer system 1200 may include a central processing unit (CPU) 1201, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1202 or the program loaded from the storage part 1208 to the random access memory (RAM) 1203, such as executing the method described in the above embodiment. In the RAM 1203, various programs and data required for system operation are also stored. The CPU 1201, ROM 1202 and RAM 1203 are connected to each other through a bus 1204. An input / output (I / O) interface 1205 is also connected to the bus 1204.

[0087] The following components can be connected to the I / O interface 1205: an input section 1206 including a keyboard, a mouse, etc.; an output section 1207 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1208 including a hard disk, etc.; and a communication section 1209 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 1209 performs communication processing via a network such as the Internet. A drive 1210 is also connected to the I / O interface 1205 as needed. A removable medium 1211, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1210 as needed so that a computer program read therefrom is installed into the storage section 1208 as needed.

[0088] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program is used to perform the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication section 1209, and / or installed from a removable medium 1211. When the computer program is executed by a central processing unit (CPU) 1201, various functions defined in the system of the present application are executed.

[0089] It should be noted that the computer-readable medium shown in the embodiment of the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a computer program, which may be used by an instruction execution system, device or device or used in combination with it. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, wherein a computer-readable computer program is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which may send, propagate, or transmit programs for use by or in conjunction with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0090] The flowchart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present application. Wherein, each box in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of the boxes in the block diagram or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and a computer program.

[0091] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. The names of these units do not, in some cases, constitute limitations on the units themselves.

[0092] As another aspect, the present application also provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable medium carries one or more computer programs, and when the above one or more computer programs are executed by an electronic device, the electronic device implements the method described in the above embodiment.

[0093] It should be noted that, although several modules or units of the equipment for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into being embodied by multiple modules or units.

[0094] Through the description of the above implementation methods, it is easy for those skilled in the art to understand that the example implementation methods described here can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the implementation methods of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable an electronic device to execute the method according to the implementation methods of the present application.

[0095] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the embodiments disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary technical means in the art that are not disclosed in the present application.

[0096] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A chip testing device, characterized in that: include: A testing machine, the testing machine comprising a power output port and a first signal output port; A switch chip, wherein a plurality of switch circuits are integrated in the switch chip, one end of each switch circuit is connected to the power output port, and the other end is used to connect to the chip to be tested; Among them, the switch chip includes a first controlled port, the first controlled port is connected to the first signal output port of the test machine, and the control signal output by the first signal output port is used to control the conduction of the designated switch circuit in the switch chip, so as to transmit electric energy to the chip to be tested connected to the designated switch circuit through the power output port for testing processing.

2. The chip testing device according to claim 1, characterized in that: The switch chip further comprises a second controlled port, and the test machine further comprises a second signal output port; The second controlled port of the switch chip is connected to the second signal output port of the tester, and the second signal output port of the tester is used to transmit a clock signal to the second controlled port of the switch chip.

3. The chip testing device according to claim 1, characterized in that: The multi-way switch circuit integrated in the switch chip is connected to the same power output port on the tester.

4. The chip testing device according to claim 1, characterized in that: The switch chip further comprises a data output port, wherein the data output port is used to output a synchronization signal obtained by shifting the control signal inputted from the first controlled port; The chip testing device includes multiple switch chips, which are connected in a cascade mode; wherein the first controlled port of the first-stage switch chip among the multiple switch chips is connected to the first signal output port of the tester, and the first controlled ports of other switch chips among the multiple switch chips except the first-stage switch chip are connected to the data output port of the previous-stage switch chip.

5. The chip testing device according to claim 4, characterized in that: The switch chip further comprises a second controlled port, and the test machine further comprises a second signal output port; The second controlled ports of the plurality of switch chips are connected to the same second signal output port of the tester, and the second signal output port is used to transmit a clock signal to the second controlled ports of the plurality of switch chips.

6. The chip testing device according to claim 4, characterized in that: The multi-way switch circuits integrated in each of the switch chips are connected to the same power output port on the tester, and the switch circuits integrated in different switch chips are connected to different power output ports.

7. The chip testing device according to claim 4, characterized in that: The test machine further comprises a third signal output port, and the switch chip further comprises a third controlled port; The third controlled ports of the multiple switch chips are connected to the same third signal output port of the tester, and the third signal output port of the tester is used to transmit an enable signal to the third controlled ports of the multiple switch chips.

8. The chip testing device according to claim 4, characterized in that: The test machine further comprises a fourth signal output port, and the switch chip further comprises a fourth controlled port; The fourth controlled ports of the multiple switch chips are connected to the same fourth signal output port of the tester, and the fourth signal output port of the tester is used to transmit a reset signal to the fourth controlled ports of the multiple switch chips.

9. The chip testing device according to claim 1, characterized in that: The chip testing device includes a plurality of switch chips, and the first controlled ports of the plurality of switch chips are respectively connected to different first signal output ports on the tester to respectively receive control signals output by the corresponding first signal output ports.

10. The chip testing device according to any one of claims 1 to 9, characterized in that: The switch chip is arranged on a probe card, and the probe card is arranged on a head of the tester. The probe card is used to make contact with the chip to be tested so as to connect the switch circuit to the chip to be tested.

11. A chip testing method, applied to the chip testing device according to any one of claims 1 to 10, characterized in that: The chip testing method comprises: Generate a control signal including a multi-bit command, wherein each bit command in the multi-bit command is used to control a switch circuit; Transmitting the control signal to the first controlled port of the switch chip through the first signal output port of the tester to control the conduction of a designated switch circuit in the switch chip; Power is transmitted to the chip to be tested connected to the designated switch circuit through the power output port of the test machine, so as to perform a test process on the chip to be tested.

12. A computer readable medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the chip testing method according to claim 11 is implemented.

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