Test circuit board and construction system and construction method of chip simulation model

Abstract

The embodiment of the invention discloses a test circuit board and a construction system and method for a chip simulation model, and the method comprises the steps: placing a target chip through a test auxiliary module, testing the test auxiliary module where the target chip is placed through a test device, and carrying out the testing of the test auxiliary module where the target chip is placed. Generating a test waveform file and actual measurement eye pattern data, importing the test waveform file into a simulation module, and performing eye pattern simulation processing based on the test waveform file through the simulation module to obtain simulation eye pattern data corresponding to the target chip, and performing fitting processing on the basis of the simulation eye pattern data and the actual measurement eye pattern data to obtain a chip simulation model, so that the chip simulation model capable of replacing an IBIS model is constructed, and input / output characteristics of a chip are accurately described by utilizing the chip simulation model in circuit design and simulation. Therefore, the effect of improving the simulation accuracy of the chip signal is achieved.

Description

Technical Field

[0001] The present application relates to the field of circuit simulation technology, and in particular to a system and method for constructing a test circuit board and a chip simulation model. Background Art

[0002] In the related art, the Input / Output Buffer Information Specification (IBIS) model is mainly used to describe the electrical characteristics of the input / output interface in the digital circuit. These digital circuits can be various types of integrated circuits (ICs), such as microprocessors, microcontrollers, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), etc. The above ICs (also called chips) are often part of computers or other electronic devices. Therefore, the IBIS model of the chip is a crucial technical data in electronic design. Summary of the invention

[0003] The embodiment of the present application provides a system and method for constructing a test circuit board and a chip simulation model. The technical solution is as follows:

[0004] In a first aspect, an embodiment of the present application provides a test circuit board, comprising a chip mounting component, a signal transmission line, and a connection component, wherein the chip mounting component is connected to the connection component through the signal transmission line; wherein:

[0005] The chip mounting assembly is used to place the target chip;

[0006] The connection component is used to connect to a test device to assist the test device in testing the target chip.

[0007] In combination with the first aspect, in some possible implementations, the length of the signal transmission line is less than or equal to a preset length threshold.

[0008] In a second aspect, an embodiment of the present application provides a system for constructing a chip simulation model, including a test auxiliary module, a test device, and a simulation module; wherein:

[0009] The test auxiliary module is used to place the target chip and connect with the test equipment to assist the test equipment in testing the target chip to generate a test waveform file and measured eye diagram data;

[0010] The simulation module is used to obtain the test waveform file and the measured eye diagram data, perform eye diagram simulation processing based on the test waveform file to obtain the simulated eye diagram data corresponding to the target chip, and perform fitting processing based on the simulated eye diagram data and the measured eye diagram data to obtain a chip simulation model.

[0011] In conjunction with the second aspect, in some possible implementations, the test auxiliary module is a test circuit board, the test circuit board includes a chip mounting component, a signal transmission line, and a connection component, the chip mounting component is connected to the connection component through the signal transmission line; wherein the chip mounting component is used to place the target chip; the connection component is used to connect the test equipment to assist the test equipment in testing the target chip;

[0012] The testing device is an oscilloscope.

[0013] In a third aspect, an embodiment of the present application provides a method for constructing a chip simulation model, which is applied to the construction system described in the second aspect above, and the method includes:

[0014] Place the target chip through the test auxiliary module;

[0015] Testing the test auxiliary module on which the target chip is placed by means of a test device to generate a test waveform file and measured eye diagram data;

[0016] Importing the test waveform file into a simulation module;

[0017] The simulation module performs eye diagram simulation processing based on the test waveform file to obtain simulated eye diagram data corresponding to the target chip, and performs fitting processing based on the simulated eye diagram data and the measured eye diagram data to obtain a chip simulation model.

[0018] In conjunction with the third aspect, in some possible implementations, the obtaining of a chip simulation model by performing fitting processing based on the simulated eye diagram data and the measured eye diagram data includes:

[0019] Debug simulation debugging parameters with reference to the measured eye diagram data, determine the debugged simulated eye diagram data, compare the measured eye diagram data with the debugged simulated eye diagram data to obtain eye width error and eye height error, and obtain a chip simulation model when the eye width error is less than or equal to a first threshold and the eye height error is less than or equal to a second threshold.

[0020] In combination with the third aspect, in some possible implementations, the chip simulation model includes target parameter values ​​corresponding to the simulation debugging parameters and the test waveform file.

[0021] In combination with the third aspect and the above-mentioned implementation manner, in some possible implementation manners, the simulation debugging parameters include at least one of a signal generation rate, a number of signal bits, and a convergence factor.

[0022] In combination with the third aspect and the above-mentioned embodiments, in certain possible implementations, the test waveform file includes the signal transmission time of the target chip and voltage data corresponding to the signal transmission time.

[0023] In combination with the third aspect and the above-mentioned embodiments, in some possible implementations, the signal transmitted by the target chip is a differential signal or a single-ended signal.

[0024] In a fourth aspect, an embodiment of the present application provides a computer storage medium, which has a plurality of instructions, and the instructions are suitable for being loaded by a processor and executing some or all of the above-mentioned method steps.

[0025] In a fifth aspect, an embodiment of the present application provides an electronic device, which may include: a memory and a processor; wherein the memory stores a computer program, and the computer program is suitable for being loaded by the memory and executing some or all of the above-mentioned method steps.

[0026] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:

[0027] In the test circuit board provided in the embodiment of the present application, the chip mounting assembly can be used to place the target chip, the signal transmission line can be used to connect the chip mounting assembly and the connection assembly, and the connection assembly can be used to connect the test equipment to assist the test equipment in testing the target chip. Thus, by designing a circuit board with a simple structure to assist the test equipment in testing the target chip, the design of the test circuit board can be changed as the type of the target chip changes. Therefore, in practical applications, a test circuit board that is used in conjunction with the test equipment and the target chip can be flexibly designed.

[0028] In the chip simulation model construction system provided in the embodiment of the present application, the test auxiliary module can be used to place the target chip and connect with the test equipment to assist the test equipment in testing the target chip to generate a test waveform file and measured eye diagram data, and the simulation module can be used to obtain the test waveform file and the measured eye diagram data, perform eye diagram simulation processing based on the test waveform file to obtain the simulated eye diagram data corresponding to the target chip, and perform fitting processing based on the simulated eye diagram data and the measured eye diagram data to obtain the chip simulation model. Thus, the test waveform file corresponding to the target chip is simulated and fitted by the test circuit board and the test equipment auxiliary simulation module to obtain the chip simulation model, thereby realizing the construction of a chip simulation model that can replace the IBIS model, so as to use the chip simulation model to accurately describe the input / output characteristics of the chip in circuit design and simulation, thereby achieving the effect of improving the accuracy of chip signal simulation.

[0029] In the construction method of the chip simulation model provided in the embodiment of the present application, first, the target chip is placed through the test auxiliary module, and then, the test auxiliary module with the target chip placed is tested by the test equipment to generate a test waveform file and measured eye diagram data, and then, the test waveform file is imported into the simulation module, and then the simulation module performs eye diagram simulation processing based on the test waveform file to obtain the simulated eye diagram data corresponding to the target chip, and performs fitting processing based on the simulated eye diagram data and the measured eye diagram data to obtain the chip simulation model. Thus, the test waveform file corresponding to the target chip is simulated and fitted by the test circuit board and the test equipment auxiliary simulation module to obtain the chip simulation model, thereby realizing the construction of a chip simulation model that can replace the IBIS model, so as to use the chip simulation model to accurately describe the input / output characteristics of the chip in circuit design and simulation, thereby achieving the effect of improving the accuracy of chip signal simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 It is a structural schematic diagram of a test circuit board provided in an embodiment of the present application;

[0032] Figure 2 is a structural schematic diagram of another test circuit board provided in an embodiment of the present application;

[0033] Figure 3 is a schematic diagram of a chip simulation model construction system provided in an embodiment of the present application;

[0034] Figure 4 It is a flowchart of a method for constructing a chip simulation model provided in an embodiment of the present application;

[0035] Figure 5 is a schematic diagram of a simulated eye diagram provided in an embodiment of the present application;

[0036] Figure 6 It is a flowchart of a chip simulation model determination method provided in an embodiment of the present application;

[0037] Figure 7 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the purpose, features, and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0039] In the description of the present application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In the description of the present application, it should be noted that, unless otherwise clearly specified and limited, "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood in specific circumstances. In addition, in the description of the present application, unless otherwise specified, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B, which can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are an "or" relationship.

[0040] In the related art, the IBIS model of the chip is a crucial technical data in electronic design. For example, in high-speed signal design, the IBIS model is the basic technical data for signal integrity simulation. The purpose of signal integrity simulation is to determine through simulation whether the signal waveform emitted from the transmitting end meets the requirements of the receiving chip for the signal waveform when it reaches the receiving end after passing through physical channels such as PCB traces, vias, connectors, etc. that will attenuate the signal. However, many chip manufacturers are unable to provide the IBIS model of the chip, and the IBIS model is difficult to obtain or difficult to make. In order to replace the IBIS model, signal integrity simulation personnel choose to use the ideal model that comes with the simulation software to replace the IBIS model. However, using the ideal model that comes with the simulation software to replace the IBIS model has the problem of low simulation accuracy. Therefore, how to ensure the accuracy of chips that are difficult to obtain or make IBIS models in circuit simulation is a technical problem that needs to be solved urgently.

[0041] In order to solve the above technical problems, the present application is described in detail below in conjunction with specific embodiments.

[0042] See also Figure 1 , is a structural schematic diagram of a test circuit board provided in an embodiment of the present application.

[0043] like Figure 1 As shown, the test circuit board 1 includes a chip mounting component 12 , a signal transmission line 14 and a connection component 16 . The chip mounting component 12 is connected to the signal transmission line 14 , and the signal transmission line 14 is connected to the connection component 16 .

[0044] Specifically, the chip mounting assembly 12 can be used to place the target chip. The connecting assembly 16 can be used to connect the test equipment to assist the test equipment in testing the target chip.

[0045] In an embodiment of the present application, a test circuit board is a circuit board used to test the performance of a circuit or a device.

[0046] The target chip may be a chip that can generate high-speed signals. For example, the target chip may be a Serdes chip. High-speed signals may include display port (DisplayPort, referred to as DP) signals, high-definition multimedia interface (High Definition Multimedia Interface, referred to as HDMI) signals, peripheral component interconnect express (Peripheral Component Interconnect Express, referred to as PCIE) signals and other high-speed signals. The signal output by the target chip may be a differential signal or a single-ended signal.

[0047] Test equipment refers to an electronic measuring instrument that can graphically display the pattern of signal voltage changes over time. For example, a test device can be an oscilloscope.

[0048] Exemplarily, the test equipment tests the target chip and can generate a test waveform file and measured eye diagram data. Then the simulation module can obtain the test waveform file and the measured eye diagram data, perform eye diagram simulation processing based on the test waveform file to obtain the simulated eye diagram data corresponding to the target chip, and perform fitting processing based on the simulated eye diagram data and the measured eye diagram data to obtain the chip simulation model.

[0049] For example, see Figure 2 Another structural diagram of a test circuit board is shown below. Figure 2 The specific structure of the chip mounting component and the structure of the connection component are described in detail.

[0050] In some embodiments, Figure 2 As shown, the chip mounting component 12 may include a chip mounting unit 122, a chip power supply unit 124, and a chip peripheral unit 126. The chip mounting unit 122 is connected to the chip power supply unit 124, the chip mounting unit 122 is connected to the chip peripheral unit 126, the chip power supply unit 124 is connected to the chip peripheral unit 126, and the chip mounting unit 122 is connected to the signal transmission line 14; the connection component 16 may include a test point unit 162, and the test point unit 162 is connected to the signal transmission line 14.

[0051] Specifically, the chip installation unit can be used to place the target chip, the chip power supply unit can be used to supply power to the target chip, the chip power supply unit can specifically include devices such as a power supply and an adapter, and the chip peripheral unit can include peripheral capacitors and / or peripheral resistors corresponding to the target chip, and the peripheral capacitors or peripheral resistors can cooperate with the target chip to put the target chip in normal working state.

[0052] Specifically, the test point unit is used to connect the test equipment, and the specific design of the test point unit may be a via or a pad.

[0053] In some embodiments, the length of the signal transmission line can be understood as the length of the transmission line required from the position for placing the output pin of the target chip in the chip mounting assembly to the position where the test point unit in the connection assembly is located. The length of the signal transmission line can be configured to be less than or equal to a preset length threshold. For example, the preset length threshold can be configured to be 500 milli-inches. For example, in an embodiment of the present application, the length of the signal transmission line can be configured to be 370 milli-inches. Thus, by limiting the length of the signal transmission line, the test results obtained by the test equipment during the test process can be closer to the test results obtained by the test equipment when testing at the location of the output pin of the target chip.

[0054] In some embodiments, the signal transmission line can adopt different designs according to the chips of different signal types, such as differential design or single-ended design. The differential design refers to the design using two signal transmission lines, and the single-ended design refers to the design using a single signal transmission line. For example, for chips that can generate signal types such as DP, HDMI, and PCIE, a differential design is adopted for the signal transmission line in the test circuit board; for chips that can generate signal types such as Serial Peripheral Interface (SPI) signals and IIC (Inter-Integrated Circuit, IIC), a single-ended design is adopted for the signal transmission line in the test circuit board.

[0055] Optionally, the connection between the connection component and the test equipment can be welded, and the probe of the test equipment can be welded to the connection component, so that the test process of the test equipment on the target chip remains stable.

[0056] Optionally, the impedance configuration in the test circuit board can be set according to different signal protocol requirements. For example, for a test circuit board with a differential design of the signal transmission line, the value of the via impedance can be configured to be 100Ω, 92Ω, 85Ω, etc. For a test circuit board with a single-ended design of the signal transmission line, the value of the via impedance can be configured to be 50Ω, 45Ω, 40Ω, etc.

[0057] In the test circuit board provided in the embodiment of the present application, the chip mounting assembly can be used to place the target chip, the signal transmission line can be used to connect the chip mounting assembly and the connection assembly, and the connection assembly can be used to connect the test equipment to assist the test equipment in testing the target chip. Thus, by designing a circuit board with a simple structure to assist the test equipment in testing the target chip, the design of the test circuit board can be changed as the type of the target chip changes. Therefore, in practical applications, a test circuit board that is used in conjunction with the test equipment and the target chip can be flexibly designed.

[0058] See also Figure 3 , is a schematic diagram of a chip simulation model construction system provided in an embodiment of the present application. Figure 3 As shown, the chip simulation model construction system may include a test auxiliary module 32 , a test device 34 , and a simulation module 36 .

[0059] In some embodiments, the test auxiliary module can be used to place the target chip and connect to the test equipment to assist the test equipment in testing the target chip to generate a test waveform file and measured eye diagram data. The simulation module can be used to obtain the test waveform file and the measured eye diagram data, perform eye diagram simulation processing based on the test waveform file to obtain the simulated eye diagram data corresponding to the target chip, and perform fitting processing based on the simulated eye diagram data and the measured eye diagram data to obtain a chip simulation model.

[0060] Optionally, the test auxiliary module can be connected to the test device by welding. The test device and the simulation module can be connected by wired connection or wireless connection.

[0061] In some embodiments, the test auxiliary module can be a test circuit board. The structure and function of the test circuit board, the implementation method of placing the target chip using the test circuit board, and the connection implementation method of the test circuit board and the test equipment can be specifically referred to in Figure 1-2 The description of the relevant parts of the illustrated embodiment will not be repeated here. The test device refers to an electronic measuring instrument that can graphically display the law of signal voltage changing over time. For example, the test device can be an oscilloscope. The simulation module can be implemented as all or part of the module through software, hardware, or a combination of both. Optionally, the simulation module can be a part of an electronic device, and the electronic device can be a computer device such as a desktop computer, a portable computer, etc. that can run simulation software.

[0062] In the chip simulation model construction system provided in the embodiment of the present application, the test auxiliary module can be used to place the target chip and connect with the test equipment to assist the test equipment in testing the target chip to generate a test waveform file and measured eye diagram data, and the simulation module can be used to obtain the test waveform file and the measured eye diagram data, perform eye diagram simulation processing based on the test waveform file to obtain the simulated eye diagram data corresponding to the target chip, and perform fitting processing based on the simulated eye diagram data and the measured eye diagram data to obtain the chip simulation model. Thus, the test waveform file corresponding to the target chip is simulated and fitted by the test circuit board and the test equipment auxiliary simulation module to obtain the chip simulation model, thereby realizing the construction of a chip simulation model that can replace the IBIS model, so as to use the chip simulation model to accurately describe the input / output characteristics of the chip in circuit design and simulation, thereby achieving the effect of improving the accuracy of chip signal simulation.

[0063] In one embodiment, Figure 4 As shown, a method for constructing a chip simulation model is proposed, which can be implemented by a computer program and can be run on a device for constructing a chip simulation model based on the von Neumann system. The computer program can be integrated into an application or run as an independent tool application.

[0064] S401, placing the target chip through the test auxiliary module.

[0065] Specifically, the test auxiliary module can be a test circuit board. The structure and function of the test circuit board and the implementation method of placing the target chip using the test circuit board can be specifically referred to in Figure 1-2 The description of the relevant parts in the illustrated embodiment will not be repeated here.

[0066] S402, testing the test auxiliary module in which the target chip is placed by a test device to generate a test waveform file and measured eye diagram data.

[0067] Among them, the test waveform file is a spreadsheet data storage file used to store electrical data that can reflect the signal waveform. The electrical data may include the time of the signal and the voltage that changes with time. The electrical data can be used to reflect the waveform of the signal generated by the chip.

[0068] The measured eye diagram data includes the eye height and eye width in the real eye diagram generated by the test equipment after testing the target chip. Among them, the eye diagram is a graphical representation used to evaluate the quality of digital signals. It overlaps multiple signal waveforms to show the overall characteristics of the signal, including signal quality, noise and crosstalk.

[0069] In some embodiments, the probe of the test equipment can be welded to the test auxiliary module, the target chip can be controlled to be in a working state, and the target chip can be tested by the test equipment to generate a test waveform file and a measured eye diagram. Specifically, the test equipment can display the measured eye diagram, and the measured eye diagram data can be read from the measured eye diagram.

[0070] Optionally, in the process of testing the test auxiliary module in which the target chip is placed by the test equipment, the rate at which the target chip generates a signal can be adjusted so that the target chip can be tested at different signal generation rates by using the test equipment. In this way, the test waveform file and measured eye diagram data corresponding to the target chip at different signal generation rates can be obtained. For example, the target chip in the embodiment of the present application generates a non-return-to-zero signal (Non Return toZero, abbreviated as NRZ) has a maximum rate of 1.5 Gbps. During the test process, the signal generation rate of the target chip can be adjusted to 1.5 Gbps, 1.4 Gbps, 1.3 Gbps, 1.2 Gbps, 1.1 Gbps, and 1 Gbps, respectively, and the target chip is tested at the above signal generation rates by the test equipment, so as to obtain the test waveform file and the measured eye diagram data corresponding to the target chip when the signal generation rate is 1.5 Gbps, obtain the test waveform file and the measured eye diagram data corresponding to the target chip when the signal generation rate is 1.4 Gbps, obtain the test waveform file and the measured eye diagram data corresponding to the target chip when the signal generation rate is 1.3 Gbps, obtain the test waveform file and the measured eye diagram data corresponding to the target chip when the signal generation rate is 1.2 Gbps, obtain the test waveform file and the measured eye diagram data corresponding to the target chip when the signal generation rate is 1.1 Gbps, and obtain the test waveform file and the measured eye diagram data corresponding to the target chip when the signal generation rate is 1 Gbps.

[0071] It can be understood that when a target chip corresponds to multiple test waveform files generated at different signal generation rates, the file name of the test waveform file can include the chip name and signal generation rate of the target chip, so that the test waveform file corresponding to the target chip at different signal generation rates can be quickly selected according to simulation requirements.

[0072] S403, importing the test waveform file into the simulation module.

[0073] In some embodiments, the test waveform file may be imported into the simulation module via a removable storage device, or the test waveform file may be imported into the simulation module using a data transmission line.

[0074] S404, performing eye diagram simulation processing based on the test waveform file through the simulation module to obtain simulated eye diagram data corresponding to the target chip, and performing fitting processing based on the simulated eye diagram data and the measured eye diagram data to obtain a chip simulation model.

[0075] Among them, the simulated eye diagram data may include the eye height and eye width in the simulated eye diagram. Eye width refers to the horizontal width of the waveform displayed in the eye diagram, which usually indicates the effective time window of the data bit during the signal transmission process, and reflects the time domain jitter or error of the signal. Eye height refers to the vertical height of the waveform displayed in the eye diagram, that is, the difference between the maximum and minimum values ​​of the signal, and reflects the amplitude jitter or noise of the signal. For example, see Figure 5 A schematic diagram of a simulated eye diagram is shown in FIG. Figure 5 In the figure, the horizontal axis represents time and the vertical axis represents voltage. In the eye-like graph displayed by signal superposition, the difference between the maximum and minimum voltages represents the eye height, and the difference between the times represents the eye width.

[0076] In the embodiment of the present application, the chip simulation model is not an IBIS model, but a model similar to the IBIS model. Similar to the IBIS model, the chip simulation model may include voltage and time data corresponding to the target chip.

[0077] The chip simulation model may include target parameter values ​​and test waveform files corresponding to the simulation debugging parameters. Among them, the simulation debugging parameters may include at least one of the signal generation rate, the number of signal bits, and the convergence factor. Among them, the signal generation rate refers to the rate at which the chip generates signals; the number of bits refers to the bit data of the data required for the eye diagram simulation, and the number of bits can be set to an appropriate value based on experience. The convergence factor can be understood as a parameter in the eye diagram simulation project, and the value of the convergence factor is configured based on experience.

[0078] The test waveform file includes the signal transmission time of the target chip and the voltage data corresponding to the signal transmission time. Among them, the voltage data corresponding to the signal transmission time can be understood as the voltage value of the signal generated by the target chip during the signal transmission time. In the test waveform file, at least two columns of data may be included, including at least one column of voltage data and one column of time data, the column of time data includes the signal transmission time of the target chip, and the column of voltage data includes the voltage data corresponding to each signal transmission time.

[0079] Optionally, the signal transmitted by the target chip may be a differential signal or a single-ended signal. When the signal transmitted by the target chip is a differential signal, the signal transmission line in the test circuit board may be a differential design; when the signal transmitted by the target chip is a single-ended signal, the signal transmission line in the test circuit board may be a single-ended design.

[0080] In some embodiments, executing step S404 may include the following steps:

[0081] A1, performing eye diagram simulation processing based on the test waveform file through the simulation module to obtain the simulated eye diagram data corresponding to the target chip;

[0082] In some embodiments, the simulation module can call the simulation software to perform eye diagram simulation processing on the test waveform file to obtain simulated eye diagram data. Specifically, the simulation module can first determine the preset file storage path, determine the test waveform file corresponding to the target chip from the preset file storage path, use the eye diagram simulation function in the simulation software to perform eye diagram simulation on the test waveform file, obtain the simulated eye diagram corresponding to the target chip, read the eye width and eye height from the simulated eye diagram, and generate simulated eye diagram data including the eye width and eye height of the simulated eye diagram.

[0083] Specifically, the preset file storage path can be determined according to the user input instruction, and the test waveform file corresponding to the target chip can be determined from the preset file storage path according to the user selection instruction. Among them, the preset file storage path can store a test waveform file corresponding to a target chip, and can also store test waveform files corresponding to multiple target chips. The test waveform files corresponding to different chips can be distinguished according to the file name, and the file name of each test waveform file can include the chip name of the corresponding target chip. The user input instruction can refer to the instruction formed by the user inputting the preset file storage path in the simulation software. The user selection instruction can refer to the instruction formed by the user inputting the operation of selecting the test waveform file in the preset file storage path.

[0084] Exemplarily, the simulation software may be Advanced Design System (ADS). The eye diagram simulation function in ADS may include channel simulation and transient simulation. Then, channel simulation or transient simulation may be used to perform eye diagram simulation on the test waveform file to obtain a simulated eye diagram.

[0085] A2: Debug simulation debugging parameters with reference to the measured eye diagram data, determine the debugged simulated eye diagram data, compare the measured eye diagram data with the debugged simulated eye diagram data to obtain the eye height error and the eye width error, and obtain the chip simulation model when the eye width error is less than or equal to the first threshold and the eye height error is less than or equal to the second threshold.

[0086] In one possible implementation, see Figure 6 , is a flow chart of a chip simulation model determination method provided in an embodiment of the present application, Figure 6 The method flow chart shown includes the specific implementation steps of step A2. Specifically, the chip simulation model determination method includes the following steps:

[0087] S602, determining simulation debugging parameters through a simulation module.

[0088] It is understandable that simulation debugging parameters may include but are not limited to signal generation rate, bit number, and convergence factor. During simulation, the rate at which the chip generates signals needs to be accurately set. For example, when setting the value of the rate, the value of N digits after the decimal point needs to be accurately set. For example, if the chip generates a 1Gbps signal, the actual rate may be 0.99999266Gbps. In this case, the rate needs to be set to 0.99999266Gbps.

[0089] Specifically, the simulation debugging parameters for the target chip can be determined according to the parameter selection instruction input by the user in the simulation software, and the parameter selection instruction can include the simulation debugging parameters selected by the user. For example, the user can input the parameter selection instruction on a parameter selection interface in the simulation software, and the parameter selection instruction can include parameters such as signal generation rate, number of bits, and convergence factor.

[0090] S604, debugging simulation debugging parameters through the simulation module, determining the debugged simulation eye diagram data, and comparing the measured eye diagram data with the debugged simulation eye diagram data to obtain the eye width error and the eye height error.

[0091] Specifically, the reference adjustment value corresponding to the simulation debugging parameter can be determined through the simulation module, and the simulation debugging parameter can be configured as the reference adjustment value through the simulation module to determine the simulated eye diagram data after debugging, and the eye width error and eye height error can be obtained by comparing the measured eye diagram data with the simulated eye diagram data after debugging. Among them, the reference adjustment value can be determined according to the parameter configuration instruction input by the user. The simulation debugging parameter can be configured as the reference adjustment value to obtain the simulated eye diagram after debugging, and the eye width and eye height of the simulated eye diagram after debugging can be identified from the simulated eye diagram after debugging, and the simulated eye diagram data after debugging can be generated, and the simulated eye diagram data after debugging includes the eye width and eye height of the simulated eye diagram after debugging.

[0092] The eye width error may be calculated by: calculating the eye width difference between the eye width in the simulated eye diagram data and the eye width in the measured eye diagram data, calculating a first quotient of the eye width difference and the eye width in the measured eye diagram data, and calculating the absolute value of the first quotient to obtain the eye width error. The eye height error may be calculated by: calculating the eye height difference between the eye height in the simulated eye diagram data and the eye height in the measured eye diagram data, calculating a second quotient of the eye height difference and the eye height in the measured eye diagram data, and calculating the absolute value of the second quotient to obtain the eye height error.

[0093] For example, see the multiple sets of eye diagram error data shown in Table 1 below.

[0094] Table 1 Eye diagram error data between simulated eye diagram data and measured eye diagram data at different signal generation rates

[0095]

[0096] Table 1 shows the eye diagram error data between the simulated eye diagram data and the measured eye diagram data of a certain chip provided in the embodiment of the present application at different signal generation rates. The rate in Table 1 refers to the signal generation rate of the chip; the difference in Table 1 includes the eye width difference obtained by subtracting the eye width of the measured eye diagram from the eye width of the simulated eye diagram, and the eye height difference obtained by subtracting the eye height of the measured eye diagram from the eye height of the simulated eye diagram; the error in Table 1 includes the eye width error calculated based on the eye width difference and the eye width in the measured eye diagram, and the eye height error calculated based on the eye height difference and the eye height in the measured eye diagram; the unit of the eye width in Table 1 is picosecond, and the unit of the eye height in Table 1 is millivolt.

[0097] It can be seen from Table 1 that the maximum eye width error absolute value calculated by the chip simulation model method of the embodiment of the present application is 7.04%, and the maximum eye height error absolute value calculated is 5.79%. Therefore, when the simulated eye diagram is debugged by the chip simulation model method of the embodiment of the present application, the adjusted simulated eye diagram can be made more consistent with the measured eye diagram.

[0098] S606: Determine whether the eye width error is less than or equal to a first threshold, and determine whether the absolute value of the eye height error is less than or equal to a second threshold.

[0099] S608: If the eye width error is less than or equal to the first threshold, and the absolute value of the eye height error is less than or equal to the second threshold, a chip simulation model is generated through a simulation module.

[0100] Specifically, generating a simulation model through a simulation module may include: determining a target parameter value corresponding to a simulation debugging parameter through the simulation module, wherein the target parameter value is the parameter value of the simulation debugging parameter when the adjusted simulation eye diagram data is displayed through the simulation module; and generating a chip simulation model including a test waveform file and a target parameter value through the simulation module.

[0101] It is understandable that the first threshold and the second threshold can be set according to expert experience. For example, in the embodiment of the present application, the first threshold can be set to 10%, and the second threshold can be set to 10%.

[0102] It can be understood that if the eye width error is less than the first threshold and the eye height error is less than the second threshold, a chip simulation model is generated. If the eye width error is less than the first threshold and the eye height error is equal to the second threshold, a chip simulation model is generated. If the eye width error is equal to the first threshold and the eye height error is less than the second threshold, a chip simulation model is generated. If the eye width error is equal to the first threshold and the eye height error is equal to the second threshold, a chip simulation model is generated.

[0103] It can be understood that if the eye width error is less than or equal to the first threshold, and at the same time, the eye height error is less than or equal to the second threshold, it means that the simulated eye diagram data after debugging is closer to the measured eye diagram data, that is, the simulated eye diagram after debugging is more consistent with the measured eye diagram. In this case, the accuracy of the generated chip simulation model is also higher.

[0104] If the eye width error is greater than the first threshold, and / or the eye height error is greater than the second threshold, return to step S604: debug the simulation debugging parameters through the simulation module, determine the debugged simulation eye diagram data, and compare the measured eye diagram data with the debugged simulation eye diagram data to obtain the eye width error and the eye height error.

[0105] Specifically, it can be recorded as condition one: the eye width error is greater than the first threshold, condition two: the eye height error is greater than the second threshold. If at least one of condition one and condition two is met, it means that the gap between the debugged simulated eye diagram data and the measured eye diagram data is large. In this case, the accuracy of the generated chip simulation model is low, so the chip simulation model cannot be generated, and it is necessary to continue to debug the simulated eye diagram corresponding to the debugged simulated eye diagram data, then you can return to execute step S604.

[0106] In the construction method of the chip simulation model provided in the embodiment of the present application, first, the target chip is placed through the test auxiliary module, and then the test auxiliary module with the target chip placed is tested through the test equipment to generate a test waveform file and measured eye diagram data, and then the test waveform file is imported into the simulation module, and then the simulation module performs eye diagram simulation processing based on the test waveform file to obtain the simulated eye diagram data corresponding to the target chip, and performs fitting processing based on the simulated eye diagram data and the measured eye diagram data to obtain the chip simulation model. Thus, the test waveform file corresponding to the target chip is simulated and fitted by the test circuit board and the test equipment auxiliary simulation module to obtain the chip simulation model, thereby realizing the construction of a chip simulation model that can replace the IBIS model, so as to use the chip simulation model to accurately describe the input / output characteristics of the chip in circuit design and simulation, thereby achieving the effect of improving the accuracy of chip signal simulation.

[0107] Please refer to Figure 7 , Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Exemplarily, the electronic device in the embodiment of the present application may specifically include a simulation module, and the electronic device may include one or more of the following components: a processor 110, a memory 120, an input device 130, an output device 140, and a bus 150. The processor 110, the memory 120, the input device 130, and the output device 140 may be connected via a bus 150.

[0108] The processor 110 may include one or more processing cores. The processor 110 uses various interfaces and lines to connect various parts of the entire electronic device, and executes various functions of the electronic device and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 120, and calling data stored in the memory 120. Optionally, the processor 110 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 110 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing display content; and the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the processor 110, but may be implemented separately through a communication chip.

[0109] The memory 120 may include a random access memory (RAM) or a read-only memory (ROM). Optionally, the memory 120 includes a non-transitory computer-readable storage medium. The memory 120 may be used to store instructions, programs, codes, code sets or instruction sets. The memory 120 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (e.g., a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the following various method embodiments, etc. The operating system may be an Android system, including a system deeply developed based on the Android system, an IOS system developed by Apple, including a system deeply developed based on the IOS system or other systems.

[0110] In order for the operating system to distinguish the specific application scenarios of third-party applications, it is necessary to open up data communication between third-party applications and the operating system so that the operating system can obtain the current scenario information of third-party applications at any time, and then perform targeted system resource adaptation based on the current scenario.

[0111] The input device 130 is used to receive input commands or data, and includes but is not limited to a keyboard, a mouse, a camera, a microphone, or a touch device. The output device 140 is used to output commands or data, and includes but is not limited to a display device and a speaker. In one example, the input device 130 and the output device 140 can be combined, and the input device 130 and the output device 140 are touch screen displays.

[0112] The touch display screen can be designed as a full screen, a curved screen or a special-shaped screen. The touch display screen can also be designed as a combination of a full screen and a curved screen, or a combination of a special-shaped screen and a curved screen, which is not limited in the embodiments of the present application.

[0113] In addition, those skilled in the art will appreciate that the structure of the electronic device shown in the above drawings does not constitute a limitation on the electronic device, and the electronic device may include more or fewer components than shown, or combine certain components, or arrange the components differently. For example, the electronic device also includes a radio frequency circuit, an input unit, a sensor, an audio circuit, a wireless fidelity (WiFi) module, a power supply, a Bluetooth module and other components, which will not be described in detail here.

[0114] exist Figure 6 In the electronic device shown, the processor 110 may be used to call a program of a method for determining a chip simulation model stored in the memory 120, and specifically perform the following operations:

[0115] The simulation module performs eye diagram simulation processing based on the test waveform file to obtain simulated eye diagram data corresponding to the target chip, and performs fitting processing based on the simulated eye diagram data and the measured eye diagram data to obtain a chip simulation model.

[0116] In some embodiments, when the processor 110 performs the step of performing fitting processing based on the simulated eye diagram data and the measured eye diagram data to obtain a chip simulation model, the following operations are specifically performed:

[0117] Debug simulation debugging parameters with reference to the measured eye diagram data, determine the debugged simulated eye diagram data, compare the measured eye diagram data with the debugged simulated eye diagram data to obtain eye width error and eye height error, and obtain a chip simulation model when the eye width error is less than or equal to a first threshold and the eye height error is less than or equal to a second threshold.

[0118] In some embodiments, the chip simulation model includes target parameter values ​​corresponding to the simulation debugging parameters and the test waveform file.

[0119] In some embodiments, the simulation debugging parameters include at least one of a signal generation rate, a signal bit number, and a convergence factor.

[0120] In some embodiments, the test waveform file includes the signal transmission time of the target chip and voltage data corresponding to the signal transmission time.

[0121] In some embodiments, the signal transmitted by the target chip is a differential signal or a single-ended signal.

[0122] An embodiment of the present application further provides a computer-readable storage medium, which stores at least one instruction, and the at least one instruction is used to be executed by a processor to implement part or all of the method steps described in the above embodiments.

[0123] An embodiment of the present application also provides a computer program product, which stores at least one instruction, and the at least one instruction is loaded and executed by the processor to implement part or all of the method steps described in the above embodiments.

[0124] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented with hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein the communication media include any media that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that a general or special-purpose computer can access.

[0125] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A test circuit board, characterized in that: It includes a chip mounting component, a signal transmission line and a connection component, wherein the chip mounting component is connected to the connection component through the signal transmission line; wherein, The chip mounting assembly is used to place the target chip; The connection component is used to connect to a test device to assist the test device in testing the target chip.

2. The test circuit board according to claim 1, characterized in that: The length of the signal transmission line is less than or equal to a preset length threshold.

3. A chip simulation model construction system, characterized in that: It includes test auxiliary module, test equipment and simulation module; among which, The test auxiliary module is used to place the target chip and connect with the test equipment to assist the test equipment in testing the target chip to generate a test waveform file and measured eye diagram data; The simulation module is used to obtain the test waveform file and the measured eye diagram data, perform eye diagram simulation processing based on the test waveform file to obtain the simulated eye diagram data corresponding to the target chip, and perform fitting processing based on the simulated eye diagram data and the measured eye diagram data to obtain a chip simulation model.

4. The construction system according to claim 3, characterized in that: The test auxiliary module is a test circuit board, which includes a chip mounting component, a signal transmission line and a connection component, wherein the chip mounting component is connected to the connection component through the signal transmission line; wherein the chip mounting component is used to place the target chip; and the connection component is used to connect the test equipment to assist the test equipment in testing the target chip; The testing device is an oscilloscope.

5. A method for constructing a chip simulation model, characterized in that: Applied to the construction system as claimed in claim 3, the method comprises: Place the target chip through the test auxiliary module; Testing the test auxiliary module on which the target chip is placed by means of a test device to generate a test waveform file and measured eye diagram data; Importing the test waveform file into a simulation module; The simulation module performs eye diagram simulation processing based on the test waveform file to obtain simulated eye diagram data corresponding to the target chip, and performs fitting processing based on the simulated eye diagram data and the measured eye diagram data to obtain a chip simulation model.

6. The method according to claim 5, characterized in that The chip simulation model is obtained by performing fitting processing based on the simulated eye diagram data and the measured eye diagram data, including: Debug simulation debugging parameters with reference to the measured eye diagram data, determine the debugged simulated eye diagram data, compare the measured eye diagram data with the debugged simulated eye diagram data to obtain eye width error and eye height error, and obtain a chip simulation model when the eye width error is less than or equal to a first threshold and the eye height error is less than or equal to a second threshold.

7. The method according to claim 5, characterized in that The chip simulation model includes the target parameter values ​​corresponding to the simulation debugging parameters and the test waveform file.

8. The method according to claim 6 or 7, characterized in that: The simulation debugging parameters include at least one of a signal generation rate, a signal bit number, and a convergence factor.

9. The method according to claim 6 or 7, characterized in that: The test waveform file includes the signal transmission time of the target chip and voltage data corresponding to the signal transmission time.

10. The method according to claim 6 or 7, characterized in that: The signal transmitted by the target chip is a differential signal or a single-ended signal.

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