Device and method for testing stability of data transmission link between chips

Abstract

The embodiment of the invention discloses an inter-chip data transmission link stability testing device and testing method, relates to the technical field of integrated circuit testing, and aims to determine the stability of data transmission of an inter-chip data transmission link. According to the device, a first data generation module is connected with a physical transmission layer of a first chip; the second chip is arranged on the substrate; the data detection module is respectively connected with the second data generation module and the physical transmission layer of the second chip; the first data generation module is used for generating first test data; the second data generation module is used for generating mirror image data of the first test data; and the data detection module is used for receiving the first test data transmitted by the first data generation module through the data transmission link and the mirror image data of the first test data generated by the second data generation module, comparing the received first test data with the mirror image data of the first test data, and determining the bit number of error codes with errors. The method is suitable for chip testing.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit testing, and in particular to a device and method for testing the stability of an inter-chip data transmission link. Background Art

[0002] With the development of technology, in order to achieve more and more powerful functions, multiple chips are used together. During the working process, data is transmitted between chips through data transmission links (data interaction between chips), and the stability of data transmission in the data transmission links between chips is particularly important. In order to improve the stability of data transmission in the data transmission links between chips, in the prior art, when designing chips, attention is paid to the design of the physical transmission layer (PHY) in the chip, which can improve the stability of data transmission in the data transmission links between chips to a certain extent. However, the specific situation of the stability of data transmission in the data transmission links between chips cannot be known. Based on this, measuring the stability of data transmission in the data transmission links between chips is a technical problem that needs to be solved urgently. Summary of the invention

[0003] In view of this, an embodiment of the present application provides an inter-chip data transmission link stability testing device and testing method, which can determine the stability of data transmission in the inter-chip data transmission link.

[0004] In a first aspect, an embodiment of the present application provides a device for testing the stability of a data transmission link between chips, comprising: a substrate; a first chip, the first chip being arranged on the substrate; a first data generation module being arranged in the first chip; the first data generation module being connected to a physical transmission layer of the first chip; a second chip, the second chip being arranged on the substrate; the physical transmission layer of the second chip being connected to the physical transmission layer of the first chip through a wiring in the substrate; a second data generation module and a data detection module being arranged in the second chip, the data detection module being connected to the second data generation module and the physical transmission layer of the second chip respectively; wherein the first data generation module is used to generate first test data; the second data generation module is used to generate mirror data of the first test data; the data detection module is used to receive the first test data transmitted by the first data generation module through a data transmission link, and the mirror data of the first test data generated by the second data generation module, and compare the received first test data with the mirror data of the first test data to determine the number of error bits; wherein the data transmission link is a link for transmitting data between the physical transmission layer of the first chip and the physical transmission layer of the second chip.

[0005] According to a specific implementation method of the embodiment of the present application, it also includes: a test interface, which is arranged on the substrate, for receiving a test start instruction sent by the test machine, and sending the test start instruction to the first data generation module and the delay module, so that the first data generation module generates the first test data according to the test start instruction; the delay module is respectively connected to the test interface and the second data generation module, for receiving the test start instruction, and delaying the received test start instruction for a preset delay time, and then sending it to the second data generation module, so that the second data generation module generates mirror data of the first test data when the data detection module receives the first test data transmitted through the data transmission link.

[0006] According to a specific implementation method of an embodiment of the present application, the data detection module includes: a data detection unit, used to compare a bit in the received first test data with a corresponding bit in the mirror data of the first test data; an error counter, the error counter is connected to the data detection unit, and is used to count up by 1 when the data detection unit detects that a bit in the first test data and a corresponding bit in the mirror data of the first test data are inconsistent.

[0007] According to a specific implementation method of an embodiment of the present application, the test interface is also used to receive a delay configuration instruction sent by the test machine before receiving a test start instruction sent by the test machine to configure the delay length of the delay module.

[0008] According to a specific implementation method of an embodiment of the present application, the test interface is also used by the test machine to read the number of error bits of the error counter. If the number of error bits is greater than or equal to a preset threshold within a preset time, a delay reconfiguration instruction is sent to reconfigure the delay length of the delay module.

[0009] According to a specific implementation method of an embodiment of the present application, it also includes: a first frequency conversion module, the first frequency conversion module is connected to the first data generation module, and is used to convert the test start instruction with the first frequency sent by the test interface into the test start instruction with the second frequency to adapt to the working frequency of the first data generation module; and / or, a second frequency conversion module, the second frequency conversion module is connected to the delay module, and is used to convert the test start instruction with the first frequency sent by the test interface into the test start instruction with a third frequency to adapt to the working frequency of the second data generation module.

[0010] According to a specific implementation method of an embodiment of the present application, it also includes: a first training controller, which is connected to the physical transmission layer of the first chip and is used to receive training instructions sent by a test machine to train the physical transmission layer of the first chip to establish a link connection with the physical transmission layer of the second chip; a second training controller, which is connected to the physical transmission layer of the second chip and is used to receive training instructions sent by a test machine to train the physical transmission layer of the second chip to establish a link connection with the physical transmission layer of the first chip.

[0011] In a second aspect, an embodiment of the present application provides a method for testing the stability of a data transmission link between chips, including: establishing a data transmission link between a first chip and a second chip; receiving a test start instruction; the first chip generates first test data according to the test start instruction; the second chip generates mirror data of the first test data according to the test start instruction; the second chip receives the first test data transmitted by the first chip through the data transmission link, and compares the received first test data with the mirror data of the first test data to determine the number of error bits; wherein the data transmission link is a link for transmitting data between the physical transmission layer of the first chip and the physical transmission layer of the second chip.

[0012] According to a specific implementation method of the embodiment of the present application, the first chip generates first test data according to the test start instruction, including: a first data generation module in the first chip generates first test data according to the test start instruction; the second chip generates mirror data of the first test data according to the test start instruction, including: a delay module in the second chip receives the test start instruction, and delays the received test start instruction for a preset delay length, and then sends it to a second data generation module in the second chip; the second data generation module generates mirror data of the first test data when the data detection module in the second chip receives the first test data transmitted through the data transmission link.

[0013] According to a specific implementation manner of the embodiment of the present application, before receiving the test start instruction, the method further includes: receiving a delay configuration instruction to configure the delay length of the delay module.

[0014] According to a specific implementation manner of an embodiment of the present application, the method further includes: receiving a reconfiguration instruction to reconfigure the delay length of the delay module when the number of error bits is greater than or equal to a preset threshold within a preset time.

[0015] According to a specific implementation method of an embodiment of the present application, the method also includes: converting the test start instruction with the first frequency into the test start instruction with the second frequency to adapt to the working frequency of the first data generation module; and / or converting the test start instruction with the first frequency into the test start instruction with a third frequency to adapt to the working frequency of the second data generation module.

[0016] According to a specific implementation method of an embodiment of the present application, the comparison of the received first test data and the mirror data of the first test data to determine the number of error bits includes: comparing a bit in the received first test data with a corresponding bit in the mirror data of the first test data; when the data detection unit detects that a bit in the first test data and a corresponding bit in the mirror data of the first test data are inconsistent, adding 1 to the count.

[0017] According to a specific implementation method of an embodiment of the present application, establishing a data transmission link between a first chip and a second chip includes: the first chip and the second chip respectively receive training instructions, and respectively train the physical transmission layer of the first chip to establish a link connection with the physical transmission layer of the second chip according to the training instructions.

[0018] In the inter-chip data transmission link stability testing device and testing method of the present embodiment, a first data generation module is provided in the first chip; the first data generation module is connected to the physical transmission layer of the first chip; the physical transmission layer of the second chip is connected to the physical transmission layer of the first chip through the wiring in the substrate; a second data generation module and a data detection module are provided in the second chip, and the data detection module is respectively connected to the second data generation module and the physical transmission layer of the second chip. Since the first data generation module generates the first test data and the second data generation module generates the mirror data of the first test data, the data detection module receives the first test data transmitted by the first data generation module through the data transmission link, and the mirror data of the first test data generated by the second data generation module, and compares the received first test data with the mirror data of the first test data to determine the number of error bits. Furthermore, the bit error rate can be determined according to the number of error bits, and the stability of data transmission in the data transmission link between the first chip and the second chip is determined by the bit error rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A schematic diagram of the structure of a device for testing the stability of a data transmission link between chips provided in one embodiment of the present application; Figure 2 A schematic diagram of a flow chart of a method for testing the stability of a chip-to-chip data transmission link provided in an embodiment of the present application; Figure 3 A flowchart of a method for testing the stability of an inter-chip data transmission link provided in a specific embodiment of the present application is provided. DETAILED DESCRIPTION

[0021] The embodiments of the present application are described in detail below in conjunction with the accompanying drawings. It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0022] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0023] In order to enable those skilled in the art to better understand the technical concept, implementation plan and beneficial effects of the embodiments of the present application, specific embodiments are described in detail below.

[0024] Figure 1 A schematic diagram of the structure of a device for testing the stability of a data transmission link between chips provided in an embodiment of the present application is shown in FIG. Figure 1As shown, the inter-chip data transmission link stability testing device of this embodiment may include: a substrate 1, a first chip 2 and a second chip 3; the first chip 2 and the second chip 3 are respectively arranged on the substrate 1; the first chip 2 is provided with a first data generation module 21; the first data generation module 21 is connected to the physical transmission layer 22 of the first chip 2; the physical transmission layer 31 of the second chip 3 is connected to the physical transmission layer 22 of the first chip 2 through the wiring in the substrate 1; the second chip 3 is provided with a second data generation module (not shown in the figure) and a data detection module 32, and the data detection module 32 is respectively connected to the second data generation module and the physical transmission layer 31 of the second chip 3.

[0025] In this embodiment, the first data generation module 21 is used to generate the first test data; the second data generation module is used to generate the mirror data of the first test data; the data detection module 32 is used to receive the first test data transmitted by the first data generation module 21 through the data transmission link, and the mirror data of the first test data generated by the second data generation module, and compare the received first test data with the mirror data of the first test data to determine the number of error bits. The data transmission link is a link for transmitting data between the physical transmission layer 22 of the first chip 2 and the physical transmission layer 31 of the second chip 3.

[0026] Substrate is generally made of conductive or insulating materials and is used to support circuit elements or devices. It can provide support and electrical connections for electronic components arranged thereon.

[0027] In some examples, the first chip 2 and the second chip 3 may be chiplets, which are chips that are divided according to functions or computing units at the beginning of the design. Each unit is designed and manufactured using a suitable process, and then modules with different processes and functions are interconnected through advanced packaging technology. In another example, the first chip 2 and the second chip 3 may be chips with complete functions.

[0028] The physical transmission layer 22 of the first chip 2 and the physical transmission layer 31 of the second chip 3 are connected via the wiring in the substrate 1 , thereby achieving a physical connection between the two.

[0029] A data transmission link can be established between the physical transmission layers (PHY, Physical Layer) of the chip to realize data transmission.

[0030] The first test data and the mirror data of the first test data are the same data. The first data generating module 21 and the second data generating module are configured in the same manner, so that the first data generating module 21 and the second data generating module can generate the same test data.

[0031] The first data generation module 21 in the first chip 2 generates first test data, and the first test data is transmitted to the data detection module 32 via a data transmission link between the physical transmission layer 22 of the first chip 2 and the physical transmission layer 31 of the second chip 3 .

[0032] During the transmission process, there are various interferences in the environment, such as thermal noise, crosstalk, channel attenuation, etc. The bit error rate (BER) can reflect the stability of data transmission. That is, a low bit error rate means that the transmission has a stronger anti-interference ability and a higher stability of data transmission. A low bit error rate means that the transmission has a worse anti-interference ability and a lower stability of data transmission. The bit error rate refers to the ratio of the number of erroneous bits in data transmission to the total amount of data transmitted per unit time.

[0033] The second data generation module in the second chip 3 generates mirror data of the first test data and sends it to the data detection module 32. The data detection module 32 receives the first test data transmitted through the data transmission link and the mirror data of the first test data sent by the second data generation module, and compares the two to determine the number of error bits. The bit error rate can be determined by the number of error bits.

[0034] For chips with a bit error rate less than or equal to the preset threshold, it can be considered that the data transmission link between chips transmits data relatively stably. Such chips can enter subsequent tests or normal use. For chips with a bit error rate greater than the preset threshold, it can be considered that the data transmission link between chips transmits data unstablely. Such chips need to be further optimized before entering subsequent tests or normal use, or they need to be directly discarded.

[0035] In some examples, the tester can read the number of errored bits and determine the bit error rate.

[0036] In this embodiment, a first data generation module 21 is provided in the first chip 2; the first data generation module 21 is connected to the physical transmission layer 22 of the first chip 2; the physical transmission layer 31 of the second chip 3 is connected to the physical transmission layer 22 of the first chip 2 through the wiring in the substrate 1; a second data generation module and a data detection module 32 are provided in the second chip 3, and the data detection module 32 is respectively connected to the second data generation module and the physical transmission layer 31 of the second chip 3. Since the first data generation module 21 generates the first test data and the second data generation module generates the mirror data of the first test data, the data detection module 32 receives the first test data transmitted by the first data generation module 21 through the data transmission link, and the mirror data of the first test data generated by the second data generation module, and compares the received first test data with the mirror data of the first test data to determine the number of error bits. Furthermore, the bit error rate can be determined according to the number of error bits, and the stability of data transmission in the data transmission link between the first chip 2 and the second chip 3 is determined by the bit error rate.

[0037] The transmission path of the first test data generated by the first data generation module 21 in the first chip 2 needs to be transmitted to the data detection module 32 in the second chip 3 through the data transmission link, which is longer than the transmission path of the second data generated by the second data generation module in the second chip 3 and transmitted to the data detection module 32 also in the second chip 3. The longer transmission path requires a longer transmission time. In order to improve the accuracy of the test results, in some examples, it also includes: a test interface 4 and a delay module 33; the test interface 4 is arranged on the substrate 1, and is used to receive a test start instruction sent by the test machine, and send the test start instruction to the first data generation module 21 and the delay module 33, so that the first data generation module 21 generates the first test data according to the test start instruction; the delay module 33 is respectively connected to the test interface 4 and the second data generation module, and is used to receive the test start instruction, and after delaying the received test start instruction for a preset delay time, send it to the second data generation module, so that the second data generation module generates mirror data of the first test data when the data detection module 32 receives the first test data transmitted through the data transmission link.

[0038] The test interface 4 may be an interface based on a preset protocol. In a specific example, the interface is an interface based on a JTAG protocol.

[0039] The test machine sends a test start instruction through the test machine interface to start the test of the test device. The test start instruction sent by the test machine is sent to the first data generation module 21 and the delay module 33 through the test interface 4. The first data generation module 21 receives the test start instruction and generates the first test data, and transmits the first test data to the data detection module 32 through the data transmission link.

[0040] In this embodiment, the delay module 33 will receive the test start instruction sent by the test interface 4, delay for a preset delay time, and then send the test start instruction to the second data generation module. In this way, when the data detection module 32 receives the first test data transmitted through the data transmission link, the second data generation module generates mirror data of the first test data. Furthermore, the data at the corresponding positions of the first test data and the mirror data of the first test data can be compared, that is, the full synchronization comparison of the first test data and the mirror data of the first test data is achieved. In this way, a more accurate number of error bits can be obtained.

[0041] The test device of this embodiment can realize full synchronous testing. The first test data and the mirror data of the first test data are not restricted by the data form, and the data form that the user wants to use can be set arbitrarily.

[0042] There are many implementation methods for the data detection module 32 to compare the first test data and the mirror data of the first test data. In some examples, the data detection module 32 may include: a data detection unit and a bit error counter; the data detection unit is used to compare a bit in the received first test data with a corresponding bit in the mirror data of the first test data; the bit error counter is connected to the data detection unit, and is used to count up by 1 when the data detection unit detects that a bit in the first test data and a corresponding bit in the mirror data of the first test data are inconsistent.

[0043] The data detection unit compares each bit in the first test data with the corresponding bit in the mirror data of the first test data. When a bit in the first test data is inconsistent with the corresponding bit in the mirror data of the first test data, the count is increased by 1, that is, the number of error bits is increased by 1 on the basis of the original value. After the comparison of each bit of the first test data with the corresponding bit in the mirror data of the first test data is completed, the count value is the final number of error bits.

[0044] In order to be able to flexibly configure the delay length of the delay module 33, in some examples, the test interface 4 is also used to receive a configuration instruction sent by the test machine before receiving a test start instruction sent by the test machine to configure the delay length of the delay module 33.

[0045] The test machine sends the configuration instruction to the test interface 4 , and the test interface 4 then sends the configuration instruction to the delay module 33 , thereby configuring the delay time of the delay module 33 .

[0046] It is understandable that the configuration instruction may include a configured delay duration; a duration may also be pre-stored in the delay module 33, and after the delay module 33 receives the configuration instruction, the duration may be used as the delay duration of the delay module 33.

[0047] The delay duration configured once may not necessarily satisfy the second data generation module to generate mirror data of the first test data when the data detection module 32 receives the first test data transmitted through the data transmission link. In this case, it is necessary to further adjust the delay duration in the delay module 33 to make the test result more accurate. In some examples, the test interface 4 is also used by the test machine to read the number of error bits in the error counter. If the number of error bits within the preset time is greater than or equal to the preset threshold, a delay reconfiguration instruction is sent to reconfigure the delay duration of the delay module 33.

[0048] If the number of erroneous bits is greater than or equal to the preset threshold within the preset time, it indicates that the delay length previously configured for the delay module 33 is inaccurate. In this embodiment, the test interface 4 receives the delay reconfiguration instruction and sends the delay reconfiguration instruction to the delay module 33 to reconfigure the delay length of the delay module 33.

[0049] The frequency of the test start instruction sent by the test machine received by the test interface 4 may be the same as or different from the working frequency of the first generation module. In the case where the frequency of the test start instruction sent by the test machine is different from that of the first generation module, the first generation module cannot process the test start instruction. In such a case, an embodiment of the present application further includes: a first frequency conversion module 23; the first frequency conversion module 23 is connected to the first data generation module 21, and is used to convert the test start instruction with the first frequency sent by the test interface 4 into a test start instruction with the second frequency to adapt to the working frequency of the first data generation module 21.

[0050] The first frequency conversion module 23 in this embodiment can convert the first frequency into the second frequency, so that the first data generation module 21 receives the test start instruction with the second frequency, and the second frequency can be adapted to the working frequency of the first data generation module 21.

[0051] The frequency of the test start instruction sent by the test machine received by the test interface 4 may be the same as or different from the working frequency of the delay module 33. In the case where the frequency of the test start instruction sent by the test machine is different from that of the delay module 33, the delay module 33 cannot process the test start instruction. In such a case, in one embodiment of the present application, it also includes: a second frequency conversion module 34, which is connected to the delay module 33 and is used to convert the test start instruction with the first frequency sent by the test interface 4 into a test start instruction with a third frequency to match the working frequency of the second data generation module.

[0052] The second frequency conversion module 34 in this embodiment can convert the first frequency into a third frequency, so that the delay module 33 receives a test start instruction with the third frequency, and the third frequency can be adapted to the working frequency of the delay module 33 .

[0053] It is understandable that the frequency of the test start instruction sent by the test machine received by the test interface 4 may be the same as or different from the working frequency of the first data generation module 21 and the delay module 33. In the case where the frequency of the test start instruction sent by the test machine is different from that of the first data generation module 21 and the delay module 33, the first data generation module 21 and the delay module 33 cannot process the test start instruction. In such a case, an embodiment of the present application further includes: a first frequency conversion module 23 and a second frequency conversion module 34; the first frequency conversion module 23 is connected to the first data generation module 21, and is used to convert the test start instruction with the first frequency sent by the test interface 4 into a test start instruction with the second frequency to match the working frequency of the first data generation module 21; the second frequency conversion module 34 is connected to the delay module 33, and is used to convert the test start instruction with the first frequency sent by the test interface 4 into a test start instruction with the third frequency to match the working frequency of the second data generation module.

[0054] In order to more accurately determine the stability of the transmission number of the data transmission link, in some examples, it may also include: a first training controller 24 and a second training controller 35; the first training controller 24 is connected to the physical transmission layer 22 of the first chip 2, and is used to receive training instructions sent by the test machine to train the physical transmission layer 22 of the first chip 2 to establish a link connection with the physical transmission layer 31 of the second chip 3; the second training controller 35 is connected to the physical transmission layer 31 of the second chip 3, and is used to receive training instructions sent by the test machine to train the physical transmission layer 31 of the second chip 3 to establish a link connection with the physical transmission layer 22 of the first chip 2.

[0055] The first training controller 24 and the second training controller 35 respectively receive training instructions sent by the test machine. After receiving the training instructions, the first training controller 24 sends control instructions to the physical transmission layer 22 of the first chip 2, and the second training controller 35 sends control instructions to the physical transmission layer 31 of the second chip 3, so as to train the physical transmission layer 22 of the first chip 2 to establish a link connection with the physical transmission layer 31 of the second chip 3.

[0056] Figure 2 A schematic diagram of a flow chart of a method for testing the stability of a chip-to-chip data transmission link provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the inter-chip data transmission link stability testing method of this embodiment includes: S101. Establish a data transmission link between a first chip and a second chip.

[0057] In some examples, the first chip and the second chip may be chiplets, which are chips that are divided according to functions or computing units at the beginning of design. Each unit is designed and manufactured using a suitable process, and then modules with different processes and functions are interconnected through advanced packaging technology. In another example, the first chip and the second chip may be chips with complete functions.

[0058] The physical transmission layer of the first chip and the physical transmission layer of the second chip receive the training instruction, so that the physical transmission layer of the first chip is trained to establish a link connection with the physical transmission layer of the second chip.

[0059] S102: Receive a test start instruction.

[0060] S103: The first chip generates first test data according to the test start instruction.

[0061] S104 . The second chip generates mirror data of the first test data according to the test start instruction.

[0062] The first test data and the mirror data of the first test data are the same data.

[0063] S105 . The second chip receives the first test data transmitted by the first chip through the data transmission link, and compares the received first test data with the mirror data of the first test data to determine the number of error bits.

[0064] The data transmission link is a link for transmitting data between the physical transmission layer of the first chip and the physical transmission layer of the second chip.

[0065] During the transmission process, there are various interferences in the environment, such as thermal noise, crosstalk, channel attenuation, etc. The bit error rate (BER) can reflect the stability of data transmission. That is, a low bit error rate means that the transmission has a stronger anti-interference ability and a higher stability of data transmission. A low bit error rate means that the transmission has a worse anti-interference ability and a lower stability of data transmission. The bit error rate refers to the ratio of the number of erroneous bits in data transmission to the total amount of data transmitted per unit time.

[0066] After the first chip generates the first test data, it transmits the first test data to the second chip through the data transmission link. The second chip compares the received first test data with the mirror data of the first test data to determine the number of error bits. Further, the bit error rate can be determined by the number of error bits.

[0067] For chips with a bit error rate less than or equal to the preset threshold, it can be considered that the data transmission link between chips transmits data relatively stably. Such chips can enter subsequent tests or normal use. For chips with a bit error rate greater than the preset threshold, it can be considered that the data transmission link between chips transmits data unstablely. Such chips need to be further optimized before entering subsequent tests or normal use, or they need to be directly discarded.

[0068] The test device of this embodiment can be used to screen chips, and then chips with data transmission links that can stably transmit numbers can be used in subsequent tests or uses, thereby improving the stability of the transmission numbers of data transmission links between chips and avoiding the problem of low stability caused by only focusing on the design of the physical transmission layer of the chip in the design.

[0069] In this embodiment, the first chip generates first test data, the second chip generates mirror data of the first test data, the second chip receives the first test data transmitted by the first chip through the data transmission link, and compares the received first test data with the mirror data of the first test data to determine the number of error bits. Furthermore, the bit error rate can be determined based on the number of error bits, and the stability of data transmission in the data transmission link between the first chip and the second chip can be determined through the bit error rate.

[0070] The first test data generated in the first chip needs to be transmitted to the second chip through a data transmission link, and the transmission needs a certain time. To improve the accuracy of the test result, in some examples, the first chip in step S103 generates the first test data according to the test start instruction, which may include: S103a. The first data generating module in the first chip generates first test data according to the test start instruction.

[0071] In step S104, the second chip generates mirror data of the first test data according to the test start instruction, which may include: S104a, the delay module in the second chip receives the test start instruction, delays the received test start instruction for a preset delay time, and then sends it to the second data generation module in the second chip.

[0072] S104b: When the data detection module in the second chip receives the first test data transmitted through the data transmission link, the second data generation module generates a mirror number of the first test data.

[0073] The transmission path of the first test data generated by the first data generation module in the first chip needs to be transmitted to the data detection module in the second chip through the data transmission link, which is longer than the transmission path of the second data generated by the second data generation module in the second chip to be transmitted to the data detection module also in the second chip, and the longer transmission path requires a longer transmission time. In this embodiment, the received test start instruction is delayed by a preset delay time through the delay module, and then the test start instruction is sent to the second data generation module. In this way, when the data detection module receives the first test data transmitted through the data transmission link, the second data generation module generates mirror data of the first test data. Furthermore, the data at the corresponding positions of the first test data and the mirror data of the first test data can be compared, that is, the full synchronization comparison of the first test data and the mirror data of the first test data is realized, so that a more accurate number of error bits can be obtained.

[0074] The test device of this embodiment can realize full synchronous testing. The first test data and the mirror data of the first test data are not restricted by the data form, and the data form that the user wants to use can be set arbitrarily.

[0075] In order to flexibly configure the delay time of the delay module, in some examples, before receiving the test start instruction in step S102, the method of this embodiment may further include: S106: Receive a delay configuration instruction to configure the delay length of the delay module.

[0076] It is understandable that the configuration instruction may include a configured delay duration; a duration may also be pre-stored in the delay module, and after the delay module receives the configuration instruction, the duration may be used as the delay duration of the delay module.

[0077] The delay time configured once may not necessarily satisfy the second data generation module to generate the mirror data of the first test data when the data detection module receives the first test data transmitted through the data transmission link. In this case, the delay time in the delay module needs to be further adjusted to make the test result more accurate. In some examples, the method of this embodiment may further include: S107 . When the number of erroneous bits is greater than or equal to a preset threshold within a preset time, receive a reconfiguration instruction to reconfigure the delay time of the delay module.

[0078] If the number of error bits is greater than or equal to the preset threshold within the preset time, it indicates that the delay time previously configured for the delay module is inaccurate. In this embodiment, a delay reconfiguration instruction can be sent to the delay module to reconfigure the delay time of the delay module.

[0079] The frequency of the test start instruction may be the same as or different from the operating frequency of the first generation module. When the frequency of the test start instruction is different from that of the first generation module, the first generation module cannot process the test start instruction. In this case, in one embodiment of the present application, the following may also be included: S108: Convert the test start instruction with the first frequency into a test start instruction with a second frequency to match the operating frequency of the first data generating module.

[0080] In this embodiment, the first frequency is converted into the second frequency, so that the first data generating module receives the test start instruction with the second frequency, and the second frequency can be adapted to the working frequency of the first data generating module.

[0081] The frequency of the received test start instruction may be the same as or different from the operating frequency of the delay module. In the case where the frequency of the test start instruction is different from that of the delay module, the delay module cannot process the test start instruction. In such a case, in one embodiment of the present application, the following may also be included: S109: Convert the test start instruction with the first frequency into a test start instruction with a third frequency to match the operating frequency of the second data generating module.

[0082] The second frequency conversion module in this embodiment can convert the first frequency into a third frequency, so that when the delay module receives a test start instruction with the third frequency, the third frequency can be adapted to the operating frequency of the delay module.

[0083] It is understandable that the frequency of the received test start instruction may be the same as or different from the operating frequency of the first data generation module and the delay module. In the case where the frequency of the test start instruction is different from that of the first data generation module and the delay module, the first data generation module and the delay module cannot process the test start instruction. In such a case, in one embodiment of the present application, the above steps S108 and S109 may be included simultaneously.

[0084] There are many implementations for comparing the first test data with the mirror data of the first test data. In some examples, comparing the received first test data with the mirror data of the first test data to determine the number of error bits in step S105 includes: S105a: Compare a bit in the received first test data with a corresponding bit in the mirror data of the first test data.

[0085] S105b: When the data detection unit detects that a bit in the first test data is inconsistent with a corresponding bit in the mirror data of the first test data, the count is increased by 1.

[0086] Each bit in the first test data is compared with the corresponding bit in the mirror data of the first test data. When a bit in the first test data is inconsistent with the corresponding bit in the mirror data of the first test data, the count is increased by 1, that is, the number of error bits is increased by 1 on the basis of the original value. After the comparison of each bit of the first test data with the corresponding bit in the mirror data of the first test data is completed, the count value is the final number of error bits.

[0087] In order to more accurately determine the stability of the transmission number of the data transmission link, in some examples, establishing the data transmission link between the first chip and the second chip in step S101 may include: S101a: The first chip and the second chip respectively receive training instructions, and respectively train the physical transmission layer of the first chip to establish a link connection with the physical transmission layer of the second chip according to the training instructions.

[0088] The solution of the present application is described in detail below with a specific embodiment.

[0089] See also Figure 1 The inter-chip data transmission link stability testing device of this embodiment may include: The test chip return package will contain two identical Dies: Die0 and Die1, and the chiplet PHYs of the two Dies will be interconnected inside the package. Die0 is used as the TX end to send data, and Die1 is used as the receiving end to detect the correctness of the data. The test device also includes two PHY training controllers (PHY Training Controller), which are used to control the PHY training process so that chiplet PHY0 and PHY1 can establish a good connection; TX data generator (TX Data Gen) (first data generation module), which is used to generate data to be transmitted (first test data), and the data format can be configured into any pattern according to user needs; TAP Controller is the control module (protocol parsing module) of the JTAG protocol, which is used to initialize, configure and control the test device; the RX end has an RX data detection module (RX Pattern Auto Check), which compares the data received by PHY1 and records the number of error bits. The data detection module also has a data generator (second data generation module) that is exactly the same as the TX. Before detection, ensure that the data generator configuration on the RX side is consistent with the TX data generator; the delay module (Configurable Delay Line) is used to balance the time taken for data to be generated from Die0 to be sent to the RX data automatic detection module, so that when the data reaches the RX data automatic detection module, the RX detection is started just in time, so that the data can be fully matched.

[0090] like Figure 3 As shown, the working process of the testing device of this embodiment is as follows: 1. Physical transmission link between training chips.

[0091] The tester sends control signals to the TAP Controller through the JTAG interface. The TAP Controller configures the PHY Training Controller module to control the chiplet PHY to complete the Training process and establish a link connection.

[0092] 2. Configure the delay time.

[0093] The test machine sends a signal to the Tap Controller through the JTAG interface to configure the value of the initial DelayLine register at the PHY1 RX end. It is usually set to 0, indicating that the signal passes through the Delay Line without delay.

[0094] The Delay Line control designed on the RX side will compensate for the time difference between the two start command paths JTAG->Die0 TAP Controller->TX Gen->Die0 Chiplet ->Die1 Chiplet ->Die1 RX Check and JTAG->Die1 TAP Controller->Die 1 RxCheck, ultimately achieving the effect of synchronous comparison of data.

[0095] The JTAG control chains of the two Dies are connected in series through Package encapsulation, so that the TX Pattern Gen module and the RX Pattern Auto Check module can be started at the same time. That is, the TX Pattern Gen module sends data0 to the RX Pattern Auto Check module, which just generates data0 for comparison.

[0096] 3. Initialize the first data generation module, the second data generation module and the data detection module.

[0097] The tester sends signals to the Tap Controller through the JTAG interface to configure the PHY0 TX Pattern Gen and PHY1 RX Pattern Check modules and reset and initialize the two modules.

[0098] 4. Enable the first data generation module and the second data generation module.

[0099] When Die0 and Die1 are packaged, the JTAG chain will be connected together, and an enable command will be sent to PHY0 TX Gen and PHY1 RX Check through the common JTAG network. The enable command to PHY1 will pass through the Delay Line.

[0100] 5. Read the number of error bits in the error register.

[0101] The test machine reads the PHY1 RX Error Counter register value through JTAG. The register bit width is 16.

[0102] 6. Determine whether the error counter is full.

[0103] If the PHY1 RX Error Counter register value is full (the register value read in step 5 is 16'hFFFF), jump to step 7. If not, jump to step 9. 7. Delay duration plus preset step length.

[0104] The initial Delay Line value of the PHY1 RX end is increased by 1. At this time, the signal passing through the Delay Line will be delayed by one FCLKRX cycle, and then return to step 2.

[0105] 8. Reset the first data generation module, the second data generation module and the data detection module.

[0106] The tester resets PHY0 TX Gen and PHY1 RX Check again through the JTAG interface, so that the two modules return to the initialization stage.

[0107] 9. The first data generation module sends quantitative data to the data detection module.

[0108] The test machine configures the amount of data that the TX Pattern Gen module needs to send through JTAG, that is, how many data records DataVol the TX needs to send. The system automatically stops after the data is sent, and then reads the PHY1 RX Error Counter register value, recorded as err_bits, and calculates BER=err_bits / DataVol.

[0109] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0110] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0111] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0112] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present application, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0113] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A device for testing the stability of a data transmission link between chips, characterized in that: include: substrate; A first chip, wherein the first chip is disposed on the substrate; a first data generating module is disposed in the first chip; The first data generation module is connected to the physical transmission layer of the first chip; a second chip, the second chip being disposed on the substrate; a physical transmission layer of the second chip being connected to a physical transmission layer of the first chip via a wiring in the substrate; a second data generation module and a data detection module being disposed in the second chip, the data detection module being connected to the second data generation module and the physical transmission layer of the second chip respectively; Wherein, the first data generating module is used to generate first test data; The second data generating module is used to generate mirror data of the first test data; The data detection module is used to receive the first test data transmitted by the first data generation module through the data transmission link, and the mirror data of the first test data generated by the second data generation module, and compare the received first test data with the mirror data of the first test data to determine the number of error bits; wherein the data transmission link is a link for transmitting data between the physical transmission layer of the first chip and the physical transmission layer of the second chip.

2. The testing device according to claim 1, characterized in that: Also includes: A test interface, the test interface is arranged on the substrate, and is used to receive a test start instruction sent by a test machine, and send the test start instruction to the first data generation module and the delay module, so that the first data generation module generates the first test data according to the test start instruction; The delay module is respectively connected to the test interface and the second data generation module, and is used for receiving the test start instruction, and after delaying the received test start instruction for a preset delay time, sending it to the second data generation module, so that the second data generation module generates mirror data of the first test data when the data detection module receives the first test data transmitted through the data transmission link.

3. The testing device according to claim 2, characterized in that: The data detection module comprises: a data detection unit, configured to compare a bit in the received first test data with a corresponding bit in the mirror data of the first test data; A bit error counter, the bit error counter is connected to the data detection unit, and is used to count up by 1 when the data detection unit detects that a bit in the first test data is inconsistent with a corresponding bit in the mirror data of the first test data.

4. The testing device according to claim 3, characterized in that: The test interface is further used to receive a delay configuration instruction sent by the test machine before receiving a test start instruction sent by the test machine, so as to configure the delay length of the delay module.

5. The testing device according to claim 4, characterized in that: The test interface is also used for the test machine to read the number of error bits in the error counter, and if the number of error bits within a preset time is greater than or equal to a preset threshold, a delay reconfiguration instruction is sent to reconfigure the delay length of the delay module.

6. The testing device according to claim 2, characterized in that: Also includes: a first frequency conversion module, the first frequency conversion module being connected to the first data generation module and configured to convert the test start instruction having the first frequency sent by the test interface into the test start instruction having the second frequency so as to adapt to the working frequency of the first data generation module; and / or, A second frequency conversion module, which is connected to the delay module, is used to convert the test start instruction with the first frequency sent by the test interface into the test start instruction with a third frequency to adapt to the working frequency of the second data generation module.

7. The testing device according to claim 1, characterized in that: Also includes: A first training controller, the first training controller is connected to the physical transmission layer of the first chip, and is used to receive a training instruction sent by a tester to train the physical transmission layer of the first chip to establish a link connection with the physical transmission layer of the second chip; A second training controller is connected to the physical transmission layer of the second chip and is used to receive training instructions sent by the tester to train the physical transmission layer of the second chip to establish a link connection with the physical transmission layer of the first chip.

8. A method for testing the stability of a data transmission link between chips, characterized in that: include: Establishing a data transmission link between the first chip and the second chip; Receive a test start instruction; The first chip generates first test data according to the test start instruction; The second chip generates mirror data of the first test data according to the test start instruction; The second chip receives the first test data transmitted by the first chip via the data transmission link, and compares the received first test data with the mirror data of the first test data to determine the number of error bits; wherein the data transmission link is a link for transmitting data between the physical transmission layer of the first chip and the physical transmission layer of the second chip.

9. The testing method according to claim 8, characterized in that: The first chip generates first test data according to the test start instruction, including: The first data generating module in the first chip generates first test data according to the test start instruction; The second chip generates mirror data of the first test data according to the test start instruction, including: The delay module in the second chip receives the test start instruction, delays the received test start instruction by a preset delay time, and then sends it to the second data generation module in the second chip; The second data generating module generates mirror data of the first test data when the data detecting module in the second chip receives the first test data transmitted through the data transmission link.

10. The testing method according to claim 9, characterized in that: Before receiving the test start instruction, the method further includes: Receive a delay configuration instruction to configure the delay length of the delay module.

11. The testing method according to claim 10, characterized in that: The method further comprises: When the number of error bits is greater than or equal to a preset threshold within a preset time, a reconfiguration instruction is received to reconfigure the delay length of the delay module.

12. The testing method according to claim 9, characterized in that: The method further comprises: converting the test start instruction with the first frequency into the test start instruction with the second frequency to match the working frequency of the first data generating module; and / or, The test start instruction with the first frequency is converted into the test start instruction with a third frequency to adapt to the working frequency of the second data generating module.

13. The testing method according to claim 8, characterized in that: The step of comparing the received first test data with the mirror image data of the first test data to determine the number of error bits that occur includes: Comparing a bit in the received first test data with a corresponding bit in the mirror data of the first test data; When the data detection unit detects that a bit in the first test data is inconsistent with a corresponding bit in the mirror data of the first test data, the count is increased by 1.

14. The testing method according to claim 8, characterized in that: The establishing of a data transmission link between the first chip and the second chip includes: The first chip and the second chip respectively receive training instructions, and respectively train the physical transmission layer of the first chip to establish a link connection with the physical transmission layer of the second chip according to the training instructions.

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