Clock conversion radar signal processing method

Abstract

The invention discloses a radar signal processing method for clock conversion, and mainly solves the problem of poor radar echo performance in the prior art. The implementation scheme is as follows: acquiring an external clock, an intermediate frequency echo and a frame synchronization signal generated by a solid-state transceiving component and an internal clock generated by a crystal oscillator; if the external clock does not meet the requirement, the clock management module is adjusted to enable an input clock source of the clock management module to be the internal clock generated by the crystal oscillator, and then the internal clock output by the clock management module is sent to the A / D sampling module; otherwise, an external clock is used as an input clock source of the clock management module, and the output of the external clock is sent to the A / D sampling module; a / D sampling frequency and time sequence are set, clock signals and digital intermediate frequency signals are processed and output to the FPGA to be processed to form echo signals, and echoes are transmitted to the DSP module to be filtered. The method can obtain the optimal echo performance when the output clock reference signal of the solid-state transmit-receive assembly is abnormal, and can be used for target detection.

Description

Technical Field

[0001] The present invention belongs to the technical field of signal processing, and in particular relates to a radar signal processing method, which can be used in target detection, target tracking, clutter suppression and echo display, and provides a clock reference signal for a whole machine outside a solid-state transceiver component to improve radar echo performance. Background Art

[0002] The solid-state transceiver component provides the clock reference signal for the whole machine, which is a relatively mature signal processing technology. Because it uses a highly accurate constant temperature crystal oscillator, it better solves the contradiction between the reference clock accuracy, transmission cable loss and electromagnetic interference. The external clock reference signal generated by the solid-state transceiver component is used as the timing reference for signal processing. Its performance directly affects the subsequent signal pulse compression processing results, continuous wave processing results and the display effect of the terminal radar echo.

[0003] Existing methods for generating clock reference signals for marine radars include the following two methods:

[0004] First, for the pulse compression radar in the marine radar, the solid-state transceiver component generates an external clock reference signal and sends it to the signal processing system through a dedicated cable. At the same time, the signal processing system generates a frame synchronization signal FSP and sends it to the solid-state transceiver component through a dedicated cable. Finally, the signal processing system completes the relevant processing work in strict accordance with the timing of the clock reference signal and the frame synchronization signal FSP.

[0005] Second, for the frequency modulated continuous wave radar in the marine radar, the solid-state transceiver component generates an external clock reference signal and a frame synchronization signal FSP, which are sent to the signal processing system through a dedicated cable. Finally, the signal processing system completes the relevant processing work in strict accordance with the timing of the clock reference signal and the frame synchronization signal FSP.

[0006] Although both of the above methods can complete the real-time processing of radar echo signals well and obtain better terminal echo display effects, when the solid-state transceiver component cannot output the external clock reference signal or the generated external clock reference signal does not meet the use requirements of the radar signal processing system, it will affect the real-time processing effect of the pulse compression radar and frequency modulation continuous wave radar signal processing system, resulting in the deterioration of the radar terminal echo, thereby affecting its use.

[0007] In response to the above problems, in recent years, relevant literature and materials have proposed methods to improve the real-time echo performance of marine radars under complex sea conditions. For example, in the paper "Research on FMCW Radar Low, Small and Slow Target Detection under Strong Clutter Background" in Radio Engineering, Issue 12, 2023, this method improves the echo performance of FMCW radar in detecting short-range low, small and slow targets by selecting appropriate radar parameters and combining signal processing algorithms. However, since it does not conduct an in-depth analysis of the radar echo from the perspective of clock changes, there is still no significant improvement in the echo performance of detecting long-range low, small and slow targets. Summary of the invention

[0008] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and to propose a clock-converted radar signal processing method so as to obtain optimal radar echo performance under the premise that no solid-state transceiver component outputs an external clock reference signal or the generated external clock reference signal does not meet the use requirements of the radar signal processing system.

[0009] To achieve the above object, the technical solution of the present invention comprises the following steps:

[0010] 1. A clock-converted radar signal processing method is based on a solid-state transceiver component and a signal processing system, wherein the signal processing system comprises: a clock management module, an A / D sampling module, an FPGA processing module, a DSP module and a crystal oscillator, wherein the implementation steps include the following:

[0011] (1) Generate an external clock reference signal, an intermediate frequency echo signal and a frame synchronization signal FSP through a solid-state transceiver component, and generate an internal clock reference signal through a crystal oscillator;

[0012] (2) Sending the external clock reference signal generated by the component and the internal clock reference signal generated by the crystal oscillator to the clock management module, and sending the intermediate frequency echo signal to the A / D sampling module;

[0013] (3) The signal processing system determines the status of the external clock reference signal output by the received solid-state transceiver component:

[0014] If the external clock reference signal generated by the component does not meet the requirements of the signal processing system, readjust its clock management module so that the input clock source signal of the clock management module is always the internal reference clock generated by the crystal oscillator, so as to eliminate the electromagnetic interference signal caused by the cable, and then send the internal clock output by the clock management module to the A / D sampling module;

[0015] Otherwise, the external clock reference signal generated by the solid-state transceiver component is preferably used as the input clock source of the clock management module, and the external clock output by the clock management module is sent to the A / D sampling module;

[0016] (4) The A / D sampling module receives the clock output by the clock management module and the intermediate frequency echo signal generated by the component, sets the sampling frequency and timing parameters of the A / D sampling processing, processes and outputs the clock signal and the digital intermediate frequency signal;

[0017] (5) The FPGA processing module receives the clock signal and the digital intermediate frequency signal to generate a digital baseband signal, and forms an echo signal through pulse compression or FFT processing and sends it to the DSP processing module;

[0018] (6) The DSP processing module performs corresponding filtering according to the status of the received echo signal.

[0019] Compared with the prior art, the present invention has the following advantages:

[0020] 1. The present invention determines the status of the clock reference signal output by the received solid-state transceiver component through the signal processing system, thereby ensuring that the radar signal processing system obtains a better clock reference signal under the condition that the clock reference signal output by the solid-state transceiver component is abnormal; at the same time, under the condition that the clock reference signal generated by the solid-state transceiver component and the clock management module are physically connected, the electromagnetic interference caused by the cable is eliminated, and the clock reference signal with the best performance is obtained.

[0021] 2. Since the present invention adjusts the clock management module to transform the clock reference signal through the control register in the FPGA processing module, the fault position can be quickly located according to the echo display status before and after the transformation without replacing the solid-state transceiver component, thereby improving the rapid repair capability of pulse compression radar and frequency modulation continuous wave radar faults.

[0022] Experiments show that the present invention can further improve the echo performance of pulse compression radar and frequency modulated continuous wave radar under abnormal conditions of the clock reference signal output by the solid-state transceiver component by obtaining the optimal performance of the radar signal processing system clock reference signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a principle block diagram of the present invention;

[0024] Figure 2 It is an implementation flow chart of the present invention. DETAILED DESCRIPTION

[0025] The implementation incentives and effects of the present invention are described in detail below in conjunction with the accompanying drawings. It should be understood that this embodiment is only for describing the present invention and does not constitute any limitation to the present invention.

[0026] The specific implementation of this example is based on a solid-state transceiver component and a signal processing system, that is, the optimal radar echo performance is obtained under the premise that no solid-state transceiver component outputs an external clock reference signal or the generated external clock reference signal does not meet the use requirements of the radar signal processing system.

[0027] Reference Figure 1 The solid-state transceiver component and signal processing system comprises: a solid-state transceiver component, a clock management module, an A / D sampling module, an FPGA processing module and a DSP processing module, wherein:

[0028] The solid-state transceiver component mainly completes the generation and transmission of the external clock reference signal, the intermediate frequency echo signal and the frame synchronization signal FSP in the frequency modulation continuous wave system, and receives the frame synchronization signal FSP in the pulse compression system;

[0029] The clock management module mainly completes the clock reference signal required for the A / D sampling module, FPGA processing module and DSP processing module;

[0030] The A / D sampling module mainly receives the clock reference signal input by the clock management module and sends it to the FPGA processing module, and converts the analog intermediate frequency signal input by the solid-state transceiver component into a digital intermediate frequency signal and sends it to the FPGA processing module;

[0031] The FPGA processing module mainly completes digital down-conversion DDC processing, low-pass filtering processing, time domain pulse compression processing in pulse compression system, and FFT processing in frequency modulation continuous wave system. For pulse compression system radar, the frame synchronization signal FSP is sent from the FPGA processing module to the solid-state transceiver component. For frequency modulation continuous wave system radar, the frame synchronization signal FSP is sent from the solid-state transceiver component to the FPGA processing module;

[0032] The DSP processing module mainly completes AMTI processing when filtering out meteorological clutter such as rain, snow and fog at low altitude on the sea surface and dynamic clutter map processing when filtering out fixed clutter at low altitude on the sea surface.

[0033] The working principles of the above modules and solid-state transceiver components are as follows:

[0034] Under the control of the control register of the FPGA processing module, the clock source signal received by the clock management module is adjusted to the internal clock reference signal generated by the crystal oscillator of the signal processing system, and the electromagnetic interference under the condition that the solid-state transceiver component is physically connected to the clock management module through a cable is eliminated. Then, the clock reference signal output by the clock management module and the analog intermediate frequency echo signal generated by the solid-state transceiver component are sent to the A / D sampling module in turn to generate a digital intermediate frequency echo. Two digital baseband signals are generated through the digital down-conversion DDC processing submodule and the low-pass filtering processing submodule. Subsequently, pulse compression processing is performed through the time domain pulse compression processing submodule or the beat echo signal is obtained through the FFT processing submodule. After that, if it is necessary to suppress meteorological clutter such as rain, snow and fog at low altitude on the sea surface, the AMTI processing submodule is used for filtering processing, and when it is necessary to suppress fixed clutter at low altitude on the sea surface, the dynamic clutter map processing submodule is used for processing, and finally the echo processing result is sent to the terminal for display. Figure 1 K1 and K2 are the selection switches of the DSP processing module, which are controlled by the display console and are closed by default.

[0035] Reference Figure 2 The specific implementation steps of the present invention are as follows:

[0036] Step 1. The solid-state transceiver component and the crystal oscillator output signals respectively.

[0037] The signals output by the solid-state transceiver assembly include: an external clock reference signal, an intermediate frequency echo signal and a frame synchronization signal FSP. The external clock reference signal is transmitted to the clock management module for conversion processing, the intermediate frequency echo signal is sent to the A / D sampling for analog-to-digital conversion processing, and the frame synchronization signal FSP is sent to the FPGA as a FFT processing reference;

[0038] The crystal oscillator generates and outputs an internal clock reference signal and transmits it to the clock management module.

[0039] Step 2: The clock management module transforms the clock reference signal.

[0040] The clock management module determines the status of the external clock reference signal output by the received solid-state transceiver component and performs different transformations based on the requirements of the signal processing system for the input clock reference signal:

[0041] When the external clock reference signal generated by the solid-state transceiver component meets the input requirements of the signal processing system, the external clock reference signal generated by the solid-state transceiver component is preferably selected as the input clock source of the clock management module, and the clock reference signal output by the clock management module is sent to the A / D sampling module;

[0042] Otherwise, if the frequency and amplitude of the external clock reference signal generated by the solid-state transceiver component are unstable and the interference increases, the clock management module is adjusted through the FPGA control register to convert the input clock source signal of the clock management module into the internal clock reference signal generated by the crystal oscillator; at the same time, ensure that the electromagnetic interference signal caused by the cable is eliminated under the condition that the solid-state transceiver component is physically connected to the clock management module, and send the clock reference signal output by the clock management module to the A / D sampling module.

[0043] Step 3. The A / D sampling module performs A / D sampling processing on the analog intermediate frequency signal.

[0044] 3.1) Set the sampling frequency and timing parameters of the A / D sampling process to convert the analog intermediate frequency signal output by the solid-state transceiver component into a digital intermediate frequency signal;

[0045] 3.2) Send the clock reference signal and digital intermediate frequency signal output by the A / D sampling process to the FPGA processing module.

[0046] Step 4: Perform digital down-conversion (DDC) processing and low-pass filtering processing on the digital intermediate frequency signal.

[0047] 4.1) Receive the clock reference signal, frame synchronization signal FSP and digital intermediate frequency signal after A / D sampling processing, and synthesize multiple digital single-ended signals under strict clock timing control;

[0048] 4.2) The multi-channel digital single-ended signals are subjected to DC subtraction processing, and under the action of the digital oscillator NCO and the multiplier MUL, the orthogonal modulation is output to output the I and Q two-channel digital baseband signals, thereby completing the digital down-conversion DDC processing;

[0049] 4.3) Receive the I and Q digital baseband signals processed by digital down-conversion DDC, and select the optimal filter and coefficients for the I and Q digital baseband signals to complete the low-pass filtering process. Finally, the filtered two-way digital baseband echo signal is sent to the time domain pulse compression processing submodule in the pulse compression system or to the FFT processing submodule in the frequency modulation continuous wave system.

[0050] Step 5: Perform time domain pulse compression processing or FFT processing on the digital baseband echo signal.

[0051] 5.1) After the time domain pulse compression processing submodule or the FFT processing submodule receives the two-way digital baseband echo signal, the clock reference signal and the frame synchronization signal FSP after the digital down-conversion DDC processing and low-pass filtering processing, it determines the subsequent processing method of the baseband signal:

[0052] When it is a pulse pressure system, execute step 5.2;

[0053] When it is a frequency modulated continuous wave system, execute step 5.3;

[0054] 5.2) Perform pulse compression processing on the digital baseband echo signal:

[0055] 5.2.1) Generate a frame synchronization signal FSP based on the clock reference signal timing, and send the frame synchronization signal FSP to the solid-state transceiver component, while receiving the following two input digital baseband signals X I and X Q :

[0056] X I =cos(n·f0 / f s ·2·π).*X T

[0057] X Q = sin(n·f0 / f s ·2·π).*X T

[0058] Where n is the number of sampling points, f0 is the center frequency of the signal, and f s is the sampling frequency, X is the digital intermediate frequency signal, X T is the transposed signal of X;

[0059] 5.2.2) According to the two input signals X I and X Q The time domain pulse compression input signal x(n) is obtained:

[0060] x(n)=X I +jX Q

[0061] Where j is a complex unit;

[0062] 5.2.3) Input the pulse compression input signal x(n) into the matched filter h(n) to obtain the output signal y(n) after time-domain pulse compression:

[0063]

[0064] Among them, x(k) is the sequence signal of the input signal, and h(nk) is the sequence signal of the matched filter;

[0065] 5.2.4) Receive the output signal y(n) after the time domain pulse compression processing, use the Hamming window function to perform windowing processing on the side lobes of the output signal, and send the processed echo signal to the AMTI processing submodule;

[0066] 5.3) Perform FFT processing on the digital baseband echo signal:

[0067] 5.3.1) Based on the received clock reference signal and frame synchronization signal FSP, the digital baseband echo signal is sent to the FFT processing submodule, and the frequency modulation slope μ and frequency modulation bandwidth B of the linear frequency modulation continuous wave sawtooth wave intermediate frequency transmission signal are calculated. s , frequency modulation period T s , echo delay time τ, calculate the beat signal frequency f b :

[0068]

[0069] Where R is the detection distance of FMCW radar, c is the speed of light, c = 3 × 10 8 m / s;

[0070] 5.3.2) The received two-way digital baseband echo signal, clock reference signal, frame synchronization signal FSP and related control signals are sent to the FFT IP core in the FPGA to identify the beat signal frequency f b , and then calculate the detection distance R of the FMCW radar:

[0071]

[0072] 5.3.3) Select the number of FFT processing points N according to the accuracy of the detection distance, and calculate the detection accuracy ΔR according to the detection distance R:

[0073]

[0074] 5.3.4) The frequency domain echo signal f obtained by FFT processing b The data is sent to the AMTI processing submodule, and R and ΔR are used as backups of distance detection and distance detection accuracy for subsequent terminal display.

[0075] Step 6: Perform AMTI processing on the echo signal that has undergone time domain pulse compression processing or FFT processing.

[0076] 6.1) The AMTI processing submodule receives radar echo signals that have been processed by time domain pulse compression or FFT, and determines the subsequent processing method based on the status of the echo signal:

[0077] When the echo signal contains meteorological clutter such as rain, snow and fog at low altitude over the sea, execute step 6.2);

[0078] Otherwise, go to step 6.3);

[0079] 6.2) Perform AMTI processing on the echo signal:

[0080] 6.2.1) Calculate the cancellation coefficient W based on the cancellation result X1 of the current frame signal and the cancellation result X2 of the previous frame signal opt :

[0081]

[0082] Where: X2 * is the conjugate function of X2;

[0083] 6.2.2) Calculate radar echo cancellation result X based on the above parameters:

[0084] X=X2-X1·W opt ;

[0085] 6.2.3) Sending the radar echo cancellation result X after AMTI processing to the dynamic clutter map processing module;

[0086] 6.3) Directly send the received radar echo signal after time domain pulse compression processing or FFT processing to the dynamic clutter map processing submodule.

[0087] Step 7. Perform dynamic clutter map processing on the echo after AMTI processing.

[0088] 7.1) The dynamic clutter image processing submodule receives the radar echo signal processed by the AMTI processing submodule and determines the subsequent processing method according to the status of the echo signal:

[0089] When there is low-altitude fixed clutter on the sea surface in the echo signal, execute step 7.2);

[0090] Otherwise, go to step 7.3);

[0091] 7.2) Perform dynamic clutter processing on the echo signal:

[0092] 7.2.1) The radar echo signal processed by AMTI is sent to the dynamic clutter map processing submodule in real time to calculate the echo data Y of the antenna scanning cycle of the current frame n :

[0093] Y n =(1-K)Y n-1 +KX n

[0094] Among them, K is a factor less than 1, X n is the echo signal currently received, Y n-1 It is the echo signal of the previous frame antenna scanning cycle;

[0095] 7.2.2) By obtaining the optimal radar echo signal Y n , that is, the suppression of fixed clutter at low altitude on the sea surface is achieved;

[0096] 7.2.3) Send the radar echo signal after dynamic clutter image processing to the display terminal to complete the echo display;

[0097] 7.3) Directly send the received radar echo signal processed by AMTI to the display terminal to complete the echo display.

[0098] At this point, the processing of the radar signal is completed, and the radar echo signal after the dynamic clutter map processing is output and displayed on the terminal display, completing the terminal echo display.

[0099] In this example, under the condition that the solid-state transceiver component outputs an abnormal clock reference signal, the FPGA control register is readjusted to control the clock management module, and the optimal performance of the clock reference signal is obtained by optimizing and improving the performance of the signal processing system without replacing the solid-state transceiver component. This provides a new method for optimizing the echo performance of pulse compression radars, optimizing the echo performance of frequency modulation continuous wave radars, and quickly solving clock reference signal failures in complex marine environments.

[0100] The above description is only a specific example of the present invention and does not constitute any limitation to the present invention. It is obvious that for professionals in this field, after understanding the content and principles of the present invention, it is possible to make various modifications and changes in form and details without departing from the principles and structures of the present invention. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A clock-converted radar signal processing method is based on a solid-state transceiver component and a signal processing system, wherein the signal processing system comprises: The clock management module, the A / D sampling module, the FPGA processing module, the DSP module and the crystal oscillator are characterized in that the implementation steps include the following: (1) Generate an external clock reference signal, an intermediate frequency echo signal and a frame synchronization signal FSP through a solid-state transceiver component, and generate an internal clock reference signal through a crystal oscillator; (2) Sending the external clock reference signal generated by the component and the internal clock reference signal generated by the crystal oscillator to the clock management module, and sending the intermediate frequency echo signal to the A / D sampling module; (3) The signal processing system determines the status of the external clock reference signal output by the received solid-state transceiver component: If the external clock reference signal generated by the component does not meet the requirements of the signal processing system, readjust its clock management module so that the input clock source signal of the clock management module is always the internal reference clock generated by the crystal oscillator, so as to eliminate the electromagnetic interference signal caused by the cable, and then send the internal clock output by the clock management module to the A / D sampling module; Otherwise, the external clock reference signal generated by the solid-state transceiver component is preferably used as the input clock source of the clock management module, and the external clock output by the clock management module is sent to the A / D sampling module; (4) The A / D sampling module receives the clock output by the clock management module and the intermediate frequency echo signal generated by the component, sets the sampling frequency and timing parameters of the A / D sampling processing, processes and outputs the clock signal and the digital intermediate frequency signal; (5) The FPGA processing module receives the clock signal and the digital intermediate frequency signal to generate a digital baseband signal, and forms an echo signal through pulse compression or FFT processing and sends it to the DSP processing module; (6) The DSP processing module performs corresponding filtering according to the status of the received echo signal.

2. The method according to claim 1, characterized in that: The clock management module is readjusted in step (3) by the signal processing system calling the control register in the FPGA processing module to adjust the parameters of the clock management module.

3. The method according to claim 1, characterized in that The implementation steps of step (5) include the following: (5a) The FPGA processing module receives the clock signal and digital intermediate frequency signal processed by the A / D sampling module and the frame synchronization signal FSP output by the solid-state transceiver component, and synthesizes multiple digital single-ended signals under strict clock timing control, and then performs DC subtraction and digital down-conversion DDC processing, outputs I and Q two-way digital baseband signals through orthogonal modulation, and filters them; (5b) Depending on the radar system, the filtered digital baseband signal is processed differently: When the radar is in pulse compression mode, it receives the digital baseband signal and generates the frame synchronization signal FSP based on the received clock reference signal. At the same time, the frame synchronization signal FSP is sent to the solid-state transceiver component, and the signal processing system completes the pulse compression processing of the baseband signal, and then sends the processed echo signal to the DSP processing module; When the radar is a frequency modulated continuous wave system, it receives the baseband signal and the frame synchronization signal FSP output by the solid-state transceiver component, and uses the received clock reference signal as a reference, performs FFT processing on the baseband signal, and sends the processed echo signal to the DSP processing module.

4. The method according to claim 3, characterized in that Different processing of digital baseband echo signals under different systems in step (5): (5a) In the pulse compression system, the digital baseband echo signal is pulse compressed: (5a1) Generate a frame synchronization signal FSP based on the clock signal timing, send the signal to the solid-state transceiver component, and receive the two input digital baseband signals X I and X Q : X I =cos(n·f0 / f s ·2·π).*X T X Q =sin(n·f0 / f s ·2·π).*X T Where n is the number of sampling points, f0 is the center frequency of the signal, and f s is the sampling frequency, X T is the transposed signal of X; (5a2) According to the two input signals X I and X Q The time domain pulse compression input signal x(n) is obtained: x(n)=X I +jX Q Where j is a complex unit; (5a3) The pulse compression input signal x(n) is input into the matched filter h(n) to obtain the time domain pulse compression output signal y(n): Among them, x(k) is the sequence signal of the input signal, and h(nk) is the sequence signal of the matched filter; (5b) In the frequency modulated continuous wave system, the digital baseband echo signal is subjected to FFT processing: (5b1) According to the frequency modulation slope μ of the linear frequency modulation continuous wave sawtooth wave intermediate frequency transmission signal, the frequency modulation bandwidth B s , frequency modulation period T s , echo delay time τ, calculate the beat signal frequency f b : Where R is the detection distance of FMCW radar, c is the speed of light, that is, c = 3 × 10 8 m / s; (5b2) Send the two-way digital baseband echo signal, clock signal, frame synchronization FSP and related control signals to the FFT IP core in the FPGA to identify the beat signal frequency f b , and then calculate the detection distance R of the FMCW radar: (5b3) The number of FFT processing points N is selected according to the accuracy of the detection distance, and the detection accuracy ΔR is calculated according to the detection distance R: (5b4) The frequency domain echo signal f obtained by FFT processing b The data is sent to the AMTI processing submodule, and R and ΔR are used as backups of distance detection and distance detection accuracy for subsequent terminal display.

5. The method according to claim 1, characterized in that Step (6) The DSP processing module performs corresponding processing according to the received echo signal status, and the implementation steps include the following: (6a) The DSP processing module receives the processed echo signal and processes it according to the echo signal status: If the echo signal contains meteorological clutter such as rain, snow and fog at low altitude over the sea, it is filtered out by AMTI and then step (6b) is performed; Otherwise, directly execute step (6b); (6b) The DSP processing module determines whether the echo signal contains fixed clutter at low altitude on the sea surface: If it is contained, it will be filtered out through the dynamic clutter map, and the processed echo signal will be sent to the terminal for display; Otherwise, it is sent directly to the terminal for display.

6. The method according to claim 5, characterized in that In step (6a), the clutter in the echo signal is filtered out by AMTI, and the implementation steps are as follows: (6a1) Receive the radar echo signal processed by (5b), and calculate the cancellation coefficient W according to the cancellation result X1 of the current frame signal and the cancellation result X2 of the previous frame signal opt : Where: X2 * is the conjugate function of X2; (6a2) Calculate the radar echo cancellation result X according to the above parameters: X=X2-X1·W opt 4 (6a3) The radar echo after AMTI processing is cancelled and the result X is sent to (6b) for processing.

7. The method according to claim 5, characterized in that In step (6b), the low-altitude fixed clutter on the sea surface in the echo is filtered out by using the dynamic clutter map. The radar echo signal processed by (6a) is sent to the dynamic clutter map submodule in real time to filter out the low-altitude fixed clutter on the sea surface in the echo signal, and the echo signal Y of the current frame antenna scanning period is obtained. n : Y n =(1-K)Y n-1 +KX n Among them, K is a factor less than 1, X n is the echo signal currently received, Y n-1 It is the echo signal of the previous frame antenna scanning cycle.

8. The method according to claim 1, characterized in that: The clock management module is used to provide the clock reference signal required for the operation of the A / D sampling module, the FPGA processing module and the DSP processing module; The A / D sampling module comprises: The receiving submodule is used to receive the reference clock signal input by the clock management module and the analog intermediate frequency signal input by the solid-state transceiver component, and send the reference clock signal to the FPGA processing module; The processing submodule is used to convert the analog intermediate frequency signal into a digital intermediate frequency signal and send it to the FPGA processing module.

9. The method according to claim 1, characterized in that: The FPGA processing module comprises: Control register, used to control the configuration register of the clock management module; The digital down-conversion DDC processing submodule is used to receive the clock signal, frame synchronization signal FSP and digital intermediate frequency signal processed by the A / D sampling module, and synthesize multiple digital single-ended signals under strict clock timing control, and then complete the digital down-conversion DDC processing under the action of the digital oscillator NCO and the multiplier MUL after DC subtraction, and then output the I and Q two-way digital baseband signals through orthogonal modulation; The low-pass filter processing submodule is used to complete the low-pass filter processing of the two-way digital baseband signals; The time-domain pulse compression processing submodule is used to receive the digital baseband signal and the clock reference signal under the pulse compression system, and generate the frame synchronization signal FSP based on the received clock reference signal and send it to the solid-state transceiver component to complete the pulse compression processing of the digital baseband signal, and then send the processed echo signal to the DSP processing module; The FFT processing submodule is used to receive the digital baseband signal and the frame synchronization signal FSP output by the solid-state transceiver component under the frequency modulation continuous wave system, and processes the baseband echo signal through FFT based on the received clock reference signal, and then sends the processed echo signal to the DSP processing module.

10. The method according to claim 1, characterized in that: The DSP module comprises: The AMTI processing submodule is used to process the meteorological clutter such as rain, snow and fog at low altitude on the sea surface in the echo signal, and send the processed echo signal to the dynamic clutter map processing submodule or the display terminal; The dynamic clutter image processing submodule is used to process the fixed clutter at low altitude on the sea surface in the echo signal, and send the processed echo signal to the terminal for display.

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