Motor controller, fault detection method thereof and electronic equipment

Abstract

The invention relates to a motor controller, a fault detection method thereof and electronic equipment, and belongs to the technical field of electronics. The method is applied to a main control chip in the motor controller, the main control chip is connected with a chip to be tested in the motor controller through an IO channel and a communication channel, and the communication channel is a channel different from the IO channel. The method comprises the following steps: sending a first signal to a to-be-tested chip based on an IO path; a second signal sent by the chip to be tested based on the communication path is received, and the second signal represents the level state of the first signal; and according to the first signal and the second signal, detecting whether an IO path between the main control chip and the to-be-detected chip has a fault or not. According to the motor controller circuit, the fault of the IO path between the main control chip and the to-be-detected chip is detected according to the first signal sent by the main control chip and the second signal sent by the to-be-detected chip, the integrity and reliability of the motor controller circuit are ensured, and therefore the driving experience and safety of an automobile are improved.

Description

Technical Field

[0001] The present application belongs to the field of electronic technology, and specifically relates to a motor controller, a fault detection method thereof, and an electronic device. Background Art

[0002] The motor controller is the core of electric vehicles. It is responsible for controlling and regulating the motor of electric vehicles to ensure the performance, efficiency and safety of the vehicle. The motor control substrate is the main body of the motor controller. When it is installed on the motor controller and experiences some extreme working conditions, some failures will occur, thus affecting the driving experience of the car and even the safe operation of the vehicle. Summary of the invention

[0003] In view of this, the purpose of the present application is to provide a motor controller and a fault detection method and electronic device thereof, so as to timely detect possible faults of the motor controller to ensure the reliability of the motor controller.

[0004] The embodiment of the present application is implemented as follows:

[0005] In the first aspect, an embodiment of the present application provides a motor controller fault detection method, which is applied to a main control chip in the motor controller, wherein the main control chip is connected to a chip to be tested in the motor controller through an IO path and a communication path, and the communication path is a path different from the IO path. The method includes: sending a first signal to the chip to be tested based on the IO path; receiving a second signal sent by the chip to be tested based on the communication path, wherein the second signal represents the level state of the first signal; and detecting whether there is a fault in the IO path between the main control chip and the chip to be tested based on the first signal and the second signal.

[0006] In the above embodiment, each time the motor controller is powered on, the key chip (chip to be tested) and the key path (IO path) on the motor controller are detected to promptly detect possible faults in the motor controller, thereby ensuring the reliability of the motor controller circuit, thereby reducing safety accidents caused by faults in the motor controller, and improving the driving experience of the car and the safety of the vehicle; and when detecting whether there is a fault in the IO path between the main control chip and the chip to be tested, a first signal is sent based on the IO path, and a second signal representing the level state of the first signal is sent based on the communication path. In this way, the accuracy of the detection can be ensured, and the abnormality of the second signal sent based on the IO path due to a fault in the IO path can be avoided, thereby avoiding misjudgment of the detection result.

[0007] In combination with a possible implementation manner of the first aspect, before sending the first signal to the chip under test based on the IO path, the method also includes: receiving a self-test result of the chip under test based on the communication path; and determining that the self-test result indicates that the chip under test has passed the self-test.

[0008] In the above embodiment, before detecting whether there is a fault in the IO path between the main control chip and the chip to be tested, the chip to be tested is first allowed to execute a self-test program. Through the self-test, it is possible to quickly identify whether the chip to be tested can work normally, thereby quickly locating the area where the fault occurs; at the same time, the self-test can also ensure the stability of the performance of the chip to be tested, guarantee the efficient operation of the motor controller, and thus ensure the safety and stability of the vehicle. The chip to be tested sends the self-test result to the main control chip. The main control chip determines that the self-test result of the chip to be tested indicates that the chip to be tested has passed the self-test, and then executes the subsequent test content. This can ensure the accuracy of the test results and reduce the problem of inaccurate test results caused by the fault of the chip to be tested itself.

[0009] In combination with a possible implementation manner of the embodiment of the first aspect, the method further includes: when the self-test result indicates that the chip under test fails the self-test, determining that the chip under test has a fault.

[0010] In the above embodiment, when the main control chip receives the self-test result of the chip under test based on the communication channel and the result indicates that the chip under test fails the self-test, it can directly determine that the chip under test has a fault, without the need to perform subsequent detection of whether there is a fault in the IO channel between the main control chip and the chip under test, which can save diagnostic time and resources.

[0011] In combination with a possible implementation manner of the embodiment of the first aspect, a three-state gate is arranged on the IO path between the main control chip and the chip under test. Before sending a first signal to the chip under test based on the IO path, the method further includes: setting the IO pin of the main control chip corresponding to the IO path to output mode, setting the IO pin of the chip under test at the opposite end of the IO path to input mode, and switching the data transmission direction of the three-state gate to the direction from the main control chip to the chip under test.

[0012] In the above embodiment, a three-state gate is set on the IO path of the main control chip and the chip to be tested, and before the main control chip sends a first signal to the chip to be tested, the IO pin of the main control chip is set to output mode, and the IO pin of the chip to be tested is set to input mode, and the data transmission direction of the three-state gate is switched to the direction from the main control chip to the chip to be tested, so that the main control chip and the chip to be tested enter the self-test mode, so as to perform fault detection and realize accurate positioning of the fault, thereby ensuring the reliability and safety of the motor controller, so as to improve the driving experience of the car and the safety of the vehicle.

[0013] In combination with a possible implementation manner of the embodiment of the first aspect, the method also includes: when there is no fault in the IO path between the main control chip and the chip under test, setting the IO pin of the main control chip corresponding to the IO path to input mode, setting the IO pin of the chip under test at the opposite end of the IO path to output mode, and switching the data transmission direction of the three-state gate to a direction from the chip under test to the main control chip.

[0014] In the above embodiment, when there is no fault in the IO path between the main control chip and the chip under test, the IO pin of the main control chip is set to input mode, the IO pin of the chip under test is set to output mode, and the data transmission direction of the three-state gate is switched to the direction from the chip under test to the main control chip, so that the main control chip and the chip under test enter the normal working mode and start normal operation.

[0015] In the second aspect, an embodiment of the present application provides a motor controller, comprising a chip to be tested and a main control chip, wherein the main control chip is connected to the chip to be tested through an IO path and a communication path, wherein the communication path is a path different from the IO path, and the main control chip is used to send a first signal to the chip to be tested based on the IO path; receive a second signal sent by the chip to be tested based on the communication path, wherein the second signal represents the level state of the first signal; and detect whether there is a fault in the IO path between the main control chip and the chip to be tested based on the first signal and the second signal.

[0016] In combination with a possible implementation manner of the embodiment of the second aspect, the main control chip is further used to receive a self-test result of the chip under test based on the communication path, and determine that the self-test result indicates that the chip under test has passed the self-test.

[0017] In combination with a possible implementation manner of the second aspect, the motor controller also includes a three-state gate, which is arranged on the IO path between the main control chip and the chip to be tested; the main control chip is used to set the IO pin of the main control chip corresponding to the IO path to output mode, set the IO pin of the chip to be tested at the opposite end of the IO path to input mode, and switch the data transmission direction of the three-state gate to the direction from the main control chip to the chip to be tested.

[0018] In combination with a possible implementation manner of the second aspect, the main control chip is also used to set the IO pin of the main control chip corresponding to the IO channel to input mode, set the IO pin of the chip under test at the opposite end of the IO channel to output mode, and switch the data transmission direction of the three-state gate to the direction from the chip under test to the main control chip.

[0019] In a third aspect, an embodiment of the present application provides an electronic device, such as a motor controller provided in the above-mentioned second aspect embodiment and / or any possible implementation method in combination with the second aspect embodiment.

[0020] Other features and advantages of the present application will be described in the following description. The purpose and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. The above and other purposes, features and advantages of the present application will be more clearly shown in the drawings.

[0022] Figure 1 A schematic diagram of the structure of a motor controller provided in an embodiment of the present application is shown.

[0023] Figure 2 A schematic diagram of the structure of another motor controller provided in an embodiment of the present application is shown.

[0024] Figure 3 A schematic diagram showing the principle of a motor controller fault detection method provided in an embodiment of the present application is shown.

[0025] Figure 4 A schematic flow chart of a motor controller fault detection method provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the scope of protection of the present application. It will be appreciated by those skilled in the art that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other.

[0027] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0028] In the description of the embodiments of the present application, unless otherwise clearly specified or limited, the technical term "connection" may refer to a direct connection or an indirect connection through an intermediate medium.

[0029] An embodiment of the present application provides a fault detection method for a motor controller, which enables the motor controller to perform self-checks on the IO (Input Output) path between the main control chip and the chip to be tested each time the motor controller is started, promptly discover faults in the motor controller, ensure the reliability of the motor controller and the integrity of the circuit, thereby improving the driving experience of the car and the safety of the car.

[0030] Combined with Figure 1 The structural diagram of the motor controller illustrates the principle of a motor controller fault detection method provided in an embodiment of the present application.

[0031] like Figure 1As shown, the motor controller includes a main control chip and a chip to be tested, and the main control chip and the chip to be tested are connected through an IO path and a communication path. The main control chip sends a first signal to the chip to be tested based on the IO path, receives a second signal sent by the chip to be tested based on the communication path, and detects whether the IO path between the main control chip and the chip to be tested is faulty according to the first signal and the second signal. Each time the motor controller is powered on, the IO path between the main control chip and the chip to be tested of the motor controller is detected, and possible faults of the motor controller can be found in time, thereby ensuring the reliability of the motor controller circuit, thereby reducing safety accidents caused by faults in the motor controller, and improving the driving experience of the car and the safety of the vehicle; and when detecting whether the IO path between the main control chip and the chip to be tested is faulty, a first signal is sent based on the IO path, and a second signal representing the level state of the first signal is sent based on the communication path. In this way, the accuracy of the detection can be ensured, and the abnormality of the second signal sent based on the IO path due to a fault in the IO path is avoided, thereby causing a misjudgment of the detection result.

[0032] Among them, the main control chip is responsible for processing the motor control algorithm and realizing precise control of the motor. The main control chip can be a single-chip microcomputer, a digital signal processor (DSP), a microprocessor, and other types of chips. The paths on the main control chip can be set to different forms such as analog input / output (AI / O) and digital input / output (DI / O) according to actual needs. The chips to be tested are other chips in the motor controller except the main control chip, such as current management chips, resolver chips, switch chips, etc.

[0033] The communication path is different from the IO path. The communication path may be an SPI (Serial Peripheral Interface) path or a CAN (Controller Area Network) path.

[0034] In one implementation, the communication path is an SPI path, and the main control chip and the chip to be tested are connected through an IO path and an SPI path. Among them, SPI is a common serial communication protocol used for communication between a microcontroller and various peripheral devices. In a motor controller provided in an embodiment of the present application, SPI is used for communication between the main control chip and the chip to be tested. The SPI communication protocol involves at least four paths: SCLK (clock signal), MOSI (host output / slave input), MISO (host input / slave output) and CS (chip select signal).

[0035] In one implementation, the communication path is a CAN path, and the main control chip and the chip to be tested are connected through an IO path and a CAN path. Among them, the CAN bus is a serial communication protocol commonly used in the automotive field. The CAN path usually includes signal lines such as CANH (CAN high), CANL (CAN low), GND (ground wire) and CAN_SHLD (shield wire).

[0036] The second signal represents the level state of the first signal. Therefore, when the first signal is consistent with the second signal, it indicates that there is no fault in the IO path between the main control chip and the chip under test; when the first signal is inconsistent with the second signal, it indicates that there is a fault in the IO path between the main control chip and the chip under test.

[0037] When the main control chip fails to output, or the IO path between the main control chip and the chip to be tested is disconnected, etc., the IO path between the main control chip and the chip to be tested will fail, resulting in inconsistency between the first signal and the second signal. For example, under normal circumstances, the communication path of the chip to be tested is set to output mode, and when the communication path outputs a low level, it means that the chip to be tested has no faults. However, if the IO path between the main control chip and the chip to be tested is disconnected, the second signal fed back to the main control chip through the communication path is a high level. When the first signal sent by the main control chip to the chip to be tested based on the IO path is a low level, the first signal and the second signal will be inconsistent. At this time, it is determined that the IO path between the main control chip and the chip to be tested has a fault.

[0038] In order to achieve effective detection of motor controller faults, in the embodiment of the present application, the main control chip must send high and low levels to the chip to be tested at least once. In this implementation, if the second signal sent by the chip to be tested received by the main control chip twice is consistent with the level state of the first signal sent by the corresponding main control chip, it indicates that there is no fault in the IO path between the main control chip and the chip to be tested. When the second signal sent by the chip to be tested received by the main control chip once is inconsistent with the level state of the first signal sent by the corresponding main control chip, it indicates that there is a fault in the IO path between the main control chip and the chip to be tested.

[0039] In one implementation manner, in order to improve detection accuracy, the main control chip is also used to receive a self-test result of the chip under test based on a communication path, and determine that the self-test result indicates that the chip under test has passed the self-test.

[0040] The purpose of the self-test of the chip under test is to detect whether the chip under test can start normally. If the self-test of the chip under test passes, it indicates that the chip under test can start normally. In this implementation, the motor controller can perform further fault detection. In addition, the chip under test needs to be initialized before the self-test of the chip under test.

[0041] In one implementation mode, when the main control chip receives the self-test result of the chip under test based on the communication channel and the result indicates that the chip under test fails the self-test, it indicates that there is a fault in the chip under test and the chip under test cannot work normally. The main control chip reports the fault information to the vehicle controller of the car and controls the motor controller to enter the fault mode.

[0042] like Figure 2 As shown, the motor controller may further include a three-state gate, which is arranged on an IO path between the main control chip and the chip to be tested.

[0043] A tri-state gate is a digital logic circuit element that has three states: high, low, and high impedance (also called high Z or tri-state). The characteristic of a tri-state gate is that it can not drive its load when it does not output any signal (i.e., high impedance state), which enables multiple devices to share the same communication bus without interfering with each other. The tri-state gate has an additional control input, called an enable signal (Enable). When the enable signal is activated, the tri-state gate will output a high or low level state according to its logic input; when the enable signal is not activated, the tri-state gate outputs a high impedance state. Among them, Figure 2 EN0 and EN1 are the enable signals of the three-state gate. EN1 is obtained by reversing EN0, so that the data transmission direction of the three-state gate can be controlled by one signal.

[0044] In one implementation mode, before the main control chip sends a first signal to the chip under test based on the IO channel, the main control chip is used to set the IO pin of the main control chip corresponding to the IO channel to output mode, set the IO pin of the chip under test at the other end of the IO channel to input mode, and switch the data transmission direction of the three-state gate to the direction from the main control chip to the chip under test.

[0045] Through the above settings, the main control chip, the chip to be tested and the three-state gate are set to the self-test mode, and fault detection can be performed. The self-test mode and normal working mode status of the main control chip, the chip to be tested and the three-state gate are shown in Table 1 below:

[0046]

[0047] In one implementation mode, when there is no fault in the IO path between the main control chip and the chip under test, the main control chip is also used to set the IO pin of the main control chip corresponding to the IO path to input mode, set the IO pin of the chip under test at the opposite end of the IO path to output mode, and switch the data transmission direction of the three-state gate to the direction from the chip under test to the main control chip.

[0048] In this implementation mode, the main control chip, the chip to be tested and the tri-state gate are in a normal working mode. After being in the normal mode, the main control chip and the chip to be tested are reinitialized and start working normally.

[0049] In one implementation mode, when there is a fault in the IO path between the main control chip and the chip to be tested, the main control chip reports fault information and controls the motor controller to enter a fault mode.

[0050] In a possible implementation manner, the detection principle of the above motor controller can be as follows Figure 3 shown.

[0051] The present application also provides a motor controller fault detection method. Figure 4 The present application provides a motor controller fault detection method, comprising the following steps:

[0052] S10: Sending a first signal to the chip under test based on the IO path.

[0053] In step S10, the main control chip is connected to the chip to be tested in the motor controller via an IO path and a communication path, and the communication path is a path different from the IO path. The first signal can be a high level or a low level.

[0054] S20: Receive a second signal sent by the chip under test based on the communication path.

[0055] The second signal represents the level state of the first signal.

[0056] S30: Detect whether there is a fault in the IO path between the main control chip and the chip to be tested according to the first signal and the second signal.

[0057] Among them, when the first signal is consistent with the second signal, it indicates that there is no fault in the IO path between the main control chip and the chip under test. At this time, the main control chip and the chip under test are reinitialized and enter the normal working mode; when the first signal is inconsistent with the second signal, it indicates that there is a fault in the IO path between the main control chip and the chip under test. At this time, the main control chip reports fault information and controls the motor controller to enter the fault mode.

[0058] In a possible implementation, before sending the first signal to the chip under test based on the IO channel, the motor controller fault detection method further includes: receiving a self-test result of the chip under test based on the communication channel; and determining that the self-test result indicates that the chip under test has passed the self-test. Further fault detection can be performed at this time.

[0059] In a possible implementation, before sending the first signal to the chip under test based on the IO path, the motor controller fault detection method further includes: when the self-test result indicates that the chip under test fails the self-test, determining that the chip under test has a fault. At this time, it is necessary to report the fault information and control the motor controller to enter the fault mode.

[0060] In a possible implementation, a tri-state gate is provided on the IO path between the main control chip and the chip to be tested. Before sending the first signal to the chip to be tested based on the IO path, the motor controller fault detection method further includes: setting the IO pin of the main control chip corresponding to the IO path to output mode, setting the IO pin of the chip to be tested at the opposite end of the IO path to input mode, and switching the data transmission direction of the tri-state gate to the direction from the main control chip to the chip to be tested. The main control chip, the chip to be tested, and the tri-state gate are put into a self-test mode to perform fault detection.

[0061] In a possible implementation, the motor controller fault detection method further includes: when there is no fault in the IO path between the main control chip and the chip to be tested, the IO pin of the main control chip corresponding to the IO path is set to input mode, the IO pin of the chip to be tested at the opposite end of the IO path is set to output mode, and the data transmission direction of the three-state gate is switched to the direction from the chip to be tested to the main control chip. The main control chip, the chip to be tested and the three-state gate enter the normal working mode and start normal work.

[0062] The motor controller fault detection method provided in the embodiment of the present application has the same implementation principle and technical effects as those of the aforementioned motor controller embodiment. For the sake of brief description, for matters not mentioned in the method embodiment, reference may be made to the corresponding contents in the aforementioned motor controller embodiment.

[0063] The present application also provides an electronic device, which includes the motor controller provided in the present application. In some implementations, the electronic device may include a motor and a motor controller, and the electronic device may be any electronic device including a motor controller, such as an aircraft in the aerospace field, a medical imaging device in the medical field, a car in the transportation field, etc.

[0064] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0065] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0066] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A motor controller fault detection method, characterized in that: A main control chip is applied to the motor controller, the main control chip is connected to the chip to be tested in the motor controller through an IO path and a communication path, and the communication path is a path different from the IO path. The method includes: Sending a first signal to the chip under test based on the IO path; receiving a second signal sent by the chip under test based on the communication path, wherein the second signal represents a level state of the first signal; According to the first signal and the second signal, it is detected whether there is a fault in the IO path between the main control chip and the chip to be tested.

2. The method according to claim 1, characterized in that Before sending the first signal to the chip under test based on the IO path, the method further includes: Receiving a self-test result of the chip under test based on the communication path; Determining the self-test result indicates that the chip under test has passed the self-test.

3. The method according to claim 2, characterized in that The method further comprises: When the self-test result indicates that the chip under test fails the self-test, it is determined that the chip under test has a fault.

4. The method according to claim 1, characterized in that: A tri-state gate is provided on the IO path between the main control chip and the chip under test. Before sending the first signal to the chip under test based on the IO path, the method further includes: The IO pin of the main control chip corresponding to the IO channel is set to output mode, the IO pin of the chip under test at the opposite end of the IO channel is set to input mode, and the data transmission direction of the three-state gate is switched to the direction from the main control chip to the chip under test.

5. The method according to claim 4, characterized in that The method further comprises: When there is no fault in the IO path between the main control chip and the chip under test, The IO pin of the main control chip corresponding to the IO channel is set to input mode, the IO pin of the chip under test at the opposite end of the IO channel is set to output mode, and the data transmission direction of the three-state gate is switched to the direction from the chip under test to the main control chip.

6. A motor controller, characterized in that: include: Chip to be tested; A main control chip is connected to the chip under test through an IO path and a communication path, wherein the communication path is a path different from the IO path, and the main control chip is used to send a first signal to the chip under test based on the IO path; receive a second signal sent by the chip under test based on the communication path, wherein the second signal represents the level state of the first signal; and detect whether there is a fault in the IO path between the main control chip and the chip under test according to the first signal and the second signal.

7. The motor controller according to claim 6, characterized in that: The main control chip is further used to receive a self-test result of the chip under test based on the communication path, and determine that the self-test result indicates that the chip under test has passed the self-test.

8. The motor controller according to claim 6, characterized in that: The motor controller further comprises: a tri-state gate arranged on an IO path between the main control chip and the chip to be tested; The main control chip is used to set the IO pin of the main control chip corresponding to the IO channel to output mode, set the IO pin of the chip under test at the opposite end of the IO channel to input mode, and switch the data transmission direction of the three-state gate to the direction from the main control chip to the chip under test.

9. The motor controller according to claim 8, characterized in that: The main control chip is also used to set the IO pin of the main control chip corresponding to the IO channel to input mode, set the IO pin of the chip under test at the opposite end of the IO channel to output mode, and switch the data transmission direction of the three-state gate to the direction from the chip under test to the main control chip.

10. An electronic device, characterized in that: A motor controller as claimed in any one of claims 6 to 9.

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